Semiconductor device

Abstract

To provide a semiconductor device excellent in semiconductor characteristics, particularly in electrical characteristics.SOLUTION: A semiconductor device includes at least a semiconductor layer, and a first electrode and a second electrode each of which is arranged on the side of a first surface of the semiconductor layer. The semiconductor device is configured in such a manner as to cause a current to flow in the semiconductor layer in a first direction from the first electrode toward the second electrode. The semiconductor layer has a corundum structure, and a direction of a c-axis in the semiconductor layer is the first direction.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a semiconductor device that is useful for a power device or the like. [Background technology]

[0002] Conventionally, there is a problem of cracks and lattice defects occurring when growing crystals on a foreign substrate. To address this problem, methods such as matching the lattice constant and thermal expansion coefficient of the substrate and film have been considered. In addition, when mismatching occurs, film formation techniques such as ELO have also been considered.

[0003] Patent Document 1 describes a method of forming a buffer layer on a heterogeneous substrate and growing a zinc oxide-based semiconductor layer on the buffer layer. Patent Document 2 describes forming a nanodot mask on a heterogeneous substrate and then forming a single crystal semiconductor material layer. Non-Patent Document 1 describes a method of growing GaN crystals on sapphire via GaN nanocolumns. Non-Patent Document 2 describes a method of growing GaN crystals on Si(111) using a periodic SiN intermediate layer to reduce defects such as pits.

[0004] However, with each of these techniques, the deposition rate was slow, and cracks, dislocations, warping, and the like occurred in the substrate, and dislocations, cracks, and the like occurred in the epitaxial film, making it difficult to obtain a high-quality epitaxial film. Also, these techniques caused problems when increasing the diameter of the substrate and the thickness of the epitaxial film.

[0005] In addition, semiconductor devices using gallium oxide (Ga2O3), which has a large band gap, are attracting attention as next-generation switching elements that can achieve high voltage resistance, low loss, and high heat resistance, and are expected to be applied to power semiconductor devices such as inverters. Furthermore, due to its wide band gap, it is expected to be used as a light-emitting device such as an LED or a sensor. The band gap of gallium oxide can be controlled by mixing indium and aluminum, either individually or in combination, and it constitutes an extremely attractive material family as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductors refer to In X Al Y Ga Z O3 (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5), and can be viewed as being in the same material family that contains gallium oxide.

[0006] However, since the most stable phase of gallium oxide is the β-gallium structure, it is difficult to form a crystalline film having a corundum structure unless a special film formation method is used, and many problems still remain in terms of crystal quality, etc. In response to this, several studies are currently being conducted on the formation of a crystalline semiconductor film having a corundum structure. Patent Document 3 describes a method for producing an oxide crystal thin film by mist CVD using gallium or indium bromide or iodide. Patent Documents 4 to 6 describe a multilayer structure in which a semiconductor layer having a corundum crystal structure and an insulating film having a corundum crystal structure are laminated on a base substrate having a corundum crystal structure.

[0007] Recently, as described in Patent Documents 7 to 9, ELO growth of a gallium oxide film having a corundum structure has been considered. According to the methods described in Patent Documents 7 to 9, it is possible to obtain a gallium oxide film having a good corundum structure. However, even with the ELO film formation method using the thermal expansion coefficient difference described in Patent Document 7, when the crystal film is actually examined, it tends to grow as facets, and there are problems such as dislocations and cracks caused by this facet growth. In addition, as described in Patent Document 10, it has been considered that the electrical properties can be improved depending on the surface direction, but it is still not satisfactory for application to a semiconductor device having excellent electrical properties. Patent Documents 3 to 10 are all publications related to patents or patent applications filed by the present applicant. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2010-232623 A [Patent Document 2] Special Publication No. 2010-516599 [Patent Document 3] Patent No. 5397794 [Patent Document 4] Patent No. 5343224 [Patent Document 5] Patent No. 5397795 [Patent Document 6] JP 2014-72533 A [Patent Document 7] JP 2016-98166 A [Patent Document 8] JP 2016-100592 A [Patent Document 9] JP 2016-100593 A [Patent Document 10] JP 2018-082144 A [Non-patent literature]

[0009] [Non-Patent Document 1] Kazuhide Kusakabe., et al., “Overgrowth of GaN layer on GaN nano-columns by RF-molecular beam epitaxy”, Journal of Crystal Growth 237-239 (2002) 988-992 [Non-Patent Document 2] KY Zang., et al., “Defect reduction by periodic SiNx interlayers in gallium nitride grown on Si (111)”, Journal of Applied Physics 101, 093502 (2007) Summary of the Invention [Problem to be solved by the invention]

[0010] An object of the present invention is to provide a semiconductor device having excellent semiconductor characteristics, particularly excellent electrical characteristics. [Means for solving the problem]

[0011] As a result of intensive research to achieve the above-mentioned object, the inventors have found that electrical characteristics are anisotropic not in relation to the primary surface of gallium oxide having a corundum structure, but in relation to the relationship between each crystal axis and the direction of current flow, and have succeeded in creating a semiconductor device that has at least a semiconductor layer and a first electrode and a second electrode each arranged on a first surface side of the semiconductor layer, and is configured so that a current flows in the semiconductor layer in a first direction from the first electrode to the second electrode, wherein the semiconductor layer has a corundum structure and the direction of the c-axis of the semiconductor layer is the first direction, and have found that such a semiconductor device has excellent semiconductor characteristics, particularly electrical characteristics, and can solve the above-mentioned conventional problems in one fell swoop. After obtaining the above findings, the inventors conducted further studies and completed the present invention.

[0012] That is, the present invention relates to the following inventions. [1] A semiconductor device comprising at least a semiconductor layer, a first electrode and a second electrode each arranged on a first surface side of the semiconductor layer, wherein a current flows in the semiconductor layer in a first direction from the first electrode to the second electrode, the semiconductor layer having a corundum structure, and the direction of the c-axis of the semiconductor layer is the first direction. [2] The semiconductor device according to [1], wherein the semiconductor layer contains a metal oxide containing at least one metal selected from the group consisting of gallium, indium, rhodium and iridium. [3] The semiconductor device according to [1], wherein the semiconductor layer is mainly composed of a metal oxide containing at least gallium. [4] The carrier concentration of the semiconductor layer is 1×10 19 / cm 3 The semiconductor device according to any one of the above [1] to [3], [5] The semiconductor device according to any one of [1] to [4], wherein the first surface is an m-plane. [6] The semiconductor device according to any one of [1] to [5] above, which is a power device. [7] The semiconductor device according to [6] above, which is a power module, an inverter or a converter. [8] The semiconductor device according to [6] above, which is a power card. [9] The semiconductor device according to [8], further comprising a cooler and an insulating member, the cooler being provided on both sides of the semiconductor layer, with at least the insulating member interposed therebetween.

[10] The semiconductor device according to [9], wherein a heat dissipation layer is provided on each side of the semiconductor layer, and the cooler is provided on the outside of the heat dissipation layer with at least the insulating member interposed therebetween.

[11] A semiconductor system including a semiconductor device, the semiconductor device being the semiconductor device according to any one of [1] to

[10] above. Effect of the Invention

[0013] The semiconductor device of the present invention has excellent semiconductor characteristics, particularly excellent electrical characteristics. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic diagram showing the configuration of a film forming apparatus preferably used in the present invention. [Diagram 2] FIG. 2 is a schematic diagram of a film forming apparatus (mist CVD) of another embodiment different from that of FIG. 1, which is preferably used in the present invention. [Diagram 3] FIG. 1 is a diagram illustrating a preferred example of a power supply system. [Figure 4] FIG. 1 is a diagram illustrating a preferred example of a system device. [Diagram 5] FIG. 1 is a diagram illustrating a preferred example of a power supply circuit diagram of a power supply device. [Figure 6] FIG. 1 is a diagram illustrating an example of a metal oxide semiconductor field effect transistor (MOSFET) as one embodiment of a semiconductor device of the present invention. [Figure 7] 1A and 1B are schematic top views of a semiconductor device according to one embodiment of the present invention. [Figure 8] FIG. 8 is a schematic partial cross-sectional view of one embodiment of a semiconductor device of the present invention, and shows, for example, an example of the AA cross section in FIG. [Figure 9] FIG. 8 is a partial cross-sectional view showing a specific example as one embodiment of the semiconductor device of the present invention, for example, showing an example of a specific cross section taken along line AA in FIG. [Figure 10] FIG. 2 is a diagram showing a schematic diagram of a preferred example of a power card. [Figure 11] FIG. 1 is a diagram showing the results of Test Example 1. [Figure 12] FIG. 1 shows the results of Test Example 2. [Figure 13] FIG. 13 is a graph showing the results of Test Example 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The semiconductor device of the present invention has at least a semiconductor layer, a first electrode and a second electrode each arranged on a first surface side of the semiconductor layer, and is configured so that a current flows in the semiconductor layer in a first direction from the first electrode to the second electrode, and is characterized in that the semiconductor layer has a corundum structure and the direction of the c-axis of the semiconductor layer is the first direction. In an embodiment of the present invention, the semiconductor layer contains a metal oxide containing at least one metal selected from gallium, indium, rhodium, and iridium. In an embodiment of the present invention, the semiconductor layer is mainly composed of a metal oxide containing at least gallium, which can provide better semiconductor properties such as high breakdown voltage. The term "main component" means that the metal oxide is contained in an atomic ratio of 50% or more of the total components in the semiconductor layer, preferably 70% or more, more preferably 90% or more, and may be 100% in some embodiments. It is also preferable that the metal oxide contains at least gallium and further contains indium, rhodium, or iridium, and it is also preferable that the metal oxide contains at least gallium and further contains indium or / and aluminum. It is more preferable that the metal oxide contains at least gallium, since it can provide better properties as a power device, such as switching properties. In the present invention, it is also preferable that the first surface is an m-plane, since it can provide better electrical properties.

[0016] The semiconductor layer is a crystalline oxide semiconductor layer, and preferably contains a crystalline oxide semiconductor. The crystalline oxide semiconductor contains the metal oxide, and as described above, it is preferable that it contains at least gallium, and more preferably contains gallium oxide and its mixed crystal as a main component. The crystal structure of the crystalline oxide semiconductor is not particularly limited, but in the present invention, the crystalline oxide semiconductor preferably contains a metal oxide having a corundum structure as a main component. The metal oxide is not particularly limited, but it is preferable that it contains at least one or more metals in the fourth to sixth periods of the periodic table, more preferably contains at least gallium, indium, rhodium or iridium, and most preferably contains gallium. In the present invention, the metal oxide also preferably contains gallium and indium and / or aluminum. Examples of the metal oxide containing gallium include α-Ga2O3 or its mixed crystal. A semiconductor layer containing such a preferable metal oxide as a main component can have better crystallinity and heat dissipation, and can also have better semiconductor properties. For example, when the metal oxide is α-Ga2O3, the atomic ratio of gallium contained in the semiconductor layer is 50% or more relative to the total metal components in the semiconductor layer, and α-Ga2O3 is contained in the semiconductor layer. In the present invention, the atomic ratio of gallium in the metal components of the semiconductor layer is preferably 70% or more, more preferably 80% or more, relative to the total metal components in the semiconductor layer. The semiconductor layer may be single crystal or polycrystalline. The semiconductor layer is usually in the form of a film, but is not particularly limited as long as it does not impede the object of the present invention, and may be in the form of a plate or a sheet.

[0017] The semiconductor layer may contain a dopant. The dopant is not particularly limited as long as it does not impede the object of the present invention. It may be an n-type dopant or a p-type dopant. Examples of the n-dopant include tin, germanium, silicon, titanium, zirconium, vanadium, and niobium. The carrier concentration may be appropriately set, and specifically, for example, about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the carrier concentration may be, for example, about 1×10 17 / cm 3 In addition, as an example of the embodiment, the carrier concentration of the semiconductor layer may be set to about 1×10 20 / cm 3 Although the above-mentioned high concentration may be used, in the embodiment of the present invention, a lower carrier concentration in the semiconductor layer can make the anisotropy more effective and improve the semiconductor characteristics. For example, the carrier concentration is set to 1×10 19 / cm 3 It is preferable to set it to 5×10 or less. 18 / cm 3 It is more preferable to set it to 1×10 or less. 18 / cm 3 Most preferably, the following:

[0018] The semiconductor layer can be obtained by, for example, the following suitable film formation method: For example, a crystal substrate having a second side shorter than a first side is used, and the semiconductor layer is formed by epitaxial crystal growth by a mist CVD method or a mist epitaxy method so that a current flows in a first direction from the first electrode to the second electrode, with the c-axis direction being a first direction, to fabricate a semiconductor device.

[0019] <Crystal substrate> The crystal substrate is not particularly limited as long as it does not impede the object of the present invention, and may be a known substrate. It may be an insulating substrate, a conductive substrate, or a semiconductor substrate. It may be a single crystal substrate or a polycrystalline substrate. The crystal substrate may be, for example, a substrate containing a crystalline substance having a corundum structure as a main component. The "main component" refers to a substrate containing the crystalline substance in a composition ratio of 50% or more, preferably 70% or more, and more preferably 90% or more. The crystal substrate having the corundum structure may be, for example, a sapphire substrate, an α-type gallium oxide substrate, or an α-type mixed crystal substrate containing Ga2O3 and Al2O3, with Al2O3 being more than 0 wt% and 60 wt% or less.

[0020] In the present invention, the crystal substrate is preferably a sapphire substrate. Examples of the sapphire substrate include a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, and an r-plane sapphire substrate. In the embodiment of the present invention, it is preferable to use an m-plane sapphire substrate or an m-plane α-Ga2O3 substrate. The sapphire substrate may have an off-angle. The off-angle is not particularly limited, and is, for example, 0.01° or more, preferably 0.2° or more, and more preferably 0.2° to 12°. The sapphire substrate preferably has a crystal growth surface that is an a-plane, an m-plane, or an r-plane, and is also preferably a c-plane sapphire substrate having an off-angle of 0.2° or more. The thickness of the crystal substrate is not particularly limited, but is usually 10 μm to 20 mm, and more preferably 10 to 1000 μm.

[0021] In the present invention, an ELO mask may be used to control the direction of crystal growth, etc., in the semiconductor layer so that the second side is shorter than the first side, the linear thermal expansion coefficient in the first crystal axis direction is smaller than the linear thermal expansion coefficient in the second crystal axis direction, the first side direction is parallel or approximately parallel to the first crystal axis direction, and the second side direction is likely to be parallel or approximately parallel to the second crystal axis direction. Suitable shapes for the crystal substrate include, for example, polygonal shapes such as triangles, quadrilaterals (eg, rectangles or trapezoids), pentagons or hexagons, U-shapes, inverted U-shapes, L-shapes and C-shapes.

[0022] In the present invention, other layers such as a buffer layer and a stress relaxation layer may be provided on the crystal substrate. The buffer layer may be a layer made of a metal oxide having the same crystal structure as the crystal substrate or the semiconductor layer. The stress relaxation layer may be an ELO mask layer.

[0023] The epitaxial crystal growth means is not particularly limited and may be any known means as long as it does not impede the object of the present invention. Examples of the epitaxial crystal growth means include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD. In the present invention, the epitaxial crystal growth means is preferably mist CVD or mist epitaxy.

[0024] In the mist CVD method or mist epitaxy method, a raw material solution containing a metal is atomized (atomization process), the droplets are suspended, the resulting atomized droplets are transported to the vicinity of the crystal substrate by a carrier gas (transportation process), and then the atomized droplets are thermally reacted (film formation process).

[0025] (Raw material solution) The raw material solution contains a metal as a film-forming raw material, and is not particularly limited as long as it can be atomized, and may contain an inorganic material or an organic material. The metal may be a single metal or a metal compound, and is not particularly limited as long as it does not impede the object of the present invention. Examples of the metal include gallium (Ga), iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (Tb), and the like. Examples of suitable metals include one or more metals selected from the group consisting of W, tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca) and zirconium (Zr). In the present invention, the metal preferably includes at least one or more metals from the fourth to sixth periods of the periodic table, and more preferably includes at least gallium, indium, rhodium or iridium. In the present invention, the metal preferably includes gallium and indium and / or aluminum. By using such a preferred metal, the semiconductor layer can be formed, which can be more suitably used in semiconductor devices and the like.

[0026] In the present invention, the raw material solution can be suitably used in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or salt. Examples of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of the salt include organic metal salts (e.g., metal acetates, metal oxalates, and metal citrates), metal sulfides, metal nitrates, metal phosphates, and metal halides (e.g., metal chlorides, metal bromides, and metal iodides).

[0027] The solvent of the raw material solution is not particularly limited as long as it does not impair the object of the present invention, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, it is preferable that the solvent contains water.

[0028] The raw material solution may be mixed with additives such as hydrohalogenated acid and oxidizing agents. Examples of the hydrohalogenated acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Examples of the oxidizing agent include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.

[0029] The raw material solution may contain a dopant. The dopant is not particularly limited as long as it does not impede the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants. The concentration of the dopant is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the concentration of the dopant may be, for example, about 1×10 17 / cm 3 In accordance with the present invention, the dopant may be present in a concentration as low as about 1×10 20 / cm 3 It may be contained in a concentration higher than the above.

[0030] (Atomization process) In the atomization step, a raw solution containing a metal is prepared, the raw solution is atomized, the droplets are suspended, and the atomized droplets are generated. The blending ratio of the metal is not particularly limited, but is preferably 0.0001 mol / L to 20 mol / L with respect to the whole raw solution. The atomization means is not particularly limited as long as it can atomize the raw solution, and may be a known atomization means, but in the present invention, it is preferable that it is an atomization means using ultrasonic vibration. The mist used in the present invention is one that floats in the air, and is more preferably a mist that has an initial velocity of zero and can be transported as a gas floating in space, rather than being sprayed like a spray, for example. The droplet size of the mist is not particularly limited, and may be droplets of about several mm, but is preferably 50 μm or less, more preferably 1 to 10 μm.

[0031] (Transportation process) In the transport step, the atomized droplets are transported to the substrate by the carrier gas. The type of carrier gas is not particularly limited as long as it does not impede the object of the present invention, and suitable examples include oxygen, ozone, inert gas (e.g., nitrogen, argon, etc.), and reducing gas (hydrogen gas, forming gas, etc.). The type of carrier gas may be one type, but may be two or more types, and a dilution gas (e.g., 10-fold dilution gas, etc.) with a changed carrier gas concentration may be further used as a second carrier gas. The number of supply points of the carrier gas may be not only one but also two or more. The flow rate of the carrier gas is not particularly limited, but is preferably 1 LPM or less, and more preferably 0.1 to 1 LPM.

[0032] (Film forming process) In the film-forming step, the atomized droplets are reacted to form a film on the crystal substrate. The reaction is not particularly limited as long as a film is formed from the atomized droplets, but in the present invention, a thermal reaction is preferred. The thermal reaction may be performed as long as the atomized droplets react with heat, and the reaction conditions are not particularly limited as long as the object of the present invention is not hindered. In this step, the thermal reaction is usually performed at a temperature equal to or higher than the evaporation temperature of the solvent in the raw material solution, but is preferably at a temperature not too high, more preferably 650°C or lower. In addition, the thermal reaction may be performed under any atmosphere, such as a vacuum, a non-oxygen atmosphere, a reducing gas atmosphere, or an oxygen atmosphere, as long as the object of the present invention is not hindered, and may be performed under any condition, such as atmospheric pressure, pressurized, or reduced pressure. In the present invention, the thermal reaction is preferably performed under atmospheric pressure, because the calculation of the evaporation temperature is easier and the equipment can be simplified. The film thickness can be set by adjusting the film-forming time.

[0033] Hereinafter, a film forming apparatus 19 suitable for use in the present invention will be described with reference to the drawings. The film forming apparatus 19 in Fig. 1 includes a carrier gas source 22a for supplying a carrier gas, a flow rate control valve 23a for controlling the flow rate of the carrier gas sent from the carrier gas source 22a, a carrier gas (dilution) source 22b for supplying a carrier gas (dilution), a flow rate control valve 23b for controlling the flow rate of the carrier gas (dilution) sent from the carrier gas (dilution) source 22b, a mist generating source 24 in which a raw material solution 24a is stored, a container 25 in which water 25a is stored, an ultrasonic vibrator 26 attached to the bottom surface of the container 25, a film forming chamber 30, a quartz supply pipe 27 connecting the mist generating source 24 to the film forming chamber 30, and a hot plate (heater) 28 installed in the film forming chamber 30. A substrate 20 is placed on the hot plate 28.

[0034] Then, as shown in FIG. 1, the raw solution 24a is accommodated in the mist generating source 24. Next, the substrate 20 is placed on the hot plate 28, and the hot plate 28 is operated to raise the temperature in the film forming chamber 30. Next, the flow rate control valve 23 (23a, 23b) is opened to supply the carrier gas from the carrier gas source 22 (22a, 22b) into the film forming chamber 30, and the atmosphere in the film forming chamber 30 is sufficiently replaced with the carrier gas, and then the flow rate of the carrier gas and the flow rate of the carrier gas (dilution) are adjusted. Next, the ultrasonic vibrator 26 is vibrated, and the vibration is propagated to the raw solution 24a through the water 25a, thereby atomizing the raw solution 24a to generate the mist droplets 24b. The atomized droplets 24b are introduced into the film formation chamber 30 by the carrier gas and transported to the substrate 20. The atomized droplets 24b then undergo a thermal reaction in the film formation chamber 30 under atmospheric pressure, forming a film (semiconductor layer) on the substrate 20.

[0035] It is also preferable to use a mist CVD apparatus 19 as the film forming apparatus shown in Fig. 2. The mist CVD apparatus 19 in Fig. 2 includes a susceptor 21 on which a substrate 20 is placed, a carrier gas supplying means 22a for supplying a carrier gas, a flow rate control valve 23a for controlling the flow rate of the carrier gas sent from the carrier gas supplying means 22a, a carrier gas (dilution) supplying means 22b for supplying a carrier gas (dilution), a flow rate control valve 23b for controlling the flow rate of the carrier gas sent from the carrier gas (dilution) supplying means 22b, a mist generating source 24 in which a raw material solution 24a is contained, a container 25 in which water 25a is contained, an ultrasonic vibrator 26 attached to the bottom surface of the container 25, a supply pipe 27 made of a quartz tube with an inner diameter of 40 mm, a heater 28 installed in the periphery of the supply pipe 27, and an exhaust port 29 for discharging mist, droplets, and exhaust gas after the thermal reaction. The susceptor 21 is made of quartz, and the surface on which the substrate 20 is placed is inclined from the horizontal plane. By making both the supply pipe 27, which serves as the film formation chamber, and the susceptor 21 from quartz, impurities originating from the apparatus are prevented from being mixed into the film formed on the substrate 20. This mist CVD apparatus 19 can be used in the same manner as the film formation apparatus 19 described above.

[0036] By using the suitable film formation apparatus, the semiconductor layer can be more easily formed on the crystal growth surface of the crystal substrate. The semiconductor layer is usually formed by epitaxial crystal growth.

[0037] The semiconductor layer is useful for semiconductor devices, particularly power devices. Examples of semiconductor devices formed using the semiconductor layer include transistors such as MIS and HEMT, TFTs, Schottky barrier diodes using semiconductor-metal junctions, JBS, PN or PIN diodes combined with other P layers, and light-emitting and receiving devices. In the present invention, the crystalline oxide semiconductor is grown to form a semiconductor layer, and can be peeled off from the crystal substrate as desired and used as a semiconductor layer (film) in a semiconductor device. The semiconductor layer can also be disposed on a substrate having a higher thermal conductivity than the crystal substrate.

[0038] The semiconductor device is preferably used in a lateral element (lateral device) in which an electrode is formed on one side of a semiconductor layer. Suitable examples of the semiconductor device include a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), and a light emitting diode (LED).

[0039] Hereinafter, preferred examples of the semiconductor device in which the semiconductor layer of the present invention is applied to an n-type semiconductor layer (an n+ type semiconductor layer, an n- type semiconductor layer, etc.) will be described with reference to the drawings, but the present invention is not limited to these examples.

[0040] FIG. 6 shows an example of a lateral MOSFET. The semiconductor device according to the embodiment of the present invention has at least one semiconductor layer (e.g., 131a), and at least a first electrode (e.g., 135b) and a second electrode (e.g., 135c) arranged on the first surface side of the semiconductor layer. The semiconductor layer is configured so that a current flows in a first direction from the first electrode to the second electrode. The semiconductor layer has a corundum structure, and the direction of the c-axis of the semiconductor layer is the first direction. In the embodiment of the present invention, it is preferable that the first surface of the semiconductor layer is an m-plane, and according to such a preferable embodiment, the electrical characteristics of the semiconductor device can be improved. In detail, the MOSFET in FIG. 6 includes an n-type semiconductor layer 131a, a first n+ type semiconductor layer 131b, a second n+ type semiconductor layer 131c, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, a drain electrode 135c, a buffer layer 138, and a semi-insulating layer 139. Also, for example, as shown in FIG. 6, by burying an n+ type semiconductor layer in an n- type semiconductor layer, a current can be passed more satisfactorily than in other lateral MOSFETs.

[0041] The electrode material may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; metal oxide conductive films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures and laminates thereof.

[0042] The electrode can be formed by a known method such as vacuum deposition or sputtering. More specifically, for example, when forming an electrode using two types of metals, a first metal and a second metal, the electrode can be formed by stacking a layer made of the first metal and a layer made of the second metal, and patterning the layer made of the first metal and the layer made of the second metal using a photolithography method.

[0043] FIG. 7 shows a schematic partial top view for explaining the main parts of one embodiment of a semiconductor device of the present invention, but the number, shape, and arrangement of electrodes of the semiconductor device can be appropriately selected.

[0044] FIG. 8 is a partial cross-sectional view for explaining a main part as one embodiment of the semiconductor device of the present invention, and shows, for example, the AA cross section of FIG. 7. The semiconductor device 100 in the embodiment of the present invention has at least one semiconductor layer (for example, 2), and at least a first electrode (for example, 5b) and a second electrode (for example, 5c) arranged on the first surface side of the semiconductor layer 2. The semiconductor layer is configured so that a current flows in a first direction from the first electrode to the second electrode. The semiconductor layer has a corundum structure, and the direction of the c-axis of the semiconductor layer is the first direction. In the embodiment of the present invention, it is preferable that the first surface of the semiconductor layer is an m-plane, and according to such a preferable embodiment, the electrical characteristics of the semiconductor device can be improved. The semiconductor device 100 has an oxide semiconductor film 2 including a crystal containing at least gallium oxide. The oxide semiconductor film 2 includes an inversion channel region 2a. The crystal contains gallium oxide as a main component. The crystal may be a mixed crystal. The semiconductor device 100 has an oxide film 2b at a position in contact with the inversion channel region 2a.

[0045] FIG. 9 is a schematic cross-sectional view for explaining a specific example as one embodiment of the semiconductor device of the present invention, and shows, for example, an example of a specific AA cross section of FIG. 7. The semiconductor device 200 in the embodiment of the present invention has at least one semiconductor layer (e.g., 2), and at least a first electrode (e.g., 5b) and a second electrode (e.g., 5c) arranged on the first surface side of the semiconductor layer 2. The semiconductor layer is configured so that a current flows in a first direction from the first electrode to the second electrode. The semiconductor layer has a corundum structure, and the direction of the c-axis of the semiconductor layer is the first direction. In the embodiment of the present invention, it is preferable that the first surface of the semiconductor layer is an m-plane, and according to such a preferable embodiment, the electrical characteristics of the semiconductor device can be improved. The semiconductor device 200 has an oxide semiconductor film 2 including a crystal containing at least gallium oxide, and the oxide semiconductor film 2 includes an inversion channel region 2a. The crystal has a corundum structure. Furthermore, the semiconductor device 200 has a first semiconductor region 1a and a second semiconductor region 1b. In this embodiment, as shown in FIG. 9, the inversion channel region 2a is located between the first semiconductor region 1a and the second semiconductor region 1b in a plan view. When a voltage is applied to the semiconductor device 200, the inversion channel region of the oxide semiconductor film 2 is inverted, and the first semiconductor region 1a and the second semiconductor region 1b are electrically connected. In this embodiment, the first semiconductor region 1a and the second semiconductor region 1b are located in the oxide semiconductor film 2, and are arranged in the oxide semiconductor film 2 so that the upper surface of the first semiconductor region 1a, the upper surface of the second semiconductor region 1b, and the upper surface of the inversion channel region 2a are flush with each other. On the first surface side 200a of the semiconductor device 200, the oxide semiconductor film 2 including the first semiconductor region 1a and the inversion channel region 2a, and the second semiconductor region 1b form a flat surface, which facilitates design including the arrangement of electrodes, and also leads to a thinner semiconductor device. As described below, the case where the oxide semiconductor film 2 has an oxide film 2b provided in contact with the inversion channel region 2a2 is included in the case where the first semiconductor region 1a, the oxide semiconductor film 2 including the inversion channel region 2a, and the second semiconductor region 1b have flat surfaces. The first semiconductor region 1a and the second semiconductor region 1b may be embedded in the oxide semiconductor film 2, or may be disposed in the oxide semiconductor film 2 by ion implantation. In addition, the oxide semiconductor film 2 in this embodiment is a p-type semiconductor film, and the first semiconductor region 1a and the second semiconductor region 1b are n-type. The oxide semiconductor film 2 may contain a p-type dopant. Furthermore, the semiconductor device 200 may have an oxide film 2b disposed on the inversion channel region 2a. In the embodiment of the present invention, it is also preferable that the oxide film 2b has a crystal structure belonging to the trigonal system to which the corundum structure belongs. The oxide film 2b contains at least one element of Group 15 of the periodic table, and preferably contains phosphorus.In another embodiment, the oxide film 2b may further include at least one element of group 13 of the periodic table, and the semiconductor device 200 has a first electrode 5b electrically connected to the first semiconductor region 1a and a second electrode 5c electrically connected to the second semiconductor region 1b. The semiconductor device 200 further has a third electrode 5a between the first electrode 5b and the second electrode 5c, which is separated from the inversion channel region 2a by an insulating film 4a. As shown in the drawing, the first electrode 5b, the second electrode 5c, and the third electrode 5a are arranged on the first surface side 200a of the semiconductor device 200. In detail, the semiconductor device 200 has an insulating film 4a arranged on the oxide film 2b on the inversion channel region 2a, and the third electrode 5a is arranged on the insulating film 4a. In addition, in the semiconductor device 200, the first electrode 5b and the first semiconductor region 1a are electrically connected, but the insulating film 4b may be partially located between the first electrode 5b and the first semiconductor region 1a. In addition, the second electrode 5c and the second semiconductor region 1b are electrically connected, but the insulating film 4b may be partially located between the second electrode 5c and the second semiconductor region 1b. Furthermore, the semiconductor device 200 may have another layer on the second surface side 200b of the semiconductor device 200, that is, the lower surface side of the oxide semiconductor film 2, and may have a substrate 9 as shown in FIG. 9. In addition, as shown in FIG. 7, the first semiconductor region 1a has a portion overlapping the first electrode 5b and a portion overlapping the third electrode 5a in a plan view. In addition, the second semiconductor region 1b has a portion overlapping the second electrode 5c and a portion overlapping the third electrode 5a in a plan view. In this embodiment, when a positive voltage is applied to the third electrode 5a with respect to the first electrode 5b, the inversion channel region 2a of the oxide semiconductor film 2 is inverted from p-type to n-type to form an n-type channel layer, the first semiconductor region 1a and the second semiconductor region 1b are electrically connected, and electrons flow from the source electrode to the drain electrode. In addition, by setting the voltage of the third electrode 5b to zero, no channel layer is formed in the inversion channel region 2a, and the device is turned off.In this embodiment, for example, the first electrode 5b may be a source electrode, the second electrode 5c may be a drain electrode, and the third electrode 5a may be a gate electrode. In this case, the insulating film 4a is a gate insulating film, and the insulating film 4b is a field insulating film.

[0046] The oxide semiconductor film containing crystals containing gallium oxide and / or the oxide semiconductor film containing crystals having a corundum structure can be obtained by forming the film using an epitaxial crystal growth method. The epitaxial crystal growth method is not particularly limited and may be a known method as long as it does not impede the object of the present invention. Examples of the epitaxial crystal growth method include a CVD method, a MOCVD (Metal Organic Chemical Vapor) method, a MOVPE (Metalorganic Vapor-phase epitaxy) method, a mist CVD method, a mist epitaxy method, a MBE (Molecular Beam Epitaxy) method, a HVPE (Hydride Vapor Phase Epitaxy) method, and a pulse growth method. In an embodiment of the present invention, when forming an oxide semiconductor film by the epitaxial crystal growth, it is preferable to use a mist CVD method or a mist epitaxy method.

[0047] Examples of materials for the first electrode 165a and the second electrode 165b include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), or indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof. The method for forming the electrode film is not particularly limited, and the electrode can be formed on the substrate according to a method appropriately selected from wet methods such as printing, spraying, and coating, physical methods such as vacuum deposition, sputtering, and ion plating, and chemical methods such as CVD and plasma CVD, taking into consideration the suitability of the material.

[0048] In addition to the above, the semiconductor device of the present invention can be suitably used as a power module, inverter, or converter by using a known method, and can also be suitably used in a semiconductor system using a power supply device. The power supply device can be manufactured from the semiconductor device or as the semiconductor device by connecting to a wiring pattern or the like in a normal manner. FIG. 3 shows a power supply system 170 using a plurality of the power supply devices 171 and 172 and a control circuit 173. The power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182 as shown in FIG. 4. An example of a power supply circuit diagram of a power supply device is shown in FIG. 5. FIG. 5 shows a power supply circuit of a power supply device consisting of a power circuit and a control circuit, in which a DC voltage is switched at a high frequency by an inverter 192 (composed of MOSFETs A to D) and converted to AC, then insulated and transformed by a transformer 193, rectified by a rectifier MOSFET 194 (A to B'), smoothed by a DCL 195 (smoothing coils L1, L2) and a capacitor, and a DC voltage is output. At this time, a voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls an inverter 192 and a rectifying MOSFET 194 so as to obtain a desired output voltage.

[0049] In the present invention, the semiconductor device is preferably a power card, and includes a cooler and an insulating member. More preferably, the cooler is provided on both sides of the semiconductor layer via at least the insulating member, and most preferably, a heat dissipation layer is provided on both sides of the semiconductor layer, and the cooler is provided on the outside of the heat dissipation layer via at least the insulating member. FIG. 10 shows a power card according to a preferred embodiment of the present invention. The power card in FIG. 10 is a double-sided cooling type power card 201, and includes a refrigerant tube 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin part 209, a semiconductor chip 301a, a metal heat transfer plate (protruding terminal part) 302b, a heat sink and electrode 303, a metal heat transfer plate (protruding terminal part) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308. The thickness direction cross section of the refrigerant tube 202 has many flow paths 222 partitioned by many partition walls 221 extending in the flow path direction at a predetermined interval from each other. Such a suitable power card can realize higher heat dissipation and can satisfy higher reliability.

[0050] The semiconductor chip 301a is joined to the inner main surface of the metal heat transfer plate 302b with a solder layer 104, and the metal heat transfer plate (protruding terminal portion) 302b is joined to the remaining main surface of the semiconductor chip 301a with a solder layer 304, so that the anode electrode surface and the cathode electrode surface of the flywheel diode are connected in so-called anti-parallel to the collector electrode surface and the emitter electrode surface of the IGBT. Examples of materials for the metal heat transfer plates (protruding terminal portions) 302b and 303b include Mo and W. The metal heat transfer plates (protruding terminal portions) 302 and 303b have a thickness difference that absorbs the thickness difference of the semiconductor chips 101a and 101b, and as a result, the outer surface of the metal heat transfer plate 102 is flat.

[0051] Resin sealing portion 209 is made of, for example, epoxy resin, and is molded to cover the side surfaces of metal heat transfer plates 302b and 303b, and semiconductor chip 301a is molded with resin sealing portion 209. However, the outer main surfaces, i.e., the contact heat receiving surfaces, of metal heat transfer plates 302b and 303b are completely exposed. Metal heat transfer plates (protruding terminal portions) 302b and 303b protrude from resin sealing portion 209 to the right in Fig. 10, and control electrode terminal 305, which is a so-called lead frame terminal, connects, for example, the gate (control) electrode surface of semiconductor chip 301a on which an IGBT is formed to control electrode terminal 305.

[0052] The insulating plate 208, which is an insulating spacer, is made of, for example, an aluminum nitride film, but may be another insulating film. The insulating plate 208 completely covers and adheres to the metal heat transfer plates 302b and 303b, but the insulating plate 208 and the metal heat transfer plates 302b and 303b may simply be in contact with each other, or may be coated with a good heat transfer material such as silicon grease, or may be joined by various methods. Also, an insulating layer may be formed by ceramic spraying, or the insulating plate 208 may be joined to the metal heat transfer plate, or may be joined or formed on the refrigerant tube.

[0053] The refrigerant tubes 202 are made by cutting a plate material formed by pultrusion or extrusion of an aluminum alloy to a required length. The thickness direction cross section of the refrigerant tubes 202 has many flow paths 222 partitioned by many partition walls 221 extending in the flow path direction at a predetermined interval from each other. The spacer 203 may be, for example, a soft metal plate such as a solder alloy, or may be a film formed by coating or the like on the contact surface of the metal heat transfer plates 302b and 303b. The surface of this soft spacer 3 easily deforms and fits the minute unevenness and warping of the insulating plate 208 and the minute unevenness and warping of the refrigerant tubes 202 to reduce thermal resistance. Note that a known good thermal conductive grease or the like may be applied to the surface of the spacer 203, or the spacer 203 may be omitted.

[0054] (Test Examples 1 to 3) Using the mist CVD method, m-plane α-Ga2O3 semiconductor films and c-plane α-Ga2O3 semiconductor films were formed, and the relationship between electrical resistivity and carrier concentration × mobility (conductivity) was analyzed using a terahertz spectrometer (a general-purpose terahertz spectrometer manufactured by Nippo Precision Co., Ltd., "TeraProspector (registered trademark, trademark registration number 5550188)" (2019)). The anisotropy of the c-axis and a-axis was evaluated. The results are shown in Figure 11 (Test Example 1) and Figure 12 (Test Example 2). As is clear from Figures 11 and 12, anisotropy in which the resistivity is lower in the c-axis direction was confirmed, and further, anisotropy in which the resistivity is slightly lower in the m-axis direction was confirmed. In addition, when the carrier concentration of each sample in Test Example 1 was examined using a Hall effect measurement device, the results shown in Figure 13 (Test Example 3) were obtained, and it was found that the lower the carrier concentration, the greater the anisotropy. [Industrial Applicability]

[0055] The semiconductor device of the present invention can be used in a wide variety of fields, including semiconductors (eg, compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful as power devices. [Explanation of symbols]

[0056] 1a First semiconductor region 1b Second semiconductor region 2. Oxide semiconductor film 2a Inversion channel region 2b Oxide film 4a Insulating film 4b Insulating film 5a Third electrode 5b First electrode 5c Second electrode 9 Substrate 19 Film deposition equipment 20 Substrate 21 Susceptor 22a Carrier gas supply source 22b Carrier gas (dilution) supply source 23a Carrier gas flow control valve 23b Carrier gas (dilution) flow control valve 24 Mist Source 24a Raw material solution 24b Atomized droplets 25 Container 25a water 26 Ultrasonic transducer 27 Supply pipe 28 Hot plate (heater) 29 Exhaust port 30 Deposition chamber 100 Semiconductor device 100a Page 1 131a n-type semiconductor layer 131b First n+ type semiconductor layer 131c second n+ type semiconductor layer 132 p-type semiconductor layer 132a p+ type semiconductor layer 134 Gate insulating film 135a Gate electrode 135b Source electrode 135c Drain electrode 139 Substrate 170 Power System 171 Power supply 172 Power supply 173 Control circuit 180 System Unit 181 Electronic circuit 182 Power System 192 Inverter 193 Trans 194 Rectifier MOSFET 195 DCL 196 PWM control circuit 197 Voltage Comparator 200 Semiconductor device 200a 1st page 200b 2nd page 201 Double-sided cooled power card 202 Refrigerant tube 203 Spacer 208 Insulating plate (insulating spacer) 209 Sealing resin part 221 Bulkhead 222 Channel 301a Semiconductor chip 302b Metal heat transfer plate (protruding terminal part) 303 Heat sink and electrodes 303b Metal heat transfer plate (protruding terminal part) 304 solder layer 305 Control electrode terminal 308 Bonding Wire

Claims

1. A semiconductor layer; a gate electrode disposed directly on the semiconductor layer or via another layer; the semiconductor device is configured such that a current flows in the semiconductor layer in a first direction along an interface between the semiconductor layer and the gate electrode; The semiconductor device, wherein the semiconductor layer has a corundum structure, and the c-axis direction of the semiconductor layer is the first direction.

2. The semiconductor device according to claim 1 , wherein the first direction is a direction along an upper surface of the semiconductor layer.

3. The semiconductor device according to claim 2 , wherein the upper surface is an m-plane.

4. a gate insulating film is provided between the semiconductor layer and the gate electrode; 4. The semiconductor device according to claim 1, wherein the interface is an interface between the semiconductor layer and the gate insulating film.

5. 5. The semiconductor device according to claim 1, wherein the semiconductor layer contains a metal oxide containing at least one metal selected from the group consisting of gallium, indium, rhodium and iridium.

6. 6. The semiconductor device according to claim 1, wherein the semiconductor layer is mainly composed of a metal oxide containing gallium.

7. The carrier concentration of the semiconductor layer is 1×10 １９ / cm ３ The semiconductor device according to any one of claims 1 to 6, wherein:

8. 8. The semiconductor device according to claim 1, which is a power module, an inverter, a converter, or a power card.

9. A semiconductor system comprising a semiconductor device, the semiconductor device being the semiconductor device according to any one of claims 1 to 8.

Images