Semiconductor device, semiconductor module, LED drive device, dc / dc converter, and vehicle

Abstract

To enhance convenience of semiconductor devices.SOLUTION: A semiconductor device (1, 1A, 1B) for controlling a driver circuit (2, 2C) that drives an electronic device includes: a processing circuit (3) having a configuration capable of controlling the driver circuit (2, 2C) according to a device address setting signal (Sa, Sb, Sc) and a control signal (Sin); and an autonomous processing circuit (4) provided independently of the processing circuit (3) and having a configuration capable of controlling the driver circuit (2, 2C) under a preset condition. When the device address setting signal (Sa, Sb, Sc) falls within a predetermined condition, the processing circuit (3) is enabled and the autonomous processing circuit (4) is disabled. When the device address setting signal (Sa, Sb, Sc) deviates from the predetermined condition, the autonomous processing circuit (4) is enabled and the processing circuit (2) is disabled.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and to a semiconductor module, an LED driving device, a DC / DC converter, and a vehicle that use the semiconductor device. [Background technology]

[0002] In an electronic device having multiple semiconductor devices, a device address is assigned to each semiconductor device to identify them. When sending an instruction to a semiconductor device, the device address and an operation associated with the device address are transmitted. This makes it possible to send an instruction to a specified semiconductor device (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-153822 A

[0004] [overview] There is a demand to ensure the functionality of electronic devices even when the device address cannot be obtained accurately.

[0005] A semiconductor device according to an aspect of the present disclosure controls a driver circuit that drives an electronic device. The semiconductor device includes a processing circuit configured to be able to control the driver circuit in response to an external device address setting signal and an external control signal, and an autonomous processing circuit provided independently of the processing circuit and configured to be able to control the driver circuit under preset conditions. When the device address setting signal falls within a predetermined condition, the processing circuit is enabled and the autonomous processing circuit is disabled, and when the device address setting signal does not fall within the predetermined condition, the autonomous processing circuit is enabled and the processing circuit is disabled. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a semiconductor device. [Diagram 2] FIG. 2 is a block diagram of a semiconductor device including a setting circuit. [Diagram 3] FIG. 3 is a block diagram of a semiconductor module. [Figure 4] FIG. 4 is a schematic diagram of an address table. [Diagram 5] FIG. 5 is a flowchart showing the operation of the semiconductor device. [Figure 6] FIG. 6 is a schematic circuit diagram of an address signal output circuit according to a first modified example. [Figure 7] FIG. 7 is a schematic circuit diagram of another example of an address signal output circuit of the first modified example. [Figure 8] FIG. 8 is a schematic circuit diagram showing an address signal output circuit of the second modified example. [Figure 9] FIG. 9 is a schematic diagram of an address table when the address signal output circuit shown in FIG. 8 is used. [Figure 10] FIG. 10 is a schematic circuit diagram of another example of an address signal output circuit of the second modified example. [Figure 11] FIG. 11 is a schematic diagram of an address table when the address signal output circuit shown in FIG. 10 is used. [Figure 12] FIG. 12 is a schematic circuit diagram of a DC / DC converter. [Figure 13] FIG. 13 is a diagram showing the external appearance of the vehicle.

[0007] [Detailed Description] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In this specification, when it is stated that members are connected to each other, this includes the case where they are mechanically connected, and also the case where they are electrically connected, in other words, the case where they are in a state where electricity flows. Therefore, "connect" includes the case where they are "electrically connected."

[0008] A signal may be referred to as being at a Hi level or a Lo level. When the voltage of a signal is higher than a threshold, it is referred to as a Hi level, and when the voltage of a signal is lower than the threshold, it is referred to as a Lo level.

[0009] <Semiconductor device 1> FIG. 1 is a block diagram of a semiconductor device 1. As shown in FIG. 1, the semiconductor device 1 controls a driver circuit 2. An electronic device 9 is connected to the driver circuit 2, and drives the electronic device 9. In this embodiment, the electronic device 9 connected to the driver circuit 2 is, for example, a lamp unit having a plurality of LEDs (Light Emitting Diodes). The electronic device 9 has a plurality of LEDs 91 connected in series, and the anodes of the LEDs 91 are connected to an input voltage Vin, and the cathodes are connected to the driver circuit 2. The driver circuit 2 is also connected to a ground GND, and the driver circuit 2 passes a current Id through the LEDs 91 to light them up. The driver circuit 2 adjusts the current Id by PWM (Pulse Width Modulation) control, and controls the dimming of the LEDs 91. That is, in the following description, when the output setting for the driver circuit 2 is referred to, it refers to the pulse period and on-duty in PWM control.

[0010] However, without being limited thereto, the driver circuit 2 may be a power supply circuit that outputs a specified current to a connected device. In this case, the output setting indicates the output current value. Furthermore, the driver circuit 2 may be a power supply circuit that outputs a specified voltage to a connected device. In this case, the output setting indicates the output voltage value. In addition to these, the output setting includes setting information necessary for driving the device to which the driver circuit 2 is connected.

[0011] As shown in Fig. 1, the semiconductor device 1 has a processing circuit 3 and an autonomous processing circuit 4. A device address Ad (see Fig. 9, etc.) for identifying each individual semiconductor device 1 is set in the semiconductor device 1. A control signal Sin is input from the outside to the semiconductor device 1, and the control signal Sin contains information on the device address. The semiconductor device 1 operates according to drive information contained in the control signal Sin which contains information on its own device address.

[0012] The processing circuit 3 receives a device address setting signal Sa from an address signal output circuit 6 described later and a control signal Sin from a control device 5 described later. The processing circuit 3 recognizes the device address Ad of the semiconductor device 1 based on the device address setting signal Sa. The control signal Sin includes address information specifying the device address Ad and drive information associated with the device address information and including output settings. Note that the control signal Sin may have one piece of address information and one piece of drive information, or may have multiple pieces of address information and drive information associated with each piece of address information.

[0013] The processing circuit 3 refers to the recognized device address Ad and the address information of the control signal Sin, and outputs a first drive signal Sd1 to the driver circuit 2 according to the drive information associated with the address information that matches the device address Ad.

[0014] The first drive signal Sd1 is a signal for driving the driver circuit 2. The first drive signal Sd1 includes operation designation information that designates whether the driver circuit 2 operates or stops, and output setting information that includes an output setting. The driver circuit 2 receives the first drive signal Sd1, and selects either operation or stop according to the operation designation information. Also, the driver circuit 2 drives the LED 91 with an output setting according to the output setting information.

[0015] That is, the drive information of the control signal Sin includes an output setting. For example, in the case of a configuration for controlling the driver circuit 2 that drives the LED 91, the drive information may be information specifying the lighting state including the luminance of the LED 91 instead of the pulse frequency and on-duty. That is, the drive information of the control signal Sin may be information specifying the operating state of the device controlled by the driver circuit 2.

[0016] Furthermore, the processing circuit 3 switches between an enabled state and an disabled state. When the processing circuit 3 is in the enabled state, the driver circuit 2 is controlled in response to the first drive signal Sd1 output from the processing circuit 3. When the processing circuit 3 is in the disabled state, the driver circuit 2 is not driven by the first drive signal Sd1 output from the processing circuit 3.

[0017] The processing circuit 3 being in an invalid state may, for example, be in a state where it does not output the first drive signal Sd1, or where it outputs a signal that the driver circuit 2 cannot recognize as the first drive signal Sd1. The processing circuit 3 executes operations even when in an invalid state, and outputs a switching signal Sw to the autonomous processing circuit 4. In other words, the invalid state of the processing circuit 3 can be a wide variety of states in which the driver circuit 2 is not driven and the autonomous processing circuit 4 can be enabled.

[0018] The autonomous processing circuit 4 is provided independently of the processing circuit 3. The autonomous processing circuit 4 being independent of the processing circuit 3 means that in the process of controlling the driver circuit 2, the process of the autonomous processing circuit 4 is executed as a process completely different from the process of the processing circuit 3. Therefore, being independent also includes a case where the autonomous processing circuit 4 is switched between enabled and disabled by a switching signal Sw from the processing circuit 3. Furthermore, it is sufficient that the process of the processing circuit 3 and the process of the autonomous processing circuit 4 are independent, and part of the circuit may be shared.

[0019] The autonomous processing circuit 4 receives a switching signal Sw from the processing circuit 3. The switching signal Sw is a signal that takes on a Lo level and a Hi level. When the processing circuit 3 is in an enabled state, the switching signal Sw is at Lo level. When the processing circuit 3 is in an disabled state, the switching signal Sw is at Hi level. Then, when the autonomous processing circuit 4 receives a Hi level switching signal Sw, it is in an enabled state. Also, when the autonomous processing circuit 4 receives a Lo level switching signal Sw, it is in an disabled state.

[0020] When the autonomous processing circuit 4 is in an enabled state, it outputs a second drive signal Sd2 to the driver circuit 2. The driver circuit 2 is driven to provide an output according to the operation designation information and output setting information of the second drive signal Sd2 output from the autonomous processing circuit 4. The operation designation information and output setting information of the second drive signal Sd2 have predetermined information regardless of the control signal Sin.

[0021] For example, if it is preferable to keep the LED 91 constantly on, the drive information of the control signal Sin includes information to turn on the LED 91. When the driver circuit 2 is driven by the first drive signal Sd1 from the processing circuit 3, the LED 91 is turned on. On the other hand, when the autonomous processing circuit 4 is in an enabled state, the driver circuit 2 is driven by the second drive signal Sd2. As described above, the second drive signal Sd2 has predetermined operation designation information and output setting information, so that the driver circuit 2 is driven by the second drive signal Sd2 regardless of the control signal Sin, and turns on the LED 91. In other words, the LED 91 is turned on even when the processing circuit 3 is not operating, which improves user convenience.

[0022] In addition, the second drive signal Sd2 may be output to operate the device connected to the driver circuit 2 so as to improve the user's convenience. In this way, the user's convenience can be improved. Also, when the processing circuit 3 is not operating, not operating the device connected to the driver circuit 2 may improve the user's convenience. In such a case, the second drive signal Sd2 may include information to stop the device connected to the driver circuit 2. For example, the second drive signal Sd2 may include stop information as the operation designation information. The driver circuit 2 itself may be stopped.

[0023] Furthermore, when the autonomous processing circuit 4 is in a disabled state, the driver circuit 2 is not driven by the second drive signal Sd2 output from the autonomous processing circuit 4. The autonomous processing circuit 4 being in a disabled state can be, for example, a state in which the autonomous processing circuit 4 is stopped, a state in which the second drive signal Sd2 is not output, or a state in which the autonomous processing circuit 4 outputs a second drive signal Sd2 that cannot be recognized by the driver circuit 2. In addition to these, when the autonomous processing circuit 4 is disabled, this broadly includes settings that prevent the autonomous processing circuit 4 from driving the driver circuit 2.

[0024] In the semiconductor device 1, when the processing circuit 3 is in an enabled state, the autonomous processing circuit 4 is in an disabled state. Also, when the processing circuit 3 is in an disabled state, the autonomous processing circuit 4 is in an enabled state. In the semiconductor device 1, when the processing circuit 3 is in an enabled state and the autonomous processing circuit 4 is in an disabled state, the driver circuit 2 is controlled by a first drive signal Sd1. Also, when the processing circuit 3 is in an disabled state and the autonomous processing circuit 4 is in an enabled state, the driver circuit 2 is controlled by a second drive signal Sd2.

[0025] A memory 41 is connected to the autonomous processing circuit 4. Information for setting the second drive signal Sd2 is stored in the memory 41, and the autonomous processing circuit 4 outputs the second drive signal Sd2 including the information stored in the memory 41.

[0026] The memory 41 may be, for example, a random access memory (RAM) that is a storage element, and may be configured such that the setting information can be changed before or after the shipment of the semiconductor device 1. Note that a built-in memory that allows rewriting of information, such as an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM), may also be used. Furthermore, the memory 41 may be a removable external memory using a flash memory or the like. Also, a storage element other than these may also be used. Furthermore, a memory that allows only the output of setting information, such as a read-only memory (ROM), may also be used.

[0027] The semiconductor device 1 has the above-described configuration. The semiconductor device 1 may be a functional IC (Integrated Circuit) 10. In this case, the driver circuit 2 may also be incorporated into the functional IC 10.

[0028] Further, the driver circuit 2 may be configured to output, for example, a voltage signal for controlling an electronic device to a connected electronic device. In such a configuration, a setting circuit 42 as shown in FIG. 2 may be connected to the autonomous processing circuit 4. FIG. 2 is a block diagram of the semiconductor device 1 including the setting circuit 42. The setting circuit 42 has at least one of a resistor 421 and a capacitor 422. The setting circuit 42 is connected to a power supply voltage VDD, and outputs a designation signal Sp that designates output setting information of the second drive signal Sd2. The autonomous processing circuit 4 may generate the second drive signal Sd2 that can execute an output according to the designation signal Sp.

[0029] <Semiconductor module 100> Fig. 3 is a block diagram of a semiconductor module 100. The semiconductor module 100 shown in Fig. 3 includes a plurality of electronic devices 9 each having an LED 91, and constitutes a part of an LED driving device 90 that controls driving of the LED 91. As shown in Fig. 3, the semiconductor module 100 includes a control device 5, a plurality of semiconductor devices 1, a plurality of driver circuits 2, and an address signal output circuit 6. In the semiconductor module 100, at least the semiconductor device 1, the driver circuit 2, the control device 5, and the address signal output circuit 6 may be formed in one package.

[0030] 3, the semiconductor module 100 of this embodiment has four semiconductor devices 1. However, the number of semiconductor devices 1 in the semiconductor module 100 is not limited to four. In addition, the same number of driver circuits 2 as the semiconductor devices 1 are provided.

[0031] A device address Ad is set for each semiconductor device 1. In the semiconductor module 100, the device addresses Ad are 0, 1, 2, and 3. The semiconductor devices 1 having device addresses Ad of 0, 1, 2, and 3 may be referred to as semiconductor devices 1_0, 1_1, 1_2, and 1_3, respectively. Also, the semiconductor module 100 may include a plurality of semiconductor devices 1 having the same device address Ad.

[0032] As described above, the processing circuit 3 receives the device address setting signal Sa and recognizes the device address of the semiconductor device 1 including the processing circuit 3. Here, the address signal output circuit 6 that outputs the device address setting signal Sa and the device address setting signal Sa will be described.

[0033] 3, the address signal output circuit 6 has voltage dividing resistors R1 and R2 and an AD converter C1. The address signal output circuit 6 is a circuit that outputs a device address setting signal Sa to each of the semiconductor devices 1. Therefore, the address signal output circuits 6 connected to each of the semiconductor devices 1 may also be described with subscripts. Furthermore, the components of the address signal output circuit 6 may also be described with subscripts as necessary.

[0034] In the address signal output circuit 6, the voltage dividing resistors R1 and R2 are connected in series. A first end of the voltage dividing resistors R1 and R2 connected in series is connected to a power supply voltage VDD. A second end of the voltage dividing resistors R1 and R2 is connected to the ground GND. An AD converter C1 is connected to a connection point P1 between the voltage dividing resistors R1 and R2. When the semiconductor device 1 is configured with a functional IC 10, at least the AD converter C1 may be incorporated in the functional IC 10. The voltage dividing resistors R1 and R2 may also be incorporated in the functional IC 10. In the address signal output circuit 6 of this embodiment, the AD converter C1 is configured to be incorporated in the functional IC 10.

[0035] In the address signal output circuit 6, the address voltage Vp obtained by dividing the power supply voltage VDD by voltage dividing resistors R1 and R2 is input to the AD converter C1. The AD converter C1 digitizes the address voltage Vp, which is analog information, and outputs it to the processing circuit 3 as a device address setting signal Sa.

[0036] Fig. 4 is a schematic diagram of the address table Tb1. The address table Tb1 shown in Fig. 4 associates the device address setting signal Sa with the device address Ad. The processing circuit 3 recognizes the device address by referring to the address table Tb1 and the device address setting signal Sa shown in Fig. 4.

[0037] The address voltage Vp for generating the device address setting signal Sa may vary due to variations in the voltage dividing resistors R1 and R2, the resistance of the circuit, etc. Therefore, in the address table Tb1, the device address setting signal Sa associated with each device address Ad is configured to have a certain range.

[0038] For example, in the address table Tb1 shown in Figure 4, when the device address setting signal Sa is 0.1 times or more and less than 0.3 times the power supply voltage VDD, the device address Ad is "0." Similarly, when the device address setting signal Sa is 0.3 times or more and less than 0.5 times the power supply voltage VDD, the device address Ad is "1." Furthermore, when the device address setting signal Sa is 0.5 times or more and less than 0.7 times the power supply voltage VDD, the device address Ad is "2." When the device address setting signal Sa is 0.7 times or more and less than 0.9 times the power supply voltage VDD, the device address Ad is "3."

[0039] For example, in the address signal output circuit 6_0 connected to the semiconductor device 1_0 with device address "0", the voltage dividing resistors R1 and R2 are set so that the address voltage Vp is within 0.1 to 0.3 times the power supply voltage VDD. In this embodiment, for example, in the address signal output circuit 6_0 with the device address Ad being "0", the voltage dividing resistors R1 and R2 are set so that the device address setting signal Sa is in the middle of the range, that is, approximately 0.2 times the power supply voltage VDD.

[0040] In the other address signal output circuits 6_1, 6_2, and 6_3, the voltage dividing resistors R1 and R2 are set so that the address voltage Vp is, for example, about 0.4 times, about 0.6 times, and about 0.8 times the power supply voltage VDD, respectively. By setting in this way, it is possible to obtain the device address Ad even if the address voltage Vp becomes larger or smaller than the set value due to the variation of the voltage dividing resistors R1 and R2. Note that the voltage dividing resistors R1 and R2 are not limited to the above as long as they are set so that the device address setting signal Sa falls within each range of the address table Tb1 shown in FIG. 4.

[0041] In addition, in the address signal output circuit 6, the connection with the power supply voltage VDD may become insufficient, that is, may become open, due to an abnormality in the wiring connected to the power supply voltage VDD. In this case, the address voltage Vp becomes approximately 0. In addition, the voltage dividing resistor R1 may become short-circuited, in which case the address voltage Vp becomes approximately the power supply voltage VDD.

[0042] There may also be cases where the connection to ground GND becomes open. In this case, the address voltage Vp becomes approximately the power supply voltage VDD. There may also be a short circuit to ground GND, in which case the address voltage Vp becomes approximately 0. In this way, when an abnormality occurs in the address signal output circuit 6, the address voltage Vp becomes approximately 0 or approximately the power supply voltage VDD.

[0043] In preparation for such an abnormality occurring, the address table Tb1 shown in Fig. 4 associates autonomous operation with a device address setting signal Sa that is less than 0.1 times the power supply voltage VDD or 0.9 times the power supply voltage VDD or more. When the processing circuit 3 recognizes autonomous operation from the device address setting signal Sa, it does not set the device address Ad.

[0044] In the semiconductor module 100 of this embodiment, if the first threshold Th1 is 0.1 and the second threshold Th2 is 0.9, the processing circuit 3 is in an effective state when the device address setting signal Sa is equal to or greater than the first threshold Th1 and less than the second threshold Th2. If it is known that the device address setting signal Sa will not be substantially equal to the value of the power supply voltage VDD, only the first threshold Th1 may be used as the address table Tb1. If it is known that the device address setting signal Sa will not be substantially 0, only the second threshold Th2 may be used as the address table Tb1.

[0045] Next, the operation of the semiconductor device 1 will be described with reference to the drawings. Fig. 5 is a flowchart showing the operation of the semiconductor device 1. In the address signal output circuit 6, a power supply voltage VDD is supplied simultaneously with the start of operation of the semiconductor module 100. Therefore, the processing circuit 3 receives a device address setting signal Sa simultaneously with the start of operation of the semiconductor module 100 (step S101). Then, the processing circuit 3 recognizes the device address Ad of the semiconductor device 1 by referring to the device address setting signal Sa and the address table Tb1 (step S102).

[0046] In the semiconductor module 100, the processing circuit 3 of each semiconductor device 1 receives the control signal Sin (step S103). As described above, the control signal Sin output from the control device 5 is a signal output to all semiconductor devices 1, and is a signal including common information. For example, the control signal Sin is a signal including information that associates the device address Ad with drive information that determines the lighting state (operating state) of the LED 91, which is an appliance. As shown in FIG. 1, the control signal Sin is input to the processing circuit 3 of the semiconductor device 1. Note that the reception of the control signal Sin is not limited to after the recognition of the device address Ad. For example, the control signal Sin may be received at the same timing as or before the device address setting signal Sa.

[0047] The processing circuit 3 judges whether the device address setting signal Sa is within the valid range based on the device address setting signal Sa (step S104). Note that the device address setting signal Sa being within the valid range indicates that the device address setting signal Sa is equal to or greater than the first threshold value Th1 and less than the second threshold value Th2. In this embodiment, when the device address setting signal Sa is equal to or greater than 0.1 times and less than 0.9 times the power supply voltage VDD, the device address setting signal Sa is deemed to be within the valid range.

[0048] If the device address setting signal Sa is within the valid range (Yes in step S104), the processing circuit 3 judges whether the address information of the control signal Sin includes the device address Ad of the semiconductor device 1 that includes itself (step S105). If the control signal Sin includes the device address Ad (Yes in step S105), the processing circuit 3 outputs a first drive signal Sd1 to the driver circuit 2 to execute an operation associated with the device address Ad (step S106). The first drive signal Sd is a signal that operates the driver circuit 2 so that the LED 91 is turned on in a drive state associated with the device address Ad of the control signal Sin. The content of the control signal Sin from the control device 5 may change. Therefore, the processing circuit 3 returns to step S103 and continues to receive the control signal Sin.

[0049] If the address information of the control signal Sin does not include the device address Ad of the semiconductor device 1 including the processing circuit 3 (No in step S105), the processing circuit 3 maintains the current state, returns to step S103, and continues processing. Note that if the address information of the control signal Sin does not include the device address Ad, the processing circuit 3 may continue to output the first drive signal Sd1 up to that point. Also, if the address information of the control signal Sin does not include the device address Ad, the processing circuit 3 may stop outputting the first drive signal Sd1 without maintaining the current state.

[0050] Furthermore, if the device address setting signal Sa is not within the valid range (No in step S104), the processing circuit 3 switches the switching signal Sw to Hi level to switch to autonomous operation, disables the processing circuit 3 itself, and switches the autonomous processing circuit 4 to an enabled state (step S107).

[0051] The autonomous processing circuit 4 then outputs the second drive signal Sd2 to the driver circuit 2 (step S108). Thereafter, the process returns to step S101 and resumes with the reception of the device address setting signal Sa. At this time, the processing circuit 3 is in an invalid state, but it simply does not output a valid first drive signal Sd1, and processing such as recognition of the device address Ad is possible. Therefore, even if the processing circuit 3 is in an invalid state, processing continues.

[0052] As described above, in the semiconductor module 100 including the semiconductor device 1, the semiconductor device 1 can recognize its own device address Ad and execute processing according to the device address Ad. With such a configuration, signal processing can be simplified compared to the case where control signals having individual information are transmitted to a plurality of semiconductor devices 1.

[0053] Furthermore, the configuration of the address signal output circuit 6 is simple, and it is possible to prevent the driver circuit 2 from being controlled with an incorrect output setting when the correct device address setting signal Sa is not output due to a malfunction of the address signal output circuit 6. At the same time, a predetermined second drive signal Sd2 is output from the autonomous processing circuit 4, so that the driver circuit 2 can be controlled with a determined output setting.

[0054] In the above-described process, the processing circuit 3 recognizes the device address Ad at the beginning of the process, but the present invention is not limited to this. As described above, the address signal output circuit 6 has a configuration that outputs a device address setting signal Sa to the semiconductor device 1 when the semiconductor module 100 starts up. Therefore, before the process is executed, the processing circuit 3 may be in a state where it recognizes the device address Ad of the semiconductor device 1 in which it is included.

[0055] In this embodiment, the processing circuit 3 is configured to always receive the device address setting signal Sa and recognize the device address Ad, but is not limited to this. For example, the device address Ad recognized when the semiconductor module 100 is started up, in other words, when the power is turned on, may be stored, and thereafter, the processing circuit 3 may use the stored device address Ad until the power of the semiconductor module 100 is turned off.

[0056] With this configuration, even if there is a problem with the address signal output circuit 6, the driver circuit 2 can be controlled to light up the LED 91. This improves user convenience.

[0057] <First Modification> Fig. 6 is a schematic circuit diagram of an address signal output circuit 7 of a first modified example. The address signal output circuit 7 shown in Fig. 6 differs from the address signal output circuit 6 in that it has a constant current circuit 71. Other than this, the address signal output circuit 7 has substantially the same configuration as the address signal output circuit 6. Therefore, the same reference numerals are used to designate the substantially same parts of the address signal output circuit 7 as those of the address signal output circuit 6, and detailed descriptions of the same parts will be omitted.

[0058] 6, in the address signal output circuit 7, a constant current circuit 71 is connected to a wiring W1 that connects a connection point P1 between the voltage dividing resistors R1 and R2 and the AD converter C1. One end of the constant current circuit 71 is connected to the wiring W1 that connects the connection point P1 and the AD converter C1, and the other end is connected to the ground GND. The constant current circuit 71 is connected so as to pull out a current from the wiring that connects the connection point P1 and the AD converter C1 to the ground, and the constant current circuit 71 constitutes a pull-down circuit. In the semiconductor device 1, the constant current circuit 71 may be incorporated inside the functional IC 10.

[0059] In this way, by providing the constant current circuit 71, when the wiring between the connection point P1 between the voltage dividing resistors R1 and R2 and the AD converter C1 is cut, the address voltage Vp input to the processing circuit 3 is lowered by the constant current circuit 71. In the address signal output circuit 7, the constant current circuit 71 is set so that the address voltage Vp is less than 0.1 times the power supply voltage VDD when the wiring W1 between the connection point P1 and the AD converter C1 is cut. This allows the processing circuit 3 to select autonomous operation by referring to the address table Tb1 shown in FIG. 4 when the wiring W1 between the connection point P1 and the AD converter C1 is cut.

[0060] For example, assume that the AD converter C1 is incorporated in the functional IC 10, and the voltage dividing resistors R1 and R2 are disposed outside the functional IC 10. In this state, the wiring W1 may be disconnected when the connection between the connection point P1 between the voltage dividing resistors R1 and R2 and the external terminal T1 of the functional IC 10 becomes open. As shown in Fig. 6, by incorporating a constant current circuit 71 in the functional IC 10 constituting the semiconductor device 1A, it is possible to reliably perform autonomous operation when the connection to the external terminal T1 becomes insufficient.

[0061] Fig. 7 is a schematic circuit diagram of another example of the address signal output circuit of the first modified example. As in the address signal output circuit 7A shown in Fig. 7, a constant current circuit 72 may be provided between the wiring W1 connecting the connection point P1 and the AD converter C1 and the power supply voltage VDD. By providing the constant current circuit 72 in this manner, a current is caused to flow into the wiring W1 connecting the connection point P1 and the AD converter C1, and the constant current circuit 72 constitutes a pull-up circuit. Note that in the semiconductor device 1, the constant current circuit 72 may be incorporated inside the functional IC 10.

[0062] In this way, by providing the constant current circuit 72, when the wiring between the connection point P1 between the voltage dividing resistors R1 and R2 and the AD converter C1 is cut, the address voltage Vp input to the processing circuit 3 is increased by the constant current circuit 72. In the address signal output circuit 7, the constant current circuit 72 is set so that the address voltage Vp becomes 0.9 times or more the power supply voltage VDD when the wiring between the connection point P1 and the AD converter C1 is cut. This makes it possible to cause the processing circuit 3 to select autonomous operation by referring to the address table Tb1 shown in FIG. 4 when the wiring between the connection point P1 and the AD converter C1 is cut.

[0063] As shown in FIG. 7, by incorporating a constant current circuit 72 in the functional IC 10 constituting the semiconductor device 1A, autonomous operation can be ensured when the connection to the external terminal T1 becomes insufficient.

[0064] By using the address signal output circuits 7 and 7A of the first modification, the processing circuit 3 can be made to select autonomous operation not only when either the voltage dividing resistor R1 or the voltage dividing resistor R2 is open or short-circuited, but also when the wiring is open. This makes it possible to operate in a manner that is convenient for the user.

[0065] <Second Modification> Fig. 8 is a schematic circuit diagram showing an address signal output circuit 8 of a second modified example. Fig. 9 is a schematic diagram of an address table Tb2 when the address signal output circuit 8 shown in Fig. 8 is used. The address signal output circuit 8 shown in Fig. 8 is different from the address signal output circuit 7A in that it has a constant current circuit 81 and has a resistor R3 instead of the voltage dividing resistors R1 and R2. Other than this, the address signal output circuit 8 has substantially the same configuration as the address signal output circuit 6. Therefore, the same reference numerals are used to designate substantially the same parts of the address signal output circuit 8 as those of the address signal output circuit 6, and detailed descriptions of the same parts will be omitted.

[0066] As shown in FIG. 8, the constant current circuit 81 is a pull-up circuit. In the address signal output circuit 8 connected to the semiconductor device 1B, the constant current circuit 81 may be incorporated inside the functional IC 10. A power supply voltage VDD is connected to the wiring W2 via the constant current circuit 81, and a current flows from the constant current circuit 81 to the wiring W2. The current flowing from the constant current circuit 81 to the wiring W2 flows to a resistor R3. If the current flowing from the constant current circuit 81 to the wiring W2 is a current I and the resistance value of the resistor R3 is a resistance value R, the address voltage Vq is given by the product of the current I and the resistance value R. Therefore, the address voltage Vq can be adjusted by adjusting the resistance value R.

[0067] The address signal output circuit 8 shown in FIG. 8 is configured so that the device address Ad can be determined by the value of a device address setting signal Sb obtained by digitally converting an address voltage Vq.

[0068] For example, in the address table Tb2 shown in Fig. 9, when the device address setting signal Sb is equal to or greater than S1 and less than S2, the device address Ad is "0." Similarly, when the device address setting signal Sb is equal to or greater than S2 and less than S3, the device address Ad is "1." Furthermore, when the device address setting signal Sb is equal to or greater than S3 and less than S4, the device address Ad is "2." When the device address setting signal Sb is equal to or greater than S4 and less than S5, the device address Ad is "3."

[0069] Furthermore, in the address signal output circuit 8, an abnormality in the wiring connected to resistor R3 may cause the connection with resistor R3 to become insufficient, i.e., the connection may become open. In this case, the address voltage Vq becomes approximately the power supply voltage VDD. Also, the resistance value of resistor R3 may become very small. In this case, the address voltage Vq becomes approximately 0. In this way, when an abnormality occurs in the address signal output circuit 8, the address voltage Vq becomes approximately 0 or approximately the power supply voltage VDD.

[0070] In preparation for the occurrence of such an abnormality, in the address table Tb2 shown in FIG. 9, an autonomous operation is associated with a device address setting signal Sb that is less than S1 or equal to or greater than S6.

[0071] FIG. 10 is a schematic circuit diagram of another example of the address signal output circuit 8A of the second modified example. FIG. 11 is a schematic diagram of an address table Tb3 when the address signal output circuit 8A shown in FIG. 10 is used. As in the address signal output circuit 8A shown in FIG. 10, a power supply voltage VDD is connected to the AD converter C1 via a resistor R4. A constant current circuit 82 is connected to a wiring W3 that connects the resistor R4 and the AD converter C1. The constant current circuit 82 is connected to the ground GND. The constant current circuit 82 is configured so that a current is drawn from the wiring W3 to the ground GND. The constant current circuit 82 constitutes a pull-down circuit. In the semiconductor device 1B, the constant current circuit 82 may be incorporated inside the functional IC 10.

[0072] 10, the current flowing through the wire W3 is extracted to the ground via the constant current circuit 82. Therefore, if the current flowing through the wire W3 is the current I and the resistance value of the resistor R4 is the resistance value R, the address voltage Vr is a voltage drop from the power supply voltage VDD given by the product of the current I and the resistance value R. Therefore, by adjusting the resistance value R, the address voltage Vr can be adjusted.

[0073] By using the address signal output circuit 8A shown in FIG. 10, the device address Ad can be determined by the value of the device address setting signal Sb obtained by digitally converting the address voltage Vr.

[0074] For example, in the address table Tb3 shown in FIG. 11, when the device address setting signal Sc is equal to or greater than VDD - U1 and less than VDD - U2, the device address Ad is "0". Similarly, when the device address setting signal Sc is equal to or greater than VDD - U2 and less than VDD - U3, the device address Ad is "1". Also, when the device address setting signal Sc is equal to or greater than VDD - U3 and less than VDD - U4, the device address Ad is "2". When the device address setting signal Sc is equal to or greater than VDD - U4 and less than VDD - U5, the device address Ad is "3".

[0075] Also, in the address signal output circuit 8, due to an abnormality in the wiring connected to the resistor R4 or the like, the connection to the resistor R3 may become insufficient, that is, an open state may occur. In this case, the address voltage Vr becomes approximately 0. Also, the resistance value of the resistor R4 may become extremely small. In this case, the address voltage Vr becomes approximately the power supply voltage VDD. Thus, when an abnormality occurs in the address signal output circuit 8A, the address voltage Vr becomes approximately 0 or approximately the power supply voltage VDD.

[0076] In preparation for such an abnormality, in the address table Tb3 shown in FIG. 11, autonomous operation is associated with the device address setting signal Sc that is less than VDD - U1 or greater than or equal to VDD - U5.

[0077] By using the address signal output circuits 8 and 8A of the second modification example, the circuit configuration can be simplified.

[0078] <Application to DC / DC Converter> Fig. 12 is a schematic circuit diagram of a DC / DC converter 200. A semiconductor module 100C shown in Fig. 12 differs from the driver circuit 2 in that a driver circuit 2C drives an output stage 201 of a DC / DC converter. The semiconductor module 100C is substantially the same as the semiconductor module 100 in other respects, and the substantially same parts are denoted by the same reference numerals and detailed description of the same parts is omitted. In the DC / DC converter 200 shown in Fig. 12, a schematic circuit diagram of only one output stage 201 is shown, and the remaining output stages 201 are shown as blocks.

[0079] The DC / DC converter 200 shown in Fig. 12 includes a semiconductor module 100C. An output stage 201 of the DC / DC converter 200 is connected to each driver circuit 2C of the semiconductor module 100C. The output stage 201 of the DC / DC converter 200 is a circuit constituting a part of a step-down DC / DC converter that steps down and outputs an input voltage Vin, but is not limited to this and may be a step-up type that steps up and outputs the input voltage Vin. As shown in Fig. 12, the output stage 201 includes a high-side switching element Q1 and a low-side switching element Q2 connected in series.

[0080] An input voltage Vin is supplied to one end of the high-side switching element Q1. The high-side switching element Q1 and the low-side switching element are connected at a connection point O1, which is connected to a smoothing circuit consisting of an inductor L1 and a capacitor Cp. The switch voltage generated at the connection point O1 is rectified and smoothed by the smoothing circuit and output as an output voltage. The low-side switching element Q2 is connected to the ground GND.

[0081] In the DC / DC converter 200, a high-side drive signal HG is supplied to the high-side switching element Q1, and a low-side drive signal LG is supplied to the low-side switching element Q2 by the driver circuit 2C. This causes the high-side switching element Q1 and the low-side switching element Q2 to be controlled to be ON / OFF complementarily. Note that "complementary" refers to a state in which the high-side switching element Q1 and the low-side switching element Q2 alternate between ON / OFF. To explain further, this does not only include a case in which they are completely switched, but also includes, for example, a dead time in which the high-side switching element Q1 and the low-side switching element Q2 are both OFF.

[0082] Each driver circuit 2C outputs a high-side drive signal HG and a low-side drive signal LG so as to obtain an output instructed by the drive information of the first drive signal Sd1 from the processing circuit 3. This adjusts the switching voltage. As described above, when the autonomous operation starts, the second drive signal Sd2 is received from the autonomous processing circuit 4 and a high-side drive signal HG and a low-side drive signal LG are output. This allows an output voltage of a determined voltage to be output even if it cannot be specified by the control signal Sin. The DC / DC converter 200 is configured to use a semiconductor module 100 having an address signal output circuit 6, but is not limited to this, and may be configured to use a semiconductor module having any of the address signal output circuits 7, 7A, 8, and 8A.

[0083] <Application to vehicles> 13 is a diagram showing the external appearance of the vehicle 300. The vehicle 300 of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0084] Vehicle 300 includes not only engine vehicles but also electric vehicles (battery electric vehicles [BEVs], hybrid electric vehicles [HEVs], plug-in hybrid electric vehicles / plug-in hybrid vehicles [PHEVs / PHVs], or xEVs such as fuel cell electric vehicles / fuel cell vehicles [FCEVs / FCVs]).

[0085] The semiconductor module 100 described above can be incorporated into a power supply device that supplies power to electronic devices mounted on the vehicle 300. It can also be incorporated into the electronic devices themselves. By incorporating the semiconductor module 100 into a power supply device that supplies power to electronic devices, for example, like the tail lamps of the vehicle 300, the driver circuit 2 is controlled by the second drive signal Sd2 from the autonomous processing circuit 4, so that the tail lamps can be kept on even when they cannot be controlled by the control signal Sin. This can improve user convenience.

[0086] <Other> The above-described embodiments should be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0087] <Additional Notes> The semiconductor device (1, 1A, 1B) described above is a semiconductor device that controls a driver circuit (2, 2C) that drives an electronic device, and includes a processing circuit (3) having a configuration capable of controlling the driver circuit (2, 2C) in response to an external device address setting signal (Sa, Sb, Sc) and an external control signal (Sin), and an autonomous processing circuit (4) that is provided independently of the processing circuit (3) and has a configuration capable of controlling the driver circuit (2, 2C) under preset conditions, and is configured (first configuration) such that when the device address setting signal (Sa, Sb, Sc) falls within the predetermined conditions, the processing circuit (3) is enabled and the autonomous processing circuit (4) is disabled, and when the device address setting signal (Sa, Sb, Sc) does not fall within the predetermined conditions, the autonomous processing circuit (4) is enabled and the processing circuit (2) is disabled.

[0088] In the semiconductor device (1, 1A, 1B) of the first configuration described above, the processing circuit (2) is configured (second configuration) to be enabled when the device address setting signal (Sa, Sb, Sc) is equal to or greater than a first threshold value (Th1).

[0089] In the semiconductor device (1, 1A, 1B) of the first or second configuration, the processing circuit (2) is configured (third configuration) to be enabled when the device address setting signal (Sa, Sb, Sc) is less than a second threshold (Th2).

[0090] In the semiconductor device (1, 1A, 1B) having any of the first to third configurations described above, the autonomous processing circuit (4) is configured to control the driver circuit (2, 2C) to drive the electronic device (201) with predetermined settings (fourth configuration).

[0091] In the semiconductor device (1, 1A, 1B) having any of the first to fourth configurations, the autonomous processing circuit (4) is configured to be connectable to a memory (42), and the autonomous processing circuit (4) is configured to control the driver circuit (2) under setting conditions set in the external memory (41) (fifth configuration).

[0092] In the semiconductor device (1, 1A, 1B) having any one of the first to fifth configurations, the autonomous processing circuit (4) is configured to control the driver circuit (2, 2C) to stop (sixth configuration).

[0093] The semiconductor device (1, 1A, 1B) of any one of the first to sixth configurations described above further has a setting circuit including at least one of a resistor and a capacitor, and the autonomous processing circuit (4) is configured to control the driver circuit (2, 2C) based on an input from the setting circuit (seventh configuration).

[0094] In the semiconductor device (1, 1A, 1B) of any of the first to seventh configurations described above, the device address setting signal (Sa, Sb) is a voltage signal obtained by dividing a reference voltage (VDD) by voltage dividing resistors (R1, R2) (eighth configuration).

[0095] In the semiconductor device (1C) of any of the first to seventh configurations, the device address setting signal (Sc) is a voltage signal provided by a current flowing through a constant current circuit (81, 82) and resistors (R3, R4) (ninth configuration).

[0096] The semiconductor module (100, 100C) has a configuration (tenth configuration) including a plurality of semiconductor devices (1, 1A, 1B) having any one of the first to ninth configurations, a driver circuit (2) having any one of the first to ninth configurations, and a control device (5) that transmits a control signal (Sin) to each of the semiconductor devices (1, 1A, 1B).

[0097] The semiconductor module (100, 100C) of the tenth configuration has a configuration (eleventh configuration) formed in one package.

[0098] The LED driving device has a configuration (12th configuration) including a semiconductor module (100) of the 10th or 11th configuration described above, and an LED (9) driven by a driver circuit (2) of the semiconductor module (100).

[0099] The DC / DC converter (200) has a configuration (13th configuration) including the semiconductor module (100C) described in the 10th or 11th configuration above, and switching elements (Q1, Q2) driven by a driver circuit (2C) of the semiconductor module (100C).

[0100] The electric vehicle (300) has a configuration (fourteenth configuration) including the semiconductor module (100) of the tenth or eleventh configuration. [Explanation of symbols]

[0101] 1, 1A, 1B Semiconductor Device 2. 2C driver circuit 3 Processing circuit 4 Autonomous Processing Circuit 41 Memory 42 Setting circuit 5. Control device 6, 7, 7A, 8, 8A Address signal output circuit 71, 72, 81, 82 constant current circuit 90 LED driver 9 Electronic equipment 91 LED 100, 100C Semiconductor Module 200 DC / DC Converter 201 Output stage 300 vehicles C1 A / D Converter Cp Capacitor L1 Inductor

Claims

1. A semiconductor device for controlling a driver circuit that drives an electronic device, a processing circuit configured to control the driver circuit in response to an external device address setting signal and an external control signal; an autonomous processing circuit that is provided independently of the processing circuit and has a configuration capable of controlling the driver circuit under preset conditions; A semiconductor device configured such that, when the device address setting signal falls within a predetermined condition, the processing circuit is enabled and the autonomous processing circuit is disabled, and, when the device address setting signal does not fall within the predetermined condition, the autonomous processing circuit is enabled and the processing circuit is disabled.

2. 2 . The semiconductor device according to claim 1 , wherein the processing circuit is configured to be valid when the device address setting signal is equal to or greater than a first threshold value.

3. The semiconductor device according to claim 1 , wherein the processing circuit is configured to be valid when the device address setting signal is less than a second threshold value.

4. 2. The semiconductor device according to claim 1, wherein the autonomous processing circuit has a configuration for controlling the driver circuit so as to drive the electronic device with a predetermined setting.

5. 2. The semiconductor device according to claim 1, wherein the autonomous processing circuit is configured to be connectable to a memory, and the autonomous processing circuit is configured to control the driver circuit under conditions set in the memory.

6. The semiconductor device according to claim 1 , wherein the autonomous processing circuit has a configuration for controlling the driver circuit to stop.

7. Further comprising a setting circuit including at least one of a resistor and a capacitor; 2. The semiconductor device according to claim 1, wherein the autonomous processing circuit controls the driver circuit based on an input from the setting circuit.

8. 2. The semiconductor device according to claim 1, wherein the device address setting signal is a voltage signal obtained by dividing a reference voltage by a voltage dividing resistor.

9. 2. The semiconductor device according to claim 1, wherein the device address setting signal is a voltage signal provided by a current flowing through a constant current circuit and a resistor.

10. A plurality of the semiconductor devices according to any one of claims 1 to 9; The driver circuit according to any one of claims 1 to 9; a control device that transmits the control signals to each of the semiconductor devices.

11. The semiconductor module according to claim 10 , wherein the semiconductor module is formed in one package.

12. The semiconductor module according to claim 10; an LED driven by the driver circuit of the semiconductor module;

13. The semiconductor module according to claim 10; a switching element driven by the driver circuit of the semiconductor module.

14. A vehicle having a configuration comprising the semiconductor module according to claim 10.

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