Integrated circuit security using programmable switches

Abstract

To provide a security mechanism for providing a security mechanism for computer chips using programmable switches.SOLUTION: In the security mechanism, a user sets each of programmable switches included in a computer chip, receives a security key, identifies programmable switches (PSs) that must be "open" to cause the computer chip to function, and identifies PSs that must be "closed" to cause the computer chip to function; in response to identifying a set of PSs that must be "open" to cause the computer chip to function, the user applies reset pulses to each of the PSs, and disconnects using electronic fuses; if all of the PSs are set to "open" or "closed" according to the security key, and the electronic fuses are opened for all of the PSs, then power is removed from the computer chip.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates generally to the field of integrated circuits (i.e., computer chips, or simply chips), and more particularly to providing a security mechanism for computer chips using programmable switches. [Background technology]

[0002] Computer chips have revolutionized the world. These chips are used in many consumer products, from indoor robot vacuums to outdoor robot lawnmowers. Improvements in how chips are manufactured have led to the evolution from the first handheld calculators, capable of performing only basic mathematical functions, to today's modern smartphones, which can be held and operated in one hand. Sales of computer chips are expected to exceed $400 billion worldwide this year. With such a lucrative market, companies need a way to protect their chip designs from being copied by competitors. Summary of the Invention [Means for solving the problem]

[0003] One embodiment of the present invention includes a method for providing a security mechanism for a computer chip using programmable switches. In one embodiment, a security key associated with a plurality of programmable switches included in an integrated circuit is received. The plurality of programmable switches is configured to render the plurality of programmable switches conductive. A reset pulse is applied to a first set of programmable switches included in the plurality of programmable switches based on the received security key.

[0004] According to one aspect, a method is provided, the method including receiving, by one or more computer processors, a security key associated with a plurality of programmable switches comprised in an integrated circuit; configuring, by the one or more computer processors, the plurality of programmable switches to render the plurality of programmable switches conductive; and applying, by the one or more computer processors, a reset pulse to a first set of programmable switches included in the plurality of programmable switches based on the received security key.

[0005] According to another aspect, a programmable switch is provided comprising a first electrode and a second electrode, where the first electrode and the second electrode are separated by a phase change material at a first surface; a first heater on a first side of the phase change material; and a second heater on a second side of the phase change material, where the first heater and the second heater face each other and are separated by the phase change material at a second surface perpendicular to the first surface.

[0006] According to another aspect, a method is provided that includes forming a plurality of non-volatile logic devices in alignment with vias and wires during a back end-of-line manufacturing process of a functional integrated circuit, where each non-volatile logic device in the plurality of non-volatile logic devices has two electrodes separated by a phase change material and two heaters disposed on two opposite sides of the phase change material; forming a locking circuit electrically connected to the two heaters of the plurality of non-volatile logic devices, where the locking circuit is electrically isolated from back end-of-line wiring of the functional integrated circuit; and changing a state of the phase change material by passing a current through each of the two heaters.

[0007] Preferred embodiments of the invention will now be described, by way of example only, with reference to the following drawings, in which: [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 illustrates a cross section of a computer chip showing possible locations of programmable switches (PS) according to one embodiment of the present invention. [Diagram 2] FIG. 2 illustrates the three-dimensional (3D) structure of PS, according to one embodiment of the present invention. [Diagram 3] FIG. 3 illustrates a top view of the PS, associated circuitry, and chip circuitry according to one embodiment of the present invention. [Figure 4] FIG. 4 illustrates a top view of the PS and the current flow in various circuits according to one embodiment of the present invention. [Figure 5A] FIG. 5A illustrates a top view of a PS, current flow in various circuits, and the formation of amorphous regions, according to one embodiment of the present invention. [Figure 5B] FIG. 5B illustrates a top view of a PS, current flow in various circuits, and the formation of multiple amorphous regions, according to one embodiment of the present invention. [Figure 6] FIG. 6 illustrates FIG. 5A and associated logic tables according to one embodiment of the present invention. [Figure 7A] FIG. 7A illustrates a simplified process flow diagram for producing PS according to one embodiment of the present invention. [Figure 7B] FIG. 7B illustrates a simplified process flow diagram for producing PS according to one embodiment of the present invention. [Figure 7C] FIG. 7C illustrates a simplified process flow diagram for producing PS according to one embodiment of the present invention. [Figure 7D] FIG. 7D illustrates a simplified process flow diagram for producing PS according to one embodiment of the present invention. [Figure 8]FIG. 8 illustrates a flow chart diagram for providing a security mechanism for a computer chip using PS according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment of the present invention recognizes that many companies around the world manufacture computer chips. In some cases, a company manufactures its own chips, and in other cases, a first company may subcontract a second company to manufacture or electrically test those chips. Today, the intellectual property contained in the chips can be protected by using a logic lock method. Herein, additional logic circuits are inserted between the existing functional logic circuits. The inputs to these additional logic circuits are treated as keys, and without the keys, the chip will not function as intended. The logic lock method has several drawbacks: (i) valuable chip real estate is taken up by the additional logic circuits; (ii) the additional logic circuits consume power; and (iii) the additional logic circuits can introduce delays into the operation of the functional logic circuits. A protection method is needed that can protect the chips and overcome these drawbacks.

[0010] In accordance with an embodiment of the present invention, it is recognized that there is an approach to provide a security mechanism for a computer chip using programmable switches (PS). In one embodiment, any number of PSs are inserted into the standard functional logic of a chip. The PSs are composed of a phase change material (PCM). In a crystalline state, the PCM has high electrical conductivity and the PS is considered "closed". In an amorphous state, the PCM has high resistance (i.e., low conductance) and the PS is considered "open". The state of the PCM can be controlled by proximity heaters that are fabricated as part of the PS. By requiring that a certain number of PSs should be "closed" and that a certain number of PSs should be "open" for the chip to function properly, a security key can be designed into the chip that does not require extra real estate, does not require constant power, and does not affect the performance of the chip. The use of this security key enhances the technology of integrated circuits (ie, computer chips) by providing a simple protection mechanism to prevent intellectual property theft.

[0011] References herein to "one embodiment," "an embodiment," "exemplary embodiment," or the like are intended to indicate that the described embodiment may include a particular feature, structure, or characteristic, but that not all embodiments may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not expressly described.

[0012] For purposes of the following description, the terms "upper", "right", "left", "vertical", "horizontal", "top", "bottom", "on", "under" and derivatives thereof shall refer to the disclosed structures and methods oriented in the drawings. The terms "overlapping", "top", "located on" or "located on" mean that a first element, e.g., a first structure, is above a second element, e.g., a second structure, and that an intervening element, e.g., an interfacial structure, may be between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected at the interface of the two elements without an intermediate conductive, insulating or semiconducting layer.

[0013] As referred to herein, certain elements referred to in the singular can also be considered to be in the plural. In the examples below, the word "X" refers to both a single "X" and more than one "X", such as "programmable switch", "PS" and "via".

[0014] The present invention will be described in detail below with reference to the accompanying drawings.

[0015] 1 is an exemplary cross-section of a complementary metal-oxide semiconductor (CMOS) computer chip, generally designated 100, in accordance with one embodiment of the present invention. FIG. 1 is merely illustrative of one implementation and does not imply any limitations with respect to different implementations that may be implemented. Many modifications to the illustrated implementation may be made by one skilled in the art without departing from the scope of the present invention as set forth in the claims.

[0016] Typically, a CMOS chip is fabricated in two parts: front-end-of-line (FEOL) and back-end-of-line (BEOL). Typically, in FEOL processing, each device (e.g., transistor, capacitor, resistor, etc.) is patterned on a silicon base. BEOL processing includes the formation of metal interconnect layers of the chip. BEOL includes contacts, insulating layers, metal levels, and bonding sites for chip-to-package connections. The PS of the preferred embodiment of the present invention is fabricated in BEOL.

[0017] In one embodiment, cross section 100 includes M3 metal 102 (where M3 refers to layer 4 of the chip), dielectric 104, M3 / M2 via 106, dielectric 108, programmable switch (PS) 110, M2 metal 112, M2 / M1 via 114, dielectric 116, dielectric 118, M1 metal 120, M1 / FET via 122 (where FET is a field effect transistor), FET gate 124, FET source 126A, FET drain 126B, and silicon 128. The combination of FET source 126A, FET gate 124, and FET drain 126B comprise a FET. In one embodiment, the balance of the structures that comprise cross section 100, other than PS 110, are included in currently manufactured computer chips.

[0018] In one embodiment, the FET gate 124 is disposed on a base layer made of silicon 128. The FET source 126A and the FET drain 126B are doped regions in the silicon 128 and are adjacent to the FET gate 124. A dielectric 118 is deposited over the silicon and the FET. A hole (i.e., a via) is formed in the dielectric 118 and filled with tungsten or other suitable material to form the M1 / FET via 122 (i.e., the interconnect between the M1 metal 120 and one of the FET source 126A and the FET drain 126B). Chemical mechanical planarization (CMP) is used to remove the excess of the M1 / FET via 122 on the dielectric 118. A dielectric 116 is deposited over the device and patterned to form trenches into which the M1 metal 120 is deposited to form the overall first layer circuitry. CMP is then used to remove the excess of the M1 metal 120 on the dielectric 116. This process is repeated for the remaining metal layers of the structure. A discussion of how PS 110 is fabricated is provided later in this specification in the discussion of Figures 7A-7D.

[0019] M3 metal 102, M2 metal 112, M1 metal 120 are typically composed of one of copper and aluminum. M3 / M2 via 106, M2 / M1 via 114, and M1 / FET via 122 are holes in dielectric 108, dielectric 116, and dielectric 118, respectively, that are filled with tungsten to provide electrical connections between layers. Dielectric 108, dielectric 116, and dielectric 118 are materials that provide electrical insulation between parts of the structure. Silicon dioxide (SiO2) or any material with a low dielectric constant is commonly used as a dielectric material in chip fabrication. FET source 126A, FET gate 124, and FET drain 126B are the three terminals that make up a FET device, which is a transistor that uses an electric field to control the flow of current in a channel connecting FET source 126A and FET drain 126B. FETs are commonly constructed with silicon-based channels, although other materials, such as silicon-germanium alloys and III-V semiconductors, can be used.

[0020] FIG. 2 illustrates a 3D structure of a PS, generally designated 200, according to one embodiment of the present invention. FIG. 2 is merely an illustration of one implementation and does not imply any limitations with respect to different implementations that may be implemented. Many modifications to the illustrated implementation may be made by one skilled in the art without departing from the scope of the present invention as set forth in the claims.

[0021] In one embodiment, the PS 200 comprises a phase change material (PCM) 202, a heater 204, a heater 205, a spacer sidewall 206, and a hard mask 208. The PCM 202 can be in one or two of the following states: crystalline and amorphous. In the crystalline state, the PCM 202 is conductive. In the amorphous state, the PCM 202 is non-conductive. Examples of PCM 202 include, but are not limited to, germanium antimony telluride (Ge2Sb2Te5), germanium telluride (GeTe), antimony telluride (Sb2Te3), GaSb (gallium antimony), and the like. In this embodiment, germanium telluride is used for the PCM 202. The heaters 204 and 205 are resistive heaters (i.e., devices that generate heat when an electric current flows through them). For example, the heater 204 and the heater 205 can be made of tantalum nitride (TaN). The heater 204 and the heater 205 face each other on opposite sides of the PCM 202 as shown in FIG. 2. Generally, the surface comprising the heater 204 and the heater 205 is perpendicular to the main surface of the PCM 202. The heater 204 and the heater 205 are electrically insulated from the PCM 202 and thermally coupled to the PCM 202 by the spacer sidewall 206. Thus, the spacer sidewall 206 is both an electrical insulator and a thermal conductor. Examples of the spacer sidewall 206 include, but are not limited to, aluminum nitride (AlN) and hexagonal boron nitride (hex-BN). In this embodiment, aluminum nitride is used for the spacer sidewall 206. A hard mask 208 is used to define (i.e., etch) the PCM 202 during the manufacturing process. The hard mask 208 also serves as a "stop layer" during a chemical mechanical planarization (CMP) process, which is performed so that the tops of the heater 204, heater 205, spacer sidewalls 206, and hard mask 208 are all approximately at the same level (i.e., on the same plane).

[0022] 3 illustrates a top view of a PS, generally designated 300, according to one embodiment of the present invention. FIG. 3 is merely illustrative of one implementation and does not imply any limitations with respect to different implementations that may be implemented. Many modifications to the illustrated implementation may be made by one skilled in the art without departing from the scope of the present invention as set forth in the claims.

[0023] In one embodiment, the PS 300 includes the PCM 202, heater 204, heater 205, and spacer sidewall 206 described above. The PS 300 also includes the following new features: PS input 302A, PS output 302B (which are two electrodes separated by the PCM 202), heater 204 input 304A, heater 204 output 304B, heater 205 input 305A, and heater 205 output 305B. The PS input 302A, PS output 302B, heater 204 input 304A, heater 204 output 304B, heater 205 input 305A, and heater 205 output 305B are wiring (i.e., electrode) inputs that carry current. Note that the input and output currents have no inherent directionality. However, in this embodiment, current flows into the heater 204 along the heater 204 input 304A and flows out of the heater 204 along the heater 204 output 304B. Similarly, in one embodiment, current flows into the heater 205 along the heater 205 input 305A and flows out of the heater 205 along the heater 205 output 305B. The conductivity of the PS 202 (i.e., opening or closing the switch), i.e., controlling the current through the PS 202, controls how the heater 204 and heater 205 are heated or cooled or heated and cooled. The PS input 302A and the PS output 302B are part of the functional logic of the chip. The heater 204 input 304A, the heater 204 output 304B, the heater 205 input 305A, and the heater 205 output 305B are circuits dedicated to the heater 204 and heater 205, and these circuits are separate from the functional logic of the device. The PS input 302A and the PS output 302B can be any of the M1 metal 120, M2 metal 112, M3 metal 102, M1 / FET via 122, M2 / M1 via 114, and M3 / M2 via 106 of FIG.

[0024] 4 illustrates a PS, generally designated 400, and illustrates a top view of the PS 300 of FIG. 3 showing the current flow of the PS and the current flow of the functional logic circuitry that comprises the PS 300, according to one embodiment of the present invention. FIG. 4 is merely illustrative of one implementation and does not imply any limitations with respect to different implementations that may be implemented. Many modifications to the illustrated implementation may be made by one skilled in the art without departing from the scope of the present invention as set forth in the claims.

[0025] In one embodiment, current is delivered to the PS 300 along PS input 302A, as shown by current flow 402A, the current flows through the PCM 202 (i.e., a portion of the PS 300), and the current flows out of the PCM 202 along PS output 302B (as shown by current flow 402B). Current flow 402A and current flow 402B are part of the operating current of the computer chip. Here, when the PS 300 is "closed," current can pass through the programmable switch, as shown by current flow 402A and current flow 402B. When the PS 300 is "open," no current flows through either current flow 402A or current flow 402B. As shown by current flow 404A, current is delivered along heater 204 input 304A to heater 204 (so that heater 204 provides heat to PCM 202), and current out of heater 204 flows along heater 204 output 304B (as shown by current flow 404B). As shown by current flow 405A, current is delivered along heater 205 input 305A to heater 205 (so that heater 205 provides heat to PCM 202), and current out of heater 205 flows along heater 205 output 305B (as shown by current flow 405B).

[0026] In one embodiment, when PCM 202 is initially in a crystalline state and current flow 404A and current flow 405A are reset pulses, the crystalline regions in PCM 202 change state and become amorphous. The reset pulse is a current flow (i.e., pulse) that raises the temperature of the PCM above its melting point followed by a quenching (i.e., rapid decrease in current resulting in rapid cooling) of the PCM. The rapid cooling does not allow the PCM enough time to crystallize, resulting in amorphous regions. This process is also known as "melt-quench." When PCM 202 is initially in an amorphous state and current flow 404A and current flow 405A are set pulses, the amorphous regions in PCM 202 change state and become crystalline. The set pulse is a current flow that raises the temperature of the PCM above its crystallization temperature followed by a slow decrease in the temperature of the PCM. This setting process changes the PCM from an amorphous state to a crystalline state. As one example, for Ge2Sb2Te5 (germanium antimony telluride alloy), the crystallization temperature is about 160° C. and the melting point is about 600° C. As another example, the melting points of antimony telluride (Sb2Te3) and germanium telluride (GeTe) are about 620° C. and 725° C., respectively.

[0027] FIG. 5A illustrates a PS generally designated 500, illustrating the PS 300 of FIG. 3, associated circuitry, and current flow of FIG. 4, and the amorphous regions of the PCM, according to one embodiment of the present invention. FIG. 5A is merely illustrative of one implementation and does not imply any limitations with respect to different implementations that may be implemented. Many modifications to the illustrated implementation may be made by one skilled in the art without departing from the scope of the present invention as set forth in the claims.

[0028] In one embodiment, when a current flow 404A (reset current pulse) flows through the heater 204 (i.e., current flows in along the heater 204 input 304A and out along the heater 204 output 304B), the heater 204 emits a heat pulse, which initiates the formation of the PCM 202 to form an amorphous region 502 adjacent to the heater 204. Thus, when the heater 204 heats up (caused by the current flow 404A), an amorphous region 502 adjacent to the heater 204 is formed in the PCM 202. Because the amorphous region 502 in the PCM 202 does not extend across the entire width of the PCM 202, the current flow 402A can still flow through the PCM 202 (i.e., a portion of the PCM 202 remains crystalline and therefore highly conductive and the PS remains "closed").

[0029] FIG 5B illustrates the PS 500 of FIG 5A and a PS generally designated 550 illustrating a second amorphous region according to one embodiment of the present invention. FIG 5B is merely illustrative of one implementation and does not imply any limitations with respect to different implementations that may be implemented. Many modifications to the illustrated embodiment may be made by one skilled in the art without departing from the scope of the present invention as set forth in the claims.

[0030] In one embodiment, the amorphous region 502 is formed as described above. Similarly, current flow 405A (which is also a reset current pulse) flows through the heater 205 (i.e., current flows in along the heater 205 input 305A and out along the heater 205 output 305B), providing a heat pulse to the heater 205, resulting in the formation of an amorphous region 552 in the PCM 202. Now, because the amorphous region 502 and the amorphous region 552 have coalesced, a current path through the crystalline portion of the PCM 202 is unavailable and the PS is now "open".

[0031] Thus, by utilizing set and reset pulses with appropriate programmable switches, each PS can be individually "closed" or "opened" according to a security key. If the security key is followed, the chip functions fully. If the security key is not followed correctly, the chip will not function.

[0032] 6 illustrates a PS, generally designated 600, which is PS 400 of FIG. 4 with a single amorphous region 552. PS 600 will be used in the discussion of how the PS can function as a logic device that implements a NAND truth table 602 contained in FIG.

[0033] In one embodiment, the initial state of PCM 202 is crystalline and therefore conductive. When no current flows through heater 204 and heater 205 (i.e., current flow 404A and current flow 405A are both zero), PCM 202 remains fully crystalline and PS 600 remains conductive. This is shown in NAND truth table 602 where "input" 404A and "input" 405A are both "0" and "output" 402B is "1" (i.e., PS 600 is conductive). When current flow 404A is zero and current flow 405A is a reset pulse, a single amorphous region is formed in PCM 202. This is shown in NAND truth table 602 where "input" 404A is "0" (i.e., no current) and "input" 405A is "1" (i.e., reset pure). In this situation, amorphous region 552 is formed adjacent to heater 205. If the pulses were reversed (i.e., "INPUT" 404A is "1" and "INPUT" 405A is "0"), amorphous region 552 would not be formed and would be replaced by amorphous region PCM 202 (not shown in FIG. 6 but shown in FIG. 5A) adjacent heater 204. In either case, PS 600 would remain conductive as shown in NAND truth table 602 (i.e., one of "INPUT" 404A and "INPUT" 405A is "0" and the other is "1", resulting in "OUTPUT" 402B being "1" indicating the PS is closed). Finally, when both current flow 404A and current flow 405A are reset pulses, an amorphous region 552 is formed adjacent to heater 205 and another amorphous region is formed adjacent to heater 204 (not shown in FIG. 6 but shown in FIG. 5B). As the two amorphous regions merge, PS 600 becomes non-conductive and the PS is open. This is shown in NAND truth table 602 as both "INPUT" 404A and "INPUT" 405A are "1" and the corresponding "OUTPUT" 402B is "0".

[0034] 7A-7D illustrate simplified diagrams of the formation of a PS. In FIG. 7A, the phase change material (i.e., PCM 202) is deposited into gaps formed in an existing metal layer (i.e., M2 metal 112). The excess of PCM 202 can be removed using photolithography and reactive ion etching (RIE), leaving only PCM 202. An insulating material that is both a good thermal conductor and a poor electrical conductor is blanket deposited, and spacer sidewalls 206 are formed from the insulating material using a reactive ion etching process. Note that the hard mask 208 used to define PCM 202 remains on top of PCM 202.

[0035] In Figure 7B, dielectric 702 (corresponding to dielectric 116 in Figure 1) is a material that is deposited over the PS structure. The top surface of dielectric 702 is planarized using a chemical mechanical planarization (CMP) process that results in the top of dielectric 702 and the top of hard mask 208 being flush.

[0036] 7C, trenches in the dielectric 702 are created on either side of the PCM 202 by an etching process that simply removes portions of the dielectric 702 adjacent the spacer sidewalls 206.

[0037] In Figure 7D, heater 204 and heater 205 are formed by filling the previously created trenches with a resistive material, such as tantalum nitride (TaN). The entire structure is planarized again using a CMP process, resulting in the top surfaces of all of the structure's features being the same plane.

[0038] 8 is a flow chart diagram of a workflow 800 illustrating a methodology for a user to "unlock" a computer chip that is protected by any number of programmable switches. In one embodiment, the workflow 800 is performed by a user who has access to an appropriate security key.

[0039] According to one embodiment, in step 802, the user "configures" the device. In other words, the user configures each of a number of programmable switches (PS) contained in a computer chip (i.e., an integrated circuit). In one embodiment, the actual programming of each PS on the chip (there can be many programmable switches) is typically performed by another circuit on the chip. In some embodiments, the circuit may comprise a state machine or microcontroller that receives a security key from the user as described below and configures the device via one or more computer processors. In one embodiment, the user configures each PS by using a set pulse for each PS that causes the phase change material (PCM) in the PS to crystallize and form a conductive structure. In another embodiment, the user heats the entire chip to a temperature above the crystallization temperature of the PCM and then cools the chip to ambient room temperature. This process sets all PSs to be conductive. After the device (i.e., computer chip) is configured, all of the PSs are conductive, but the chip is non-functional. Furthermore, a programmable switch that is "set" is considered "closed" because it is conductive and allows current to flow (similar to a light switch that turns on a light when "closed" (i.e., placed in the "on" position) and turns off a light when "open" (i.e., placed in the "off" position). For example, in a chip with 300 PS, all 300 are "set" to be closed.

[0040] In one embodiment, the user receives a security key in step 804. In other words, the user receives or obtains a security key associated with a computer chip. According to one embodiment, the security key defines which PS should be "open" and which PS should be "closed" for the chip to function properly. The security key is provided by a chip designer, which may be a chip manufacturer. In this example, the security key states that a first set of 300 PS should remain "closed" while a second set of 300 PS should be "open" (i.e., made non-conductive) for the device to function.

[0041] According to one embodiment, in step 806, the user identifies the programmable switches that must be "open" for the device to function. In other words, the user identifies from the security key a list of PSs that must be reset to be non-conductive by changing the state of the PCM from crystalline to amorphous. The identification can be done by the user entering the security key, and the microcontroller identifies the various PSs and further programs the PSs when necessary. In an example, out of 300 programmable switches (i.e., "1" to "300"), the PSs associated with odd numbers need to be "open" (i.e., PS numbers "1", "3", "5", ..., "297" and "299").

[0042] In one embodiment, in step 808, the user identifies the programmable switches that must be "closed" for the device to function. In other words, the user identifies from the security key a list of PSs that must be set to conductive by changing the state of the PCM from amorphous to crystalline. Here, no action by the user is required with respect to this list of PSs that must be "set" since the device was "set" in a previous step. In a situation where the initial state of each PS is unknown and the user did not perform the "set" step of the device, it would be important to know which PSs should be "set" (i.e., closed). In an example, of the 300 programmable switches (i.e., "1" through "300"), the PSs associated with the even numbers need to be "closed" (i.e., PS numbers "2", "4", "6", ..., "298" and "300"). In general, the positions of the programmable switches would be completely random, rather than "odd" and "even" as used in this example.

[0043] According to one embodiment, in step 810, a reset pulse is applied to the appropriate programmable switches. In other words, in response to identifying the set of PSs that must be "open" for the device to function, the user applies a reset pulse to each of the PSs. In one embodiment, the reset pulse changes the state of the PCM from crystalline (and conductive) to amorphous (and non-conductive). Once complete, each of the PSs is "open." In an example, a reset pulse is applied to each of the odd-numbered PSs.

[0044] In one embodiment, in step 812, the pin associated with each PS is disconnected using an electronic fuse. In other words, each PS is electrically isolated from its associated input pin. According to one embodiment, the user provides an input current exceeding a threshold that "overloads" an electronic fuse embedded in the wiring (i.e., circuit) associated with each PS, thus creating an electrical open in the wiring. As a result of disconnecting the pin from the associated PS, the respective PS can no longer be "set" or "reset" (i.e., "closed" or "opened"). The device is set to function forever (assuming the PS is "opened" or "closed" according to the security key). According to another embodiment, the use of an electronic fuse is optional (i.e., it is not necessary to include an electronic fuse in the wiring associated with a PS), and not including the electronic fuse does not affect the operation of the programmable switch. In an example, the user overloads each of the electronic fuses associated with each of the 300 PSs by inputting a current exceeding a threshold.

[0045] According to one embodiment, power is removed from all of the programmable switches in step 814. In other words, once all of the PS have been set to "open" or "closed" according to the security key and the electronic fuses are open for all of the PS (if so equipped), power is removed from the device since the PS do not require constant power to function (i.e., the PS will remain in that state until a set pulse is applied for a sufficiently amorphous PCM, or a reset pulse is applied for a sufficiently crystalline PCM).

[0046] The use of phase change material to implement the programmable switch provides several advantages. First, the PS can be opened and closed multiple times according to the security key, as long as the electronic fuse is not opened. For example, a chip manufacturer may manufacture a chip, electrically test the chip in-house, disable the chip, send the chip for visual inspection by a non-trusted company, receive the chip, enable the chip, electrically test the chip again in-house, disable the chip, send the chip to another non-trusted company for identification marking, receive the chip, enable the chip, and continue packaging the chip into a module.

[0047] A second advantage of using a PCM is that it does not require electrical probing of the chip to disable it, since probing could also unintentionally damage the chip, by simply annealing the chip above the crystallization temperature of the PCM, all of the PS crystallizes and becomes conductive, which renders the chip unusable.

[0048] A third advantage of PS is that it can be placed at any level of metal within the chip. Figure 1 shows PS insertion at M3 metal 102, M2 metal 112, M1 metal 120, M3 / M2 via 106, M2 / M1 via 114, and M1 / FET via 122. Furthermore, PS requires less chip "real estate" compared to the area required by logic clocks, which require additional logic circuits to be inserted between existing logic circuits.

[0049] A fourth advantage of the PS is that once set to "open" or "closed", the PS will maintain that state without power. This is because the PS forms a non-volatile memory (i.e., it does not require constant power to retain the memory). This is different from current logic clocking schemes, which must be powered to function properly.

[0050] A fifth advantage of the PS is that, based on the selection of the PCM, the duration for which the PS remains "open" can be controlled (i.e., the lifetime of the integrated circuit can be controlled). This duration is the average time (i.e., operating time or lifetime) that the phase change material remains in the amorphous phase before spontaneously (i.e., naturally) transitioning (i.e., reverting) to the more stable crystalline phase. This retention time depends on the ambient temperature and the composition of the material (i.e., the particular PCM selected for the application). This time can be adjusted from at least 10 years down to a few minutes. The ability to control the retention time allows the manufacturer to enable the chip for a specific period of use, after which the chip may cease to function.

[0051] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that as used herein, the words "comprises" or "comprising" or combinations thereof specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof, or combinations thereof.

[0052] Having described embodiments of a PCM-based PS that allows chips to be enabled and disabled, a process for manufacturing the PS, and a method for "unlocking" a disabled chip (which are illustrative and not limiting), it is noted that modifications and variations can be made by those skilled in the art in light of the above teachings. It is therefore to be understood that changes can be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims.

[0053] One embodiment of the present invention is as follows. [Section 1] receiving, by one or more computer processors, a security key associated with a plurality of programmable switches comprised within the integrated circuit; configuring the plurality of programmable switches by one or more computer processors to render the plurality of programmable switches conductive; and applying, by one or more computer processors, a reset pulse to a first set of programmable switches included in the plurality of programmable switches based on the received security key. The method includes: [Section 2] Item 11. The method of item 1, wherein the plurality of programmable switches comprises a set of non-volatile logic devices. [Section 3] configuring the plurality of programmable switches by one or more computer processors to render the plurality of programmable switches conductive; heating the integrated circuit by one or more computer processors to a temperature above a crystallization temperature of a phase change material contained within the plurality of programmable switches; and cooling said integrated circuit to ambient room temperature by one or more computer processors. The method according to item 1, comprising: [Section 4] Item 2. The method of item 1, wherein the integrated circuit is rendered non-functional by setting the plurality of programmable switches contained within the integrated circuit. [Section 5] Item 14. The method of item 1, wherein applying the reset pulse to the first set of programmable switches opens the programmable switches, rendering them non-conductive. [Section 6] The security key is the first set of programmable switches and a second set of programmable switches; defining the first set of programmable switches of the plurality of programmable switches that are required to be open for the integrated circuit to function; and further defining said second set of programmable switches of said plurality of programmable switches that are required to be closed for said integrated circuit to function. The method according to item 1. [Section 7] disconnecting, by one or more computer processors, pins associated with the plurality of programmable switches; and removing power from said plurality of programmable switches by one or more computer processors; The method of claim 1, further comprising: [Section 8] disconnecting, by one or more computer processors, pins associated with the plurality of programmable switches; inputting, by one or more computer processors, a current that exceeds a threshold value to overload an electronic fuse associated with the plurality of programmable switches, thereby causing an electrical open circuit in wiring associated with the plurality of programmable switches. The method according to item 7, comprising: [Section 9] The lifetime of the integrated circuit can be controlled based on the selection of the phase change material comprising the plurality of programmable switches and the ambient temperature at which the integrated circuit will operate; and the lifetime of the integrated circuit being the time the integrated circuit operates before the phase change material spontaneously reverts from an amorphous state to a more stable crystalline state; The method according to item 1. [Section 10] A programmable switch comprising: a first electrode and a second electrode, wherein the first electrode and the second electrode are separated at a first surface by a phase change material; a first heater on a first side of the phase change material; and a second heater on a second side of the phase change material, where the first heater and the second heater face each other and are separated by the phase change material in a second plane perpendicular to the first plane; The programmable switch. [Section 11] Item 11. The programmable switch of item 10, wherein applying a current to both the first heater and the second heater causes a change in state of the phase change material. [Section 12] 12. The programmable switch of claim 11, wherein the applied current is a reset pulse and the change of state of the phase change material is from crystalline to amorphous. [Section 13] Item 12. The programmable switch of item 11, wherein the applied current is a set pulse and the change to state of the phase change material is from amorphous to crystalline. [Section 14] The reset pulse is a current pulse that raises the temperature of the phase change material above its melting point, followed by a first cooling that forms amorphous regions in the phase change material; and Known as melt quench, Item 13. The programmable switch of item 12. [Section 15] Item 14. The programmable switch of item 13, wherein the set pulse is a current pulse that raises the temperature of the phase change material above its crystallization temperature, followed by a second cooling that produces a fully crystallized phase change material. [Section 16] Item 11. The programmable switch of item 10, wherein applying a combination of current inputs to the first heater and the second heater changes the state of the phase change material such that the conductivity between the first electrode and the second electrode follows a NAND truth table. [Section 17] forming a plurality of non-volatile logic devices in line with vias and wires during a back-end-of-line manufacturing process of a functional integrated circuit, wherein each non-volatile logic device in the plurality of non-volatile logic devices comprises: two electrodes separated by a phase change material; and Two heaters disposed on two opposite sides of the phase change material. Equipped with; forming a locking circuit electrically connected to the two heaters of the plurality of non-volatile logic devices, where the locking circuit is electrically isolated from back-end-of-line wiring of the functional integrated circuit; and changing the state of the phase change material by passing an electric current through each of the two heaters; The method includes: [Section 18] the two electrodes and the wire being constructed from copper; and the vias are made of tungsten Item 18. The method according to item 17, comprising: [Section 19] 20. The method of claim 17, wherein the phase change material is selected from the group consisting of germanium antimony telluride, germanium telluride, antimony telluride, and gallium antimony. [Section 20] The two heaters are a resistive heater that generates heat based on a current flowing through each of the two heaters; electrically insulated from the phase change material; and thermally coupled to the phase change material; Item 18. The method according to item 17.

Claims

1. A programmable switch comprising: a first electrode and a second electrode, wherein the first electrode and the second electrode are separated at a first surface by a phase change material; a first heater on a first side of the phase change material; and a second heater on a second side of the phase change material, where the first heater and the second heater face each other and are separated by the phase change material in a second plane perpendicular to the first plane; It is equipped with applying a first reset current pulse to the first heater to form a first amorphous region in the phase change material adjacent to the first heater, the first amorphous region being smaller than a width of the phase change material; applying a second reset current pulse to the second heater to form a second amorphous region in the phase change material adjacent to the second heater, the second amorphous region being smaller than a width of the phase change material; the second amorphous region overlaps the first amorphous region, thereby blocking flow of electrical current through a crystalline portion of the phase change material. The programmable switch.

2. 10. The programmable switch of claim 1, wherein applying a current to both the first heater and the second heater causes a change in state of the phase change material.

3. 3. The programmable switch of claim 2, wherein the applied current is a reset pulse and the change to the state of the phase change material is from crystalline to amorphous.

4. 3. The programmable switch of claim 2, wherein the applied current is a set pulse and the change to state of the phase change material is from amorphous to crystalline.

5. The reset pulse is a current pulse that raises the temperature of the phase change material above its melting point, followed by a first cooling that forms amorphous regions in the phase change material; and Known as melt quench, 4. The programmable switch of claim 3.

6. 5. The programmable switch of claim 4, wherein the set pulse is a current pulse that raises the temperature of the phase change material above its crystallization temperature, followed by a second cooling that produces a fully crystallized phase change material.

7. 2. The programmable switch of claim 1, wherein applying a combination of current inputs to the first heater and the second heater changes the state of the phase change material such that the conductivity between the first electrode and the second electrode follows a NAND truth table.

8. 1. A method, comprising: forming a plurality of non-volatile logic devices in line with vias and wires during a back-end-of-line manufacturing process of a functional integrated circuit, wherein each non-volatile logic device in the plurality of non-volatile logic devices comprises: two electrodes separated by a phase change material; and Two heaters disposed on two opposite sides of the phase change material Equipped with; forming a locking circuit electrically connected to the two heaters of the plurality of non-volatile logic devices, where the locking circuit is electrically isolated from back-end-of-line wiring of the functional integrated circuit; and changing the state of the phase change material by passing an electric current through each of the two heaters; Including, The flowing of the current applying a first reset current pulse to the first heater to form a first amorphous region in the phase change material adjacent to the first heater, the first amorphous region having a width smaller than that of the phase change material; and applying a second reset current pulse to the second heater to form a second amorphous region in the phase change material adjacent to the second heater, the second amorphous region having a width smaller than that of the phase change material; and wherein the second amorphous region overlaps the first amorphous region, thereby blocking current flow through a crystalline portion of the phase change material. The method.

9. the two electrodes and the wire being constructed from copper; and the vias are made of tungsten The method of claim 8 , comprising:

10. 9. The method of claim 8, wherein the phase change material is selected from the group consisting of germanium antimony telluride, germanium telluride, antimony telluride, and gallium antimony.

11. The two heaters are a resistive heater that generates heat based on a current passing through each of the two heaters; electrically insulated from the phase change material; and thermally coupled to the phase change material; The method according to claim 8.

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