Power supply circuit and detection device

Abstract

To provide a power supply circuit capable of supplying a stable voltage.SOLUTION: The power supply circuit includes: a first regulator 10a that includes a first input terminal Tin1 to which a first voltage V1 is input, a first output terminal Tout1 from which a second voltage is output, and a first adjustment terminal Adj1, and adjusts the second voltage based on the voltage of the first adjustment terminal; a second regulator 12 including a second input terminal Tin2 to which the first voltage is input and a second output terminal Tout2 from which a third voltage V3 is output; and a differential amplifier circuit 15 that outputs a signal to the first adjustment terminal, the signal corresponding to a difference between the third voltage and a fourth voltage V4 of a first node N1 that is between a plurality of first resistors connected in series between the first output terminal and a reference potential lower than the second voltage.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a power supply circuit and a detection device. [Background technology]

[0002] 2. Description of the Related Art A power supply circuit that uses two regulators to supply two DC voltages as an internal circuit of an electronic device or the like is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-102676 A [Patent Document 2] JP 2007-14176 A Summary of the Invention [Problem to be solved by the invention]

[0004] There are cases where two DC voltages are supplied so that the voltage ratio between them is a constant ratio. One possible method is to supply two DC voltages from the power supply voltage using resistive voltage division. However, with this method, the supplied DC voltage fluctuates due to the current flowing through the load. Another possible method is to use two regulators to supply two DC voltages. However, there is an error in the reference voltage of the regulators. For this reason, it is difficult to maintain a constant voltage ratio between the two DC voltages.

[0005] The present disclosure has been made in consideration of the above problems, and has an object to supply a stable voltage. [Means for solving the problem]

[0006] A power supply circuit according to one embodiment of the present disclosure includes a first regulator having a first input terminal for inputting a first voltage, a first output terminal for outputting a second voltage, and a first adjustment terminal, and adjusting the second voltage based on a voltage of the first adjustment terminal; a second regulator having a second input terminal for inputting the first voltage and a second output terminal for outputting a third voltage; and a differential amplifier circuit for outputting a signal to the first adjustment terminal corresponding to a difference between the third voltage and a fourth voltage at a first node between a plurality of first resistors connected in series between the first output terminal and a reference potential lower than the second voltage. Effect of the Invention

[0007] According to the present disclosure, a stable voltage can be supplied. [Brief description of the drawings]

[0008] [Figure 1] 1 is a circuit diagram of a power supply circuit according to a first embodiment. [Diagram 2] FIG. 2 is a circuit diagram of a regulator in the first embodiment. [Diagram 3] FIG. 2 is a circuit diagram of a power supply circuit according to a first comparative example. [Figure 4] FIG. 11 is a circuit diagram of a power supply circuit according to Comparative Example 2. [Diagram 5] FIG. 2 is a circuit diagram of the first embodiment used in a simulation. [Figure 6] FIG. 13 is a diagram showing a voltage V2 versus time in a simulation of Comparative Example 3. [Figure 7] FIG. 13 is a diagram showing a voltage V2 versus time in the first embodiment in a simulation. [Figure 8] FIG. 11 is a block diagram of a detection device according to a second embodiment. [Figure 9] FIG. 4 is a diagram showing a signal versus time in the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. EXAMPLES

[0010] FIG. 1 is a circuit diagram of a power supply circuit according to a first embodiment. The power supply circuit 100 includes regulators 10 and 12 and an error amplifier circuit 14. The regulator 10 includes terminals Tin1, Tout1, Adj1, and Gnd1. The regulator 12 includes terminals Tin2, Tout2, Adj2, and Gnd2. The regulators 10 and 12 are, for example, LDO (Low Dorp Out) type linear regulators. A reference potential Vg (for example, ground potential, 0 V) ​​is supplied to the terminal Gnd. A DC power supply 16 supplies a voltage V1.

[0011] A voltage V1 (first voltage) is input to a terminal Tin1 (first input terminal) of a regulator 10 (first regulator). The regulator 10 converts the voltage V1 to a voltage V2 (second voltage) and outputs the voltage V2 to a terminal Tout1 (first output terminal). A terminal Gnd1 of the regulator 10 is electrically connected to a terminal Gnd. A plurality of second resistors (resistors R2a and R2b) are connected in series between the terminal Tout1 and a reference potential Vg. A node N2 (second node) between the resistors R2a and R2b is electrically connected to a terminal Adj1 (first adjustment terminal) of the regulator 10. The voltage at the node N2 is a voltage V5. The regulator 10 adjusts the voltage V2 based on the voltage V5 at the terminal Adj1. The voltage V2 is output from the terminal Tout1 to a terminal T1.

[0012] A voltage V1 is input to a terminal Tin2 (second input terminal) of a regulator 12 (second regulator). The regulator 12 converts the voltage V1 to a voltage V3 (third voltage) and outputs the voltage V3 to a terminal Tout2 (second output terminal). A terminal Gnd2 of the regulator 12 is electrically connected to a terminal Gnd. A plurality of fifth resistors (resistors R3a and R3b) are connected in series between the terminal Tout2 and a reference potential Vg. A node N3 (fourth node) between the resistors R3a and R3b is electrically connected to a terminal Adj2 (second adjustment terminal) of the regulator 12. The voltage at the node N3 is a voltage V6. The regulator 12 adjusts the voltage V3 based on the voltage V6 (fifth voltage) of the terminal Adj2. The voltage V3 is output from the terminal Tout2 to the terminal T2.

[0013] FIG. 2 is a circuit diagram of the regulator in the first embodiment. The regulators 10 and 12 include a transistor 20 and a second differential amplifier circuit 22. The transistor 20 is connected in series between a terminal Tin1 (and Tin2) and a terminal Tout1 (and Tout2). The transistor 20 is, for example, a metal oxide semiconductor field effect transistor (MOSFET) and is an NchFET. The drain of the transistor 20 is electrically connected to the terminal Tin1 (and Tin2), and the source is electrically connected to the terminal Tout1 (and Tout2). The second differential amplifier circuit 22 receives the reference voltage Vref1 (and Vref2) and the signal of the terminal Adj1 (and Adj2). The output terminal of the second differential amplifier circuit 22 is connected to the control terminal (for example, the gate) of the transistor 20.

[0014] In FIG. 1, when the voltage V5 (and V6) input to the terminal Adj1 (and Adj2) becomes higher than the reference voltage Vref1 (and Vref2), the voltage V7 output from the output terminal of the second differential amplifier circuit 22 becomes negative. Therefore, the current flowing between the drain and source of the transistor 20 is narrowed, and the resistance between the drain and source of the transistor 20 becomes high. This increases the voltage drop in the transistor 20, and the voltage V2 (and V3) becomes low. When the voltage V5 (and V6) becomes lower than the reference voltage Vref1 (and Vref2), the voltage V7 output from the output terminal of the second differential amplifier circuit 22 becomes positive. Therefore, the current flowing between the drain and source of the transistor 20 becomes large, and the resistance between the drain and source of the transistor 20 becomes low. This reduces the voltage drop in the transistor 20, and the voltage V2 (and V3) becomes high. In this manner, regulators 10 and 12 adjust voltages V2 (and V3) based on voltages V5 (and V6) at terminals Adj1 (and Adj2).

[0015] The resistance values ​​of the resistors R2a, R2b, R3a, and R3b in FIG. 1 are R2a, R2b, R3a, and R3b, respectively. In this case, if there is no error amplifier circuit 14 (i.e., if there is no connection line between node N4 and node N2), the voltage V2=Vref1×(R2a+R2b) / R2b, and the voltage V3=Vref2×(R3a+R3b) / R3b. When V3=V2 / N, the resistance values ​​of the resistors R2a, R2b, R3a, and R3b should be determined so that the ratio N=(Vref1×R3b×(R2a+R2b)) / (Vref2×R2b×(R3a+R3b)). However, the resistors used have errors, and the value of the voltage ratio between the voltages V3 and V2 is affected by the accuracy of the reference voltages Vref1 and Vref2. Therefore, by adding the error amplifier circuit 14 (i.e., when there is a connection line between node N4 and node N2), it is possible to improve the accuracy of the ratio of voltages V3 and V2, and the value of N. When the error amplifier circuit 14 is added, the accuracy of the ratio of V3 and V2 is determined almost entirely by the accuracy of the resistance values ​​of resistors R1a and R1b. For this reason, by using highly accurate resistors for resistors R1a and R1b, for example resistors with a high accuracy of 1% or 0.5% or less, even if the accuracy of the reference voltages Vref1 and Vref2 and the accuracy of the other resistors are not good (for example, even if the accuracy is 5%), the ratio N can be made to be 1% or 0.5% or less of the target value.

[0016] Although regulators 10 and 12 have been described as being LDO type linear regulators, regulators 10 and 12 may be other types, for example, switching regulators, and the input voltage of regulator 10 may be different from the input voltage of regulator 12. In particular, regulator 12 may be a regulator that does not have terminal Adj2.

[0017] Returning to Fig. 1, the error amplifier circuit 14 includes resistors R1a and R1b and a first differential amplifier circuit 15 (differential amplifier circuit). A plurality of first resistors (R1a and R1b) are connected in series between the terminal T1 and a reference potential Vg. The voltage of a node N1 (first node) between the resistors R1a and R1b is V4 (fourth voltage).

[0018] The first differential amplifier circuit 15 includes transistors Q1 (first transistor), Q2 (second transistor), resistors R4a (fourth resistor), R4b (third resistor), and R5. The transistors Q1 and Q2 are, for example, PNP bipolar transistors. The emitters of the transistors Q1 and Q2 are commonly connected to, for example, a node N5. For example, a resistor R5 is connected between the node N5 and a terminal T1. The resistor R5 functions as a current source. The collector of the transistor Q1 is electrically connected to a terminal Gnd via resistors R4a and R4b in series. The collector of the transistor Q2 is electrically connected to, for example, the terminal Gnd. The base of the transistor Q1 is electrically connected to a terminal Tout2. The base of the transistor Q2 is electrically connected to a node N1. Voltages V3 and V4 are input to the bases of the transistors Q1 and Q2, respectively. A node N4 between the resistors R4a and R4b is electrically connected to a node N2 and a terminal Adj1.

[0019] When the voltage V4 becomes higher than the voltage V3, the potential of the node N4 tends to become higher. This causes a current I1 to flow from the node N4 to N2, and the voltage V5 of the node N2 becomes higher. Therefore, the regulator 10 lowers the voltage V2. When the voltage V4 becomes lower than the voltage V3, the potential of the node N4 tends to become lower. This causes a current I1 to flow from the node N2 to N4, and the voltage V5 of the node N2 becomes lower. Therefore, the regulator 10 raises the voltage V2. The resistance values ​​of the resistors R1a and R1b are R1a and R1b, respectively. This causes the ratio of the voltage V2 to the voltage V3 to be a desired ratio determined by the resistance values ​​of the resistors R1a and R1b.

[0020] If the target value of the ratio of voltage V2 to voltage V3 is N=V2 / V3, then the ratio N should be (R1a+R1b) / R1b. Although there is manufacturing error in the resistance values, in Figure 1 the accuracy of the ratio of voltages V3 and V2 is mostly determined by the accuracy of the resistance values ​​of resistors R1a and R1b. For this reason, highly accurate resistors, for example, resistors with a high accuracy of 1% or 0.5% or less, are used only for resistors R1a and R1b. This makes it possible to make the ratio N accurate to within 1% or 0.5% of the target value even if the accuracy of the reference voltages Vref1 and Vref2 and the accuracy of the other resistors are not good (for example, even if the accuracy is 5%).

[0021] If the resistance values ​​of resistors R4a and R4b are too high, the voltage V5 at node N2 barely changes even if the difference between voltages V3 and V4 becomes large. On the other hand, if the resistance values ​​of resistors R4a and R4b are too low, the voltage V5 at node N2 changes greatly with respect to the difference between voltages V3 and V4. In addition, the first differential amplifier circuit 15 and the second differential amplifier circuit 22 oscillate, so the resistance values ​​of resistors R4a and R4b are appropriately set so as to operate as described above.

[0022] A resistor may be provided between the transistor Q2 and the terminal Gnd. The first differential amplifier circuit 15 does not need a differential output, so there is no need to provide a resistor between the transistor Q2 and the reference potential Vg. This allows the number of components to be reduced, leading to cost savings.

[0023] The transistors Q1 and Q2 may be PchFETs, NPN bipolar transistors, or NchFETs. When the transistors Q1 and Q2 are NPN bipolar transistors or NchFETs, a resistor R5 is provided between the terminal Gnd and the emitters or sources of the transistors Q1 and Q2, and resistors R4a and R4b are provided between the transistor Q1 and the terminal T1. When the voltage of the node N2 is close to the voltage V2, the transistors Q1 and Q2 may be configured as NPN bipolar transistors or NchFETs.

[0024] [Comparative Example 1] 3 is a circuit diagram of a power supply circuit according to Comparative Example 1. In the power supply circuit 110 of Comparative Example 1, the regulator 12 is not provided. A node N1 between resistors R1a and R1b is connected to a terminal T2. By setting the resistance values ​​of the resistors R1a and R1b to be the same as those of the resistors R1a and R1b in the first embodiment, a voltage V3 can be generated at the node N1. A noise-cutting capacitor C5 is connected between the node N1 and the terminal Gnd. The other configurations are the same as those in the first embodiment.

[0025] In the comparative example 1, the voltages V2 and V3 change depending on the current consumption between the terminal T1 or T2 and the terminal Gnd. As a result, the voltage ratio between the voltages V2 and V3 is not constant. When the frequency of the change in the voltage V2 is high, the noise can be cut by the capacitor C5. However, when the frequency of the change in the voltage V2 is low, for example, about 10 Hz, the noise cannot be cut. As a result, the ratio between the voltages V2 and V3 cannot be constant.

[0026] [Comparative Example 2] 4 is a circuit diagram of a power supply circuit according to Comparative Example 2. In a power supply circuit 112 of Comparative Example 2, an error amplifier circuit 14 is not provided. A regulator 10 adjusts a voltage V2 using a voltage V5 and a reference voltage Vref1 of FIG. 2. A regulator 12 adjusts a voltage V3 using a voltage V6 and a reference voltage Vref2 of FIG. 2. The other configurations are the same as those of the first embodiment.

[0027] In the comparative example 2, the regulators 10 and 12 adjust the voltages V2 and V3 so that the voltages V2 and V3 do not fluctuate. Therefore, it is possible to suppress the fluctuation of the voltages V2 and V3 due to the current consumption. However, there is a manufacturing error between the reference voltage Vref1 of the regulator 10 and the reference voltage Vref2 of the regulator 12. For example, a linear regulator is inexpensive, but the error of the reference voltage is large. Therefore, in order to set the ratio of the voltages V2 and V3 to a desired ratio, the resistance values ​​of the resistors R2a, R2b, R3a, and R3b must be adjusted for each of the regulators 10 and 12, which increases the manufacturing cost.

[0028] On the other hand, in the first embodiment, as shown in FIG. 1, the first differential amplifier circuit 15 outputs a signal S corresponding to the difference between the voltage V4 at the node N1 between the resistors R1a and R1b and the voltage V3, which is the output voltage of the regulator 12, to the terminal Adj1 (adjustment terminal) of the regulator 10. In this manner, the voltage V2 is adjusted based on the difference between the voltage V4 obtained by resistively dividing the voltage V2 and the reference potential Vg, and the voltage V3. This allows the voltage ratio between the voltages V2 and V3 to be a constant ratio within the range of the error in the resistance values ​​of the resistors R1a and R1b. By selecting resistors with a resistance value tolerance of 1% or less, 0.5% or less, or 0.2% or less as the resistors R1a and R1b, the error in the voltage ratio between the voltages V2 and V3 can be reduced.

[0029] The terminal Adj1 is electrically connected to a node N2 between the resistors R2a and R2b. As a result, the voltage V5 divided by the resistors R2a and R2b is fine-adjusted based on the difference between the voltages V3 and V4. The regulator 10 adjusts the voltage V2 based on the fine-adjusted voltage V5. As a result, the voltage ratio between the voltages V2 and V3 can be made constant.

[0030] In the first differential amplifier circuit 15, the transistors Q1 (first transistor) and Q2 (second transistor) are connected in parallel between the terminal Tout1 and the reference potential Vg. A voltage V3 is input to the base (control terminal) of the transistor Q1, and a voltage V4 is input to the base (control terminal) of the transistor Q2. A resistor R4b (third resistor) is connected in series with the transistor Q1 between the terminal Tout2 and the reference potential Vg, and is connected in parallel with the transistor Q2. A node N4 (third node) between the resistor R4b and the transistor Q1 is electrically connected to the node N2. This allows a current to flow from the node N4 to the node N2 based on the difference between the voltages V2 and V4. This allows fine adjustment of the voltage V5 of the node N2.

[0031] A resistor R4a (fourth resistor) is connected between the terminal Tout1 and the reference potential Vg, in series with the transistor Q1 and the resistor R4b, so that the voltage V5 of the node N2 can be finely adjusted regardless of the direction of the current flowing between the nodes N4 and N2.

[0032] [simulation] A simulation was performed assuming an error in the reference voltages Vref1 and Vref2 of the regulators 10 and 12. FIG. 5 is a circuit diagram of the embodiment 1 used in the simulation. In the power supply circuit 102 according to the embodiment 1 used in the simulation, the regulators 10 and 12 are provided with terminals En1 and En2. The terminals En1 and En2 are terminals to which the regulators 10 and 12 are activated and deactivated, respectively, when a high level and a low level are input. Capacitors C3 and C4 are connected in parallel to the DC power supply 16. A resistor R6 is commonly connected between the terminal Tin1 and the terminals En1 and En2. A resistor R7 is connected between the terminal Tout2 and the base of the transistor Q1. A capacitor C1 is connected between the terminal Tout1 and the reference potential Vg. A capacitor C2 is connected between the terminal Tout2 and the reference potential Vg. The other circuit configurations are the same as those in FIG. 1.

[0033] In the comparative example 3 in the simulation, the error amplifier circuit 14 in FIG. 5 is not provided.

[0034] Table 1 shows the resistance value of each resistor in FIG. [Table 1]

[0035] Table 2 shows the capacitance values ​​of the capacitors in FIG. [Table 2]

[0036] Table 3 shows the voltages in FIG. [Table 3]

[0037] The regulators 10 and 12 are products with reference voltages Vref1 and Vref2 of 0.8V. However, since there is no simulation model with reference voltages Vref1 and Vref2 of 0.8V, the reference voltages Vref1 and Vref2 are 1.0V. A DC power supply 40 for boosting voltage V5 by 0.2V is provided between node N2 and terminal Adj1, and a DC power supply 42 for boosting voltage V6 by 0.2V is provided between node N3 and terminal Adj2. The boost voltage of the DC power supply 40 is fixed at 0.20V, and the boost voltage of the DC power supply 42 is a sine wave that varies by ±0.02V around 0.20V. ±0.02V represents the error of the reference voltage Vref1 as the fluctuation of the boost voltage of the DC power supply 42. The period of the sine wave is set to 0.5 ms.

[0038] 6 is a diagram showing voltage V2 versus time in Comparative Example 3 in a simulation. Voltage V2 is a sine wave centered around 3.3 V, and the difference A1 between the center and the maximum or minimum value is about 0.1 V. Voltage V3 is 1.6562 V. Thus, in Comparative Example 3, assuming that the reference voltage Vref1 of regulator 10 changes by 0.02 V, voltage V2 changes by ±0.1 V.

[0039] FIG. 7 is a diagram showing the voltage V2 with respect to time in the first embodiment in the simulation. The voltage V2 is a sine wave centered around 3.315V, and the difference A2 between the center and the maximum or minimum value is about 0.004V. The voltage V2 is 1.6562V. Thus, in the first embodiment, even if it is assumed that the reference voltage Vref1 of the regulator 10 changes by 0.02V, the change in the voltage V2 is 0.004V. Thus, in the first embodiment, even if there is an error between the reference voltage Vref1 of the regulator 10 and the reference voltage Vref2 of the regulator 12, the voltage V3 can be set as the midpoint of the voltage V2. EXAMPLES

[0040] Example 2 is an example in which Example 1 is used in a detection device. FIG. 8 is a block diagram of the detection device according to Example 2. The detection device 104 of Example 2 mainly includes a power supply circuit 100, a sensor 30, an operational amplifier 32, an A / DC (Analog Digital Converter) 34, and a detection unit 36. The power supply circuit 100 is the power supply circuit of Example 1, and outputs voltages V2 and V3 to terminals T1 and T2, respectively. V3=V2 / 2. The voltage V2 is supplied from the power supply circuit 100 to the terminal T3 as a power supply voltage VDD. The voltage V3 is supplied from the power supply circuit 100 to the terminal T4 as a voltage VDD / 2 that is the midpoint of the power supply voltage VDD. A reference potential Vg (for example, ground potential, 0 V) ​​is supplied to the terminal Gnd.

[0041] An output signal S1 of the sensor 30 is input to the positive end of an operational amplifier 32 via a capacitor C6. The positive end of the operational amplifier 32 is connected to a terminal T4 via a resistor R10. The terminal T4 is input to the negative end of the operational amplifier 32 via a resistor R9. An output signal S3 of the operational amplifier 32 is input to an A / DC 34 and is fed back to the negative end via a resistor R8. A reference potential Vg and a power supply voltage VDD are supplied to the A / DC 34. A digital signal output by the A / DC 34 is output to a detection unit 36. The detection unit 36 ​​is a processor such as a CPU (Central Processing Unit) and processes the digital signal.

[0042] 9(a) to 9(c) are diagrams showing signals versus time in the second embodiment. Although the actual signals S1 to S3 are not necessarily sine waves, the following description will use sine waves. The sensor 30 is, for example, a millimeter wave laser sensor or a vibration sensor. As shown in FIG. 9(a), the output signal S1 of the sensor 30 relative to the reference potential Vg has a waveform that oscillates in the positive and negative directions around 0V, and has a frequency of, for example, several Hz to several hundreds of Hz. The capacitor C6 removes the DC component of the signal S1.

[0043] A voltage VDD / 2 is supplied to the positive end of the operational amplifier 32 via resistor R10. As a result, as shown in FIG. 9(b), the signal S2 input to the positive end has a waveform that oscillates around the voltage VDD / 2. A voltage VDD / 2 is supplied to the negative end. As a result, the operational amplifier 32 amplifies the difference between the signal S2 and the voltage VDD / 2, with the voltage VDD / 2 as the reference. The gain of the operational amplifier 32 is set by the resistance values ​​of resistors R8 and R9. As shown in FIG. 9(c), the operational amplifier 32 amplifies the signal S2 around the voltage VDD / 2, and outputs the amplified signal S3.

[0044] The A / DC 34 digitizes the voltage between the reference potential Vg and the power supply voltage VDD at equal intervals. For example, if the resolution of the A / DC 34 is 16 bits, the value is 0x0000 when the signal S3 is at 0V, which is the reference potential Vg, and 0xFFFF when the signal S3 is at the power supply voltage VDD. When the signal S3 is at the voltage VDD / 2, the value is 0x7FFF or 0x8000.

[0045] When the voltage V3 at the terminal T4 is slightly shifted from the voltage VDD / 2 to the voltage VDD / 2+α, the operational amplifier 32 amplifies the difference between the signal S2 and the voltage VDD / 2+α with the voltage VDD / 2+α as the reference. Therefore, the zero point of the signal S3 is significantly shifted from the voltage VDD / 2. This narrows the dynamic range. Or it affects the signal processing in the detection unit 36. Thus, in the second embodiment, it is important that the voltage at the terminal T4 is the voltage VDD / 2.

[0046] Therefore, the voltage V2 of the power supply circuit 100 of the first embodiment is set as the power supply voltage VDD of the A / DC 34 (A / D converter), and the operational amplifier 32 (operational amplifier circuit) amplifies the output signal S2 of the sensor 30 with reference to the voltage V3 (VDD / 2) of the power supply circuit 100. This allows the A / DC 34 to perform A / D conversion with the voltage VDD / 2 as the midpoint. Note that the voltage V3 does not have to be exactly 1 / 2 of the voltage V2, and the voltage V3 may be 0.475 times or more and 0.525 times or less, 0.49 times or more and 0.51 times or less, or 0.495 times or more and 0.505 times or less of the voltage V2. To A / D convert information from a more accurate sensor, a higher voltage accuracy is required to increase the gain of the operational amplifier, for example. However, even when a general-purpose LDO type linear regulator is used, the output voltage accuracy can be improved by utilizing this embodiment and increasing the resistance accuracy of the resistors R1a and R1b, for example.

[0047] Although the power supply circuit 100 of the first embodiment is used in the detection device 104, the power supply circuit 100 may be used in electronic devices other than the detection device 104.

[0048] The present disclosure is not limited to the above-described embodiment, and can be implemented in various modified forms without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0049] 10, 12 regulator, 14 error amplifier circuit, 15 first differential amplifier circuit, 22 second differential amplifier circuit, 16 DC power supply, 30 sensor, 32 operational amplifier, 34, A / DC, 36, detection unit

Claims

1. a first regulator including a first input terminal to which a first voltage is input, a first output terminal to which a second voltage is output, and a first adjustment terminal, and configured to adjust the second voltage based on a voltage of the first adjustment terminal; a second regulator including a second input terminal to which the first voltage is input and a second output terminal to which a third voltage is output; a differential amplifier circuit that outputs to the first adjustment terminal a signal corresponding to a difference between the third voltage and a fourth voltage at a first node between a plurality of first resistors that are connected in series between the first output terminal and a reference potential lower than the second voltage; A power supply circuit comprising:

2. 2. The power supply circuit according to claim 1, wherein the first adjustment terminal is connected to a second node between a plurality of second resistors connected in series between the first output terminal and the reference potential.

3. The differential amplifier circuit includes: a first transistor connected in parallel between the first output terminal and the reference potential, the first transistor having a control terminal to which the third voltage is input, and a second transistor having a control terminal to which the fourth voltage is input; a third resistor connected in series with the first transistor and in parallel with the second transistor between the first output terminal and the reference potential; 2. The power supply circuit according to claim 1, wherein a third node between the third resistor and the first transistor is electrically connected to the first adjustment terminal.

4. a fourth resistor connected in series with the first transistor and the third resistor between the first output terminal and the reference potential, 4. The power supply circuit according to claim 3, wherein the third node is a node between the third resistor and the fourth resistor.

5. 5. The power supply circuit according to claim 1, wherein, when a resistance value between the first node and the first output terminal is R1a, a resistance value between the first node and the reference potential is R1b, and a ratio of the second voltage to a target third voltage V3 is N, (R1a+R1b) / R1b is 0.95 to 1.05 times N.

6. 5. The power supply circuit according to claim 1, wherein the second regulator has a second adjustment terminal and adjusts the third voltage based on a fifth voltage at a fourth node between a plurality of fifth resistors connected in series between the third voltage and the reference potential.

7. A power supply circuit according to any one of claims 1 to 4; A sensor; an operational amplifier circuit that amplifies a difference between the output of the sensor and the third voltage; an A / D converter to which the output of the operational amplifier circuit is input and which uses the second voltage as a power supply voltage; A detection device comprising:

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