Method for manufacturing vertical semiconductor device

Abstract

To provide a method for manufacturing a vertical semiconductor device which suppresses the generation of defects in gate electrodes due to removal of a resist mask.SOLUTION: In a method for manufacturing a vertical semiconductor device in which a gate electrode 15 is embedded in a trench T formed in a semiconductor layer 20 via a gate insulating film 14, a peeling liquid F is sprayed from a spray nozzle 31 of a peeling device 30 onto a surface of the semiconductor layer 20 to remove a resist mask 21 covering a region covering the trench T of the gate electrode 15 and its periphery. When a spray pressure of the peeling liquid F in the spray nozzle 31 is P [MPa] and a length of a protruding portion 15a, which is a portion extending in a direction perpendicular to the stacking direction Y of the semiconductor layer 20 outside the trench T in a joint surface between the gate electrode 15 and the gate insulating film 14 in a cross section parallel to the stacking direction Y of the semiconductor layer 20 and perpendicular to an extending direction T1 of the trench T as viewed from the stacking direction Y of the semiconductor layer 20, is L [μm], a relation P / L≤34 [MPa / μm] is satisfied.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a vertical semiconductor device. [Background technology]

[0002] Conventionally, as a method for forming a gate electrode in a vertical semiconductor device in which the gate electrode is embedded in a trench formed in a wafer made of a semiconductor layer via a gate insulating film, Patent Document 1 discloses a method in which a resist mask is formed on a gate electrode formed on a gate insulating film, etching is performed, and then a stripping liquid is sprayed to remove the resist mask. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-54250 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the method disclosed in Patent Document 1, the gate electrode has a protruding portion that protrudes from the periphery of the trench opening. If the protruding portion is reduced in size in response to the demand for miniaturization of vertical semiconductor devices, the protruding portion will peel off due to the spray pressure of the stripping solution when the resist mask is removed, causing defects in the gate electrode and reducing yield.

[0005] The present invention has been made in view of the above-mentioned problems, and aims to provide a method for manufacturing a vertical semiconductor device that can prevent defects from occurring in the gate electrode due to removal of the resist mask. [Means for solving the problem]

[0006] One aspect of the present invention is A method for manufacturing a vertical semiconductor device in which a gate electrode is embedded in a trench formed in a semiconductor layer via a gate insulating film, the method comprising: a trench forming step of forming the trench on the wafer made of the semiconductor layer; a gate insulating film forming step of forming the gate insulating film on the surface of the wafer including the trench; a gate electrode forming step of forming the gate electrode on the gate insulating film; a gate electrode resist mask forming step of forming a resist mask that covers a region of the gate electrode that covers the trench and a periphery of the trench; a gate electrode removing step of removing a region of the gate electrode where the resist mask is not provided; a gate electrode resist mask removing step of removing the resist mask by spraying a stripping liquid for stripping the resist mask from a spray nozzle onto the surface of the semiconductor layer; Including, The ejection pressure of the stripping solution ejected from the ejection nozzle is P [MPa], In a cross section parallel to the stacking direction of the semiconductor layers and perpendicular to the extending direction of the trench as viewed from the stacking direction of the semiconductor layers, when the length of a protruding portion of a junction surface between the gate electrode and the gate insulating film, which is a portion extending outside the trench in a direction perpendicular to the stacking direction of the semiconductor layers, is defined as L [μm], P / L≦34 [MPa / μm] The present invention is a method for manufacturing a vertical semiconductor device that satisfies the above relationship. [Effects of the Invention]

[0007] In the method for manufacturing a vertical semiconductor device according to the above aspect, in the gate electrode resist mask removal step, the ejection pressure P [MPa] of the remover and the length L [μm] of the protruding portion at the interface between the gate electrode and the gate insulating film satisfy the relationship P / L≦34 [MPa / μm]. This makes it easier to maintain the bond between the gate electrode and the gate insulating film at the protruding portion formed around the periphery of the opening of the trench in the gate electrode against the ejection pressure of the remover when removing the resist mask. As a result, peeling of the protruding portion of the gate electrode can be reduced, and defects in the gate electrode can be suppressed. As a result, yield can be improved.

[0008] As described above, according to the above aspect, it is possible to provide a method for manufacturing a vertical semiconductor device that can prevent defects from occurring in the gate electrode due to removal of the resist mask. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing the configuration of a vertical semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing a trench pattern on the upper surface of the wafer of the first embodiment. [Figure 3] 1 is a flow diagram showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] FIG. 2 is a diagram showing a rotation mode of a wafer in the first embodiment. [Figure 16] FIG. 2 is a diagram showing the results of a confirmation test of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the gate electrode resist mask removal step, the distance between the tip of the spray nozzle and the surface of the wafer is preferably within a range of 5 to 50 mm. If the distance between the tip of the spray nozzle and the surface of the wafer is less than 5 mm, the spray nozzle or wafer may shake during the gate electrode resist mask removal step due to spraying of the stripping solution, which may cause physical contact between the tip of the spray nozzle and the surface of the wafer, resulting in damage to the wafer or the gate electrode formed on the wafer. Furthermore, if the distance between the tip of the spray nozzle and the surface of the wafer is greater than 50 mm, the stripping solution sprayed from the spray nozzle may scatter before reaching the wafer surface, making it impossible to obtain the required resist mask removal power.

[0011] In the gate electrode resist mask removing step, the resist mask is removed by spraying the remover solution from the spray nozzle onto the surface of the wafer while rotating the wafer around an axis parallel to the stacking direction, thereby preventing the resist mask removed by the remover solution and the remover solution from remaining on the wafer surface and improving the ability to remove the resist mask.

[0012] The rotation speed of the wafer is preferably within a range of 100 rpm to 1000 rpm, which allows the stripping solution sprayed from the spray nozzle to be more uniformly distributed over the wafer surface, further improving the ability to remove the resist mask.

[0013] In the gate electrode resist mask removing step, the spray pressure P of the remover is preferably within a range of 3 to 12 MPa. In this case, both physical removal, which occurs when the remover collides with the resist mask to remove it, and chemical removal, which occurs when the resist mask is decomposed by a chemical reaction between the remover and the resist mask, are achieved in a well-balanced manner, thereby further improving the ability to remove the resist mask while suppressing damage to the gate electrode.

[0014] (Embodiment 1) 1. Overview of the configuration of vertical semiconductor device 1 The configuration of the vertical semiconductor device 1 of the first embodiment will be described below. As shown in Fig. 1, the vertical semiconductor device 1 of the first embodiment is a FET of a vertical semiconductor device, and includes a substrate 10, a first n layer 11, a p layer 12, a second n layer 13, a trench T, a recess R, a gate insulating film 14, a gate electrode 15, a p body electrode 16, a source electrode 17, and a drain electrode 18. The first n layer 11, the p layer 12, and the second n layer 13 form a semiconductor layer 20.

[0015] The substrate 10 is a 300 μm-thick flat substrate made of Si-doped n-GaN with a c-plane as the principal surface. The Si concentration is 1×10 18 / cm 3 In addition to n-GaN, any material that is conductive and can serve as a growth substrate for a group III nitride semiconductor can be used as a substrate. For example, ZnO, Si, etc. can also be used. However, from the viewpoint of lattice matching, it is preferable to use a GaN substrate as in this example.

[0016] The first n-layer 11 is a 10 μm-thick Si-doped n-GaN layer stacked on the substrate 10. The Si concentration is 1×10 16 / cm 3 is.

[0017] The p-layer 12 is a 1.0 μm-thick Mg-doped p-GaN layer stacked on the first n-layer 11. The Mg concentration is 2×10 18 / cm 3 is.

[0018] The second n-layer 13 is a 0.3 μm thick Si-doped n-GaN layer stacked on the p-layer 12. The Si concentration is 3×10 18 / cm 3 A portion of second n-layer 13 (the region where p-body electrode 16 and source electrode 17 are to be formed) is removed by etching to provide a recess R, and p-layer 12 is exposed at the bottom surface thereof.

[0019] Trench T is a groove formed in the surface of second n layer 13 at a position of a predetermined pattern described later, as shown in Fig. 2, and has a depth that penetrates second n layer 13 and p layer 12 to reach first n layer 11, as shown in Fig. 1. First n layer 11 is exposed at bottom surface Ta of trench T, and first n layer 11, p layer 12, and second n layer 13 are exposed at side surface Tb of trench T. The side surface of p layer 12 exposed at side surface Tb of trench T is a region that operates as a channel of the FET of embodiment 1.

[0020] The gate insulating film 14 is made of Al2O3 and is provided in the form of a continuous film over the bottom surface Ta, side surface Tb, and top surface Tc of the trench T (the surface of the second n layer 13, a region near the side surface Tb of the trench T). The gate insulating film 14 also has a portion that protrudes outward from the trench T at the periphery of the opening of the trench T. The thickness of the gate insulating film 14 is 100 nm. In addition to Al2O3, the gate insulating film 14 can be made of SiO2, SiN, SiON, AlN, AlON, ZrON, HfO2, ZrO2, or the like. The gate insulating film 14 does not need to be a single layer and may be made up of multiple layers.

[0021] The gate electrode 15 is provided in the form of a film that is continuous on the bottom surface Ta, side surface Tb, and upper surface of the trench T, with the gate insulating film 14 interposed therebetween. The gate electrode 15 also has a protruding portion 15a that protrudes outward from the trench T on the periphery of the opening of the trench T.

[0022] The length L of the protruding portion 15a is the length of the portion of the junction surface between the gate electrode 15 and the gate insulating film 14 that extends outside the trench T in a direction perpendicular to the stacking direction Y of the semiconductor layer 20 in a cross section (i.e., the cross section shown in FIG. 1) that is parallel to the stacking direction Y of the semiconductor layer 20 shown in FIG. 1 and perpendicular to the extension direction T1 of the trench T in FIG. 2 viewed from the stacking direction Y of the semiconductor layer 20.

[0023] The gate electrode 15 is made of TiN, TiN / Al / Ti, W, or the like. In particular, from the viewpoint of adhesion to the gate insulating film 14, it is preferable that the first layer of the gate electrode 15 (the entire gate electrode 15 in the case of a single layer) that is bonded to the gate insulating film 14 is made of a Ti-based material. The thickness of the gate electrode 15 is not limited and can be any thickness.

[0024] FIG. 2 is a diagram showing the planar patterns of the recesses R and trenches T. As shown in FIG. 2, the semiconductor device of embodiment 1 has a unit cell having a regular hexagonal shape, and the regular hexagons are arranged in a honeycomb pattern. The trenches T partition the second n layer 13 into a regular hexagonal pattern. The recesses R are regular hexagonal patterns that are smaller than the regular hexagons of the second n layer 13 and are concentric with the regular hexagons of the second n layer 13. Note that FIG. 1 shows a cross section of the structure of the minimum unit cell of the vertical semiconductor device 1 indicated by the dashed line in FIG. 2, and the device as a whole has a structure in which regular hexagonal unit cells are arranged in a honeycomb pattern and connected in parallel.

[0025] P body electrode 16 is provided continuously from the bottom surface of recess R to the periphery of recess R on second n layer 13. P body electrode 16 is made of Pd.

[0026] Source electrode 17 is provided continuously on p-body electrode 16 and around the periphery of recess R on second n-layer 13. Source electrode 17 is made of a conductive material that makes ohmic contact with second n-layer 13 and is made of Ti / Al. Other materials that can be used include Ti / Al / Ni / Au, TiN / Al, Pd / Ti / Al, and Ti / Al / Pd.

[0027] Drain electrode 18 is provided in contact with the rear surface of substrate 10 (the surface opposite to the surface on which first n-layer 11 is provided). Drain electrode 18 is made of a conductive material that forms ohmic contact with substrate 10, and is the same material as source electrode 17. Of course, different materials may be used for source electrode 17 and drain electrode 18 as long as they form ohmic contact.

[0028] 2. Manufacturing method of vertical semiconductor device 1 Next, a method for manufacturing the vertical semiconductor device 1 of the first embodiment will be described with reference to the flow chart shown in FIG.

[0029] First, in step S1 shown in FIG. 3, a wafer formation process is performed to form a wafer 20a in which a semiconductor layer 20 is stacked on a substrate 10. In the wafer formation process S1, a substrate 10 made of n-GaN with a c-plane as the primary surface is prepared, and a first n-layer 11, a p-layer 12, and a second n-layer 13 are sequentially formed by MOCVD to form the semiconductor layer 20 (see FIG. 4). In the MOCVD process, the nitrogen source is ammonia, the Ga source is trimethylgallium (Ga(CH3)3:TMG), the In source is trimethylindium (In(CH3)3:TMI), and the Al source is trimethylaluminum (Al(CH3)3:TMA). The n-type dopant gas is silane (SiH4), and the p-type dopant gas is cyclopentadienylmagnesium (Mg(C5H5)2:CP2Mg). The carrier gas is hydrogen or nitrogen.

[0030] Next, in step S2 of FIG. 3, a trench formation step is performed in which trenches T are formed by dry etching the surface of the second n layer 13 at predetermined pattern positions (see FIG. 5). A chlorine-based gas is used for dry etching in the trench formation step S2. Examples include Cl2, SiCl4, and CCl4. Any dry etching method, such as ICP etching, can be used. In this embodiment 1, recesses R are also formed in the trench formation step S2. The trenches T are formed by dry etching through the second n layer 13 and the p layer 12 until the first n layer 11 is exposed. The recesses R are formed by dry etching until the p layer 12 is exposed. It is not important to form either the trenches T or the recesses R first.

[0031] Since the dry etching in the trench formation step S2 forms damaged layers on the side surfaces Tb of the trench T and the side surfaces of the recess R, the damaged layers may be removed by wet etching. This can reduce current leakage through the side surfaces. In this case, tetramethylammonium hydroxide (TMAH) or the like can be used as a wet etching solution.

[0032] 3, a gate insulating film formation process is performed in which a gate insulating film 14 made of SiO2 is formed on the entire surface of the semiconductor layer 20 by a CVD method (see FIG. 6). Note that the gate insulating film 14 may be formed by an ALD method, sputtering, or the like instead of the CVD method.

[0033] Next, in step S4, a gate electrode formation step is performed in which a gate electrode 15 made of TiN, TiN / Al / Ti, W, or the like is formed on the entire surface of the gate insulating film 14 by sputtering (see FIG. 7).

[0034] 3, a gate electrode resist mask forming step is performed in which a resist mask 21 is formed on the gate electrode 15 in a position that covers a projection area of ​​the trench T projected in the stacking direction and the periphery of the projection area (see FIG. 8). The resist mask 21 can be formed by photolithography. The material of the resist mask 21 is not limited, and a known material can be used.

[0035] 3, a gate electrode removal process is performed in which the gate electrode 15 is removed by dry etching except for the region directly under the resist mask 21 (see FIG. 9). The etching gas can be, for example, a mixed gas of Cl2 and BCl3, and any method can be used for dry etching, such as ICP etching. As a result, the gate electrode 15 remains in the form of a continuous film on the bottom surface Ta of the trench T, the side surface Tb of the trench T, and the top surface Tc of the second n layer 13 near the side surface Tb of the trench T, via the gate insulating film 14.

[0036] 3, a gate electrode resist mask removal step is performed in which a remover F for removing the resist mask 21 is sprayed onto the surface of the semiconductor layer 20 from a spray nozzle 31 provided in the removal device 30 to remove the resist mask 21 (see FIG. 10). The type of remover F is not limited, but examples that can be used include NMP (N-methyl-2-pyrrolidone) and DMSO (dimethyl sulfoxide). In the gate electrode resist mask removal step S7, the distance D between the spray nozzle 31 and the upper surface of the wafer 20a can be set within a range of 5 to 50 mm.

[0037] When the ejection pressure of the remover F ejected from the ejection nozzle 31 is P [MPa] and the protrusion length of the protrusion portion 15a of the gate electrode 15 is L [μm], the two satisfy the relationship P / L [MPa / μm]≦34 [MPa / μm]. The value P of the ejection pressure of the remover F can be set to, for example, 3 to 12 MPa. The protrusion length L of the protrusion portion 15a can be set to, for example, within the range of 0.1 to 0.5 μm.

[0038] 15, the stripping device 30 includes a spray nozzle 31 that sprays the stripping solution F, as well as a turntable 32. The turntable 32 has a wafer 20a that constitutes the semiconductor layer 20 placed on its upper surface, and is configured to be rotatable around an axis C that is parallel to the stacking direction of the semiconductor layer 20 on the wafer by a drive mechanism 33. The rotation speed of the turntable 32 is controlled within a range of 100 to 1000 rpm by a rotation control unit 34 that controls the drive of the drive mechanism 33.

[0039] In the gate electrode resist mask removing step S7, while the wafer 20a is rotated on the turntable 32, the spray nozzle 31 sprays the remover F and moves across the wafer 20a as shown by the arrow 31a. The spray nozzle 31 may move back and forth across the wafer 20a repeatedly while spraying the remover F. The moving speed of the spray nozzle 31 is not particularly limited. In the gate electrode resist mask removing step S7, the resist mask 21 is removed while maintaining the length L of the protruding portion 15a (see FIG. 11).

[0040] 3, a gate insulating film resist mask forming step is performed to form a resist mask 22 for the gate insulating film. The resist mask 22 can be formed by photolithography. The resist mask 22 is formed in the same position as the resist mask 21 (see FIG. 12).

[0041] Next, in step S9 of FIG. 3, the gate insulating film 14 is removed by dry etching except for the region directly under the resist mask 22 for the gate insulating film (see FIG. 13). The etching gas is, for example, a fluorine-based gas or a chlorine-based gas. A fluorine-based gas is particularly preferred. This allows the gate insulating film 14 to be etched more easily. Instead of dry etching, wet etching may be used. In this case, the wet etching solution is, for example, hydrofluoric acid or buffered hydrofluoric acid. Hydrofluoric acid is particularly preferred. This allows the gate insulating film 14 to be etched more easily. This etching leaves the gate insulating film 14 in a continuous film form on the bottom surface Ta of the trench T, the side surface Tb of the trench T, and the upper surface Tc of the second n layer 13 near the side surface Tb of the trench T. Then, the resist mask 22 for the gate insulating film is removed (see FIG. 14).

[0042] 3, p-body electrode 16 and source electrode 17 are formed in this order using a lift-off method. Furthermore, drain electrode 18 is formed on the back surface of substrate 10 using a lift-off method, thereby completing vertical semiconductor device 1 (see FIG. 1). Note that drain electrode 18 may be formed before p-body electrode 16. Alternatively, gate insulating film 14 and gate electrode 15 may be formed in this order after source electrode 17 is formed.

[0043] Although a resist mask is used as a mask for patterning the gate insulating film 14 and the gate electrode 15 in the first embodiment, a material other than resist may be used as long as it is resistant to both etching processes. However, using a resist mask as in the first embodiment is simple and preferable.

[0044] 3. Confirmation test Next, in the gate electrode resist mask removal step S7 of the manufacturing method of the vertical semiconductor device 1, a test was conducted to confirm whether or not there was any damage to the protruding portion 15a of the gate electrode 15 when the value of P / L [MPa / μm] was changed.

[0045] The test conditions were as follows, and the combinations of the respective values ​​for Test Examples 1 to 5 and Comparative Example 1 were as shown in Table 1. Then, the above-mentioned gate electrode resist mask removing step S7 was carried out. Gate insulating film: SiO2 Gate electrode: TiN Stripping solution: ST120 (Tokyo Ohka Kogyo Co., Ltd.) Distance between the spray nozzle and the wafer: 10 mm Injection nozzle pressure P: 6MPa, 8MPa Gate electrode protrusion length L: 0.20, 0.25, 0.30, 0.35 (μm)

[0046] [Table 1]

[0047] In Table 1, the defect occurrence probability indicates the proportion of gate electrodes 15 that have defects in the entire wafer. The relationship between the defect occurrence probability and P / L is shown in Figure 16. The evaluation results were evaluated as follows: a defect occurrence probability of 20% or less was considered a good product (◯), 0% was considered the best product (◎), and anything over 20% was considered a defective product (×). As shown in Figure 16, it was confirmed that if P / L ≦ 34 MPa / μm, a good product was evaluated, and if P / L ≦ 24 MPa / μm, a best product was evaluated. Therefore, it is sufficient if P / L ≦ 34 MPa / μm, and more preferably P / L ≦ 24 MPa / μm.

[0048] 4. Effects According to the manufacturing method of the vertical semiconductor device 1 of the first embodiment, in the gate electrode resist mask removal step S7, the spray pressure P [MPa] of the remover F and the length L [μm] of the protruding portion 15a at the interface between the gate electrode 15 and the gate insulating film 14 satisfy the relationship P / L≦34 [MPa / μm]. This makes it easier to maintain the bond between the gate electrode 15 and the gate insulating film 14 at the protruding portion 15a formed around the periphery of the opening of the trench R in the gate electrode 15 against the spray pressure of the remover F when removing the resist mask 21. As a result, peeling of the protruding portion 15a of the gate electrode 15 can be reduced, and damage to the gate electrode 15 can be suppressed. As a result, the yield can be improved.

[0049] Furthermore, in the first embodiment, in the gate electrode resist mask removal step S7, the distance D between the tip of the jet nozzle 31 and the surface of the wafer 20a is within a range of 5 to 50 mm. Therefore, if the distance D between the tip of the jet nozzle 31 and the surface of the wafer is less than 5 mm, the tip of the jet nozzle 31 may come into physical contact with the surface of the wafer 20a due to shaking of the jet nozzle or wafer caused by the spraying of the stripping solution F in the gate electrode resist mask removal step S7, which may damage the wafer 20a or the gate electrode 15 formed on the wafer. Furthermore, if the distance between the tip of the jet nozzle 31 and the surface of the wafer 20a is greater than 50 mm, the stripping solution F sprayed from the jet nozzle 31 may scatter before reaching the surface of the wafer 20a, and the required resist mask removal power may not be obtained.

[0050] In the first embodiment, in the gate electrode resist mask removal step S7, the resist mask 21 is removed by spraying the stripping solution F from the spray nozzle 31 onto the surface of the wafer 20a while rotating the wafer 20a around an axis C parallel to the stacking direction Y. This prevents the resist mask 21 and the stripping solution C removed by the stripping solution F from remaining on the surface of the wafer 20a, thereby improving the ability to remove the resist mask 21.

[0051] In addition, in the present embodiment 1, the rotation speed of the wafer 20a is preferably within a range of 100 rpm to 1000 rpm. In this case, the stripping solution F sprayed from the spray nozzle 31 can be more easily spread evenly over the surface of the wafer 20a, and the ability to remove the resist mask 21 can be further improved.

[0052] Furthermore, in the gate electrode resist mask removing step S7 of the present embodiment 1, the spray pressure P of the remover F is within a range of 3 to 12 MPa. This allows for a well-balanced removal of the resist mask 21, which is physical removal caused by the remover F colliding with the resist mask 21 to remove the resist mask 21, and also chemical removal caused by the decomposition of the resist mask 21 due to a chemical reaction between the remover F and the resist mask, thereby further improving the ability to remove the resist mask 21 while suppressing damage to the gate electrode 15.

[0053] In this embodiment 1, a MOSFET is used as the vertical semiconductor device 1, but this is not limited to this, and other semiconductor devices (IGBT, HEMT, SBD) can be used as long as they have a structure in which an insulating film and an electrode are formed in the trench T.

[0054] As described above, according to the above embodiment, it is possible to provide a method for manufacturing the vertical semiconductor device 1 that can prevent defects from occurring in the gate electrode 15 due to removal of the resist mask 21.

[0055] The present invention is not limited to the above-described embodiments, and can be applied to various embodiments within the scope of the present invention. [Explanation of symbols]

[0056] 1 Vertical semiconductor device 10 Substrate 11 First n-layer 12 p layer 13 Second n-layer 14 Gate insulating film 15 gate electrode 15a Protruding part 16 p-body electrode 17 Source electrode 18 Drain electrode 20 Semiconductor layer 20a wafer 21, 22 Resist mask 30 Peeling device 31 Injection nozzle 32 Rotating Platform 33 Drive mechanism 34 Rotation control section

Claims

1. A method for manufacturing a vertical semiconductor device in which a gate electrode is embedded in a trench formed in a semiconductor layer via a gate insulating film, comprising the steps of: a trench forming step of forming the trench on the wafer made of the semiconductor layer; a gate insulating film forming step of forming the gate insulating film on the surface of the wafer including the trench; a gate electrode forming step of forming the gate electrode on the gate insulating film; a gate electrode resist mask forming step of forming a resist mask covering a region of the gate electrode covering the trench and a periphery of the trench; a gate electrode removing step of removing a region of the gate electrode where the resist mask is not provided; a gate electrode resist mask removing step of removing the resist mask by spraying a stripping liquid for stripping the resist mask from a spray nozzle onto the surface of the semiconductor layer; Including, The ejection pressure of the stripping solution ejected from the ejection nozzle is P [MPa], In a cross section parallel to the stacking direction of the semiconductor layers and perpendicular to the extension direction of the trench as viewed from the stacking direction of the semiconductor layers, a protruding portion of a junction surface between the gate electrode and the gate insulating film, the protruding portion extending in a direction perpendicular to the stacking direction of the semiconductor layers outside the trench, is defined as L [μm]. P / L≦34 [MPa / μm] The present invention relates to a method for manufacturing a vertical semiconductor device.

2. 2. The method for manufacturing a vertical semiconductor device according to claim 1, wherein in said gate electrode resist mask removing step, a distance between a tip of said jet nozzle and the surface of said wafer is within a range of 5 to 50 mm.

3. 3. The method for manufacturing a vertical semiconductor device according to claim 1, wherein in the gate electrode resist mask removing step, the resist mask is removed by spraying the stripping solution from the spray nozzle onto the surface of the wafer while rotating the wafer around an axis parallel to the stacking direction.

4. 4. The method for manufacturing a vertical semiconductor device according to claim 3, wherein the rotation speed of the wafer is within a range of 100 rpm to 1000 rpm.

5. 3. The method for manufacturing a vertical semiconductor device according to claim 1, wherein in the gate electrode resist mask removing step, a spray pressure P of the stripping solution is within a range of 3 to 12 MPa.

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