Inspection circuit for semiconductor wafer

Abstract

To provide an inspection circuit for a semiconductor wafer that can measure the dielectric strength of a semiconductor element for monitor test with high precision in a short time.SOLUTION: The present invention relates to an inspection circuit 100 for a semiconductor wafer provided in a PCMTEG region formed on a surface of a semiconductor substrate, and the inspection circuit has: a MOS transistor M1 and a MOS transistor M2 which are connected in parallel between a VDD terminal P1 and a VSS terminal P2; a resistance element R1 which is connected in series with the MOS transistor M1 between the VDD terminal P1 and MOS transistor M1; and a resistance element R2 which is connected between the VDD terminal P1 and MOS transistor M2 in series with the MOS transistor M2 so as to be parallel with the resistance element R1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor wafer test circuit. [Background technology]

[0002] The semiconductor elements (called internal elements) used in semiconductor integrated circuits are easily damaged by the intrusion of external electrical noise such as static electricity due to miniaturization and the adoption of an electric field relaxation structure. For this reason, protective elements that are highly resistant to electrical noise are installed on all electrode pads to which external signals are input.

[0003] The protective element temporarily operates to pass noise to a ground terminal or the like without affecting the internal element. Therefore, the electrical characteristics required for this protective element include, first, that it is not completely destroyed when a predetermined voltage or current assumed to be electrical noise is applied. The second electrical characteristic includes that the temporary operation of the protective element starts at a voltage higher than the maximum operating voltage required for the semiconductor integrated circuit and lower than the breakdown voltage of the internal element. This second electrical characteristic allows the protective element to protect the internal element from noise by passing most of the current due to noise to a ground terminal or the like by the temporary operation of the protective element so that the internal element is not destroyed when electrical noise enters and the potential of the electrode pad rises.

[0004] In the manufacture of semiconductor integrated circuits, whether or not the protective element is formed so that its activation voltage is equal to or lower than the breakdown voltage of the internal element is confirmed by electrically measuring and inspecting the internal element and the protective element for monitor testing formed on the semiconductor wafer. Such internal element and protective element are formed in a PCMTEG region on the semiconductor wafer as a process control monitor test element group (hereinafter referred to as PCMTEG).

[0005] Since the productivity of the manufacturing process of semiconductor integrated circuits can be improved if the measurement time of PCMTEG can be reduced, various proposals have been made to reduce the measurement time. For example, in order to reduce the measurement time by minimizing the movement of the probe, a proposal was made for a semiconductor device in which the PCMTEG region is divided into a main region and a sub-region, and all TEGs having standardized electrical characteristic values ​​are arranged together in the sub-region (see Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2021-12970 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one aspect of the present invention is to provide a semiconductor wafer inspection circuit that can measure the withstand voltage of a monitor test semiconductor element in a short time with high accuracy. [Means for solving the problem]

[0008] In one embodiment of the present invention, a semiconductor wafer inspection circuit includes: A semiconductor wafer inspection circuit provided in a PCMTEG region formed on a surface of a semiconductor substrate, comprising: a first semiconductor element and a second semiconductor element connected in parallel between a first power supply terminal and a second power supply terminal; a first resistance element connected in series with the first semiconductor element between the first power supply terminal and the first semiconductor element; a second resistance element connected in series with the second semiconductor element between the first power supply terminal and the second semiconductor element so as to be in parallel with the first resistance element; has. Effect of the Invention

[0009] An object of one aspect of the present invention is to provide a semiconductor wafer inspection circuit that can measure the withstand voltage of a monitor test semiconductor element in a short time with high accuracy. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram showing an inspection circuit for a semiconductor wafer provided in a PCMTEG region in the first embodiment. [Diagram 2] FIG. 2 is a graph showing the results of measuring the IV characteristics of the inspection circuit in the first embodiment. [Diagram 3] FIG. 3 is a graph showing the results of measuring the IV characteristics of the inspection circuit in the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In recent years, the increase in the scale of semiconductor integrated circuits and the accompanying progress in miniaturization have led to a decrease in the maximum operating voltage of semiconductor integrated circuits, as well as a decrease in the breakdown voltage (withstand voltage) of internal elements. At the same time, there is a tendency for the voltage difference between the maximum operating voltage and the breakdown voltage of the internal elements to also decrease. Therefore, in order to confirm that the protection elements operate at a lower voltage than the internal elements, it is necessary to measure multiple monitor test elements with high accuracy at voltages as small as possible, making it difficult to reduce the test time.

[0012] Therefore, in one embodiment of the present invention, a semiconductor wafer inspection circuit is configured such that, within the PCMTEG area, semiconductor elements for monitor testing are connected in parallel between a first power supply terminal and a second power supply terminal, and a resistive element is connected in series to each semiconductor element.

[0013] As a result, when a sweep voltage is applied between the first and second power supply terminals from a low to a high voltage, even if the semiconductor element is destroyed and short-circuited, the two power supply terminals will not be short-circuited and the current will increase according to the resistance value of the resistive element, making it possible to obtain a stepped IV characteristic without reaching the current limit of the power supply. By setting the voltage at which the current suddenly increases in this IV characteristic as the withstand voltage of each semiconductor element, multiple withstand voltage measurements can be performed in a short time with a single sweep application, and high-precision measurements can be performed by applying a sweep voltage in fine steps.

[0014] Furthermore, the resistance values ​​of the resistor elements connected in series to the semiconductor elements may be different.

[0015] As a result, when a semiconductor element is destroyed and short-circuited, a current corresponding to the resistance value of the resistive element connected in series with the semiconductor element flows suddenly; however, by determining in advance a standard corresponding to the increase in this current, it is possible to identify the semiconductor element that has been destroyed and short-circuited.

[0016] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0017] In the drawings, the same components are denoted by the same reference numerals, and duplicate explanations may be omitted. (First embodiment) In addition to the semiconductor chips that will become the products, semiconductor wafers are also equipped with process control monitor test element groups (hereinafter referred to as PCMTEG) to check the progress of the semiconductor wafer manufacturing process.

[0018] The PCMTEG region is the region where the PCMTEG is provided, and is formed in one or more locations on the semiconductor wafer. This PCMTEG region may be located in a scribe line region for cutting out multiple semiconductor chips (scribe line TEG), or may be located in a specific region without forming a semiconductor chip (external TEG).

[0019] Fig. 1 is a circuit diagram showing an inspection circuit for a semiconductor wafer provided in a PCMTEG region in the first embodiment. Fig. 1 shows an inspection circuit 100 in which MOS (Metal-Oxide-Semiconductor) transistors M1 and M2, which are semiconductor elements for monitor testing, are connected in parallel between a VDD terminal P1, which is a first power supply terminal, and a VSS terminal P2, which is a second power supply terminal, in the PCMTEG region.

[0020] The gate terminals of the MOS transistors M1 and M2 serving as the first and second semiconductor elements are connected to the VSS terminal P2. Furthermore, the MOS transistors M1 and M2 are connected in series with resistance elements R1 and R2, respectively.

[0021] The MOS transistor M1 is formed in the PCMTEG region in a process for forming an electrostatic protection element, known as an "off transistor" or "ggNMOS (gate grounded NMOS)", on a semiconductor chip. The MOS transistor M1 is set to have a lower breakdown voltage than the MOS transistor M2.

[0022] The MOS transistor M2 is formed in the PCMTEG region in a process for forming internal elements in a semiconductor chip. The withstand voltage of the MOS transistor M2, which corresponds to the internal element, is set higher than the withstand voltage of the MOS transistor M1, which corresponds to the protection element.

[0023] The first and second resistor elements R1 and R2 are polysilicon films doped with impurities by ion implantation. The resistance values ​​of the resistor elements R1 and R2 are adjusted by their lengths and widths, and the impurity concentrations may be different.

[0024] The IV characteristics of the inspection circuit 100 are obtained by applying a voltage V between the VDD terminal P1 and the VSS terminal P2 in a sweep manner from a low voltage to a high voltage, and measuring a current I flowing through the VSS terminal P2.

[0025] FIG. 2 is a graph showing the results of measuring the IV characteristics of the inspection circuit in the first embodiment.

[0026] As shown in Figure 2, when the voltage V is applied in a sweep from low to high voltages, the current I increases suddenly each time a MOS transistor breaks down and shorts, so the IV characteristics are observed in a step-like pattern. From this IV characteristic, it can be recognized that the voltages V1 and V2 at which the current I increases suddenly are the breakdown voltages of either the MOS transistors M1 or M2.

[0027] In this embodiment, since the MOS transistor M1 is a protection element and the MOS transistor M2 is an internal element, it can be inferred that the voltage V1 is the breakdown voltage of the MOS transistor M1, which has a low withstand voltage, and the voltage V2 is the breakdown voltage of the MOS transistor M2, which has a high withstand voltage.

[0028] In this way, the resistance elements R1 and R2 are connected in series to the MOS transistors M1 and M2, which are connected in parallel, respectively, so that the breakdown voltage of multiple MOS transistors can be measured with one sweep application. Therefore, even if the measurement is performed with fine voltage steps, the measurement can be performed in a short time, and as a result, highly accurate measurements can be performed in a short time.

[0029] In this embodiment, the semiconductor elements are two MOS transistors M1 and M2, but the more semiconductor elements for monitor testing there are, the greater the effect of shortening the measurement time. Second Embodiment In the second embodiment, the resistance value r1 of the resistive element R1 in the first embodiment is made different from the resistance value r2 of the resistive element R2, so that it is possible to identify at which voltage either of the MOS transistors M1 and M2 is destroyed.

[0030] Specifically, consider the case where the resistance value r1 of resistor element R1 is made greater than the resistance value r2 of resistor element R2. In this case, if "ΔI1" is the increase in current that flows when MOS transistor M1 breaks down and shorts out, and "ΔI2" is the increase in current that flows when MOS transistor M2 breaks down and shorts out, then the following equation is obtained: ΔI1<ΔI2. By setting a standard for this current increase in advance, it is possible to identify at what voltage either MOS transistor M1 or M2 has broken down based on the IV characteristics.

[0031] FIG. 3 is a graph showing the results of measuring the IV characteristics of the inspection circuit in the second embodiment.

[0032] 3, when the voltage is lower than voltage V1, MOS transistors M1 and M2 are not destroyed, and the current I flowing into VSS terminal P2 is low and falls within the range of standard 1. Next, when the sweep voltage becomes voltage V1 and MOS transistor M1 is destroyed and short-circuited, an increased current ΔI1 = V1 / r1 according to the resistance value r1 of resistor R1 is added, and current I falls within the range of standard 2. Then, when the sweep voltage becomes voltage V2 and MOS transistor M2 is destroyed and short-circuited, an increased current ΔI2 = V2 / r2 according to the resistance value r2 of resistor R2 is further added, and current I falls within the range of standard 4.

[0033] 3, when the sweep voltage is V1, MOS transistor M2 will break down and short-circuit before MOS transistor M1, and the current I with the additional current ΔI3=V1 / r2 will fall within the range of standard 3. When the sweep voltage becomes V2 and MOS transistor M1 breaks down and shorts out, an additional current ΔI4=V2 / r1 will be added, and the current I will fall within the range of standard 4.

[0034] In this way, by making the resistance values ​​of the resistive elements connected in series with each MOS transistor different, it is possible to identify which MOS transistor has been destroyed based on the range of specifications within which the current I falls.

[0035] In particular, since the breakdown voltage of internal elements is decreasing as the maximum operating voltage of semiconductor integrated circuits decreases, it is extremely useful to be able to identify a destroyed MOS transistor when the difference between the withstand voltage of the protection element and the withstand voltage of the internal elements is small.

[0036] Specifically, even if the withstand voltages of the respective semiconductor elements are set differently, if the difference between the maximum operating voltage and the withstand voltage of the internal element is reduced, the magnitude relationship between them may be reversed due to manufacturing variations, resulting in manufacturing defects. For example, if the protective element has a higher withstand voltage than the internal element, the electrostatic resistance will drop significantly, but by adopting this embodiment, it is possible to detect manufacturing defects at the electrical characteristics inspection stage after semiconductor wafer manufacturing without performing a complicated electrostatic resistance test.

[0037] Next, an inspection method for determining whether or not a semiconductor wafer can be shipped using the inspection circuit of this embodiment will be described.

[0038] The inspection program used in this inspection method is as follows.

[0039] In the inspection program, the current specification values ​​S2, S3, and S4 for determining whether or not a product can be shipped are set based on the expected withstand voltages V1 and V2 of the MOS transistors M1 and M2 as shown in the following equations (1), (2), and (3).

[0040] 0 <S2<V1 / r1 ···(1) V1 / r2 <S3<V1 / r2 ···(2) V1 / r2 <S4<V2 / r2 ···(3) The inspection program then measures the IV characteristics of the inspection circuit of the semiconductor wafer in this embodiment, and stores the voltage values ​​when the acquired IV characteristics exceed the current standard values ​​S2, S3, and S4, respectively, as VM2, VM3, and VM4 in a specified memory unit.

[0041] When any one of VM1, VM2, and VM3 stored in the specified storage unit is equal to or lower than the maximum operating voltage of the semiconductor chip that becomes the product, since the desired operation of the semiconductor chip cannot be expected, it is determined as "not shippable".

[0042] Also, when the breakdown voltage of MOS transistor M1 is lower than the breakdown voltage of MOS transistor M2, the I-V characteristics shown by the solid line in FIG. 3 are obtained, so the following equation holds: VM2 < VM3 = VM4. For such measurement results, since it is a tendency in line with the initial assumption, it is determined as "shippable".

[0043] Furthermore, when the breakdown voltage of MOS transistor M1 is higher than the breakdown voltage of MOS transistor M2, the I-V characteristics shown by the broken line in FIG. 3 are obtained, so the following equation holds: VM2 = VM3 < VM4. For such measurement results, since the desired electrostatic resistance cannot be expected, it is determined as "not shippable".

[0044] Note that in this embodiment, the breakdown voltages of MOS transistors M1 and M2 are made different, but it may be applied to semiconductor elements that are expected to have the same structure in design and the same breakdown voltage. For example, even if the semiconductor elements have the same structure in design, their structures may have different breakdown voltages due to manufacturing variations. Therefore, for the purpose of identifying the factor of such variations, it may be possible to identify which semiconductor element was destroyed at which voltage.

[0045] As described above, the inspection circuit of the semiconductor wafer in one embodiment of the present invention is provided in the PCMTEG region formed on the surface of the semiconductor substrate, and includes first and second semiconductor elements connected in parallel between the first power supply terminal and the second power supply terminal. Further, this inspection circuit includes a first resistance element connected between the first power supply terminal and the first semiconductor element, and a second resistance element connected between the first power supply terminal and the second semiconductor element.

[0046] Thereby, this inspection circuit of the semiconductor wafer can perform the breakdown voltage measurement of the semiconductor element for monitor test in a short time and with high accuracy.

[0047] In the above embodiment, the semiconductor elements are MOS transistors, but the present invention is not limited to this and may be, for example, bipolar transistors, diode elements, resistor elements, capacitors, or combinations of these.

[0048] Furthermore, in the above embodiment, the number of semiconductor elements is limited to two, but three or more semiconductor elements may be mounted. [Explanation of symbols]

[0049] 100 Inspection circuit M1 MOS transistor (first semiconductor element) M2 MOS transistor (second semiconductor element) P1 VDD pin (first power supply pin) P2 VSS pin (second power supply pin) R1 Resistor element (first resistor element) R2 Resistor element (second resistor element)

Claims

1. A semiconductor wafer inspection circuit provided in a PCMTEG region formed on a surface of a semiconductor substrate, comprising: a first semiconductor element and a second semiconductor element connected in parallel between a first power supply terminal and a second power supply terminal; a first resistance element connected in series with the first semiconductor element between the first power supply terminal and the first semiconductor element; a second resistance element connected in series with the second semiconductor element between the first power supply terminal and the second semiconductor element so as to be in parallel with the first resistance element; 1. A semiconductor wafer inspection circuit comprising:

2. 2. The semiconductor wafer inspection circuit according to claim 1, wherein a first resistance value of the first resistive element is different from a second resistance value of the second resistive element.

3. 3. The semiconductor wafer inspection circuit according to claim 2, wherein the withstand voltage of the first semiconductor element is different from that of the second semiconductor element.

4. The first semiconductor element is formed in a process for forming a protection element, 4. The semiconductor wafer inspection circuit according to claim 3, wherein the second semiconductor element is formed in a process for an internal element having a withstand voltage higher than a withstand voltage of the protection element.

5. 5. The semiconductor wafer inspection circuit according to claim 1, wherein the first semiconductor element and the second semiconductor element are both MOS transistors.

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