Semiconductor device and method for manufacturing the same

Abstract

To electrically separate a temperature detection diode from an active portion.SOLUTION: A semiconductor device includes: a semiconductor substrate having an upper surface; an upper-surface cathode region of a first conductivity type provided in the semiconductor substrate and exposed to the upper surface; an upper-surface anode region of a second conductivity type provided in the semiconductor substrate and exposed to the upper surface; an anode electrode connected to the upper-surface anode region; a cathode electrode connected to the upper-surface cathode region; an isolation trench portion provided from the upper surface toward an inside of the semiconductor substrate and surrounding the upper-surface anode region and the upper-surface cathode region on the upper surface; a first bottom region of the second conductivity type provided below the upper-surface anode region and the upper-surface cathode region so as to overlap with the entire upper-surface anode region and upper-surface cathode region and be in contact with a lower end of the isolation trench portion; and a first region of the first conductivity type provided between the upper-surface anode region and the first bottom region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventionally, silicon carbide semiconductor devices having a temperature detection region are known (see, for example, Patent Document 1). Also, efforts have been made to improve the temperature detection accuracy of a temperature detection diode (see, for example, Patent Document 2). Patent Document 1: JP2022-191813 Patent Document 2: JP-A-9-36356 Summary of the Invention [Problem to be solved by the invention]

[0003] The temperature sensing diode is preferably electrically isolated from the active portion. [Means for solving the problem]

[0004] In a first aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate having an upper surface. The semiconductor device may include a first conductive type upper cathode region provided in the semiconductor substrate and exposed to the upper surface. Any of the semiconductor devices may include a second conductive type upper anode region provided in the semiconductor substrate and exposed to the upper surface. Any of the semiconductor devices may include an anode electrode connected to the upper anode region. Any of the semiconductor devices may include a cathode electrode connected to the upper cathode region. Any of the semiconductor devices may include an isolation trench portion provided from the upper surface toward the inside of the semiconductor substrate and surrounding the upper anode region and the upper cathode region on the upper surface. Any of the semiconductor devices may include a second conductive type first bottom region provided below the upper anode region and the upper cathode region, overlapping the entire upper anode region and the upper cathode region, and contacting a lower end of the isolation trench portion. Any of the above semiconductor devices may further comprise a first region of a first conductivity type provided between the top anode region and the first bottom region.

[0005] Any of the above semiconductor devices may further include a transistor portion or a diode portion provided in the semiconductor substrate in a region different from a region surrounded by the isolation trench portion. Any of the above semiconductor devices may further include an active portion which is a region in which the transistor portion or the diode portion is provided. Any of the above semiconductor devices may further include an emitter electrode provided above the top surface of the active portion. In any of the above semiconductor devices, the first bottom region may be electrically connected to the emitter electrode.

[0006] Any of the above semiconductor devices may further include a well region of a second conductivity type provided from the top surface to an interior of the semiconductor substrate and surrounding the active portion on the top surface. In any of the above semiconductor devices, the first bottom region may be electrically connected to the emitter electrode via the well region.

[0007] Any of the above semiconductor devices may further comprise a second region of a second conductivity type provided between the top surface cathode region and the first region.

[0008] Any of the above semiconductor devices may further include a transistor portion provided in the semiconductor substrate in a region different from a region surrounded by the isolation trench portion, and an active portion in which the transistor portion is provided. In any of the above semiconductor devices, a first contact region of a second conductivity type may be provided in the active portion in contact with the top surface of the semiconductor substrate. In any of the above semiconductor devices, the top anode region may include a junction region in contact with the top cathode region and having a doping concentration lower than that of the first contact region. In any of the above semiconductor devices, the top anode region may include a second contact region of a second conductivity type disposed away from the top cathode region and having a doping concentration equal to that of the first contact region.

[0009] In any of the above semiconductor devices, the isolation trench portion may have a frame trench portion surrounding the upper surface anode region and the upper surface cathode region, and an internal trench portion provided in a region surrounded by the frame trench portion. In any of the above semiconductor devices, the frame trench portion may be separated from the internal trench portion.

[0010] In any of the above semiconductor devices, the internal trench portion may extend in an extension direction and be separated into a plurality of portions along the extension direction.

[0011] In any of the above semiconductor devices, the internal trench portion may be separated at a junction between the upper surface anode region and the upper surface cathode region.

[0012] Any of the above semiconductor devices may further include a transistor portion or a diode portion provided in the semiconductor substrate in a region different from a region surrounded by the isolation trench portion, an active portion which is a region in which the transistor portion or the diode portion is provided, and a plurality of active trench portions in the active portion extending from the top surface toward the inside of the semiconductor substrate. In any of the above semiconductor devices, a distance separating the frame trench portion and the internal trench portion may be equal to or less than a distance between the active trench portions.

[0013] Any of the above semiconductor devices may further include a transistor portion or a diode portion provided in the semiconductor substrate in a region different from the region surrounded by the isolation trench portion, and an active portion in which the transistor portion or the diode portion is provided. Any of the above semiconductor devices may further include a well region of a second conductivity type provided from the upper surface to the inside of the semiconductor substrate and surrounding the active portion on the upper surface. Any of the above semiconductor devices may further include a connection trench portion disposed between the isolation trench portion and the well region and provided from the upper surface toward the inside of the semiconductor substrate. In any of the above semiconductor devices, the first bottom region may be in contact with a lower end of the connection trench portion.

[0014] Any of the above semiconductor devices may further include a transistor portion or a diode portion provided in the semiconductor substrate in a region different from a region surrounded by the isolation trench portion, an active portion in which the transistor portion or the diode portion is provided, and a plurality of active trench portions in the active portion extending from the top surface toward the inside of the semiconductor substrate. In any of the above semiconductor devices, the distance between the isolation trench portion and the connection trench portion may be equal to or less than the interval between the active trench portions.

[0015] Any of the above semiconductor devices may further include a transistor portion provided in the semiconductor substrate. In any of the above semiconductor devices, the transistor portion may have a gate trench portion provided from the upper surface toward the inside of the semiconductor substrate, and a second bottom region of a second conductivity type provided at a lower end of the gate trench portion.

[0016] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a semiconductor substrate having an upper surface. In the method for manufacturing a semiconductor device, an isolation trench may be formed from the upper surface toward the inside of the semiconductor substrate. In any of the methods for manufacturing a semiconductor device, a first bottom region of a second conductivity type may be formed in contact with a lower end of the isolation trench. In any of the methods for manufacturing a semiconductor device, a first region of a first conductivity type may be formed between the upper surface and the first bottom region. In any of the methods for manufacturing a semiconductor device, a first conductivity type upper surface cathode region and a second conductivity type upper surface anode region exposed on the upper surface of the region surrounded by the isolation trench may be formed. In any of the methods for manufacturing a semiconductor device, an anode electrode connected to the upper surface anode region and a cathode electrode connected to the upper surface cathode region may be formed.

[0017] In any of the above-described methods for manufacturing a semiconductor device, a trench may be formed from the top surface toward an inside of the semiconductor substrate when forming the isolation trench portion. In any of the above-described methods for manufacturing a semiconductor device, a dopant may be injected through the trench and annealed to diffuse the dopant, thereby forming the first bottom region.

[0018] In any of the above methods for manufacturing a semiconductor device, the trench may have a plurality of portions, and the first bottom region may be formed by annealing the dopants implanted through the plurality of portions so as to be connected to each other. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing an example of a cross section AA in FIG. [Diagram 3] FIG. 2 is a diagram showing a comparative example of a cross section taken along the line AA in FIG. [Figure 4] 2 is a diagram showing another example of the cross section AA in FIG. 1. FIG. [Diagram 5] FIG. 2 is a diagram showing an example of an area B in FIG. [Figure 6] 1. FIG. 4 is a diagram showing another example of the region B in FIG. [Figure 7] 3 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. [Figure 8A] 10 shows a cross-sectional view of the temperature sensing portion 111 at a well region forming step S1000. [Figure 8B] 1 shows a cross-sectional view of the temperature sensing portion 111 at the trench formation step S1002. [Figure 8C] 1 shows a cross-sectional view of the temperature sensing portion 111 at the ion implantation step S1004. [Figure 8D] 1 shows a cross-sectional view of the temperature sensing portion 111 in the annealing step S1006. [Figure 8E] 1 shows a cross-sectional view of the temperature sensing portion 111 in a trench portion forming step S1008. [Figure 8F] 1 shows a cross-sectional view of the temperature sensing portion 111 in the first region and second region forming step S1010. [Figure 8G] 10 shows a cross-sectional view of the temperature sensing portion 111 in the upper anode region / upper cathode region formation step S1012. [Figure 8H] 1 shows a cross-sectional view of the temperature sensing portion 111 in an interlayer insulating film / contact hole forming step S1014. [Figure 8I] 1 shows a cross-sectional view of the temperature sensing portion 111 in electrode formation step S1016. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0021] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0022] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0023] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0024] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0025] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0026] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type.

[0027] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0028] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. In this specification, the outer peripheral edge of the semiconductor substrate 10 in a top view is referred to as an outer peripheral edge 140. The top view refers to a view parallel to the Z-axis from the top surface side of the semiconductor substrate 10. In addition, one of the edges of the outer peripheral edge 140 of the semiconductor substrate 10 in a top view is referred to as a first edge 142. In a top view, a direction parallel to the first edge 142 is referred to as an X-axis direction, and a direction perpendicular to the first edge 142 is referred to as a Y-axis direction.

[0029] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active portion 120, but is omitted in Fig. 1. In this example, the region overlapping with the emitter electrode 52 described below is defined as the active portion 120.

[0030] The active section 120 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a first direction. That is, the first direction is the arrangement direction of the transistor sections 70 and the diode sections 80. The first direction may be the arrangement direction of trench sections described later. The transistor sections 70 or the diode sections 80 may be provided in a region different from the region surrounded by an isolation trench section described later.

[0031] The transistor section 70 and the diode section 80 may each have a longitudinal direction in the second direction. That is, the second direction is the extension direction of the transistor section 70 and the diode section 80. In this specification, the first direction is the X-axis direction, and the second direction is the Y-axis direction. The length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. However, the transistor section 70 and the diode section 80 may have a longitudinal direction in the first direction and be arranged in the second direction.

[0032] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate 10. In this specification, the region in which the diode section 80 is extended in the Y-axis direction to a well region 29 described later may also be included in the diode section 80. A collector region is provided on the lower surface of the extended region.

[0033] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has an N+ type emitter, a P+ type contact region, a P- type base region, a gate trench portion having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0034] A plurality of pad sections (in the example of FIG. 1, an anode pad 114, a cathode pad 115, and a gate pad 116) are provided above the upper surface of the semiconductor substrate 10. The anode pad 114 and the cathode pad 115 are connected to a temperature sensing section 111, which will be described later. The gate pad 116 is connected to a gate conductive section of the transistor section 70. In this example, the gate pad 116 is connected to each gate conductive section via a gate runner provided above the upper surface of the semiconductor substrate 10. The number and types of pad sections provided on the semiconductor substrate 10 are not limited to the example shown in FIG. 1.

[0035] Each pad is made of a metal material such as aluminum. The multiple pad portions are arranged in a predetermined direction between the active portion 120 and a first edge 142 on the upper surface of the semiconductor substrate 10. The multiple pad portions in this example are disposed between the active portion 120 and the first edge 142 in the Y-axis direction. The multiple pad portions in this example are provided above a well region 29, which will be described later.

[0036] The semiconductor substrate 10 has a well region 29. The well region 29 surrounds the transistor section 70 and the diode section 80 in a top view. The well region 29 surrounds the active section 120 in a top view. The well region 29 is a second conductive type region having a higher doping concentration than the base region. The well region 29 in this example is of P+ type. The pad sections in this example are disposed above the well region 29. In FIG. 1, the well region 29 is hatched. The well region 29 may have an extension section 28 that extends from a portion surrounding the active section 120 to a temperature sensing section 111 described later. In this specification, the extension section 28 may be referred to as the well region 29.

[0037] Edge termination structure 90 is provided on the top surface of semiconductor substrate 10, between well region 29 and outer periphery edge 140 of semiconductor substrate 10. Edge termination structure 90 may be arranged in an annular shape surrounding well region 29 on the top surface of semiconductor substrate 10. Edge termination structure 90 in this example is arranged along outer periphery edge 140 of semiconductor substrate 10. Edge termination structure 90 relieves electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 has, for example, a guard ring, a field plate, a resurf, or a structure combining these.

[0038] The temperature sense wiring 112 is provided above the extension 28 of the well region 29. The temperature sense wiring 112 may be a semiconductor wiring. One end of the temperature sense wiring 112 is connected to the temperature sensor 111. The other end of the temperature sense wiring 112 is connected to an anode pad 114 and a cathode pad 115.

[0039] The semiconductor substrate 10 is provided with a temperature sensing section 111. The temperature sensing section 111 in this example is provided in the center of the active section 120. The temperature sensing section 111 may be sandwiched between the active sections 120 in a top view. The temperature sensing section 111 in this example is disposed between the active sections 120 in the X-axis direction. The temperature sensing section 111 in this example is disposed between the active sections 120 and the extension section 28 in the Y-axis direction. A temperature sensing diode, which will be described later, is formed in the temperature sensing section 111, and measures the temperature of the semiconductor substrate 10. As an example, the temperature of the semiconductor substrate 10 may be measured by measuring the forward voltage of the temperature sensing diode at the anode pad 114 and the cathode pad 115. The temperature sensing section 111 may not be included in the active section 120.

[0040] The extension portion 28 may protrude into the active portion 120 along the temperature sense wiring 112 to the vicinity of the temperature sense portion 111. In other words, the temperature sense wiring 112 may be provided above the extension portion 28. The extension portion 28 may be in contact with the temperature sense portion 111, or may surround the temperature sense portion 111 in a top view. The extension portion 28 in this example surrounds the temperature sense portion 111.

[0041] However, like the pad portion, the temperature sensing portion 111 may be provided above the well region 29 surrounding the active portion 120, or may be disposed outside the well region 29 (i.e., between the well region 29 and the outer circumferential edge 140). In that case, the well region 29 does not need to have the extension portion 28. For example, the temperature sensing portion 111 may be provided between the anode pad 114 and the cathode pad 115.

[0042] 2 is a diagram showing an example of an AA cross section in FIG. 1. The AA cross section is an XZ cross section crossing the temperature sensing section 111 and the active section 120. In this example, a transistor section 70 is provided in the active section 120 adjacent to the temperature sensing section 111. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, an anode electrode 81, a cathode electrode 83, and a collector electrode 24. The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are the two main surfaces of the semiconductor substrate 10.

[0043] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A contact hole 54 is provided in the interlayer insulating film 38.

[0044] The emitter electrode 52 is provided above the upper surface 21 of the active portion 120. The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the emitter region 12 and the first contact region 15 provided on the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. A contact trench may be provided at a connection portion between the emitter electrode 52 and the emitter region 12 and the first contact region 15. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0045] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the temperature sensing section 111.

[0046] The transistor section 70 has a plurality of trench sections arranged in the arrangement direction (X-axis direction). In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are provided along the arrangement direction. The gate trench sections 40 and the dummy trench sections 30 are provided from the upper surface 21 of the semiconductor substrate 10 toward the inside. In this specification, the trench sections provided in the active section 120 may be referred to as active trench sections.

[0047] Mesa portions 60 are provided between the active trench portions in the arrangement direction. The mesa portions 60 refer to regions within the semiconductor substrate 10 that are sandwiched between the active trench portions. As an example, the upper end of the mesa portion 60 is the upper surface 21 of the semiconductor substrate 10, and the depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the active trench portion. The mesa portions 60 in this example are provided on the upper surface 21 of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the active trench portions.

[0048] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12, a P+ type first contact region 15, and a P type base region 14 are provided on the upper surface 21 side of the semiconductor substrate 10. In this specification, the region from the center in the depth direction of the semiconductor substrate 10 to the upper surface 21 may be referred to as the upper surface side. An N- type drift region 18 is provided below the base region 14.

[0049] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0050] The first contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10 at a position closer to the center of the mesa portion 60 than the emitter region 12. The first contact region 15 may be provided deeper than the emitter region 12.

[0051] The base region 14 is provided below the emitter region 12 and the first contact region 15. The base region 14 is provided in contact with the emitter region 12 and the first contact region 15. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0052] In the mesa portion 60, an N+ type accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. In other words, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in the mesa portion 60.

[0053] The transistor section 70 may be provided with a P-type second bottom region 17 provided at the lower end of the gate trench section 40. That is, the second bottom region 17 may be in contact with the lower end of the gate trench section 40. By providing the second bottom region 17, it is possible to suppress a rise in potential near the lower end of the active trench section when the semiconductor device 100 is turned on. The second bottom region 17 in this example is provided between the accumulation region 16 and the drift region 18. The second bottom region 17 may be provided so as to cover the entire lower surface of the accumulation region 16 in the mesa section 60. The second bottom region 17 may be provided continuously across a plurality of mesa sections 60. The second bottom region 17 may be in contact with the accumulation region 16 or may not be in contact with it.

[0054] In the transistor section 70, a P+ type collector region 22 is provided below the drift region 18. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0055] The collector region 22 is exposed on the lower surface 23 of the semiconductor substrate 10, and is connected to a collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0056] The active trench portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 to reach the second bottom region 17. In a region where at least one of the emitter region 12, the first contact region 15, and the accumulation region 16 is provided, the active trench portion also penetrates these doped regions to reach the second bottom region 17. The active trench portion penetrating the doped region is not limited to a case where the active trench portion is formed after the doped region is formed. A case where the active trench portion is formed and then a doped region is formed between the active trench portions is also included in the case where the active trench portion penetrates the doped region.

[0057] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0058] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is connected to a gate runner and connected to the gate pad 116 via the gate runner. The gate runner may be disposed at a position different from that of the cross section shown in FIG. 2. The gate runner may be disposed above the well region 29 surrounding the active portion 120. The gate trench portion 40 may extend in the Y-axis direction to below the gate runner and be connected to the gate runner. When a predetermined gate voltage is applied from the gate pad 116 to the gate conductive portion 44, a channel is formed by an inversion layer of electrons on the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0059] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 may be electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0060] In the temperature sensing section 111, the semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, an anode electrode 81, a cathode electrode 83, and a collector electrode 24. The collector electrode 24 may be common to the transistor section 70.

[0061] The upper surface cathode region 62 is a first conductive type region provided in the semiconductor substrate 10 and exposed to the upper surface 21. The upper surface anode region 65 is a second conductive type region provided in the semiconductor substrate 10 and exposed to the upper surface 21. The upper surface cathode region 62 and the upper surface anode region 65 are in contact with each other to form a PN junction diode. The PN junction portion may be provided from the upper surface 21 to the inside of the semiconductor substrate 10, and may not be provided on the upper surface 21. The upper surface cathode region 62 and the upper surface anode region 65 function as a diode for temperature sensing. In this specification, the upper surface cathode region 62 and the upper surface anode region 65 may be collectively referred to as a temperature sensing diode. The temperature sensing diode of this example is formed inside the semiconductor substrate 10 in the depth direction. The upper surface cathode region 62 and the upper surface anode region 65 may be entirely provided below the interlayer insulating film 38. The top cathode region 62 and the top anode region 65 in this example are provided between the top surface 21 and the bottom surface 23. The top cathode region 62 and the top anode region 65 may be formed by implanting dopant ions into the semiconductor substrate 10. The top cathode region 62, the top anode region 65 and the PN junction portion may be crystalline. The top cathode region 62 and the top anode region 65 do not include polysilicon.

[0062] The anode electrode 81 is connected to the upper surface anode region 65 through a contact hole 54 formed in the interlayer insulating film 38. The cathode electrode 83 is connected to the upper surface cathode region 62 through a contact hole 54 formed in the interlayer insulating film 38. The anode electrode 81 and the cathode electrode 83 are connected to the temperature sense wiring 112-1 and the temperature sense wiring 112-2, respectively, and may be connected to the anode pad 114 and the cathode pad 115, respectively. The anode electrode 81 and the cathode electrode 83 may be formed of a metal material such as aluminum. In another example, the anode electrode 81 and the cathode electrode 83 may be formed of polysilicon to which an impurity is added.

[0063] In the temperature sensing section 111, the semiconductor device 100 is provided with an isolating trench portion 72 that is provided from the upper surface 21 toward the inside of the semiconductor substrate 10 and surrounds the upper surface anode region 65 and the upper surface cathode region 62 on the upper surface 21. That is, the upper surface anode region 65 and the upper surface cathode region 62 are electrically isolated from the active section 120 by the isolating trench portion 72 in the XY plane. The isolating trench portion 72 is formed deeper than the upper surface anode region 65 and the upper surface cathode region 62. The isolating trench portion 72 may be formed deeper than a first region 66 and a second region 64, which will be described later.

[0064] The isolating trench portion 72 may have the same structure as the gate trench portion 40 in the cross section. That is, the isolating trench portion 72 has an isolating trench provided on the upper surface 21 of the semiconductor substrate 10, an isolating insulating film 74, and an isolating conductive portion 76. The isolating conductive portion 76 may be electrically connected to the cathode electrode 83, may be connected to the emitter electrode 52, or may be electrically floating. The isolating insulating film 74 is provided to cover the inner wall of the isolating trench. The isolating conductive portion 76 is provided inside the isolating trench and is provided on the inner side of the isolating insulating film 74. The isolating insulating film 74 insulates the isolating conductive portion 76 from the semiconductor substrate 10. The isolating conductive portion 76 may be formed of the same material as the gate conductive portion 44. For example, the isolating conductive portion 76 is formed of a conductive material such as polysilicon. The isolating conductive portion 76 may have the same length as the gate conductive portion 44 in the depth direction. However, the isolating trench portion 72 may not have the isolating conductive portion 76. The inside of the isolating trench may be filled with an insulating material. Even in this case, the upper surface anode region 65 and the upper surface cathode region 62 are electrically isolated from the active portion 120 in the XY plane.

[0065] A P-type first bottom region 67 that contacts the lower end of the isolation trench portion 72 is provided below the upper surface anode region 65 and the upper surface cathode region 62. The lower end of the isolation trench portion 72 is the portion of the isolation trench portion 72 that is closest to the lower surface 23. In this example, the lower end of the isolation trench portion 72 is disposed at the center of the isolation trench portion 72 in the X-axis direction. The first bottom region 67 may be provided so as to overlap the entire upper surface anode region 65 and the upper surface cathode region 62. The first bottom region 67 shown in FIG. 2 is provided in a range wider than the entire upper surface anode region 65 and the upper surface cathode region 62 in the X-axis direction. The first bottom region 67 may also be provided in a range wider than the entire upper surface anode region 65 and the upper surface cathode region 62 in the Y-axis direction.

[0066] An N-type first region 66 is provided between the top anode region 65 and the first bottom region 67. The first region 66 in this example is in contact with the first bottom region 67. The first region 66 may form a PN junction with the first bottom region 67. This electrically separates the top anode region 65 and the top cathode region 62 from the active portion 120 in the depth direction. The first region 66 may be in contact with the top anode region 65, or may be in contact with another P-type region. In the example of FIG. 2, the first region 66 is in contact with the second region 64. The first region 66 may form a PN junction with the top anode region 65. If the second region 64 is provided, the first region 66 forms a PN junction with the second region 64. By electrically isolating the top anode region 65 and the top cathode region 62 from the active portion 120, the potential and current of the active portion 120 are prevented from affecting the temperature sensing diode, enabling accurate temperature measurement.

[0067] The semiconductor device 100 includes a P+ type well region 29 provided from the upper surface 21 to the inside of the semiconductor substrate 10. As described above, the well region 29 may surround the active portion 120 on the upper surface 21. The well region 29 may be provided deeper than the gate trench portion 40, the dummy trench portion 30, the isolation trench portion 72, and a connection trench portion 84 described later. At least a portion of the well region 29 may be provided at the same depth as the first bottom region 67.

[0068] The first bottom region 67 may be electrically connected to the emitter electrode 52. The emitter electrode 52 in this example is connected to the well region 29 through the contact hole 54. The first bottom region 67 is also connected to the well region 29. That is, the first bottom region 67 in this example is electrically connected to the emitter electrode 52 through the well region 29. This allows holes flowing from the collector region 22 to the first bottom region 67 to be extracted to the emitter electrode 52, thereby suppressing the effect on the temperature sensing diode. However, the first bottom region 67 may be connected to the emitter electrode 52 through the base region 14 of the active portion 120. The first bottom region 67 may be connected to the base region 14 through the well region 29, or may be directly connected to the base region 14.

[0069] A P-type second region 64 may be provided between the upper surface cathode region 62 and the first region 66. The second region 64 may form a PN junction with the first region 66. This allows the temperature sensing diode and the active section 120 to be more electrically isolated, and for example, when the potential of the emitter electrode 52 increases, the current flowing from the emitter electrode 52 to the upper surface cathode region 62 can be suppressed. The P-type second region 64 may also be provided between the upper surface anode region 65 and the first region 66.

[0070] The dopant of the top anode region 65 may be the same as the dopant of the first contact region 15. The doping concentration of the top anode region 65 may be the same as the doping concentration of the first contact region 15. The top anode region 65 may be provided in the same depth range as the first contact region 15. The dopant of the top cathode region 62 may be the same as the dopant of the emitter region 12. The doping concentration of the top cathode region 62 may be the same as the doping concentration of the emitter region 12. The top cathode region 62 may be provided in the same depth range as the emitter region 12. The dopant of the first region 66 may be the same as the dopant of the accumulation region 16. The doping concentration of the first region 66 may be the same as the doping concentration of the accumulation region 16. The first region 66 may be provided in the same depth range as the accumulation region 16. The dopant of the first bottom region 67 may be the same as the dopant of the second bottom region 17. The doping concentration of the first bottom region 67 may be the same as the doping concentration of the second bottom region 17. The first bottom region 67 may be provided in the same depth range as the second bottom region 17. The dopant of the second region 64 may be the same as the dopant of the base region 14. The doping concentration of the second region 64 may be the same as the doping concentration of the base region 14. The second region 64 may be provided in the same depth range as the base region 14. This allows the temperature sensing section 111 to be formed in the same manufacturing process as the active section 120, and an additional process for providing the temperature sensing section 111 can be reduced. However, the dopant, doping concentration, and depth range may be different between the active section 120 and the temperature sensing section 111.

[0071] In the present embodiment, a connection trench portion 84 is provided inside well region 29, extending from upper surface 21 of semiconductor substrate 10 toward the inside. Like other trench portions, connection trench portion 84 has a connection insulating film 86 and a connection conductive portion 88. Providing connection trench portion 84 makes it easier to connect first bottom region 67 and well region 29 when forming first bottom region 67 by a manufacturing method described below. Like isolation trench portion 72, connection trench portion 84 does not need to have connection conductive portion 88.

[0072] Fig. 3 is a diagram showing a comparative example of the cross section taken along the line AA in Fig. 1. The semiconductor device of the comparative example differs from the semiconductor device 100 of the embodiment in the configuration of the temperature sensing section 111. In the temperature sensing section 111 of the comparative example, a temperature sensing diode made of polysilicon is provided inside the interlayer insulating film 38. Therefore, in addition to the manufacturing process of the active section 120, a new process for forming the temperature sensing section 111 is required, which increases costs.

[0073] Fig. 4 is a diagram showing another example of the cross section taken along line AA in Fig. 1. In the semiconductor device 100 of this example, the configuration of the upper surface anode region 65 is different from that of the temperature sensing section 111 shown in Fig. 2. Other parts are similar to those in Fig. 2 and will not be described as appropriate. The active section 120 is provided with a P+ type first contact region 15 in contact with the upper surface 21 of the semiconductor substrate 10.

[0074] The upper surface anode region 65 of this example has a P-type junction region 68 and a P+-type second contact region 69. The junction region 68 is in contact with the upper surface cathode region 62 and has a lower doping concentration than the first contact region 15. The second contact region 69 is disposed away from the upper surface cathode region 62 and has a doping concentration equal to the doping concentration of the first contact region 15. The junction region 68 is provided between the second contact region 69 and the upper surface cathode region 62. The junction region 68 may also be provided below the second contact region 69. That is, the P-type concentration of the PN junction portion of the temperature sensing diode of this example is lower than that of the example of FIG. 2. This allows the characteristics of the temperature sensing diode to be adjusted while sharing part of the manufacturing process of the upper surface anode region 65 with the active portion 120. The junction region 68 may be provided in the upper surface cathode region 62. That is, the top surface cathode region 62 may have an N-type junction region 68 and an N+ type contact region. In this case, the junction region 68 is an N-type region with a lower doping concentration than the emitter region 12. The junction region 68 may be provided in both the top surface cathode region 62 and the top surface anode region 65.

[0075] FIG. 5 is a diagram showing an example of region B in FIG. 1. FIG. 5 shows the positions of each member projected onto the upper surface 21 of the semiconductor substrate 10. FIG. 5 omits the configuration of the active portion 120 and the temperature sensing wiring 112. In addition, the extension portion 28 of the well region 29 in this example does not surround the temperature sensing portion 111. In this example, the extension portion 28 of the well region 29 terminates at a position away from the isolation trench portion 72. In another example, the well region 29 surrounding the active portion 120 and the well region 29 separated from each other may surround the temperature sensing portion 111 in a top view. In this case, the well region 29 surrounding the temperature sensing portion 111 may be separated from the extension portion 28, and the extension portion 28 may not be provided.

[0076] The isolation trench portion 72 of this example has a frame trench portion 77 surrounding the upper surface anode region 65 and the upper surface cathode region 62, and an internal trench portion 78 provided in the region surrounded by the frame trench portion 77. When dopants are injected through the trenches and annealed to diffuse the dopants to form the first bottom region 67, if the interval between the trenches is wide, the first bottom region 67 may not be connected even if the dopants are diffused. In this case, the first bottom region 67 may not overlap the entire upper surface cathode region 62 and the upper surface anode region 65, and carriers may flow between the temperature sensing diode and the active portion 120. By providing the internal trench portion 78, dopants are also diffused from the trench of the internal trench portion 78, and even if the region surrounded by the frame trench portion 77 is wide, the first bottom region 67 can be formed in the entire region. The internal trench portions 78 of this example are arranged in the second direction (Y-axis direction).

[0077] In this example, the frame trench portion 77 is separated from the internal trench portion 78. At the intersection of the trench portions, the insulating film may be damaged. Also, the conductive portion may become deeper at the intersection. Therefore, it is preferable that the number of intersections of the trench portions is small. By separating the frame trench portion 77 and the internal trench portion 78, the number of intersections of the trench portions can be reduced. However, the frame trench portion 77 and the internal trench portion 78 do not have to be separated. In that case, a plurality of cells (five in the example of FIG. 5) are formed, which are partitioned by the frame trench portion 77 and the internal trench portion 78, and a temperature sensing diode is formed in each cell. In that case, the plurality of cells are aligned in the second direction (Y-axis direction). Also, the upper surface anode region 65 and the upper surface cathode region 62 of each cell are aligned in the first direction (X-axis direction).

[0078] As described above, the active section 120 is provided with a plurality of active trenches extending from the upper surface 21 toward the inside of the semiconductor substrate 10. The plurality of active trenches are arranged side by side in the X-axis direction. The interval between the active trenches in the X-axis direction is defined as t1 (see FIG. 2). The distance by which the frame trench section 77 and the internal trench section 78 are separated is defined as t2. This distance may be the distance between the frame trench section 77 and the internal trench section 78 in the longitudinal direction of the internal trench section 78 (the X-axis direction in FIG. 5), or may be the shortest distance between the frame trench section 77 and the internal trench section 78. The distance t2 may be equal to or less than the interval t1. As a result, in the active section 120, the second bottom region 17 can be formed from one active trench section of the mesa section 60 to the other active trench section, and in the temperature sensing section 111, the first bottom region 67 can be formed from the internal trench section 78 to the frame trench section 77.

[0079] The distance between the internal trench portion 78 and the frame trench portion 77 in the arrangement direction of the internal trench portion 78 (Y-axis direction) is defined as t3. The distance t3 may be equal to or less than the distance t1. This allows the first bottom region 67 to be formed over the entire region surrounded by the frame trench portion 77. Furthermore, the distance t3 and the distance t2 may be the same or different.

[0080] The connection trench portion 84 is disposed outside the region surrounded by the isolation trench portion 72. The connection trench portion 84 is disposed between the isolation trench portion 72 and the well region 29 (extension portion 28 in FIG. 5) in top view. The connection trench portion 84 in this example is provided at a position that does not overlap with the well region 29 (extension portion 28) in top view. In this example, the first bottom region 67 is formed by diffusing dopant from the trench of the connection trench portion 84. Therefore, the first bottom region 67 is in contact with the lower end of the connection trench portion 84. The first bottom region 67 is connected to the well region 29 from the lower end of the isolation trench portion 72 via the connection trench portion 84. In other words, the first bottom region 67 extends from the connection trench portion 84 to the well region 29, and also extends from the connection trench portion 84 to the frame trench portion 77.

[0081] The distance between the isolation trench portion 72 and the connection trench portion 84 is t4. The distance t4 may be equal to or less than the interval t1. The interval t1 is set so that when the second bottom region 17 is formed by injecting and diffusing dopants from the lower ends of the two active trench portions, the second bottom region 17 can connect the lower ends of the two active trench portions. Therefore, by setting the distance t4 to the distance t1 or less, the first bottom region 67 can be formed from the isolation trench portion 72 to the connection trench portion 84. Similarly, the distance between the connection trench portion 84 and the well region 29 may be equal to or less than the interval t1. In addition, the connection trench portion 84 may be provided inside the well region 29 as shown in FIG. 2, and may partially overlap the well region 29.

[0082] Since it is sufficient that the first bottom region 67 is connected from the isolation trench portion 72 to the well region 29 via the connection trench portion 84, the length of the connection trench portion 84 (in this example, the length in the X-axis direction) may be shorter than the length of the isolation trench portion 72. The connection trench portion 84 may be provided between the upper surface anode region 65 and the upper surface cathode region 62 in a top view. In FIG. 5, one connection trench portion 84 is provided between the isolation trench portion 72 and the extension portion 28. In another example, a plurality of connection trench portions 84 may be arranged side by side in the Y-axis direction between the isolation trench portion 72 and the extension portion 28. This allows the first bottom region 67 to be connected to the well region 29 (extension portion 28) even if the distance between the isolation trench portion 72 and the extension portion 28 is large. The distance between the connection trench portions 84 in the Y-axis direction may also be equal to or smaller than t1.

[0083] The extension direction (i.e., longitudinal direction) of the active trench portion and the internal trench portion 78 may be the same. That is, in Fig. 5, the active trench portion may extend in the X-axis direction. This makes it easier to form the temperature sensing portion 111 in the same process as the active portion 120.

[0084] 6 is a diagram showing another example of region B in FIG. The internal trench portion 78 may be separated into multiple parts. In this example, the internal trench portion 78 extends in the extension direction (X-axis direction) and is separated into multiple parts along the extension direction. This makes it possible to increase the area of ​​the temperature sensing diode.

[0085] The internal trench portion 78 in this example is separated at the junction between the upper surface anode region 65 and the upper surface cathode region 62. In this example, the junction between the upper surface anode region 65 and the upper surface cathode region 62 is provided extending in the Y-axis direction. The internal trench portions 78 are arranged on either side of the junction in the X-axis direction. The junction may be provided continuously from one to the other of two opposing sides of the frame trench portion 77. This can increase the area of ​​the PN junction of the temperature sensing diode.

[0086] Fig. 7 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. Fig. 7 shows a manufacturing process of the temperature sensor 111. The manufacturing process of this example includes a well region forming step S1000, a trench forming step S1002, an ion implantation step S1004, an annealing step S1006, a trench portion forming step S1008, a first region and a second region forming step S1010, an upper surface anode region and an upper surface cathode region forming step S1012, an interlayer insulating film and a contact hole forming step S1014, and an electrode forming step S1016.

[0087] 8A to 8G show cross-sectional views of the temperature sensing unit 111 in each manufacturing process. Fig. 8A shows a cross-sectional view of the temperature sensing unit 111 in a well region forming step S1000. In the well region forming step S1000, a dopant is injected from an upper surface 21 of the semiconductor substrate 10 to form a well region 29 from the upper surface 21 to the inside of the semiconductor substrate 10.

[0088] FIG. 8B shows a cross-sectional view of the temperature sensor 111 in the trench formation step S1002. When forming the above-mentioned isolation trench portion 72, a trench 73 is formed from the upper surface 21 toward the inside of the semiconductor substrate 10. The trench 73 is a groove in which the isolation insulating film 74 and the isolation conductive portion 76 are not formed. The trench formation step S1002 may be performed at the same stage as the formation of the trench 73 for forming the active trench portion in the active portion 120. For example, the formation of the trenches 73 in the active portion 120 and the temperature sensor 111 is performed by dry etching through a pattern formed on the same mask. This allows the temperature sensor 111 to be formed without increasing the manufacturing process.

[0089] FIG. 8C shows a cross-sectional view of the temperature sensing unit 111 in the ion implantation step S1004. In the ion implantation step S1004, dopants are implanted through the trench 73. "Through the trench 73" refers to implanting ions below the trench 73 after the trench 73 is formed, passing through the trench 73. In FIG. 8C, the implanted ions are shown by hatching. At this time, the trench 73 may have a plurality of portions. That is, the trench 73 may have portions that will later become the frame trench portion 77, the inner trench portion 78, and the connection trench portion 84. The ion implantation step S1004 may be performed at the same stage as the ion implantation for forming the second bottom region 17 in the active unit 120. For example, ions are implanted into the active unit 120 and the temperature sensing unit 111 through a pattern formed on the same mask.

[0090] FIG. 8D shows a cross-sectional view of the temperature sensing section 111 in the annealing step S1006. In the annealing step S1006, a first bottom region 67 of the second conductivity type that contacts the lower end of the isolation trench section 72 is formed. Specifically, the semiconductor substrate 10 may be annealed to diffuse the dopant and form the first bottom region 67. Since the annealing is performed after the dopant is injected through the trench 73, the first bottom region 67 and the lower end of the trench 73 can be reliably connected. The annealing step S1006 may be performed in the active section 120 at the same stage as the annealing for forming the second bottom region 17. For example, after ion implantation for forming the first bottom region 67 and the second bottom region 17, the semiconductor substrate 10 is put into an annealing furnace and annealed, thereby forming the first bottom region 67 and the second bottom region 17 in the same annealing process.

[0091] When trench 73 has a plurality of portions, first bottom region 67 is formed by annealing so that the dopants implanted through the plurality of portions are connected to each other. As an example, first bottom region 67 may be formed by adjusting the diffusion distance of the dopant by adjusting the annealing temperature or annealing time. However, semiconductor device 100 may be manufactured in the order of forming trench 73 after forming first bottom region 67 by ion implantation and annealing.

[0092] FIG. 8E shows a cross-sectional view of the temperature sensing section 111 in the trench section forming step S1008. In the trench section forming step S1008, the isolating trench section 72 is formed from the upper surface 21 toward the inside of the semiconductor substrate 10. As an example, the inside of the trench 73 is oxidized or nitrided to form the isolating insulating film 74 inside the trench 73. Thereafter, the isolating conductive section 76 made of polysilicon is filled inside the isolating insulating film 74, and the polysilicon above the upper surface 21 is etched back. In the same process, the connecting trench section 84 may also be formed. The trench section forming step S1008 may be performed in the same stage as the formation of the active trench section of the active section 120. For example, the gate insulating film 42, the dummy insulating film 32, the isolating insulating film 74, and the connecting insulating film 86 may be formed by the same oxidation or nitridation process.

[0093] FIG. 8F shows a cross-sectional view of the temperature sensing section 111 in the first and second region forming step S1010. In the first and second region forming step S1010, a first region 66 of a first conductivity type is formed between the top surface 21 and the first bottom region 67, and a second region 64 of a second conductivity type is formed between the top surface 21 and the first region 66. The first and second regions 66 and 64 may be formed by ion implantation from the top surface 21 of the semiconductor substrate 10. The first and second region forming step S1010 may be performed at the same stage as the formation of the accumulation region 16 and the base region 14 of the active section 120. For example, ions are implanted into the active section 120 and the temperature sensing section 111 through a pattern formed on the same mask. However, in the first and second region forming step S1010, only the first region 66 may be formed. The first and second regions 66 and 64 may also be formed outside the region surrounded by the isolation trench portion 72.

[0094] 8G shows a cross-sectional view of the temperature sensing section 111 in the upper surface anode region / upper surface cathode region forming step S1012. In the upper surface anode region / upper surface cathode region forming step S1012, the first conductive type upper surface cathode region 62 and the second conductive type upper surface anode region 65 are formed, which are exposed on the upper surface 21 of the region surrounded by the isolation trench portion 72. The upper surface cathode region 62 and the upper surface anode region 65 may be formed by ion implantation from the upper surface 21 of the semiconductor substrate 10. The upper surface anode region / upper surface cathode region forming step S1012 may be performed at the same stage as the formation of the emitter region 12 and the first contact region 15 of the active section 120. For example, ions are implanted into the active section 120 and the temperature sensing section 111 through a pattern formed on the same mask.

[0095] FIG. 8H shows a cross-sectional view of the temperature sensor 111 in the interlayer insulating film and contact hole forming step S1014. In the interlayer insulating film and contact hole forming step S1014, the interlayer insulating film 38 is formed above the upper surface 21 of the semiconductor substrate 10, and the contact hole 54 is formed in the interlayer insulating film 38. Before forming the interlayer insulating film 38, the isolating insulating film 74 and the connecting insulating film 86 exposed on the upper surface 21 of the semiconductor substrate 10 may be removed. The interlayer insulating film and contact hole forming step S1014 may be performed at the same stage as the formation of the interlayer insulating film 38 and the contact hole 54 of the active section 120. For example, the interlayer insulating film 38 is formed on the temperature sensor 111 and the active section 120 in the same film forming process, and the contact hole 54 is formed in the temperature sensor 111 and the active section 120 through a pattern formed on the same mask.

[0096] FIG. 8I shows a cross-sectional view of the temperature sensing section 111 in the electrode formation step S1016. In the electrode formation step S1016, an anode electrode 81 connected to the upper surface anode region 65 and a cathode electrode 83 connected to the upper surface cathode region 62 are formed. The anode electrode 81 and the cathode electrode 83 are formed above the interlayer insulating film 38 and are connected to the upper surface anode region 65 and the upper surface cathode region 62, respectively, via contact holes 54. The electrode formation step S1016 may be performed in the same step as the formation of the emitter electrode 52 of the active section 120. The anode electrode 81 and the cathode electrode 83 may be made of the same material as the emitter electrode 52. For example, the anode electrode 81, the cathode electrode 83, and the emitter electrode 52 may be formed in the same plating process.

[0097] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0098] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0099] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 first contact region, 16 accumulation region, 17 second bottom region, 18 drift region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 28 extension portion, 29 well region, 30 dummy trench portion, 3 2 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 42 gate insulating film, 44 gate conductive portion, 52 emitter electrode, 54 contact hole, 60 mesa portion, 62 upper cathode region, 64 second region, 65 upper anode region, 66 first region, 67 1. First bottom region, 68... junction region, 69... second contact region, 70... transistor portion, 72... isolation trench portion, 73... trench, 74... isolation insulating film, 76... isolation conductive portion, 77... frame trench portion, 78... internal trench portion, 80... diode portion, 81... anode electrode, 83... cathode electrode, 84... connection trench portion, 86... connection insulating film, 88... connection conductive portion, 90... edge termination structure portion, 100... semiconductor device, 111... temperature sensing portion, 112... temperature sensing wiring, 114... anode pad, 115... cathode pad, 116... gate pad, 120... active portion, 140... outer periphery edge, 142... first edge

Claims

1. a semiconductor substrate having an upper surface; a first conductivity type top surface cathode region provided in the semiconductor substrate and exposed to the top surface; an upper surface anode region of a second conductivity type provided in the semiconductor substrate and exposed on the upper surface; an anode electrode connected to the top anode region; a cathode electrode connected to the top cathode region; an isolation trench portion provided from the upper surface toward the inside of the semiconductor substrate and surrounding the upper surface anode region and the upper surface cathode region on the upper surface; a first bottom region of a second conductivity type provided below the top anode region and the top cathode region, overlapping the entire top anode region and the top cathode region, and in contact with a lower end of the isolation trench portion; a first region of a first conductivity type disposed between the top anode region and the first bottom region; A semiconductor device comprising:

2. a transistor portion or a diode portion provided on the semiconductor substrate in a region different from a region surrounded by the isolation trench portion; an active portion in which the transistor portion or the diode portion is provided; an emitter electrode provided above the top surface of the active portion; Further comprising: The first bottom region is electrically connected to the emitter electrode. The semiconductor device according to claim 1 .

3. a well region of a second conductivity type that is provided from the upper surface to an inside of the semiconductor substrate and surrounds the active portion on the upper surface; The first bottom region is electrically connected to the emitter electrode through the well region. The semiconductor device according to claim 2 .

4. a second region of a second conductivity type provided between the top cathode region and the first region; The semiconductor device according to claim 1 .

5. a transistor portion provided on the semiconductor substrate in a region different from a region surrounded by the isolation trench portion; an active portion which is a region in which the transistor portion is provided; Further comprising: a first contact region of a second conductivity type is provided in the active portion in contact with the upper surface of the semiconductor substrate; The top anode region is a junction region in contact with the top cathode region and having a doping concentration lower than that of the first contact region; a second contact region of a second conductivity type spaced apart from the top cathode region and having a doping concentration equal to a doping concentration of the first contact region; The semiconductor device according to claim 1 .

6. The isolation trench portion is a frame trench portion surrounding the top surface anode region and the top surface cathode region; an inner trench portion provided in a region surrounded by the frame trench portion; having The frame trench portion is separated from the inner trench portion. The semiconductor device according to claim 1 .

7. The internal trench portion extends in the extension direction and is separated into a plurality of portions along the extension direction. The semiconductor device according to claim 6.

8. The interior trench portion is separated at a junction of the top anode region and the top cathode region. The semiconductor device according to claim 7.

9. a transistor portion or a diode portion provided on the semiconductor substrate in a region different from a region surrounded by the isolation trench portion; an active portion in which the transistor portion or the diode portion is provided; In the active portion, a plurality of active trench portions are formed from the upper surface toward the inside of the semiconductor substrate. Further comprising: The distance separating the frame trench portion and the inner trench portion is equal to or less than the spacing between the active trench portions. The semiconductor device according to claim 6.

10. a transistor portion or a diode portion provided on the semiconductor substrate in a region different from a region surrounded by the isolation trench portion; an active portion in which the transistor portion or the diode portion is provided; a well region of a second conductivity type provided from the upper surface to an inside of the semiconductor substrate and surrounding the active portion on the upper surface; a connection trench portion disposed between the isolation trench portion and the well region and extending from the upper surface toward the inside of the semiconductor substrate; Further comprising: The first bottom region is in contact with a lower end of the connection trench portion. The semiconductor device according to claim 1 .

11. In the active portion, a plurality of active trench portions are formed from the upper surface toward the inside of the semiconductor substrate. Further comprising: The distance between the isolation trench portion and the connection trench portion is equal to or smaller than the distance between the active trench portions. The semiconductor device according to claim 10.

12. A transistor portion provided on the semiconductor substrate, The transistor portion is a gate trench portion provided from the upper surface toward the inside of the semiconductor substrate; a second bottom region of a second conductivity type provided at a lower end of the gate trench portion; The semiconductor device according to claim 1 ,

13. 1. A method for manufacturing a semiconductor device comprising: forming an isolation trench portion from the upper surface toward the inside of the semiconductor substrate; forming a first bottom region of a second conductivity type in contact with a lower end of the isolation trench portion; forming a first region of a first conductivity type between the top surface and the first bottom region; forming an upper surface cathode region of a first conductivity type and an upper surface anode region of a second conductivity type exposed on the upper surface of the region surrounded by the isolation trench portion; forming an anode electrode connected to the upper surface anode region and a cathode electrode connected to the upper surface cathode region; A method for manufacturing a semiconductor device.

14. When forming the isolation trench portion, a trench is formed from the upper surface toward the inside of the semiconductor substrate; Injecting a dopant through the trench and annealing to diffuse the dopant to form the first bottom region. The method for manufacturing a semiconductor device according to claim 13.

15. the trench having a plurality of portions; The dopants implanted through the plurality of portions are annealed to connect with each other, thereby forming the first bottom region. The method for manufacturing a semiconductor device according to claim 14.

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