Printed circuit board

Abstract

To provide a printed circuit board capable of realizing patterns and pads having fine pitches, preventing defects in the patterns and the pads while using a low-cost process, and improving the reliability.SOLUTION: The present disclosure relates to a printed circuit board including a core layer, a plurality of first wirings arranged on the core layer, a first pad arranged on the core layer and including an adjacent portion arranged substantially parallel to adjacent wirings among the plurality of first wirings and an open portion arranged substantially non-parallel to the adjacent wirings among the plurality of first wirings, and a first build-up insulating layer arranged on the core layer and covering at least a portion of the plurality of first wirings and the first pad, and the core layer includes an insulating material substantially different from the first build-up insulating layer.SELECTED DRAWING: Figure 5b

Description

[Technical field]

[0001] The present disclosure relates to printed circuit boards. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, multi-chip packages including memory chips such as HBM (High Bandwidth Memory) and processor chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), and FPGA (Field Programmable Gate Array) are being used to process data that has increased exponentially. In particular, the number of CPU and GPU cores in server products is increasing rapidly, and the number of layers in multilayer boards is increasing to process this. Research is ongoing to reduce the number of board layers and achieve interlayer connections of fine-pitch patterns and pads while improving reliability. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objects of the present disclosure is to provide a printed circuit board capable of realizing fine pitch patterns and pads.

[0004] Another of several objects of the present disclosure is to provide a printed circuit board that can use a low-cost process while avoiding defects in patterns and pads.

[0005] Another of several objects of the present disclosure is to provide a printed circuit board that can improve reliability. [Means for solving the problem]

[0006] One of several solutions proposed through the present disclosure is to provide a printed circuit board including a core layer, a plurality of first wirings arranged on the core layer, a first pad arranged on the core layer and including an adjacent portion arranged substantially parallel to adjacent wirings among the plurality of first wirings and an open portion arranged substantially not parallel to adjacent wirings among the plurality of first wirings, and a first build-up insulating layer arranged on the core layer and covering at least a portion of the plurality of first wirings and the first pad, wherein the core layer includes an insulating material substantially different from that of the first build-up insulating layer.

[0007] Another of several solutions proposed through the present disclosure is to provide a printed circuit board including a first insulating layer, a plurality of first wirings respectively disposed on an upper surface and a lower surface of the first insulating layer, and a first pad respectively disposed on the upper surface and the lower surface of the first insulating layer, the first pad including an adjacent portion disposed substantially parallel to an adjacent wiring among the plurality of first wirings and an open portion disposed substantially not parallel to an adjacent wiring among the plurality of first wirings, wherein the distance between the adjacent portion of the first pad and the first pad and an adjacent wiring among the plurality of first wirings is substantially the same as the distance between adjacent wirings among the plurality of first wirings. Effect of the Invention

[0008] Among the various advantages of the present disclosure is the provision of a printed circuit board capable of realizing fine pitch traces and pads.

[0009] Another of the various advantages of the present disclosure is to provide a printed circuit board that can be manufactured using low-cost manufacturing techniques while avoiding defects in patterns and pads.

[0010] Another of the various advantages of the present disclosure is to provide a printed circuit board that can improve reliability. [Brief description of the drawings]

[0011] [Figure 1]FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a schematic diagram of a printed circuit board according to an example. [Figure 4a] 1 is a plan view showing a schematic design and image of a core layer of a conventional printed circuit board; [Figure 4b] 1 is a plan view showing a schematic design and image of a core layer of a conventional printed circuit board; [Figure 5a] FIG. 1 is a plan view showing a schematic diagram of a portion of a core layer design of a conventional printed circuit board. [Figure 5b] FIG. 2 is a plan view showing a schematic diagram of a portion of a core layer design of a printed circuit board according to an example. [Figure 6a] FIG. 1 is a plan view showing a schematic diagram of a portion of a core layer design of a conventional printed circuit board. [Figure 6b] FIG. 2 is a plan view showing a schematic diagram of a portion of a core layer design of a printed circuit board according to an example. [Figure 7a] FIG. 1 is a plan view showing a schematic diagram of a portion of a core layer design of a conventional printed circuit board. [Figure 7b] FIG. 2 is a plan view showing a schematic diagram of a portion of a core layer design of a printed circuit board according to an example. [Figure 8] FIG. 11 is a cross-sectional view illustrating a printed circuit board according to another example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for a clearer description.

[0013] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0014] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also coupled to other electronic components described below to form various signal lines 1090.

[0015] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). In addition, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0016] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, and may include any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with the chip-related components 1020 together.

[0017] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may include passive elements in the form of chip components used for various other applications. In addition, the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0020] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0021] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built in. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0022] Printed Circuit Board FIG. 3 is a schematic cross-sectional view of a printed circuit board according to an example.

[0023] 3, a printed circuit board according to an example includes a core layer 110, a first wiring layer 120 disposed on the core layer 110, and a through via 130 penetrating the core layer 110 and connecting the first wiring layer 120 to each other. The first wiring layer 120 may include a first wiring 126, a first pad 121, a second pad 122, and a first pattern.

[0024] The core layer 110 may include an insulating material. The insulating material may be, but is not limited to, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material in which these resins are mixed with an inorganic filler such as silica, or an organic insulating material such as a resin impregnated with a core material such as glass fiber (glass cloth, glass fabric) together with an inorganic filler, for example, a prepreg. The core layer 110 may be, but is not limited to, a CCL (Copper Clad Laminate) in which copper foil is laminated on the upper and lower sides of a resin impregnated with a core material such as glass fiber. The core layer 110 may include, but is not limited to, other insulating materials, for example, a glass plate, in addition to the organic insulating material, as necessary.

[0025] The first wiring layer 120 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include, but is not limited to, copper (Cu). The first wiring layer 120 may perform various functions according to the design. For example, the first wiring layer 120 may include a signal pattern, a power pattern, a ground pattern, a heat dissipation pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad.

[0026] Each of the components of the first wiring layer 120 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Or, it may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Or, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Instead of the electroless plating layer (or chemical copper), a sputtering layer may be included, or both may be included as necessary. The core layer 110 may be a CCL (Copper Clad Laminate) in which copper foil is formed on the upper and lower sides of the resin, and each of the components of the first wiring layer 120 may be formed of a single layer of copper, and electrolytic plating may be performed in a panel shape using the copper foil as a seed. The first wiring layer 120 may be formed using any method that patterns a circuit layer in a printed circuit board without any restrictions. However, when the core layer 110 of the printed circuit board according to an embodiment is a copper clad laminate (CCL), the printed circuit board may be formed by either a subtractive or tenting method, but is not limited thereto. The subtractive or tenting method may be performed by marking a required portion on a wide metal plate or copper foil in a panel form and then removing an unnecessary portion. In this case, the method of removing the copper foil may be a physical method or a chemical method, and as a non-limiting example, chemical etching may be used.

[0027] The through via 130 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the through via may include, but is not limited to, copper (Cu). The through via may include, but is not limited to, a plated through hole (PTH) in which the above-mentioned metal material is conformally formed on the wall of a through hole penetrating the core layer 110 by plating and an insulating material is filled inside the through via. The through via 130 may perform various functions according to the design of the corresponding layer. For example, the through via 130 may include a ground via, a power via, a signal via, and the like. The through via 130 may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included.

[0028] The first wiring layer 120 may include a first wiring 126, a first pad 121, and a second pad 122, but may also include various other patterns. The first pad 121 and the second pad 122 are connected to vias to perform interlayer connection, and the first wiring 126 may function as a signal transmission path. The first pad 121 may be connected to a through via 130. The first wiring layer 120 may be disposed on the upper and lower surfaces of the core layer 110, and the first wiring 126, the first pad 121, and the second pad 122 may be disposed on the upper and lower surfaces of the core layer 110, respectively, and may have a structure protruding from the upper and lower surfaces of the core layer 110. The fact that the first wiring layer 120 protrudes from the upper and lower surfaces of the core layer 110 may mean that each component of the first wiring layer 120 is disposed to contact the upper and lower surfaces of the core layer 110, and the remaining surfaces except for one surface are not covered by the core layer 110. That is, the first wiring layer 120 may be disposed so as to protrude on both sides based on the core layer 110. This may be the result of forming the first wiring layer 120 by removing a part of the copper foil or plating layer laminated on both sides of the core layer 110, and may be different from a build-up wiring layer disposed only on one side of a build-up insulating layer.

[0029] The first wiring 126 may be a line-shaped pattern, and the first pad 121 and the second pad 122 may be patterns having a certain shape. Also, the first wiring layer 120 is not limited thereto and may further include a first pattern 124 having another planar shape.

[0030] Each of the first pad 121 and the second pad 122 may have a plurality of pads, and the first wiring 126 may include a plurality of wirings. Each of the first pad 121 and the second pad 122 may be connected to any one of the plurality of first wirings 126.

[0031] The width W1 of the first pad 121 may be larger than the width W2 of the second pad 122. The first pad 121 may be designed to have a width larger than the width W2 of the second pad 122 to be connected to the through via 130. Each of the first pad 121 and the second pad 122 may have a width larger than the width W3 of the first wiring 126. That is, the width W1 of the first pad 121 may be larger than the width W3 of the first wiring 126, and the width W2 of the second pad 122 may be larger than the width W3 of the first wiring 126. The first pad 121 and the second pad 122 are intended to be connected to the vias of the first built-up via layer 143, and may have a width larger than the width W3 of the first wiring 126 to facilitate connection with the vias.

[0032] The width W1 of the first pad 121 and the width W2 of the second pad 122 may be measured by photographing a cut cross section of the printed circuit board using a scanning microscope. The width W3 of the first wiring 126 may also be measured by photographing a cut cross section of the printed circuit board using a scanning microscope. The width W1 of the first pad 121 and the width W2 of the second pad 122 may be measured by cutting the first pad 121 to include the first built-up via layer 143. In addition, if the shape of the first pad 121 and the second pad 122 is not circular, the width of the pad may be measured by cutting in the same direction as the cutting direction for measuring the width of the wiring. The width may be calculated as the average of distances measured at any five points.

[0033] Even if the first pad 121, the second pad 122 and the first wiring 126 have different widths, the distance d1 between the first pad 121 and the first wiring 126, the distance d2 between the second pad 122 and the first wiring 126, the distance d3 between adjacent first wirings 126, and the distance d4 between the first pad 121 and the second pad 122 may be substantially identical to each other.

[0034] The first pad 121 and the second pad 122 each include an adjacent portion arranged substantially parallel to an adjacent first wiring 126 among the plurality of first wirings 126, and may include an open portion arranged substantially not parallel to an adjacent first wiring 126 among the plurality of first wirings 126. Since the first pad 121 and the second pad 122 each include an adjacent portion and an open portion, even if an etching solution accumulates in an area of ​​the first pad 121 and the second pad 122 that is not adjacent to the first wiring 126, defects may not occur in the first pad 121 and the second pad 122. Specific details regarding the distance between the adjacent portion and the open portion and the shape and configuration of the pad will be described later.

[0035] The printed circuit board according to an example may include a first build-up insulating layer 141 disposed on the core layer and covering at least a portion of the first wiring layer 120. The first wiring layer 120 may be disposed on the upper and lower surfaces of the core layer 110, protruding from the core layer 110, and at least a portion of the first wiring layer 120 may be embedded in the first build-up insulating layer 141.

[0036] In addition, the printed circuit board of one example may include a first build-up wiring layer 142 disposed on the first build-up insulating layer 141, and a first build-up via layer 143 penetrating at least a portion of the first build-up insulating layer 141 to connect the first build-up wiring layer 142 to each other or to connect the first build-up wiring layer 142 to the first wiring layer 120.

[0037] In one example, the printed circuit board may further include a second build-up insulation layer 151 arranged on the first build-up insulation layer 141, a second build-up wiring layer 152 arranged on the second build-up insulation layer 151, and a second build-up via layer 153 penetrating at least a portion of the second build-up insulation layer 151 to connect the second build-up wiring layer 152 to each other or to connect the second build-up wiring layer 152 to the first build-up wiring layer 142.

[0038] The first build-up insulating layer 141 and the second build-up insulating layer 151 may each include an insulating material. The insulating material may be, but is not limited to, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material in which these insulating resins are mixed with an inorganic filler such as silica, or a resin impregnated into a core material such as glass fiber together with an inorganic filler, for example, an insulating material such as ABF (Ajinomoto Build-up Film), prepreg, RCC (Resin Coated Copper), or PID (Photo Imageable Dielectric). The first build-up insulating layer 141 and the second build-up insulating layer 151 may each include, but are not limited to, the same insulating material, and the second build-up insulating layer 151 may use a material that is more advantageous for a wiring layer having a finer pitch than the first build-up insulating layer 141. The thickness of the second build-up insulating layer 151 may be thinner than the thickness of the first build-up insulating layer 141. Each of the first build-up insulating layer 141 and the second build-up insulating layer 151 may include a plurality of insulating layers.

[0039] The first build-up insulating layer 141 may include an insulating material different from that of the core layer 110. The core layer 110 may include a core layer insulating material that can be used without limitation as long as it is an insulating material that has excellent rigidity and can ensure thickness as a core material of a printed circuit board, and the first build-up insulating layer 141 may be used without limitation as long as it is an insulating layer that can be used as an insulating layer for lamination of a printed circuit board. In some cases, the material of the first build-up insulating layer 141 may be selected from the material group of the core layer 110, and the material of the core layer 110 may be selected from the material group of the first build-up insulating layer 141. However, even in such a case, the physical properties of the first build-up insulating layer 141 may be different from each other, such as the thickness of the first build-up insulating layer 141 being thinner than the thickness of the core layer 110 or the rigidity of the core layer 110 being greater than that of the first build-up insulating layer 141. In addition, the core layer 110 may be distinguished from the first build-up insulating layer 141 by, for example, having copper foil laminated on it or panel plating being performed on it. In one example, a printed circuit board uses a copper foil laminated substrate as a core layer 110, and a fine-pitch first wiring layer 120 can be realized in the core layer 110, and the first build-up insulation layer 141 and the second build-up insulation layer 151 other than the core layer 110 can be distinguished from the core layer 110.

[0040] The first build-up wiring layer 142 and the second build-up wiring layer 152 may each include a metal. The metal may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and may preferably include copper (Cu), but is not limited thereto. The first build-up wiring layer 142 and the second build-up wiring layer 152 may each include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included. Furthermore, a copper foil may be further included. The first build-up wiring layer 142 and the second build-up wiring layer 152 may each perform various functions according to the design of the corresponding layer. For example, they may include a ground pattern, a power pattern, a signal pattern, etc. Each of these patterns may include a line pattern, a plane pattern, and / or a pad pattern. Each of the first build-up wiring layer 142 and the second build-up wiring layer 152 may include a plurality of wiring layers. The second build-up wiring layer 152 may include finer wiring than the first build-up wiring layer 142. For example, the thickness of the second build-up wiring layer 152 may be thinner than the thickness of the first build-up wiring layer 142, and may have a narrow pitch such as a high wiring density and a smaller line / space. In other words, the second build-up wiring layer 152 may correspond to a redistribution layer for connection to a semiconductor chip.

[0041] The first build-up via layer 143 and the second build-up via layer 153 may each include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along the wall surface of the via hole. The microvia may be arranged in a stacked type and / or staggered type. The first build-up via layer 143 and the second build-up via layer 153 may each include a metal, which may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and may preferably include, but is not limited to, copper (Cu). The first build-up via layer 143 and the second build-up via layer 153 may each include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The first build-up via layer 143 and the second build-up via layer 153 may each perform various functions according to the design of the corresponding layer. For example, they may include ground vias, power vias, signal vias, etc. The first build-up via layer 143 and the second build-up via layer 153 may each include a plurality of via layers.

[0042] The printed circuit board according to an example may further include a solder resist layer 160 on the outermost side. The solder resist layer 160 may be disposed on the first build-up insulation layer 141 and the second build-up insulation layer 151, respectively. The solder resist layer 160 may include an insulating material and may include, but is not limited to, a liquid or film type solder resist, and other types of insulating materials may be used. The solder resist layer 160 may have openings that expose at least a portion of the first build-up wiring layer 142 and the second build-up wiring layer 152.

[0043] The printed circuit board according to an example may further include a surface treatment layer 170 disposed on the first build-up wiring layer 142 and the second build-up wiring layer 152 exposed by the opening of the solder resist layer 160. The surface treatment layer 170 may include any one of metals, nickel (Ni), palladium (Pd), and gold (Au), and may be realized by a plurality of these metal layers. For example, the surface treatment layer 170 may be at least a part of an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) structure, or at least a part of an ENIG (Electroless Nickel Immersion Gold) structure. The surface treatment layer 170 is not limited thereto, and may include an OSP (Organic Solder Passivation) structure including an organic material.

[0044] Meanwhile, in FIG. 3, the second build-up insulation layer 151 and the second build-up wiring layer 152 are shown disposed on the first build-up insulation layer 141, but this is not necessarily limited thereto, and the second build-up insulation layer 151 and the second build-up wiring layer 152 may be omitted in some cases.

[0045] In addition, the printed circuit board according to the embodiment is not limited to the configuration shown in Fig. 3, but may further include other configurations or may be omitted in some cases. That is, the printed circuit board may further include configurations that can be utilized by a person having ordinary skill in the art.

[0046] 4a and 4b are schematic diagrams showing a design plan view and an image of a core layer of a conventional printed circuit board.

[0047] When chemical etching is used in the step of forming the first wiring layer 126', it is not easy to finely remove a portion of the copper foil formed widely on the core layer 110'. In particular, when forming the first wiring 126' having a fine line width, defects may occur in which the first wiring 126' is cut and opened halfway, or defects may occur in which adjacent first wirings 126' are not completely separated and short-circuited. As such, it is difficult to realize a wiring layer having a fine line width by the method of removing a portion of the copper foil.

[0048] Also, it may be difficult to realize the first pad 121' and the second pad 122' having a fine width and pitch. In particular, in the case of the pads, since no wiring is formed around the pads, the etching solution may accumulate around the first pad 121' and the second pad 122'. Therefore, the first pad 121' and the second pad 122' may have a different shape from the design shown in FIG. 4b, which is different from the design shown in FIG. 4a. That is, the first pad 121' and the second pad 122' are removed more than the design design in the area not adjacent to the first wiring 126', so that the area of ​​the first pad 121' and the second pad 122' is reduced. However, the present invention is not limited thereto, and the etching solution may not be uniformly infiltrated in the area where the first pad 121' and the second pad 122' are adjacent to the first wiring 126'. In this case, the first pad 121' and the second pad 122' are not isolated from the adjacent first wiring 126', and there is a possibility that a defect occurs due to a short circuit.

[0049] That is, when an etching solution is applied for patterning, the first pad 121' and the second pad 122' are not easily removed from the area adjacent to the first wiring 126', and conversely, the first pad 121' and the second pad 122' may be over-etched in the area not adjacent to the first wiring 126'. As the first pad 121' and the second pad 122' have shapes and positions different from the design, when the first build-up via layer 143 is formed on the first pad 121' and the second pad 122', a defect in consistency may occur, and interlayer connection may not be smooth.

[0050] 5a, 6a and 7a are plan views that show schematic diagrams of parts of the core layer design of a conventional printed circuit board.

[0051] 5a and 6a, the second pad 122' has a difference in the amount of etching solution flowing between the area connected to the wiring and the area not connected to the wiring. That is, in the area where the second pad 122' is connected to the wiring, the etching solution is restricted by the wiring connected to the second pad 122' and can permeate toward the second pad 122'. Meanwhile, in the side of the second pad 122' opposite to the area where the wiring is connected, the second pad 122' has an open area, so that the etching solution accumulates in the open area of ​​the second pad 122'. Therefore, the above-mentioned defects may occur.

[0052] 7a, the first pad 121' is adjacent to the first wiring 126' and the first pattern 124'. In this case, the etching solution may not move smoothly due to the first wiring 126' and the first pad 121', and conversely, the etching solution may accumulate in the area not adjacent to the first wiring 126' and the first pattern 124'. Therefore, the above-mentioned defects may occur in this case as well.

[0053] 5b, 6b and 7b are schematic plan views of parts of the design of a core layer of a printed circuit board according to an example.

[0054] 5b and 6b, the second pad 122 includes an adjacent portion 122-1, which is a region adjacent to the first wiring 126, and an open portion 122-2, which is not adjacent to the first wiring 126 and is not connected to other wirings.

[0055] The adjacent portion 122-1 of the second pad 122 includes a portion that is substantially parallel to the first wiring 126 adjacent to the second pad 122. The adjacent portion 122-1 of the second pad 122 being substantially parallel to the first wiring 126 may mean that the adjacent portion 122-1 of the second pad 122 has an end that is parallel to the wiring path of the first wiring 126, which is a linear pattern. Meanwhile, without being limited thereto, being substantially parallel may include a rough concept, for example, a concept that includes errors that may be included in the manufacturing stage or the measurement method.

[0056] The opening 122-2 of the second pad 122 may refer to a region of the second pad 122 that is not adjacent to the first wiring 126. The opening 122-2 of the second pad 122 may refer to a region that is not parallel to the first wiring 126, and may refer to a virtual extension line of the opening 122-2 of the second pad 122 that may contact the adjacent first wiring 126. The opening 122-2 of the second pad 122 may be located on the opposite side of the region where the second pad 122 is connected to the wiring. The opening 122-2 of the second pad 122 may be located far from the region where the first build-up via layer 143 is located. That is, the opening 122-2 of the second pad 122 is designed to have an area larger than the area required for the second pad 122 to be connected to the first build-up via layer 143.

[0057] Since the second pad 122 includes the adjacent portion 122-1 and the opening portion 122-2, the printed circuit board according to the example may prevent the etching solution from accumulating in the second pad 122 when the etching solution flows along the first wiring 126. In particular, since the adjacent portion 122-1 is substantially parallel to the first wiring 126, the etching solution may be prevented from accumulating in the second pad 122, unlike the case where the second pad 122 is circular. In addition, since the second pad 122 includes the adjacent portion 122-1, the opening portion 122-2 may be located in a region away from the wiring connected to the second pad 122. That is, in the printed circuit board according to the example, the second pad 122 may not be symmetrical with respect to the first build-up via layer 143. That is, since the second pad 122 includes the adjacent portion 122-1 and the opening portion 122-2, it may be possible to prevent defects from occurring in the second pad 122 when the etching solution penetrates to form the second pad 122.

[0058] The distance d2 between the adjacent portion 122-1 of the second pad 122 and the first wiring 126 adjacent to the second pad 122 may be substantially the same as the distance d3 between the adjacent first wirings 126. The distance between the adjacent portion 122-1 of the second pad 122 and the first wiring 126 may be measured by photographing a cut plane or a cut cross section of the printed circuit board with a scanning microscope. The distance between a certain configuration may be an average value measured at any five points, but is not necessarily limited thereto. Since the adjacent portion 122-1 of the second pad 122 is substantially parallel to the adjacent first wiring 126, the distance d2 between the adjacent portion 122-1 of the second pad 122 and the first wiring 126 may mean the distance across between the adjacent portion 122-1 of the second pad 122 and the first wiring 126. In the same vein, the distance between the adjacent first wirings 126 may mean the distance across between the adjacent first wirings 126. Meanwhile, the distance d2 between the adjacent portion 122-1 of the second pad 122 and the first wiring 126 may be measured on substantially the same plane as the distance d3 between the adjacent first wirings 126. That is, the distance between the adjacent first wirings 126 may be measured on an extension of an imaginary line for measuring the distance between the adjacent portion 122-1 of the second pad 122 and the first wiring 126.

[0059] 7b, the first pad 121 includes an adjacent portion 121-1 that is an area adjacent to the first wiring 126 and an open portion 121-2 that is not adjacent to the first wiring 126 and is not connected to other wirings. The first pad 121 may also be adjacent to a first pattern 124 having a planar shape.

[0060] A distance d1 between the adjacent portion 121-1 of the first pad 121 and the first wiring 126 may be substantially the same as a distance d3 between adjacent first wirings 126. In addition, a distance between the first pattern 124 and the first pad 121 may also be substantially the same as the distance d1 between the adjacent portion 121-1 of the first pad 121 and the first wiring 126.

[0061] Because the first pad 121 has an adjacent portion 121-1 and an open portion 121-2, the printed circuit board of one example can prevent defects such as excessive etching caused by etching solution accumulating in the first pad 121, and the first pad 121 can also have an asymmetrical shape with respect to the position where the first built-up via layer 143 is formed.

[0062] Meanwhile, Figs. 5b, 6b, and 7b show only a part of the core layer 110 of the printed circuit board according to an example, and the arrangement and shape of the first pad 121, the second pad 122, and the first pattern 124 are not limited thereto. The first pad 121 and the second pad 122 are connected to the first built-up via layer 143, and the first pad 121 and the second pad 122 include adjacent portions 121-1 and 122-1 that are regions substantially parallel to the adjacent first wiring 126, respectively, and include open portions 121-2 and 122-2 that are not adjacent to the first wiring 126, so that even if an etching solution accumulates in the first pad 121 and the second pad 122, the area of ​​the pads for forming the first built-up via layer 143 can be secured. Therefore, the first wiring layer 120 including a fine pattern on the core layer 110 can be realized at low cost.

[0063] FIG. 8 is a cross-sectional view that illustrates a schematic configuration of a printed circuit board according to another embodiment.

[0064] 8, the side surfaces of the first pad 121, the second pad 122, and the first wiring 126 of the printed circuit board according to another example may have curved surfaces. This may be the result of forming the first wiring layer on the core layer 110 using either a subtractive method or a tenting method, but is not limited thereto.

[0065] The first pad 121 may have a lower width W11 that is wider than or equal to the upper width W12, and a central width W13 that is narrower than the upper width W12. That is, the first pad 121 may satisfy the relationship W11 ≧ W12 > W13. This may be a result of adjusting the degree of penetration of the etchant in the step of removing unnecessary parts by injecting an etchant after disposing an etching mask to form the first pad 121. The shape of the pad may be adjusted by using an etching additive in the etchant, and since the upper width W12 is formed wider than the central width W13, it may be more advantageous to align the first build-up via layer 143 when it is disposed on the first pad 121.

[0066] Similarly, the second pad 122 may have a lower width W21 that is wider than or equal to the upper width W22, and a central width W23 that is narrower than the upper width W22. That is, the second pad may satisfy the relationship W21≧W22>W23. Therefore, the second pad 122 may also be advantageous in terms of alignment when the first built-up via layer 143 is disposed.

[0067] Since the first wiring 126 can be formed simultaneously when the first pad 121 and the second pad 122 are patterned, the width W31 of the lower surface of the first wiring 126 can also be wider than or equal to the width W32 of the upper surface, and the width W33 of the center portion can be narrower than the width W32 of the upper surface. That is, the first wiring can also satisfy the relationship W31≧W32>W33.

[0068] Meanwhile, since the first build-up wiring layer 142 and the second build-up wiring layer 152 can be manufactured by a method different from that of the first wiring layer 120, the first build-up wiring layer 142 and the second build-up wiring layer 152 can have a side shape different from that of the first wiring layer 120. However, this is not necessarily limited to this, and when the method for forming the first wiring layer 120 is used to form the first build-up wiring layer 142 and / or the second build-up wiring layer 152, the first build-up wiring layer 142 and / or the second build-up wiring layer 152 can also have the same shape as the first wiring layer 120.

[0069] Meanwhile, among the configurations other than those related to the shape of the side of the first wiring layer 120, such as the first pad 121, the second pad 122, and the first wiring 126, the same configurations as those of the printed circuit board of one example can also be applied to the printed circuit board of another example, and therefore, duplicate explanations regarding this will be omitted.

[0070] In the present disclosure, the cross-sectional meaning may refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and the planar meaning may refer to the shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0071] In this disclosure, for convenience, the terms upper side, top, top surface, etc. are used to mean a direction toward a surface on which electronic components can be mounted based on a cross section of a drawing, and the terms lower side, bottom, bottom surface, etc. are used to mean the opposite direction. However, this is a definition of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of such directions.

[0072] In the present disclosure, the term "connected" refers not only to a direct connection but also to an indirect connection via an adhesive layer or the like. The term "electrically connected" refers to a physical connection and a non-connection. Furthermore, the terms "first" and "second" are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the right.

[0073] In the present disclosure, the determination can be made by taking into account process errors, positional deviations, measurement errors, etc. that occur substantially in the manufacturing process. For example, being substantially perpendicular / parallel can include not only being completely perpendicular / parallel, but also being approximately perpendicular / parallel. Furthermore, being substantially coplanar can include not only being completely on the same plane, but also being approximately on the same plane.

[0074] In the present disclosure, the same material can mean not only the exact same material, but also the same type of material, and thus the compositions of the materials are substantially the same, although the specific composition ratios thereof may vary slightly.

[0075] The expression "one example" used in the present disclosure does not mean the same embodiment as the other, but is provided to emphasize and describe the unique features that are different from each other. However, the above-mentioned one example does not exclude being realized in combination with the features of another example. For example, even if the matter described in a particular example is not described in another example, it can be understood that it is a description related to the other example, unless there is a description that is opposite or contradictory to the matter in the other example.

[0076] The terms used in the present disclosure are merely used to describe an example and are not intended to limit the present disclosure. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0077] 110 Core Layer 120 1st wiring layer 121 1st pad 122 2nd pad 121-1, 122-1 adjacent area 121-2, 122-2 Open area 124 1st pattern 126 1st wiring 130 Through Via 141, 151 First and second build-up insulating layers 142, 152 First and second build-up wiring layers 143, 153 1st and 2nd build-up via layers 160 Solder resist layer 170 Surface treatment layer 1000 Electronics 1010 Mainboard 1020 Chip-related parts 1030 Network-related parts 1040 Other parts 1050 Camera module 1060 Antenna module 1070 Display 1080 Battery 1090 Signal line 1100 Smartphone 1110 Smartphone internal main board 1120 Smartphone internal electronic components 1121 Smartphone Internal Antenna Module 1130 Smartphone internal camera module 1140 Smartphone internal speaker

Claims

1. A core layer; A plurality of first wirings arranged on the core layer; a first pad disposed on the core layer, the first pad including an adjacent portion disposed substantially parallel to an adjacent one of the first wirings and an open portion disposed substantially not parallel to an adjacent one of the first wirings; a first build-up insulating layer disposed on the core layer and covering at least a portion of the first wirings and the first pads; The core layer comprises a substantially different insulating material than the first build-up insulating layer.

2. The printed circuit board according to claim 1 , wherein the first wiring and the first pad are disposed on an upper surface and a lower surface of the core layer, respectively.

3. The printed circuit board according to claim 2 , wherein the first wiring and the first pad protrude from the upper and lower surfaces of the core layer, respectively, and are embedded in the first build-up insulating layer.

4. a second pad disposed on the core layer, the second pad including an adjacent portion disposed substantially parallel to an adjacent one of the first wirings and an open portion disposed substantially not parallel to an adjacent one of the first wirings; The printed circuit board according to claim 1 , further comprising a through via connected to the second pad and penetrating the core layer.

5. The width of the first pad is narrower than the width of the second pad, The printed circuit board according to claim 4 , wherein a line width of the plurality of first wirings is narrower than a width of the first pad.

6. The printed circuit board according to claim 4 , wherein each of the first pad and the second pad has a shape in which the width of the upper surface is narrower than the width of the lower surface and the width of a central portion is narrower than the width of the upper surface.

7. The printed circuit board according to claim 6 , wherein at least one of the plurality of first wirings has a shape in which the width of an upper surface is narrower than the width of a lower surface and the width of a central portion is narrower than the width of the upper surface.

8. a distance between the adjacent portion of the first pad and one of the first wirings adjacent to the first pad is substantially equal to a distance between adjacent wirings of the first wirings; 5. The printed circuit board of claim 4, wherein a distance between an adjacent portion of the second pad and one of the first wirings adjacent to the second pad is substantially the same as a distance between adjacent wirings of the first wirings.

9. a first build-up wiring layer disposed on the first build-up insulating layer; The printed circuit board of claim 1 , further comprising: a first build-up via layer penetrating at least a portion of the first build-up insulating layer to connect the first build-up wiring layer and the first pad to each other.

10. a second build-up insulation layer disposed on the first build-up insulation layer; a second build-up wiring layer disposed on the second build-up insulating layer; The printed circuit board according to claim 9 , further comprising: a second build-up via layer penetrating at least a portion of the first build-up insulating layer to connect the second build-up wiring layer and the first build-up wiring layer to each other.

11. a second wiring connected to the first pad, The printed circuit board of claim 1 , wherein the opening of the first pad is disposed on an opposite side to a region where the first pad and the second wiring are connected.

12. a first built-up via connected to the first pad, The printed circuit board of claim 11 , wherein the first build-up via is disposed closer to the second trace than an open portion of the first pad.

13. A first insulating layer; A plurality of first wirings disposed on an upper surface and a lower surface of the first insulating layer, a first pad disposed on an upper surface and a lower surface of the first insulating layer, the first pad including an adjacent portion disposed substantially parallel to an adjacent one of the first wirings and an open portion disposed substantially not parallel to an adjacent one of the first wirings, A printed circuit board, wherein a distance between an adjacent portion of the first pad and an adjacent wiring among the plurality of first wirings is substantially the same as a distance between adjacent wirings among the plurality of first wirings.

14. a second insulating layer disposed on an upper surface and a lower surface of the first insulating layer and covering at least a portion of the first wirings and the first pads; The printed circuit board of claim 13 , further comprising a first via penetrating at least a portion of the second insulating layer and coupled to the first pad.

15. a second wiring connected to the first pad, The printed circuit board of claim 14 , wherein the opening of the first pad is disposed on an opposite side to a region where the first pad and the second wiring are connected.

16. a first built-up via connected to the first pad, The printed circuit board of claim 15 , wherein the first build-up via is disposed closer to the second trace than an open portion of the first pad.

17. a first pattern disposed on the first insulating layer and having a plane shape; 14. The printed circuit board of claim 13, wherein a distance between the first pattern and the first pad is substantially the same as a distance between an adjacent portion of the first pad and an adjacent wiring among the plurality of first wirings.

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