Display device

Abstract

To provide a semiconductor device that can reduce standby power.SOLUTION: A transistor including an oxide semiconductor as an active layer is used as a switching element, and by this switching element, the supply of power source voltage to a circuit included in an integrated circuit is controlled. Specifically, when the circuit is in an operation state, the power source voltage is supplied to the circuit by the switching element and when the circuit is in a stop state, the supply of the power source voltage to the circuit is stopped by the switching element. The circuit to which the power source voltage is supplied includes one or more semiconductor elements corresponding to the minimum unit of the integrated circuit, such as a transistor, a diode, a capacitor, a resistor, or an inductor formed using semiconductor. The semiconductor included in the semiconductor element includes silicon with crystallinity (crystalline silicon), specifically, microcrystalline silicon, polycrystalline silicon, and single-crystal silicon.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device using a thin semiconductor film. [Background technology]

[0002] Thin film transistors using semiconductor films formed on insulating surfaces are essential for semiconductor devices. Thin-film transistors are essential semiconductor elements. The manufacturing of thin-film transistors is limited by the heat resistance of the substrate. In order to achieve this, amorphous silicon, which can be formed at a relatively low temperature, and laser light or catalytic elements are used. A thin film transistor having an active layer made of polysilicon or the like obtained by crystallization using the above method is a semiconductor. This has become the mainstream type of transistor used in semiconductor displays.

[0003] In recent years, it has become possible to obtain higher mobility than amorphous silicon and Oxide semiconductors are new semiconductor materials that have uniform device characteristics obtained by silicon silicide. Metal oxides that exhibit semiconducting properties, known as semiconductors, are attracting attention. For example, indium oxide, a well-known metal oxide, is used in liquid crystal displays. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors that use metal oxides that exhibit excellent semiconductor properties in the channel formation region are already known. It has been reported (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0005] By the way, silicon wafers and SOI (Silicon on Insulator) substrates A semiconductor integrated circuit (hereinafter referred to as an integrated circuit) manufactured using a thin semiconductor film on an insulating surface The power consumption of a power supply (also called a power supply) is the power consumption when the circuit is in operation and the power consumption when the circuit is in a stopped state. The power consumption of an integrated circuit is roughly equal to the sum of the power consumption of the As the integration density increases, the operating voltage decreases. The former power consumption, which occurs during standby, is on the decline. The proportion of power consumption is increasing, and in order to further reduce power consumption, it is important to reduce standby power consumption. This becomes a major challenge.

[0006] Standby power can be classified into static standby power and dynamic standby power. A state in which no voltage is applied between the electrodes of a transistor, which is a child element, i.e., When the voltage between the source and drain electrodes is almost zero, The power is consumed due to leakage currents between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. Dynamic standby power is the power consumed by circuits in a stopped state (hereafter referred to as non-operating circuits). The voltages of various signals such as clock signals and power supply voltages are continuously supplied, This is the power consumed by charging and discharging the gate capacitance of the transistor and the parasitic capacitance of wiring, etc.

[0007] As integration progresses, the channel length of transistors becomes shorter and the gate insulating film and other The thickness of the insulating film of the semiconductor device is getting thinner. Therefore, the leakage current of the transistor is increasing. Static standby power consumption is on the rise.

[0008] In order to reduce dynamic standby power consumption, the supply of power supply voltage to non-operating circuits is stopped and non-operating circuits are turned off. It is effective to prevent unnecessary charging and discharging in various capacitances of the operating circuit. However, the switching element for stopping the supply of power voltage is usually a transistor. As mentioned above, the leakage current of transistors increases with the increase in integration density. Since current is on the rise, the leakage current prevents dynamic standby power reduction. There are.

[0009] In view of the above problems, the present invention discloses a semiconductor device and a method for manufacturing the same that realizes a reduction in standby power consumption. One of the objectives is to provide a manufacturing method. [Means for solving the problem]

[0010] A transistor having an oxide semiconductor as an active layer is used as a switching element, and the switching A switching element controls the supply of power supply voltage to the circuits that make up the integrated circuit. When the circuit is in an operating state, the switching element supplies the power supply voltage to the circuit. When the circuit is in a stopped state, the switching element controls the supply of the power supply voltage to the circuit. In addition, the circuit to which the power supply voltage is supplied is a transistor formed using a semiconductor. The smallest elements that make up an integrated circuit, such as capacitors, diodes, capacitance elements, resistance elements, and inductances. The semiconductor element has one or more unit semiconductor elements. The semiconductor element has Silicon having crystallinity (crystalline silicon), specifically, microcrystalline silicon, polycrystalline silicon, Includes silicon and monocrystalline silicon.

[0011] In the oxide semiconductor film, in the gate insulating film, or at the interface between the oxide semiconductor film and other insulating films, Impurities such as moisture or hydrogen present on the surface and its vicinity are removed by heat treatment, etc. do.

[0012] Highly purified acid with reduced impurities such as water or hydrogen, which act as electron donors. Purified OS semiconductors are i-type (intrinsic semiconductors) or very close to i-type. Therefore, the transistor including the oxide semiconductor has a feature that the off-state current is extremely low. Specifically, the highly purified oxide semiconductor can be analyzed by secondary ion mass spectrometry (SIM S: Hydrogen concentration by Secondary Ion Mass Spectroscopy The degree measurement is 5 x 10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 More details below. Preferably 5 x 10 17 / cm 3 Less than 1×10, more preferably 16 / cm 3 The following The carrier density of the oxide semiconductor film, which can be measured by Hall effect measurement, is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 1 1 / cm 3 The band gap of the oxide semiconductor is preferably 2 eV or more. is 2.5 eV or more, more preferably 3 eV or more. By using a highly purified oxide semiconductor film in which the amount of fluorine is sufficiently reduced, The off-state current can be reduced.

[0013] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor film as an active layer The low value of can be proved by various experiments. For example, when the channel width is 1×10 6 μm Even if the channel length of the device is 10 μm, the voltage between the source and drain electrodes (drain The off-state current (voltage between the gate and source electrodes) is in the range of 1V to 10V. The drain current when the input voltage is set to 0 V or less is below the measurement limit of the semiconductor parameter analyzer. , i.e. 1 × 10 -13 In this case, the off-current can be reduced to less than 1 A. The off-state current density, which corresponds to the value divided by the channel width of the transistor, is 100zA / μm or more. In addition, by connecting the capacitor and the transistor, or a circuit that controls the charge flowing out of a capacitor using the transistor. In the measurement, a highly purified oxide semiconductor film was formed in the transistor. It is used in the channel formation region, and the charge amount per unit time of the capacitance element is used to calculate the capacitance of the transistor. The off-state current density of the transistor was measured. At a voltage of 3 V, even lower off-state current densities of a few tens of yA / μm can be obtained. Therefore, in the semiconductor device according to one embodiment of the present invention, a highly purified oxide semiconductor The off-state current density of a transistor using a conductive film as an active layer was measured by Depending on the voltage between the two terminals, the current may be 100 yA / μm or less, preferably 10 yA / μm or less, and more preferably Therefore, the highly purified oxide semiconductor film can be formed with a high conductivity. The transistor used as the active layer has an off-state current of crystalline silicon. On the other hand, transistors using crystalline silicon have The transistor has higher mobility and higher on-state current than a transistor including an oxide semiconductor.

[0014] Therefore, a circuit is formed using a semiconductor element having crystalline silicon, and a transistor having an oxide semiconductor is formed using the semiconductor element having crystalline silicon. A transistor is used as a switching element, and the power supply voltage to the circuit is By controlling the supply of current, it is possible to realize high integration and high speed operation of integrated circuits while minimizing leakage current. This can suppress the increase in standby power consumption caused by the above.

[0015] The oxide semiconductor is an In-Sn-Ga-Zn-O oxide semiconductor, which is a quaternary metal oxide. Conductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors, In-Sn-Z nO-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors Conductors, binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxides Semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, , In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. In the present specification, for example, an In-Sn-Ga-Zn-O system Oxide semiconductors are made of indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The composition ratio is not particularly limited. The semiconductor may include silicon.

[0016] Alternatively, the oxide semiconductor may have the chemical formula InMO3(ZnO) m (m>0) Here, M is one or more metal elements selected from Ga, Al, Mn, and Co. Shows.

[0017] The transistor including an oxide semiconductor may be a bottom-gate type or a top-gate type. The bottom-gate transistor may be a bottom-contact type. a gate electrode on an insulating surface, a gate insulating film on the gate electrode, and The oxide semiconductor film overlaps with the gate electrode, and the source electrode and the drain electrode are formed on the oxide semiconductor film. and an insulating film on the source electrode, the drain electrode, and the oxide semiconductor film. The transistor has an oxide semiconductor film on an insulating surface, a source electrode and a A drain electrode, an oxide semiconductor film, a gate insulating film on the source electrode and the drain electrode, and a gate insulating film on the gate a gate electrode overlapping the oxide semiconductor film on the gate insulating film, and an insulating film on the gate electrode. A bottom-contact transistor has a gate electrode on an insulating surface and a A gate insulating film of the gate insulating film, a source electrode, a drain electrode, and a source electrode and a drain electrode on the gate insulating film. an oxide semiconductor film that is on the gate electrode and overlaps with the gate electrode on the gate insulating film; The gate insulating film includes a source electrode, a drain electrode, and an insulating film over the oxide semiconductor film. Effect of the Invention

[0018] By suppressing the leakage current of transistors used as switching elements, It is possible to reduce the standby power consumption of the semiconductor device while achieving integration and high-speed operation. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a block diagram of a semiconductor device. [Diagram 2] 1A and 1B are diagrams illustrating a configuration and operation of a semiconductor device using an inverter. [Diagram 3] 1A and 1B are diagrams illustrating a configuration and operation of a semiconductor device using NAND. [Figure 4] 1A and 1B are diagrams showing a configuration and operation of a semiconductor device using NOR. [Diagram 5] FIG. 13 illustrates a structure of a semiconductor device using a flip-flop. [Figure 6] 1A and 1B are diagrams illustrating a configuration and operation of a semiconductor device using a flip-flop. [Figure 7] 1A and 1B are diagrams illustrating a configuration and operation of a semiconductor device using a flip-flop. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 11] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 12] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 13] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 14] FIG. 1 is a diagram showing a configuration of a semiconductor display device. [Figure 15] FIG. 1 is a diagram showing a configuration of a semiconductor display device. [Figure 16] Electronic devices illustration. [Figure 17] 1A and 1B are diagrams illustrating a configuration and operation of a semiconductor device using a flip-flop. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0021] The present invention is applicable to integrated circuits such as microprocessors and image processing circuits, RF tags, semiconductors, etc. It can be used to manufacture various semiconductor devices, such as display devices. The LCD is a display device that has a light-emitting element, typically an organic light-emitting diode (OLED), in each pixel. Optical devices, electronic paper, DMD (Digital Micromirror Device e), PDP (Plasma Display Panel), FED (Field E mission display) and other devices that have driving circuits using semiconductor elements Other semiconductor display devices are included in this category.

[0022] (Embodiment 1) 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. Silicon wafers, SOI (Silicon on Insulator) substrates, insulators A circuit 100 made of a silicon thin film on a surface and a power supply voltage to the circuit 100 The switching element 101 controls the supply of a control signal. Specifically, when the circuit 100 is in an active state, the switching is performed according to a control signal. As a result, the switching element 101 is turned on, and the power supply voltage is supplied to the circuit 100. Also, when the circuit 100 is in a stopped state, the switching element 101 is turned off in accordance with the control signal. This causes the supply of power supply voltage to the circuit 100 to stop.

[0023] The circuit 100 includes transistors, diodes, capacitance elements, resistance elements, inductance elements, etc. The semiconductor device has one or more semiconductor elements, which are the minimum units that constitute a circuit. The semiconductor of the element is silicon having crystallinity (crystalline silicon), specifically, microcrystalline These include silicon, polycrystalline silicon, and single crystal silicon.

[0024] The circuit 100 includes basic logic elements such as inverters, NAND, NOR, AND, and OR. A flip-flop, which is a combination of these logic gates, It can be a logic circuit such as a register or a shift register, or a combination of multiple logic circuits. It may be a large-scale arithmetic circuit.

[0025] The switching element 101 is at least a transistor having an oxide semiconductor as an active layer. When the switching element 101 has a plurality of the above transistors, The transistors may be connected in parallel or in series. Alternatively, the circuits may be connected in series and parallel in combination.

[0026] The state in which the transistors are connected in series is when the source electrode of the first transistor and the drain electrode of the second transistor. In addition, transistors connected in parallel The state where the source electrode of the first transistor is connected to the source voltage of the second transistor is called the "connected" state. the drain electrode of the first transistor is connected to the drain electrode of the second transistor This means that the device is connected to

[0027] The source electrode and the drain electrode of the transistor are connected to each other. The name is changed depending on the difference in potential between the electrodes. Generally, n-channel In a transistor with a low potential, the electrode to which a high potential is applied is called the source electrode. The electrode that is connected to the drain electrode is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In this specification, for convenience, it is assumed that the source electrode and the drain electrode are fixed. In this paper, the transistor connections are explained by setting the potentials as shown above. The names of the source and drain electrodes are interchangeable.

[0028] As described above, in a transistor including an oxide semiconductor, leakage current is low when the transistor has crystallinity. This is significantly lower than that of a transistor using silicon. A transistor is used as the switching element 101, and the above circuit is By controlling the supply of power supply voltage to 100, the leakage current of the switching element 101 is reduced. This can suppress an increase in standby power consumption caused by the above.

[0029] In addition, by reducing the power consumption of the circuit 100, the operation of other circuits that control the operation of the circuit 100 can be reduced. Therefore, the entire integrated circuit using the circuit 100 and other circuits that control it can be The body's functions can be expanded.

[0030] On the other hand, a transistor using crystalline silicon is different from a transistor using an oxide semiconductor. Generally, they have higher mobility and higher on-state current than MOSFETs. By forming the circuit 100 with semiconductor elements, it is possible to achieve high integration and It is possible to realize high speed driving.

[0031] Next, a specific configuration and a circuit diagram of the semiconductor device will be described with reference to an example in which the circuit 100 is an inverter. The operation will be explained with reference to FIG.

[0032] In the semiconductor device illustrated in FIG. 2A, a circuit 100 includes a p-channel transistor 110 and The transistor 110 and the transistor 111 are n-channel transistors. Both of the transistors 110 and 111 use crystalline silicon for the active layer. and transistor 111 form an inverter.

[0033] Specifically, the drain electrode of the transistor 110 and the drain electrode of the transistor 111 The drain electrode of the transistor 110 and the drain electrode of the transistor 111 are connected to each other. The potential of the drain electrode of the transistor is given to the subsequent circuit as the potential of the output signal. The resulting wiring or electrodes have various capacitances, such as parasitic capacitance. Their capacitance is shown as load 112.

[0034] The gate electrodes of the transistors 110 and 111 are connected to an input signal The source electrode of the transistor 110 is supplied with a high-level power supply voltage VDD The source electrode of the transistor 111 is connected to the switching element 101. A low-level power supply voltage VSS is applied via the

[0035] In this specification, a connection means an electrical connection, and is a connection capable of transmitting a current or a voltage. This corresponds to a possible state.

[0036] In FIG. 2A, a switching element 101 supplies a low-level power supply voltage VS to a circuit 100. Next, FIG. 2B shows a case where the supply of S is controlled. 1 controls the supply of a high-level power supply voltage VDD to a circuit 100. The semiconductor device shown in FIG. 2B has a structure similar to that shown in FIG. The transistor 110 is a n-channel transistor and the transistor 111 is a n-channel transistor. The transistor 110 and the transistor 111 both use crystalline silicon for their active layers. The transistors 110 and 111 form an inverter. .

[0037] Specifically, the drain electrode of the transistor 110 and the drain electrode of the transistor 111 The drain electrode of the transistor 110 and the drain electrode of the transistor 111 are connected to each other. The potential of the drain electrode of the transistor is given to the subsequent circuit as the potential of the output signal. The resulting wiring or electrodes have various capacitances, such as parasitic capacitance, and in FIG. Their capacitance is shown as load 112.

[0038] The gate electrodes of the transistors 110 and 111 are connected to an input signal The source electrode of the transistor 110 is connected to the switching element 101. A high-level power supply voltage VDD is applied via the source A low-level power supply voltage VSS is applied to the electrodes.

[0039] The switching element 101 switches in response to a control signal. Taking an apparatus as an example, a period during which the circuit 100 is in an active state (active period) and a period during which the circuit 100 is in an inactive state (inactive period) will be described. The timing chart of the potentials of the input signal, output signal, and control signal during the operation period is shown in FIG. As shown in (C).

[0040] During the operation period, the control signal has a potential at which the switching element 101 is turned on. Specifically, FIG. 2C illustrates a case where the control signal has a high-level potential. Therefore, during the operation period, the power supply voltage VSS is applied to the source electrode of the transistor 111. When the potential of the input signal is at a low level, an output having a high level potential is obtained. When the potential of the input signal is at a high level, a signal having a low level potential is obtained. An output signal is obtained.

[0041] During the non-operating period, the control signal has a potential such that the switching element 101 is turned off. Specifically, FIG. 2C illustrates a case where the control signal has a low-level potential. Therefore, during the non-operating period, the power supply voltage VSS is , and the source electrode of transistor 111 is left floating. Therefore, whether the potential of the input signal is low level or high level, the potential of the output signal is The ranking will remain at a high level.

[0042] As described above, during the non-operating period, the supply of the power supply voltage to the circuit 100 is stopped. This reduces the dynamic standby power consumed by the circuit 100. Since the gate element 101 is a semiconductor element using an oxide semiconductor film, leakage current, etc. Therefore, the static standby power that depends on the power supply voltage to non-operating circuits can be reduced. This reduces both the static and dynamic standby power consumed by non-operating circuits by shutting down the supply. In this way, a semiconductor device capable of reducing the power consumption of the entire circuit can be provided.

[0043] Next, the specific configuration and operation of the semiconductor device will be described by taking the case where the circuit 100 is a NAND as an example. The operation will be explained with reference to FIG.

[0044] In the semiconductor device illustrated in FIG. 3A, a circuit 100 includes a p-channel transistor 120 and A p-channel transistor 121, an n-channel transistor 122, and an n-channel The transistor 120, the transistor 121, and the transistor 123 are of a transistor type. The transistors 122 and 123 both use crystalline silicon for their active layers. Then, transistor 120, transistor 121, transistor 122, NAND is composed of register 123.

[0045] Specifically, the source electrode of the transistor 120 and the source electrode of the transistor 121 are A high-level power supply voltage VDD is applied. The gate electrode of the transistor 122 is supplied with the potential of the input signal 1. The drain electrode of transistor 121, the drain electrode of transistor 122, The drain electrodes are connected to the drain electrodes, and the potential of these drain electrodes is output to the downstream The wiring or electrodes to which the output signal is applied have various capacitances, such as parasitic capacitance. In FIG. 3A, these capacitances are shown as loads 124. The source electrode of the transistor 122 is connected to the drain electrode of the transistor 123. The gate electrode of the transistor 121 and the gate electrode of the transistor 123 are connected to the potential of the input signal 2. The source electrode of the transistor 123 is connected to the switching element 10. A low-level power supply voltage VSS is applied via 1.

[0046] In FIG. 3A, a switching element 101 supplies a low-level power supply voltage VS to a circuit 100. Next, FIG. 3B shows a case where the supply of S is controlled. 1 controls the supply of a high-level power supply voltage VDD to a circuit 100. The semiconductor device shown in FIG. 3B has a structure similar to that shown in FIG. A transistor 120 of a p-channel type, a transistor 121 of a p-channel type, and a transistor 122 of an n-channel type The transistor 122 is a n-channel type transistor, and the transistor 123 is a n-channel type transistor. The transistors 120, 121, 122, and 123 are all crystalline. Silicon having a high thermal conductivity is used for the active layer. 121, transistor 122, and transistor 123 form a NAND.

[0047] Specifically, the source electrode of the transistor 120 is connected to a switching element 101a via A high-level power supply voltage VDD is applied to the source electrode of the transistor 121. A high-level power supply voltage VDD is applied via the switching element 101b. In FIG. 3(B), the supply of the power supply voltage VDD to the circuit 100 is controlled by a plurality of switching elements 101. a, the case where the switching element 101b is used for control is illustrated. The gate electrode of the transistor 120 and the gate electrode of the transistor 122 may be singular. The gate electrode is supplied with the potential of the input signal 1. The drain voltage of the transistor 120 is The drain electrode of the transistor 121 and the drain electrode of the transistor 122 are connected to each other. The potential of these drain electrodes is given to the subsequent circuit as the potential of the output signal. The wiring or electrodes to which the output signal is applied have various capacitances such as parasitic capacitance. In FIG. 3B, these capacitances are shown as loads 124. The source electrode of the transistor 121 is connected to the drain electrode of the transistor 123. The gate electrode of the transistor 121 and the gate electrode of the transistor 122 are supplied with the potential of the input signal 2. A low-level power supply voltage VSS is applied to the source electrode of the transistor 123. can be done.

[0048] The switching element 101 switches in response to a control signal. Taking an apparatus as an example, a period during which the circuit 100 is in an active state (active period) and a period during which the circuit 100 is in an inactive state (inactive period) will be described. The timing chart of the potentials of the input signal, output signal, and control signal during the period of operation is shown in FIG. As shown in (C).

[0049] During the operation period, the control signal has a potential at which the switching element 101 is turned on. Specifically, FIG. 3C illustrates a case where the control signal has a high-level potential. Therefore, during the operation period, the power supply voltage VSS is applied to the source electrode of the transistor 123. Then, when the potential of the input signal 1 is at a high level and the potential of the input signal 2 is at a high level, When the potential of the input signal 1 becomes low, an output signal having a low level potential is obtained. When the potential of input signal 2 is high, an output signal having a high potential is obtained. can be done.

[0050] During the non-operating period, the control signal has a potential such that the switching element 101 is turned off. Specifically, FIG. 3C illustrates a case where the control signal has a low-level potential. Therefore, during the non-operating period, the power supply voltage VSS is , and the source electrode of transistor 123 is floating. Therefore, whether the potential of input signal 1 and input signal 2 is low level or high level, The potential of the output signal remains at a high level.

[0051] As described above, during the non-operating period, the supply of the power supply voltage to the circuit 100 is stopped. This reduces the dynamic standby power consumed by the circuit 100. Since the gate element 101 is a semiconductor element using an oxide semiconductor film, leakage current, etc. Therefore, the static standby power that depends on the power supply voltage to non-operating circuits can be reduced. This reduces both the static and dynamic standby power consumed by non-operating circuits by shutting down the supply. In this way, a semiconductor device capable of reducing the power consumption of the entire circuit can be provided.

[0052] Next, the specific configuration and operation of the semiconductor device will be described by taking the case where the circuit 100 is a NOR as an example. This will be explained with reference to FIG.

[0053] In the semiconductor device illustrated in FIG. 4A, a circuit 100 includes a p-channel transistor 130 and A p-channel transistor 131, an n-channel transistor 132, and an n-channel The transistor 130, the transistor 131, and the transistor 133 are of a transistor type. The transistors 132 and 133 both use crystalline silicon for their active layers. Then, transistor 130, transistor 131, transistor 132, Register 133 constitutes a NOR.

[0054] Specifically, a high-level power supply voltage VDD is applied to the source electrode of the transistor 130. The gate electrodes of the transistors 130 and 133 are connected to an input The potential of signal 1 is applied to the drain electrode of transistor 130 and the drain electrode of transistor 1 The gate electrode of the transistor 131 and the source electrode of the transistor 31 are connected. The gate electrode of the transistor 132 is supplied with the potential of the input signal 2. the drain electrode of transistor 132; and the drain electrode of transistor 133. The drain electrodes are connected to the output terminals, and the potential of these drain electrodes is output to the downstream circuit as the potential of the output signal. The wiring or electrodes to which the output signal is applied have various capacitances such as parasitic capacitance. In FIG. 4A, these capacitances are shown as loads 134. A low-level power supply voltage VSS is applied to the source electrode of the second switching element 101a via the switching element 101a. The source electrode of the transistor 133 is supplied with a voltage via the switching element 101b. In FIG. 4A, the power supply voltage VSS is applied. The supply of the power to the circuit 100 is controlled by a plurality of switching elements 101a, 101b, However, the number of switching elements may be single.

[0055] In FIG. 4A, switching elements 101a and 101b are connected to a circuit 100. FIG. 4B illustrates a case where the supply of the power supply voltage VSS is controlled. When the switching element 101 controls the supply of a high-level power supply voltage VDD to the circuit 100, 4B shows the structure of a semiconductor device. The semiconductor device shown in FIG. 4B has a circuit 100 includes a p-channel transistor 130 and a p-channel transistor 131. , an n-channel transistor 132 and an n-channel transistor 133 Transistor 130, transistor 131, transistor 132, transistor 133 Both of the transistors 130 and 131 use crystalline silicon for their active layers. The transistors 131, 132, and 133 form a NOR. .

[0056] Specifically, the source electrode of the transistor 130 is connected to the switching element 101 via the switching element 101 as follows: A high-level power supply voltage VDD is applied. The gate electrode of the transistor 133 is supplied with the potential of the input signal 1. The drain electrode of the transistor 131 is connected to the source electrode of the transistor 131. The potential of the input signal 2 is applied to the gate electrode of the transistor 131 and the gate electrode of the transistor 132. The drain electrode of the transistor 131 and the drain electrode of the transistor 132 are , and the drain electrode of the transistor 133 are connected, and the potential of these drain electrodes is The potential of the output signal is supplied to a subsequent circuit. In FIG. 4B, these capacitances are represented as load 134. The source electrode of the transistor 132 and the source electrode of the transistor 133 are shown. A low-level power supply voltage VSS is applied to the

[0057] The switching element 101 switches in response to a control signal. Taking an apparatus as an example, a period during which the circuit 100 is in an active state (active period) and a period during which the circuit 100 is in an inactive state (inactive period) will be described. The timing chart of the potentials of the input signal, output signal, and control signal during the period of operation is shown in FIG. As shown in (C).

[0058] During the operation period, the control signal is applied to the switching element 101a and the switching element 101b. Specifically, in FIG. 4C, the control signal has a high level potential. Therefore, during the operation period, the power supply voltage VSS has a The voltage Vcc is applied to the source electrode of the transistor 132 and the source electrode of the transistor 133. When the potential of input signal 1 is low level and the potential of input signal 2 is low level, When the potential of input signal 1 is at a high level and the potential of input signal 2 is at a low level, an output signal having a potential of When the potential of the input terminal is at a low level, an output signal having a low level potential is obtained.

[0059] During the non-operating period, the control signal is Specifically, in FIG. 4C, the control signal is at a low level. Therefore, during the non-operating period, the power supply voltage VSS is The source electrode of the transistor 132 and the source electrode of the transistor 133 are not provided with The source electrodes of the transistors 132 and 133 are floating. Therefore, even if the potential of input signal 1 and input signal 2 is at a low level, Even if the level is high, the potential of the output signal remains low.

[0060] As described above, during the non-operating period, the supply of the power supply voltage to the circuit 100 is stopped. This reduces the dynamic standby power consumed by the circuit 100. Since the gate element 101 is a semiconductor element using an oxide semiconductor film, leakage current, etc. Therefore, the static standby power that depends on the power supply voltage to non-operating circuits can be reduced. This reduces both the static and dynamic standby power consumed by non-operating circuits by shutting down the supply. In this way, a semiconductor device capable of reducing the power consumption of the entire circuit can be provided.

[0061] Next, a specific structure of the semiconductor device will be described by taking the case where the circuit 100 is a flip-flop as an example. The structure and operation will be described with reference to FIGS.

[0062] In the semiconductor device shown in FIG. 5A, the circuit 100 is a flip-flop. The clock signal is input to the terminal CK, and the output signal 1 is output from the terminal Q, and the output signal 2 is output from the terminal Qb. The specific circuit configuration of the flip-flop is to use the feedback effect to output 1 bit. Any circuit configuration is acceptable as long as it can hold data for the number of bits. 5B shows a more specific configuration of the circuit 100. The circuit 100 shown in FIG. This is a D flip-flop using AND141, NAND142, and NAND143. The potential of the input signal is applied to the first input terminal of the AND 140. The potential of the clock signal is applied to the input terminal of NAND142 and the second input terminal of NAND143. The output terminal of NAND 140 is connected to a first input terminal of NAND 142 and a second input terminal of NAND 141. The output terminal of NAND 142 is connected to the first input terminal of NAND 143. The output terminal of the NAND 141 is connected to the first input terminal of the NAND 143. The potential of the output terminal of NAND141 is connected to the input terminal, and the potential of the output terminal of NAND141 is the potential of output signal 1. The output terminal of the NAND 143 is the first input of the NAND 141. 2, and the potential of the output terminal of NAND143 is output signal 2 This potential is provided to the subsequent circuit.

[0063] The circuit 100 shown in FIG. 5B is configured to obtain an output signal 1 and an output signal 2. However, if necessary, the output signal may be reduced to one.

[0064] And the power supply to NAND140, NAND141, NAND142, and NAND143 The supply of pressure is controlled by a switching element 101. For example, the supply of the power supply voltage VSS of the bell is controlled by a switching element 101. 1, the supply of a high-level power supply voltage is controlled by a switching element 101. It's fine if it is.

[0065] FIG. 6A shows an example of a detailed circuit diagram of a semiconductor device. The connections of the transistors in 141, NAND142, and NAND143 are as follows: , see FIG. 3(A) and FIG. 3(B). NAND140, NAND141, Each transistor constituting NAND142 and NAND143 is made of crystalline silicon. In addition, in FIG. 6(A), unlike FIG. 5(A), the switching element The switching elements 101a to 101d are used to When controlling the supply of power supply voltage VSS to AND142 and NAND143 The following is an example.

[0066] Taking the semiconductor device in FIG. 6A as an example, a period in which the circuit 100 is in an operating state (operating period) and a period in which the circuit 100 is in a stopped state (operating period) are shown. The timing of the potentials of the input signals, output signals, and control signals during the stop state (non-operating period) The switching element 101a to the switching element 101 d switches in accordance with the control signal.

[0067] During the operation period, the control signal is applied to the switching elements 101a to 101d. Specifically, in FIG. 6B, the control signal has a high level potential. Therefore, in the operation period, the power supply voltage VSS has a value of NAN. The potential of the clock signal is given to NAND140 through NAND143. is a low level, and when the potential of the input signal is high level, the output signal has a high level potential. 1, an output signal 2 having a low level potential is obtained. Also, the potential of the clock signal is high. When the potential of the input signal is at a low level, the potential of the input signal is at a low level. Thus, an output signal 1 having a low potential and an output signal 2 having a high potential are obtained.

[0068] During the non-operating period, the control signal is Specifically, in FIG. 6B, the control signal is at a low level. Therefore, during the non-operating period, the power supply voltage VSS is That is, the power supply voltage is not applied to AND140 to NAND143 during operation. The source electrode of the transistor to which the voltage VSS is applied is floating during the non-operating period. Therefore, even if the potential of the clock signal and the input signal is at a low level, Even if the output is at the off level, the potentials of output signals 1 and 2 are equal to the potentials just before entering the non-operating period. Hold.

[0069] As described above, during the non-operating period, the supply of the power supply voltage to the circuit 100 is stopped. This reduces the dynamic standby power consumed by the circuit 100. Since the gate element 101 is a semiconductor element using an oxide semiconductor film, leakage current, etc. Therefore, the static standby power that depends on the power supply voltage to non-operating circuits can be reduced. This reduces both the static and dynamic standby power consumed by non-operating circuits by shutting down the supply. In this way, a semiconductor device capable of reducing the power consumption of the entire circuit can be provided.

[0070] In the semiconductor device of the present invention, when the circuit 100 is in a stopped state, The semiconductor element provides a configuration for stopping the supply of a clock signal to the circuit 100. Next, a case where the circuit 100 is a flip-flop will be taken as an example. A semiconductor device capable of controlling the supply of a power supply voltage to a power supply circuit and the supply of a clock signal to the power supply circuit. The specific configuration and operation will be described with reference to FIG.

[0071] The semiconductor device shown in FIG. 7A includes a circuit 100, a switching element 101, and a The control circuit 102 can control the supply of a clock signal to the control circuit 100. In addition to the clock signal, the circuit 102 also receives a control signal 1 for controlling the operation of the control circuit 102. FIG. 7A shows an example in which AND is used in the control circuit 102. In this figure, the clock signal and the control signal are both input to the AND. The signal output from the input terminal is input to the circuit 100. The circuit 100 is a flip-flop. The input signal is input to terminal D, the signal output from the control circuit 102 is input to terminal CK, and the signal output from terminal Q is input to terminal D. An output signal is being output from

[0072] For a specific configuration of the circuit 100 shown in FIG. 7A, refer to FIG. 5B. The specific circuit configuration of a flip-flop is to use the feedback effect to store one bit of data. Any circuit configuration may be used as long as it can hold the above. The circuit 10 shown in FIG. 7A is configured to obtain output signals 1 and 2. At 0, there is one output signal.

[0073] The supply of power supply voltage to the circuit 100 is controlled by a switching element 101. In FIG. 7(A), the supply of a low-level power supply voltage VSS is controlled by a switching element 101. The example shows a case where the supply of high-level power supply voltage is controlled by a switching element. It may be controlled by 101.

[0074] FIG. 7A shows an example in which the control circuit 102 uses AND. 2 is a circuit configuration capable of controlling the supply of a clock signal to the circuit 100 according to the control signal 1. For example, the control circuit 102 may be configured to use a NO instead of an AND. You may also use R.

[0075] The control circuit 102 includes at least one transistor having an oxide semiconductor film as an active layer. A transistor having an oxide semiconductor film as an active layer has a leakage current However, the oxidization rate is significantly lower than that of a transistor using crystalline silicon. A transistor having a semiconductor material is used as the control circuit 102. By controlling the supply of a clock signal to the circuit 100, the leakage current of the control circuit 102 is reduced. This makes it possible to suppress an increase in standby power consumption.

[0076] Taking the semiconductor device in FIG. 7A as an example, a period in which the circuit 100 is in an operating state (operating period) and a period in which the circuit 100 is in a stopped state (operating period) are shown. Input signal data, output signal data, and control signals during the stop state (non-operating period) A timing chart of the potential of control signal 1 and the potential of control signal 2 is shown in FIG.

[0077] During the operation period, the potential of the control signal 1 is at a high level, and the clock signal 2 to the flip-flop circuit 100. The potential of the control signal 2 is at a high level, and the power supply voltage VSS is supplied to the circuit 100. Therefore, the circuit 100 The flip-flop circuit 100 is in an operating state in response to the input clock signal. During the operation period, the data in the input signal changes from D0 to D1. , the data held by the output signal also changes from D0 to D1.

[0078] Next, during the non-operating period, the potential of the control signal 1 is at a low level, and the circuit of the clock signal That is, the supply to the flip-flop circuit 100 is stopped from the control circuit 102. A potential fixed at a low level is supplied to the circuit 100. The potential of the control signal 2 is at a low level, and the supply of the power supply voltage VSS to the circuit 100 is stopped. Therefore, the circuit 100 is in an inactive state, and the data of the output signal is maintained at D1. The state in which the supply of the clock signal is stopped means that the control circuit 102 The potential applied to the circuit 100 does not change between a low level and a high level. , means a state in which the signal is fixed at a low level or a high level.

[0079] As described above, during non-operational periods, the supply of clock signals to the circuit 100 is stopped. By performing so-called clock gating, the dynamic standby power consumed by the circuit 100 is In addition, by stopping the supply of the power supply voltage to the circuit 100, It is possible to reduce the dynamic standby power consumed by the circuit 100. The transistor 101 and the control circuit 102 are made of a semiconductor element using an oxide semiconductor film. Therefore, the static standby power consumption depending on the leakage current and the like can be reduced. This stops the supply of clock signals and power supply voltage to the A semiconductor device capable of reducing the power consumption of the entire circuit by reducing both the standby power and the dynamic standby power. Locations can be provided.

[0080] Even if the control circuit 102 uses a NOR instead of an AND, the clock signal The signal and the control signal are both input to the NOR. The signal output from the NOR is 17A shows a control circuit in the semiconductor device shown in FIG. The circuit 100 and the switching element 101 are connected in series. The configuration is the same as that of FIG. 7(A), so a detailed description will be omitted. Taking a semiconductor device as an example, a period during which the circuit 100 is in an operating state (operating period) and a period during which the circuit 100 is in a stopped state are shown. During the non-operating period, the data of the input signal, the data of the output signal, the potential of the control signal 1, A timing chart of the potential of the control signal 2 is shown in FIG.

[0081] When a NOR is used for the control circuit 102, the potential of the control signal 1 is low during the operation period. A clock signal is input to a flip-flop circuit 100 through a control circuit 102. The potential of the control signal 2 is at a high level, and the power supply voltage VSS is supplied to the circuit 10. 0. This puts the circuit 100 into an operational state. The circuit 100 holds data based on the input clock signal. Since the data of the input signal changes from D0 to D1, the data of the output signal also changes from D0 to D1.

[0082] Next, during the non-operating period, the potential of the control signal 1 is at a high level, and the circuit of the clock signal That is, the supply to the flip-flop circuit 100 is stopped from the control circuit 102. A potential fixed at a low level is supplied to the circuit 100. The potential of the control signal 2 is at a low level, and the supply of the power supply voltage VSS to the circuit 100 is stopped. Therefore, the circuit 100 is in an inactive state, and the data of the output signal is maintained at D1. do.

[0083] (Embodiment 2) In this embodiment, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described.

[0084] A semiconductor device according to one embodiment of the present invention includes a transistor including silicon and a transistor including an oxide semiconductor. The silicon-based transistor is made of a silicon wafer, OI (Silicon on Insulator) substrate, silicon thin film on insulating surface, etc. It can be formed using the above.

[0085] SOI substrates include, for example, UNIBOND, ELTRAN (E pitaxial layer transfer, dielectric isolation method, PACE (Pla sma Assisted Chemical Etching) method and SIMOX (S The method includes the isolation by implanted oxygen method. It is possible.

[0086] A semiconductor film of silicon formed on a substrate having an insulating surface is crystallized by known techniques. Known crystallization methods include a laser crystallization method using a laser beam and a crystallization method using a catalytic element. Alternatively, a crystallization method using a catalyst element and a laser crystallization method may be combined. In addition, when a substrate with excellent heat resistance such as quartz is used, Thermal crystallization using a thermal furnace, lamp annealing crystallization using infrared light, and catalytic element crystallization A crystallization method in which a high-temperature annealing method at about 950° C. is combined with the crystallization method using a quartz crystallization process may be used.

[0087] In addition, the semiconductor element manufactured by the above method can be mounted on a flexible substrate such as plastic. The semiconductor device may be formed by transferring the semiconductor element to a plate. A method of providing an oxide film and weakening the metal oxide film by crystallization to peel off and transfer the semiconductor element; An amorphous silicon film containing hydrogen is provided between the substrate and the semiconductor element, and the film is irradiated with laser light or etched. A method of removing the amorphous silicon film by etching to separate the substrate from the semiconductor element, The substrate on which the semiconductor element is formed is mechanically removed or removed by etching with a solution or gas. Various methods can be used, such as a method of separating and transferring a semiconductor element from a substrate by using a bonding method.

[0088] In this embodiment, a SOI (Silicon on Insulator) substrate is used. After a transistor including silicon is manufactured, a transistor including an oxide semiconductor is manufactured. A method for manufacturing a semiconductor device will be described taking the case of manufacturing a semiconductor device as an example.

[0089] First, as shown in FIG. 8A, the bond substrate 200 is cleaned, and then the surface of the bond substrate 200 is An insulating film 201 is formed on the surface.

[0090] A silicon single crystal semiconductor substrate can be used as the bond substrate 200. The bond substrate 200 is made of silicon having a strained crystal lattice, germanium with respect to silicon, and A semiconductor substrate such as silicon germanium doped with Zn may also be used.

[0091] Note that the direction of the crystal axis of the single crystal semiconductor substrate used for the bond substrate 200 is It is desirable for the lattice to be uniform, but it is also necessary to completely eliminate lattice defects such as point defects, line defects, and planar defects. It is not necessary for the crystal to be a perfect crystal.

[0092] The shape of the bond substrate 200 is not limited to a circular shape, and may be processed into a shape other than a circular shape. For example, the shape of the base substrate 203 to be attached later is generally rectangular, and Considering that the exposure area of ​​an exposure device such as a small projection exposure device is rectangular, The shape of the bond substrate 200 may be processed so that the bond substrate 200 is rectangular. This can be achieved by cutting a commercially available circular single crystal semiconductor substrate.

[0093] The insulating film 201 may be a single insulating film or a laminate of multiple insulating films. The thickness of the insulating film 201 is determined by the thickness of the insulating film 201, so that the region containing impurities will be removed later. Taking this into consideration, it is preferable to set the thickness to 15 nm or more and 500 nm or less.

[0094] The insulating film 201 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Bare film, germanium oxide film, germanium nitride film, germanium oxide nitride film, germanium nitride oxide film An insulating film containing silicon or germanium in its composition, such as a germanium film, can be used. In addition, insulating materials made of metal oxides such as aluminum oxide, tantalum oxide, and hafnium oxide are also used. films, insulating films made of metal nitrides such as aluminum nitride, aluminum oxide nitride films, etc. Insulating film made of metal oxide nitride, such as aluminum oxide nitride film An insulating film may also be used.

[0095] For example, in this embodiment, the bond substrate 200 is thermally oxidized to form a silicon oxide film. In FIG. 8A, the insulating film 201 is made of a BOF. The insulating film 201 is formed so as to cover the entire surface of the bond substrate 200. It is sufficient that the insulating layer is formed on at least one surface of the insulating layer.

[0096] In this specification, an oxynitride is a material having a composition in which oxygen is more abundant than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It refers to a substance.

[0097] In addition, when the insulating film 201 is formed by thermally oxidizing the surface of the bond substrate 200, Oxidation is carried out in two ways: dry oxidation using oxygen with a low moisture content, or oxidation using halides such as hydrogen chloride in an oxygen atmosphere. Thermal oxidation, which involves adding a gas containing hydrogen, can also be used. Pyrogenic oxidation is a process that produces water by heating high-purity water to over 100 degrees. The insulating film 201 may be formed by wet oxidation such as steam oxidation, which performs oxidation using a water vapor atmosphere.

[0098] The base substrate 203 is provided with an alkali metal or an alkaline earth metal, etc., for improving the reliability of the semiconductor device. When a substrate containing impurities that reduce the surface area is used, the impurities are separated from the base substrate 203. At least one barrier film is formed to prevent diffusion of the metal oxide into the semiconductor film formed after the separation. It is preferable that the insulating film 201 has at least one layer. The film may be a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film. The insulating film used as the barrier film has a thickness of, for example, 15 nm to 300 nm. It is preferable that the barrier film is formed to a thickness of 100 μm. An insulating film having a lower nitrogen content than the barrier film, such as a silicon film or a silicon oxynitride film, may be formed. The thickness of the insulating film having a low nitrogen content may be set to 5 nm or more and 200 nm or less.

[0099] When silicon oxide is used as the insulating film 201, the insulating film 201 is made of silane and oxygen, TEOS (TeO2). Using a mixture of tetraethoxysilane and oxygen, thermal CVD, plasma CVD, and atmospheric CV D, it can be formed by a vapor phase growth method such as bias ECRCVD. The surface of the insulating film 201 may be densified by oxygen plasma treatment. When used as 1, a mixture of silane and ammonia gas is used for gas phase deposition such as plasma CVD. It can be formed by the long method.

[0100] In addition, silicon oxide formed by chemical vapor deposition using organic silane gas is used as the insulating film 20 As the organic silane gas, ethyl silicate (TEOS: chemical formula Si( OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), Tylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (O MCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. A fluorine-containing compound can be used.

[0101] By using organic silane as the source gas, a smooth surface can be obtained at a process temperature of 350°C or less. In addition, the thermal CVD method can form a silicon oxide film having a high thermal conductivity at a heating temperature of 200°C or higher. LTO (low temperature oxide) is formed at temperatures below 500°C. The formation of LTO can be achieved by adding monosilane to the silicon source gas. The oxygen source gas is nitrogen dioxide. (NO2) etc. can be used.

[0102] For example, the insulating film 201 made of a silicon oxide film is formed by using TEOS and O2 as source gas. In this case, the flow rate of TEOS is 15 sccm, the flow rate of O2 is 750 sccm, and the deposition pressure is 100 Pa. The deposition temperature is set to 300° C., the RF output is set to 300 W, and the power supply frequency is set to 13.56 MHz.

[0103] Note that a silicon oxide film formed using an organic silane or a silicon nitride oxide film formed at a low temperature Insulating films formed at relatively low temperatures, such as those described above, have many OH groups on their surfaces. OH groups are water molecules. By hydrogen bonding with the silanol group, the base substrate and the insulating film are bonded at low temperatures. Finally, a covalent siloxane bond is formed between the base substrate and the insulating film. Therefore, the silicon oxide film formed using the above organic silane or the relatively low temperature The insulating film formed by LTO and other methods has OH groups, which are used in Smart Cut and other methods. It can be said that this is more suitable for bonding at low temperatures than a thermal oxide film that does not exist or is extremely small.

[0104] The insulating film 201 is a film for forming a smooth and hydrophilic bonding surface on the surface of the bond substrate 200. Therefore, the average roughness Ra of the insulating film 201 is 0.7 nm or less, and more preferably, 0. The thickness of the insulating film 201 is preferably 5 nm or more and 500 nm or less. More preferably, the thickness is set to be 10 nm or more and 200 nm or less.

[0105] Next, as shown in FIG. 8B, ions accelerated by an electric field are applied to the bond substrate 200. The ion beam is irradiated onto the bond substrate 200 through the insulating film 201 as shown by the arrow. An embrittlement layer 202 having microvoids is formed in a region at a certain depth from the surface of the substrate 200. For example, the embrittlement layer means a layer that is locally weakened by disturbing the crystal structure. The state of the embrittlement layer varies depending on the means for forming the embrittlement layer. The area may also be weakened to some extent, but the weakened layer is the area that will be separated later and the adjacent layers. Refers to...

[0106] The depth of the region where the embrittlement layer 202 is formed depends on the acceleration energy of the ion beam and the The acceleration energy can be adjusted by adjusting the acceleration voltage. An embrittlement layer 202 is formed in a region having a depth approximately equal to the average penetration depth of the ions. The depth at which the bonding takes place determines the thickness of the semiconductor film 204 that will be subsequently separated from the bond substrate 200 . The depth at which the embrittlement layer 202 is formed may be, for example, 50 nm or more and 500 nm or less. A preferable range of the depth is 50 nm or more and 200 nm or less.

[0107] Ions are implanted into the bond substrate 200 by an ion doping method that does not involve mass separation. In order to shorten the tact time, it is desirable to use a mass separation method. An injection method may also be used.

[0108] When hydrogen (H2) is used as the source gas, the hydrogen gas is excited to produce H + , H2 + , H3 + I live The ratio of ion species generated from the source gas depends on the plasma excitation method. By adjusting the pressure of the atmosphere in which the plasma is generated and the supply amount of the source gas, the When ion implantation is performed by the ion doping method, the ion beam is + , H2 + , H3 + H3 + Contains 50% or more, more preferably 80% or more. It is preferable that H3 + By making the ratio of ions to 80% or more, H2 + The proportion of ions is relatively small, so the hydrogen ions contained in the ion beam The variation in the average penetration depth of the ions is reduced, improving the efficiency of ion implantation and shortening the tact time. can be shortened.

[0109] Also, H3 + H + , H2 + Therefore, in an ion beam, H3 + When the ratio of H is high, + , H2 + The doping rate is higher in the case of Even if the ion implantation voltage is the same, the former case implants hydrogen into a shallow region of the bond substrate 200. In the former case, the hydrogen implanted in the bond substrate 200 is Since the concentration distribution in the embrittlement layer 202 becomes steep, the thickness of the embrittlement layer 202 itself can be made thin.

[0110] When ion implantation is performed using hydrogen gas by ion doping, the acceleration voltage is 10 kV or more. 200kV or less, dose 1×10 16 ions / cm 2 More than 6×10 16 ions / c m 2 By setting the following, the ion species and their ratio contained in the ion beam, the insulating film 201 Although it depends on the film thickness, the embrittlement layer 202 is formed at a depth of 50 nm to 500 nm in the bond substrate 200. It can be formed in an area.

[0111] For example, the bond substrate 200 is a single crystal silicon substrate, and the insulating film 201 is 100 nm thick. When the thermal oxide film is formed, the flow rate of the source gas, 100% hydrogen gas, is 50 sc cm, beam current density 5μA / cm 2 , acceleration voltage 50 kV, dose 2.0 × 10 16 a toms / cm 2 Under these conditions, a semiconductor film with a thickness of about 146 nm was separated from the bond substrate 200. In addition, the conditions for adding hydrogen to the bond substrate 200 are the same. In addition, by making the insulating film 201 thicker, the thickness of the semiconductor film can be made thinner. can be done.

[0112] Helium (He) can also be used as the source gas for the ion beam. The ion species produced is He + Therefore, ion doping without mass separation is not possible. In the He method, + can be implanted into the bond substrate 200 as the main ions. Therefore, minute voids can be efficiently formed in the embrittlement layer 202 by ion doping. When ion doping is performed using helium, the acceleration voltage is 10 kV. More than 200kV, dose 1×10 16 ions / cm 2 More than 6×10 16 ions / cm 2 It can be as follows:

[0113] Uses halogen gases such as chlorine gas (Cl2 gas) and fluorine gas (F2 gas) as the source gas. You can also be there.

[0114] When ions are implanted into the bond substrate 200 by an ion doping method, the ion doping Since impurities present in the processing device are injected into the object to be processed together with ions, the surface of the insulating film 201 is Impurities such as S, Ca, Fe, and Mo may be present near the surface of the insulating film 20. The area near the surface of 1 that is considered to have the most impurities is removed by etching or polishing. Specifically, the insulating film 201 may be removed from the surface of the insulating film 201 by 10 nm to 100 nm. It is desirable to remove the area to a depth of about 30 to 70 nm. and reactive ion etching (RIE) method. , ICP (Inductively Coupled Plasma) Etching Method, E CR (Electron Cyclotron Resonance) etching method, flat Linear plate type (capacitive coupling type) etching method, magnetron plasma etching method, dual frequency plasma Zuma etching or helicon wave plasma etching can be used. For example, when removing the surface of a silicon oxynitride film by ICP etching, the etching gas The flow rate of CHF3 was 7.5 sccm, the flow rate of He was 100 sccm, and the reaction pressure was 5.5 Pa, temperature of the lower electrode 70°C, RF (13.56MHz) power input to the coil-type electrode 475W, power input to lower electrode (bias side) 300W, etching time 10sec By setting the thickness to about 50 nm, it is possible to remove a region from the surface to a depth of about 50 nm.

[0115] In addition to the fluorine-based gas CHF3, other etching gases include Cl2, BCl3, and SiC Chlorine gases such as l4, CCl4, fluorine gases such as CF4, SF6, NF3, and O2 It can be used appropriately. In addition, an inert gas other than He can be added to the etching gas used. For example, the inert element to be added is one selected from Ne, Ar, Kr, and Xe. Alternatively, a plurality of kinds of elements can be used. When removing by etching, use hydrofluoric acid containing ammonium hydrogen fluoride or ammonium fluoride. The solution of this type can be used as an etchant. The polishing is performed by chemical mechanical polishing (CMP). : Chemical Mechanical Polishing or Liquid Jet This can be done by polishing or the like.

[0116] After the formation of the embrittlement layer 202, the highly contaminated area near the surface of the insulating film 201 is etched. The semiconductor film 2 formed on the base substrate 203 is removed by etching or polishing. In addition, the amount of impurities mixed into the semiconductor device 04 can be reduced. In the case of MOS transistors, the influence of impurities can cause transistor defects such as threshold voltage fluctuation and increased leakage current. This can prevent the occurrence of deterioration in electrical characteristics and deterioration in reliability.

[0117] Next, as shown in FIG. 8(C), the bond substrate 200 and the base substrate 210 are bonded together with the insulating film 201 sandwiched therebetween. The base substrate 203 is attached to the substrate.

[0118] Before bonding the base substrate 203 and the bond substrate 200 together, In this embodiment, the insulating film 201 formed on the bond substrate 200 and the base are On the surface of the base substrate 203, in order to improve the bonding strength between the insulating film 201 and the base substrate 203, It is preferable to subject the plate to a surface treatment such as the following.

[0119] Surface treatment can be wet treatment, dry treatment, or a combination of wet and dry treatment. Combinations of different wet processes or different dry processes As the wet treatment, ozone treatment using ozone water (ozone water cleaning), Ultrasonic cleaning such as megasonic cleaning or two-fluid cleaning (using functional water such as pure water or hydrogen-added water) (Method of spraying with carrier gas such as nitrogen), cleaning with hydrochloric acid and hydrogen peroxide, etc. Dry processing includes inert gas neutral atom beam processing, inert gas ion beam processing, etc. Beam treatment, UV treatment, ozone treatment, plasma treatment, biased plasma treatment, By performing the above-mentioned surface treatment, the following problems can be solved. This increases the hydrophilicity and cleanliness of the surface to be bonded, thereby improving the bonding strength.

[0120] The bonding is performed by closely adhering the base substrate 203 to the insulating film 201 on the bond substrate 200. Thereafter, a pressure of 1 N / cm was applied to a part of the overlapped base substrate 203 and bond substrate 200. 2 Over 50 0N / cm 2 Less than 11N / cm, preferably 11N / cm 2 More than 20N / cm 2 Apply pressure of the following magnitude: When pressure is applied, the base substrate 203 and the insulating film 201 start to bond from that portion, Eventually the bond will extend over the entire contact surface.

[0121] The bonding is achieved using van der Waals forces and hydrogen bonds, resulting in a strong bond even at room temperature. Since the above bonding can be performed at a low temperature, the base substrate 203 is Various materials can be used. For example, the base substrate 203 is an aluminosilicate. Cate glass, barium borosilicate glass, aluminoborosilicate glass, etc. for electronics industry In addition to the various glass substrates used in the Furthermore, the base substrate 203 may be made of silicon, gallium arsenide, indium, or the like. A semiconductor substrate such as a silicon phosphide substrate can be used. Alternatively, a stainless steel substrate can be used. A metal substrate may be used as the base substrate 203. The glass substrate has a thermal expansion coefficient of 25×10 -7 / ℃ or more 50×10 -7 / ℃ or less (preferably is 30 x 10 -7 / ℃ or more 40×10 -7 / ℃ or less), and the strain point is 580℃ or more6 It is preferable to use a substrate having a temperature of 80° C. or less (preferably, 600° C. or more and 680° C. or less). In addition, if a non-alkali glass substrate is used as the glass substrate, the semiconductor device can be prevented from being damaged by impurities. This can reduce pollution.

[0122] The glass substrate used can be a mother glass substrate developed for the manufacture of liquid crystal panels. As for mother glass, for example, 3rd generation (550mm x 650mm), ...4th generation (550mm x 650mm), 5th generation (550mm x 650mm), 6th generation (550mm x 650mm), 7th generation (550mm x 650mm), 8th generation (550mm x 650mm), 9th generation (55 5th generation (600mm x 720mm), 4th generation (680mm x 880mm or 730 mm×920mm), 5th generation (1100mm×1300mm), 6th generation (1500mm m×1850mm), 7th generation (1870mm×2200mm), 8th generation (2200m Substrates with sizes of up to 2000 x 2400 mm are known. By using it as a base substrate 203 to manufacture an SOI substrate, it is possible to increase the area of ​​the SOI substrate. If the area of ​​SOI substrates can be increased, it will be possible to manufacture many IC and LSI chips at once. This allows more chips to be manufactured from a single substrate, dramatically increasing productivity. can be improved to.

[0123] EAGLE2000 (Corning) and other similar products can be heated to produce a large shimmer. When a glass substrate that links the substrate is used as the base substrate 203, the substrate is bonded after the bonding process. Therefore, it is necessary to avoid poor lamination caused by shrinkage. In order to achieve this, the base substrate 203 may be subjected to heat treatment in advance before bonding.

[0124] In addition, an insulating film may be formed on the base substrate 203. Although an insulating film is not necessarily formed on the surface, it is preferable to form an insulating film on the surface of the base substrate 203. By forming the above, alkali metal or aluminum can be easily transferred from the base substrate 203 to the bond substrate 200. It is possible to prevent impurities such as potassium earth metals from entering. In the case where an insulating film is formed on the surface, the insulating film on the base substrate 203 is bonded to the insulating film 201. Therefore, the types of substrates that can be used as the base substrate 203 are further expanded. Generally, substrates made of flexible synthetic resins such as plastic tend to have low heat resistance. If the substrate 203 can withstand the processing temperature in the subsequent semiconductor device manufacturing process, When an insulating film is formed on the substrate, the substrate can be used as the base substrate 203. As a plastic substrate, polyester, such as polyethylene terephthalate (PET), is used. Polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate Polycarbonate (PC), Polyetheretherketone (PEEK), Polysulfone (PSF) , polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate Polybutadiene (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride Examples of the material include polyvinyl acetate, polypropylene, and acrylic resin. When forming an insulating film on the insulating film 3, the surface of the insulating film is subjected to a surface treatment in the same manner as the insulating film 201. Then, it is recommended to paste them together.

[0125] After the bond substrate 200 is attached to the base substrate 203, the base substrate 203 and the insulating film 20 It is preferable to carry out a heat treatment to increase the bonding strength at the bonding interface with 1. The temperature is set to a temperature at which no cracks are generated in the embrittlement layer 202, and is set to a temperature of 200° C. or more and 400° C. or less. In addition, the base substrate 203 can be heated in this temperature range. By attaching the bond substrate 200, the insulating film 201 is formed between the base substrate 203. The bonding strength of the joint can be strengthened.

[0126] When the bond substrate 200 and the base substrate 203 are attached to each other, dust or the like may be present on the bonding surface. If the joint surface is contaminated by, the contaminated part will not be bonded. The bonding of the bond substrate 200 and the base substrate 203 is preferably performed in an airtight processing chamber. In addition, when the bond substrate 200 and the base substrate 203 are bonded to each other, the processing chamber is 5.0×10 -3 The atmosphere for the bonding process can be made clean by reducing the pressure to about 100 Pa. good.

[0127] Next, by performing a heat treatment, adjacent microvoids in the embrittlement layer 202 are bonded to each other. As a result, the volume of the microvoids increases. As a result, as shown in FIG. In this step, the semiconductor film 204, which is a part of the bond substrate 200, is separated from the bond substrate 200. Since the insulating film 201 is bonded to the base substrate 203, the bond is not formed on the base substrate 203. The semiconductor film 204 separated from the bond substrate 200 is fixed. The temperature of the heat treatment for separating the substrate from the base substrate 200 is set to a temperature that does not exceed the distortion point of the base substrate 203. Let us assume that.

[0128] This heat treatment is carried out using an RTA (Rapid Thermal Anneal) device, a resistance heating device, A thermal oven or a microwave heating device can be used. Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid When using a GRTA device, The heating temperature should be between 550 and 650°C, and the treatment time should be between 0.5 and 60 minutes. When using a resistance heating device, the heating temperature should be between 200°C and 650°C, and the treatment time should be 2 The period may be more than one hour and less than four hours.

[0129] The heat treatment may be performed by dielectric heating using high frequency waves such as microwaves. Heat treatment by dielectric heating is performed using a high-frequency generator with a frequency of 300 MHz or This can be achieved by irradiating the bond substrate 200 with a high frequency of 3 THz. For example, by irradiating 2.45 GHz microwaves at 900 W for 14 minutes, Adjacent microvoids are bonded together, and the bond substrate 200 is finally broken at the embrittlement layer. It can be done.

[0130] A specific method of heat treatment using a vertical furnace with resistance heating will be described. The base substrate 203 with the 00 attached thereto is placed in a boat of a vertical furnace. In order to suppress oxidation of the bond substrate 200, the inside of the chamber is first Evacuate the chamber to create a vacuum. The vacuum level is 5×10 -3 After creating a vacuum, Nitrogen is supplied into the chamber to create a nitrogen atmosphere at atmospheric pressure. Increase heat temperature to 200°C.

[0131] After the inside of the chamber is filled with nitrogen at atmospheric pressure, it is heated at a temperature of 200°C for 2 hours. Increase the temperature to 400℃ over 1 hour. Once the heating temperature of 400℃ has stabilized, leave it for 1 hour. Once the heating temperature of 600°C is stable, heat it for 2 minutes at 600°C. After that, the heating temperature is lowered to 400℃ over 1 hour, and then heated for 10 to 30 minutes. After a while, the boat is removed from the chamber. The bond substrate 200 and the base substrate 203 to which the semiconductor film 204 is attached are cooled.

[0132] The heat treatment using the resistance heating furnace strengthens the bonding strength between the insulating film 201 and the base substrate 203. A heat treatment for decomposing the embrittlement layer 202 and a heat treatment for splitting the embrittlement layer 202 are performed in succession. When the two heat treatments are performed in different equipment, for example, a resistance heating furnace is used. After performing a heat treatment at 0° C. for 2 hours, the bonded base substrate 203 and the bond The substrate 200 is removed from the furnace. Then, the substrate 200 is heated in an RTA apparatus at a processing temperature of 600° C. or more and 700° C. or less. Then, a heat treatment is performed for a treatment time of about 1 minute to several hours to form the bond substrate 200 into the embrittlement layer 20 Divide it into 2.

[0133] Note that the periphery of the bond substrate 200 may not be bonded to the base substrate 203. This is because the periphery of the bond substrate 200 is chamfered or has a curvature. Therefore, the base substrate 203 and the insulating film 201 are not in close contact with each other, or the periphery of the bond substrate 200 is This is believed to be because the embrittlement layer 202 is difficult to split at the side. The reason for this is that polishing such as CMP performed when producing the bond substrate 200 may damage the bond substrate. The peripheral portion of the plate 200 is insufficient, and the surface of the peripheral portion is rougher than that of the central portion. In addition, when the bond substrate 200 is transported, the periphery of the bond substrate 200 is moved by a carrier or the like. If the edge portion is scratched, the scratch also makes it difficult for the peripheral portion to be bonded to the base substrate 203. Therefore, the base substrate 203 is required to have a size larger than that of the bond substrate 200. A small semiconductor film 204 is attached.

[0134] Note that, before the bond substrate 200 is separated, hydrogenation treatment is performed on the bond substrate 200. The hydrogenation process is carried out, for example, in a hydrogen atmosphere at 350° C. for about 2 hours.

[0135] In addition, when the base substrate 203 and the multiple bond substrates 200 are bonded to each other, The semiconductor substrate 200 may have different crystal plane orientations. Mobility varies depending on the crystal plane orientation. Therefore, it is necessary to select a crystal plane orientation suitable for the semiconductor device to be formed. The semiconductor film 204 may be formed by appropriately selecting a bond substrate 200 having the above structure. If an n-type semiconductor element is formed using the conductive film 204, a semiconductor having a {100} surface By forming the film 204, the mobility of majority carriers in the semiconductor element can be increased. For example, if a p-type semiconductor element is formed using the semiconductor film 204, By forming the semiconductor film 204 having a {10} surface, the majority carriers in the semiconductor element If a transistor is to be formed as a semiconductor element, For example, the bonding direction of the semiconductor film 204 is determined taking into consideration the channel direction and the crystal plane orientation. Make sure that.

[0136] Next, the surface of the semiconductor film 204 may be planarized by polishing. Planarization is not necessarily required. However, by performing the planarization, the semiconductor film 206 and the semiconductor film 207 to be formed later are formed in a gate electrode. The interface characteristics of the insulating film can be improved. CMP (Chemical Mechanical Polishing) or Liquid The thickness of the semiconductor film 204 can be reduced by the above-mentioned planarization. The above-mentioned planarization may be performed on the semiconductor film 204 before etching, but it is performed after The same may be applied to the semiconductor film 206 and the semiconductor film 207 formed by etching.

[0137] Alternatively, the surface of the semiconductor film 204 may be etched instead of polished. The surface can be flattened. Etching can be performed using reactive ion etching (RI E:Reactive Ion Etching) method, ICP(Inductively Coupled Plasma Etching, ECR (Electron Cyclo Electron Resonance (ESR) etching method, parallel plate (capacitive coupling) etching method, magnetron plasma etching method, dual frequency plasma etching method or helicon wave A dry etching method such as a plasma etching method may be used.

[0138] For example, when using the ICP etching method, the flow rate of the etching gas, chlorine, is 40 sccm. ~100sccm, power input to coil-type electrode 100W~200W, lower electrode (by The power input to the gas side should be 40W to 100W, and the reaction pressure should be 0.5Pa to 1.0Pa. For example, the flow rate of the etching gas, chlorine, is 100 sccm, the reaction pressure is 1.0 Pa, The temperature of the electrode was 70°C, and the RF (13.56MHz) power input to the coil-type electrode was 150W. The power input to the lower electrode (bias side) is 40 W, and the etching time is 25 to 27 seconds. By using the method described above, the semiconductor film 204 can be thinned to about 50 nm to 60 nm. Etching gases include chlorine, boron chloride, silicon chloride, carbon tetrachloride, and other chlorine-based gases. Fluorine-based gases such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, oxygen, etc. may be used appropriately. This can be done.

[0139] The above etching reduces the semiconductor film to a thickness optimal for the semiconductor element to be formed later. Not only can the semiconductor film 204 be thinned, but the surface of the semiconductor film 204 can be flattened.

[0140] Note that the semiconductor film 204 in close contact with the base substrate 203 is not subjected to the formation of the embrittlement layer 202 and the formation of the embrittlement layer 2 The separation at 02 may result in the formation of crystal defects or the loss of flatness of the surface. Therefore, in one embodiment of the present invention, a method for reducing crystal defects and improving flatness is provided. In order to achieve this, a process is performed to remove oxide films, such as a native oxide film, formed on the surface of the semiconductor film 204. After that, the semiconductor film 204 is irradiated with laser light.

[0141] In the embodiment of the present invention, the semiconductor film 204 is immersed in DHF having a hydrogen fluoride concentration of 0.5 wt % for 1 h. Exposing for 10 seconds removes the oxide film.

[0142] The laser light irradiation is performed with an energy density sufficient to partially melt the semiconductor film 204. If the semiconductor film 204 is completely melted, random nucleation occurs in the liquid phase. Therefore, when the semiconductor film 204 is recrystallized, microcrystals are generated, and the crystallinity is reduced. By partially melting the semiconductor film 204, crystal growth occurs from the unmelted solid phase portion. The vertical growth causes the semiconductor film 20 to grow. The crystal defects in the semiconductor film 204 are reduced and the crystallinity is restored. The semiconductor film 204 is melted up to the interface with the insulating film 201 and is in a liquid state. On the other hand, the semiconductor film 204 being in a partially melted state means that the upper layer is melted and in a liquid phase. This refers to a state in which the lower layer is a solid phase.

[0143] The laser light irradiation is performed by pulse oscillation in order to partially melt the semiconductor film 204. For example, in the case of pulse oscillation, the repetition rate is 1 MHz. z or less, and the pulse width is 10 ns to 500 ns. For example, the repetition frequency is 10 Hz. A XeCl excimer laser with a frequency of 300 Hz, pulse width of 25 ns, and wavelength of 308 nm was used. This can be done.

[0144] The laser light is the fundamental or second harmonic of a solid-state laser that is selectively absorbed by the semiconductor. Specifically, for example, a laser having a wavelength in the range of 250 nm to 700 nm is preferable. The energy of the laser light can be determined by the wavelength of the laser light, the amount of the laser light, and the amount of the laser light. The thickness of the semiconductor film 204 can be determined by taking into consideration the skin depth of the semiconductor film 204. The thickness of the membrane 204 is about 120 nm, and the wavelength of the laser light is 308 nm. When using a laser, the energy density of the laser light is set to 600 mJ / cm 2 ~700mJ / cm 2 It would be fine to say so.

[0145] Pulsed lasers include Ar lasers, Kr lasers, excimer lasers, and CO2 lasers. Laser, YAG laser, Y2O3 laser, YVO4 laser, YLF laser, YAlO3 laser The, glass laser, ruby ​​laser, alexandrite laser, Ti:sapphire laser , a copper vapor laser or a gold vapor laser can be used.

[0146] In this embodiment, when the thickness of the semiconductor film 204 is about 146 nm, the laser light irradiation is performed as follows. This can be done as follows. A XeCl excimer laser is used as the laser oscillator for the laser light. (Wavelength: 308 nm, pulse width: 20 ns, repetition frequency: 30 Hz) is used. The cross section of the laser beam is shaped into a line of 0.4 mm x 120 mm. The laser beam is irradiated to the semiconductor film 204 at a speed of 0.5 mm / sec. As a result, a semiconductor film 205 in which the crystal defects have been repaired is formed, as shown in FIG. 8(E).

[0147] The laser beam is irradiated in an inert atmosphere such as a rare gas or nitrogen atmosphere, or in a reduced pressure atmosphere. In order to irradiate the laser beam in the above atmosphere, an airtight chamber is required. The laser beam is irradiated in the chamber, and the atmosphere in the chamber is controlled. If you do not use an inert gas, spray nitrogen gas or other inert gas onto the surface to be irradiated with the laser light to remove the Laser light irradiation can be achieved in an active atmosphere. Inert atmosphere or reduced pressure atmosphere By irradiating the laser beam in the atmosphere, the generation of natural oxide film is reduced compared to the case of irradiation in the air. Therefore, the semiconductor film 205 formed after the laser light irradiation is prevented from cracking or becoming pin-shaped. The occurrence of etch stripes can be suppressed, and the flatness of the semiconductor film 205 can be improved. This can widen the usable energy range.

[0148] The optical system makes the energy distribution of the laser light uniform and makes the cross-sectional shape linear. This makes it possible to achieve high throughput and uniform irradiation of the laser light. By making the beam length of the laser light longer than one side of the base substrate 203, By this scanning, the entire semiconductor film 204 attached to the base substrate 203 is irradiated with the laser light. When the beam length of the laser light is shorter than one side of the base substrate 203, the laser light can be irradiated multiple times. By this scanning, the entire semiconductor film 204 attached to the base substrate 203 is irradiated with the laser light. The length should be such that it can be

[0149] Laser light is irradiated in an inert atmosphere such as a rare gas or nitrogen atmosphere, or in a reduced pressure atmosphere. To achieve this, a laser beam is irradiated in an airtight chamber and the atmosphere in the chamber is If a chamber is not used, the surface to be irradiated with the laser light should be inert gas such as nitrogen gas. By spraying an inert gas onto the target, it is possible to irradiate the target with laser light in an inert atmosphere. By irradiating the laser beam in an active atmosphere or a reduced pressure atmosphere, The generation of a natural oxide film is suppressed more than in the case of the above, and the semiconductor film 205 formed after the laser light irradiation is The occurrence of cracks or pitch stripes is suppressed, and the flatness of the semiconductor film 205 is improved. This makes it possible to widen the usable energy range of the laser light.

[0150] Before the laser beam irradiation, the surface of the semiconductor film 204 is flattened by dry etching. In this case, damage such as crystal defects may occur near the surface of the semiconductor film 204 due to dry etching. However, the damage caused by dry etching can be reduced by the irradiation of the laser light. It is also possible to repair scratches.

[0151] Next, after the laser irradiation, the surface of the semiconductor film 205 may be etched. When the surface of the semiconductor film 205 is etched after the irradiation with the laser light, the irradiation with the laser light is not necessarily performed. It is not necessary to etch the surface of the semiconductor film 204 before the laser irradiation. If the surface of the semiconductor film 204 is etched before the laser irradiation, the semiconductor film 204 is not necessarily etched after the laser irradiation. There is no need to etch the surface of the film 205. Alternatively, after the irradiation of the laser light, Before the irradiation, the surface of the semiconductor film 205 may be etched.

[0152] The above etching reduces the semiconductor film to a thickness optimal for the semiconductor element to be formed later. Not only can the semiconductor film 205 be thinned, but the surface of the semiconductor film 205 can be flattened.

[0153] After the laser light irradiation, the semiconductor film 205 is subjected to a heat treatment at a temperature of 500° C. to 650° C. This heat treatment is preferably performed to remove the semiconductor film 2 that was not restored by the laser light irradiation. This heat treatment can eliminate the defects in the semiconductor film 205 and relax the distortion of the semiconductor film 205. , RTA (Rapid Thermal Anneal) equipment, resistance heating furnace, microwave A heating device can be used. The RTA device is a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) For example, when a resistance heating furnace is used, the temperature is set at 600 Heat at 35°C for 4 hours.

[0154] Next, as shown in FIG. 9(A), the semiconductor film 205 is partially etched to form a semiconductor The semiconductor film 205 is then used to form island-shaped semiconductor films 206 and 207. Further etching is performed to remove the area where the bonding strength is insufficient at the end of the semiconductor film 205. In this embodiment, one semiconductor film 205 is etched. The semiconductor film 206 and the semiconductor film 207 are formed by etching. The number is not limited to this.

[0155] After the semiconductor film 205 is separated from the bond substrate 200, the surface of the bond substrate 200 is planarized. Then, the semiconductor film 205 can be separated again.

[0156] Specifically, the insulating film 201 remaining mainly at the end of the bond substrate 200 is removed by etching or the like. The insulating film 201 is formed of silicon oxide, silicon oxynitride, or silicon nitride oxide. In this case, wet etching using hydrofluoric acid can be used.

[0157] Next, a protrusion formed at the end of the bond substrate 200 by separation of the semiconductor film 205 and hydrogen are The remaining embrittled layer containing excess silicon is removed. It is preferable to use wet etching, and the etching solution is tetramethylammonium hydroxide. Tetramethylammonium hydroxide (abbreviation: TM AH) solution can be used.

[0158] Next, the surface of the bond substrate 200 is polished. The polishing can be performed by CMP. In order to smooth the surface of the substrate 200, it is desirable to polish it by about 1 μm to 10 μm. After polishing, abrasive particles remain on the surface of the bond substrate 200, so RCA using hydrofluoric acid, etc. Perform cleaning.

[0159] By reusing the bond substrate 200, the material cost of the semiconductor substrate can be reduced. .

[0160] The semiconductor film 206 and the semiconductor film 207 are doped with boron, aluminum, or the like in order to control the threshold voltage. A p-type impurity such as gallium or an n-type impurity such as phosphorus or arsenic may be added. The addition of impurities to control the threshold voltage is performed on the semiconductor film before patterning. Alternatively, the semiconductor film 206 and the semiconductor film 207 formed after patterning may be subjected to the etching. Also, impurities for controlling the threshold voltage may be added to the bond substrate. Alternatively, doping of impurities can be performed on the bond substrate to roughly adjust the threshold voltage. After that, in order to fine-tune the threshold voltage, the semiconductor film before patterning is The same is also applied to the semiconductor film 206 and the semiconductor film 207 formed by patterning. You can do that too.

[0161] Next, as shown in FIG. 9B, a gate insulating film is formed to cover the semiconductor film 206 and the semiconductor film 207. The gate insulating film 208 is formed by performing a high density plasma treatment. It can be formed by oxidizing or nitriding the surfaces of the conductive film 206 and the semiconductor film 207. High-density plasma treatment is a process in which rare gases such as He, Ar, Kr, and Xe are mixed with oxygen and nitrogen oxide. The plasma is excited by a mixture of gases such as ammonia, nitrogen, and hydrogen. By introducing microwaves, it is possible to generate high density plasma with low electron temperature. Oxygen radicals (including OH radicals) generated in such high-density plasma The surface of the semiconductor film is oxidized by nitrogen radicals (which may contain NH radicals) and nitrogen radicals (which may contain NH radicals). By nitriding or oxidizing the insulating film, a thickness of 1 to 20 nm, preferably 5 to 10 nm, is formed. This 5 to 10 nm insulating film is used as the gate insulating film 208. For example, nitrous oxide (N2O) is diluted 1 to 3 times (flow ratio) with Ar, and the A microwave (2.45 GHz) power of 3 to 5 kW was applied at a pressure of 0 Pa to form the semiconductor film 2 The surfaces of the semiconductor film 206 and the semiconductor film 207 are oxidized or nitrided. An insulating film having a thickness of 2 nm (preferably 2 nm to 6 nm) is then formed. The reactor was heated to 10-30 Pa with 3-5 kW microwaves (2.4 5GHz) power is applied to form a silicon oxynitride film by vapor deposition to form a gate insulating film. By combining solid-state reactions and reactions by vapor phase growth, the interface state density is It is possible to form a gate insulating film having a low and excellent dielectric strength.

[0162] The oxidation or nitridation of the semiconductor film by the above-mentioned high-density plasma treatment proceeds as a solid-phase reaction. The interface state density between the gate insulating film 208 and the semiconductor film 206 and the semiconductor film 207 is extremely low. In addition, the semiconductor film 206 and the semiconductor film 207 can be formed by high-density plasma treatment. By directly oxidizing or nitriding the insulating film, the thickness variation of the insulating film can be suppressed. In addition, when the semiconductor film has crystallinity, the surface of the semiconductor film is etched by high-density plasma treatment. By oxidizing through a solid-state reaction, oxidation is prevented from progressing too quickly only at the grain boundaries. Therefore, it is possible to form a gate insulating film with good uniformity and low interface state density. The insulating film formed by the plasma treatment is included in part or the whole of the gate insulating film. Such a transistor can suppress variation in characteristics.

[0163] Alternatively, the semiconductor film 206 and the semiconductor film 207 are thermally oxidized to form a gate insulating film 208. Alternatively, the film may be formed by using a plasma CVD method or a sputtering method. , silicon oxide, silicon nitride oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide The gate insulating film 20 is formed by using a single layer or a laminate of a film containing tantalum oxide or tantalum oxide. 8 may be formed.

[0164] Next, as shown in FIG. 9C, a conductive film is formed on the gate insulating film 208, and then the conductive film The semiconductor film 206 and the semiconductor film 207 are processed (patterned) into a predetermined shape. An electrode 209 is formed on the opposite side. The conductive film is formed by using a CVD method, a sputtering method, or the like. The conductive film is made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), and Butan (Mo), Aluminum (Al), Copper (Cu), Chromium (Cr), Niobium (Nb) In addition, alloys containing the above metals as main components may be used. Alternatively, a compound containing an impurity element such as phosphorus that imparts electrical conductivity to the semiconductor film may be used. Alternatively, the insulating layer 12 may be formed using a semiconductor such as polycrystalline silicon doped with Zn.

[0165] The combination of two conductive layers is tantalum nitride or tantalum for the first layer and tantalum for the second layer. In addition to the above examples, tungsten nitride and tungsten, nitride can be used. Examples include molybdenum oxide and molybdenum oxide, aluminum and tantalum, and aluminum and titanium. Tungsten and tantalum nitride have high heat resistance, so after forming the two-layer conductive film, In the process, a heat treatment for the purpose of thermal activation can be performed. As a combination of, for example, silicon doped with an impurity that gives n-type and nickel Silicide, silicon doped with impurities to give n-type conductivity, tungsten silicide, etc. can also be used.

[0166] In this embodiment, the electrode 209 is formed of a single layer of conductive film. The electrode 209 is not limited to the above structure, but may be formed of a plurality of laminated conductive films. In the case of a three-layer structure in which three conductive films are laminated, a molybdenum film, an aluminum film, and a molybdenum film are laminated. It is advisable to employ a laminated film structure.

[0167] When the electrode 209 is formed, the electrode 209 is selectively formed by a droplet discharge method without using a mask. 09 may also be formed.

[0168] The droplet ejection method is a method of ejecting or spraying droplets containing a predetermined composition from a fine hole to produce a desired image. This refers to a method for forming a pattern, and the ink-jet method is included in the category.

[0169] The electrode 209 is formed by ICP (Inductively Coupled Plasma) after forming a conductive film. Plasma: Inductively coupled plasma etching method was used, and etching conditions (coil type the amount of power applied to the electrode layer on the substrate side, the amount of power applied to the electrode layer on the substrate side, the electrode temperature on the substrate side, etc. By appropriately adjusting the above, etching can be performed to obtain a desired tapered shape. The angle of the taper shape can also be controlled by changing the shape of the mask. The etching gas may be chlorine, boron chloride, silicon chloride, carbon tetrachloride, etc. Chlorine gas, fluorine gas such as carbon tetrafluoride, sulfur fluoride or nitrogen fluoride, or oxygen is used appropriately. It can be used as appropriate.

[0170] Next, as shown in FIG. 9(D), an impurity element that imparts one conductivity type is introduced using the electrode 209 as a mask. is added to the semiconductor film 206 and the semiconductor film 207. In this embodiment, n A type-imparting impurity element (such as phosphorus or arsenic) is added to impart p-type conductivity to the semiconductor film 207. An impurity element (for example, boron) is added. Note that the impurity element that gives the p-type is added to the semiconductor film 2 When doping the semiconductor film 206 with n-type impurities, the semiconductor film 206 is covered with a mask or the like, and the p-type The doping of impurity elements to be added is selective. When doping the semiconductor film 206 with p-type impurities, the semiconductor film 207 to which p-type impurities are to be doped is masked. Then, the doping of the n-type impurity element is selectively performed. An impurity that gives either p-type or n-type to the semiconductor film 206 and the semiconductor film 207 After adding the elements, the semiconductor film is selectively doped with p-type or n-type pores at a higher concentration. Alternatively, one of the impurity elements that provides the other of the two may be added. By the addition of the impurity, an impurity region 210 is formed in the semiconductor film 206, and an impurity region 211 is formed in the semiconductor film 207. is formed.

[0171] Next, as shown in FIG. 10(A), a sidewall 212 is formed on the side surface of the electrode 209. The sidewall 212 is formed, for example, by forming a new insulating film 208 and a new electrode 209. A new insulating film is formed, and the newly formed The insulating film can be partially etched to form the insulating film. By etching, the newly formed insulating film is partially etched, and a surface is formed on the side of the electrode 209. The side wall 212 is formed. Note that the gate insulating film 20 is also removed by the above-mentioned anisotropic etching. The insulating film for forming the sidewall 212 may be Silicon film, silicon oxide film, and oxide film are produced by LPCVD, plasma CVD, sputtering, etc. Silicon nitride film, silicon oxynitride film, and films containing organic materials such as organic resins are used as single layers or laminated layers. In this embodiment, a silicon oxide film having a thickness of 100 nm is formed by plasma annealing. It is formed by the CVD method. The etching gas is a mixture of CHF3 and helium. The process for forming the sidewall 212 is not limited to these. It is not something that is done.

[0172] Next, as shown in FIG. 10(B), using the electrode 209 and the sidewall 212 as a mask, An impurity element that imparts one conductivity type is added to the semiconductor film 206 and the semiconductor film 207. The semiconductor film 206 and the semiconductor film 207 are doped with the same impurity element as that doped in the previous step. The impurity element that gives the p-type conductivity is added at a higher concentration. When doping the film 207, the semiconductor film 206 to which the n-type impurity is to be doped is covered with a mask or the like. The doping of impurity elements that give n-type is selective. When an impurity element is added to the semiconductor film 206, the semiconductor film 207 to which the p-type impurity is added is a mass The semiconductor substrate is then covered with a material such as a quartz glass so that an impurity element that imparts n-type conductivity can be selectively added.

[0173] By adding the above impurity element, a pair of high concentration impurity regions 213 and a pair of high concentration impurity regions 214 are formed in the semiconductor film 206. A pair of low concentration impurity regions 214 and a channel forming region 215 are formed. By adding the pure element, a pair of high concentration impurity regions 216 and a pair of low concentration impurity regions 217 are formed in the semiconductor film 207. A high concentration impurity region 217 and a channel forming region 218 are formed. 13. The high concentration impurity region 216 functions as a source region or a drain region, and the low concentration impurity region The doped region 214 and the lightly doped region 217 are LDD (Lightly Doped Dra). The LDD region does not necessarily have to be provided, and it can be used as the source region. Alternatively, only the impurity region functioning as the drain region may be formed. The LDD region may be formed on only one side of the drain region.

[0174] A sidewall 212 formed on the semiconductor film 207 and a semiconductor film 206 formed on the semiconductor film 206 The sidewalls 212 are formed so that their widths in the direction in which the carriers move are uniform. The width of the semiconductor film 20 that becomes the p-type transistor may be different from that of the p-type transistor. The width of the sidewall 212 on the semiconductor film 206 which becomes the n-type transistor is It is preferable that the width of the wall 212 is longer than that of the source wall 212. The boron implanted to form the source and drain regions is highly diffusive and has a short channel In the p-type transistor, the width of the sidewall 212 is By making it longer, it is possible to dope the source and drain regions with a high concentration of boron. This makes it possible to reduce the resistance of the source region and the drain region.

[0175] Next, in order to further reduce the resistance of the source region and the drain region, a semiconductor film 206 and a semiconductor The silicide layer may be formed by silicidation of the semiconductor film 207. The semiconductor film is brought into contact with a metal, and then subjected to heat treatment, GRTA method, LRTA method, etc. to form a The silicide layer is formed by reacting silicon with a metal. Nickel silicide may be used. When the thickness of the semiconductor film 206 and the semiconductor film 207 are thin, Even if the silicide reaction is allowed to proceed to the bottom of the semiconductor film 206 and the semiconductor film 207 in this region, The metal materials used for silicidation are titanium (Ti), nickel (Ni), and tantalum (Tb). W, Molybdenum (Mo), Cobalt (Co), Zirconium (Zr), H f (Hafnium), Tantalum (Ta), Vanadium (V), Neodymium (Nd), Chromium ( Cr), platinum (Pt), palladium (Pd), etc. can be used. Laser irradiation Alternatively, silicide may be formed by irradiation with light from a lamp or the like.

[0176] Through the above-mentioned series of steps, an n-channel transistor 220 and a p-channel transistor A star 221 is formed.

[0177] After the process shown in FIG. 10B is completed, the transistor 220 and the transistor 2 A transistor using an oxide semiconductor is formed on the substrate 21.

[0178] First, as shown in FIG. 11(A), a transistor 220 and a transistor 221 are covered with By providing the insulating film 230, the electrode 209 is prevented from being damaged during heat treatment. The surface can be prevented from being oxidized. Specifically, the insulating film 230 is made of silicon nitride, nitride, or the like. Silicon oxide, silicon oxynitride, aluminum nitride, aluminum oxide, silicon oxide, etc. are used. In this embodiment, a silicon oxynitride film having a thickness of about 50 nm is used as the insulating film 230. Used as.

[0179] Next, as shown in FIG. 11(B), a Then, insulating films 231 and 232 are formed on the insulating film 230. The insulating layer 32 is made of a material that can withstand the heat treatment temperature in the subsequent manufacturing process. The film 231 and the insulating film 232 are made of, for example, silicon oxide, silicon nitride, silicon nitride oxide, or silicon oxynitride. For example, an inorganic insulating film such as aluminum nitride or aluminum nitride oxide can be used.

[0180] In this embodiment, the insulating film 231 and the insulating film 232 are laminated on the insulating film 230. However, the insulating film formed on the insulating film 230 may be a single-layer insulating film, or may be a three-layer insulating film or more. The films may be laminated.

[0181] The surface of the insulating film 232 may be planarized by a CMP method or the like.

[0182] Next, as shown in FIG. 11C, a conductive film is formed on the insulating film 232, and then etching is performed. By removing unnecessary portions by this method, wiring 233 and gate electrode 234 are formed. The etching is performed so that at least the end of the gate electrode 234 has a tapered shape.

[0183] The material of the conductive film is selected from molybdenum, titanium, chromium, tantalum, tungsten, and neodymium. Metallic materials such as zinc and scandium, alloy materials mainly composed of these metallic materials, or The nitrides of the metals can be used in a single layer or a multilayer structure. If the metal material can withstand the heat treatment temperature, aluminum and copper may be used. It is also possible.

[0184] For example, a conductive film having a two-layer structure in which molybdenum is laminated on aluminum is A two-layer structure with molybdenum on copper, or a two-layer structure with titanium nitride on copper. Two-layer structure with titanium or tantalum nitride laminated, two-layer structure with titanium nitride and molybdenum laminated It is preferable to have a layered structure. For a three-layer laminated structure, aluminum, aluminum and Silicon alloy, aluminum and titanium alloy, or aluminum and neodymium alloy The interlayer is made of tungsten, tungsten nitride, titanium nitride or titanium. A layered structure is preferred.

[0185] In addition, the aperture ratio can be improved by using a light-transmitting oxide conductive film for some electrodes and wirings. For example, the oxide conductive film may be made of indium oxide, an alloy of indium oxide and tin oxide, or an oxide. Indium oxide zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride , zinc gallium oxide, or the like can be used.

[0186] The thickness of the wiring 233 and the gate electrode 234 is 10 nm to 400 nm, preferably 100 nm. In this embodiment, a sputtering method using a tungsten target is used. After forming a conductive film for the gate electrode having a thickness of 100 nm, the conductive film is etched to a desired thickness. By processing (patterning) into a desired shape, wiring 233 and gate electrode 234 are formed. do.

[0187] Next, as shown in FIG. 11(D), a gate insulating film is formed on the wiring 233 and the gate electrode 234. The gate insulating film 240 is formed by plasma CVD or sputtering. Using silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, hafnium oxide, The aluminum oxide or tantalum oxide can be formed as a single layer or a multilayer. It is desirable that the gate insulating film 240 contains as little impurities as possible, such as moisture, hydrogen, and oxygen. Insulating films made of materials with high barrier properties, silicon oxide films with a low nitrogen ratio, and oxynitride films A gate insulating film 240 having a structure in which an insulating film such as a silicon film is laminated may be formed. In this case, the insulating film such as a silicon oxide film or a silicon oxynitride film has a barrier property and an oxidizing property. The insulating film with high barrier properties is formed between the semiconductor film and the silicon nitride film. Examples of the barrier film include a silicon film, an aluminum nitride film, and an aluminum oxide nitride film. By using an insulating film with this property, moisture, impurities in the atmosphere such as hydrogen, or the substrate Impurities such as alkali metals and heavy metals contained in the oxide semiconductor film and the gate insulating film 2 40 or the interface between the oxide semiconductor film and another insulating film and its vicinity. In addition, a silicon oxide film or an oxynitride film having a low ratio of nitrogen in contact with the oxide semiconductor film can be used. By forming an insulating film such as a silicon film, the insulating film made of a material with high barrier properties can be directly oxidized. This can prevent contact with the semiconductor film.

[0188] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. The gate insulating film 24 has a structure in which a silicon oxide film having a thickness of 100 nm formed by the above method is laminated. Form 0.

[0189] Next, an oxide semiconductor film is formed on the gate insulating film 240, and then the desired structure is formed by etching or the like. By processing the oxide semiconductor film into the above shape, an island-like The oxide semiconductor film 241 is formed by using an oxide semiconductor as a target. The oxide semiconductor film is formed by a sputtering method using a rare gas (for example, argon). Spatial heating in ambient air, oxygen atmosphere, or rare gas (e.g. argon) and oxygen atmosphere It can be formed by a die-casting method.

[0190] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma The reverse sputtering is performed to generate ions, and the dust and dirt adhering to the surface of the gate insulating film 240 are removed. It is preferable to remove the contaminating material. Reverse sputtering is a method in which the target is not applied with a voltage. In an argon atmosphere, a voltage is applied to the substrate side using an RF power source to bombard the substrate with Ar ions. This is a method to modify the surface by using nitrogen or helium instead of argon. Alternatively, the treatment may be performed in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. Alternatively, the treatment may be performed in an argon atmosphere to which chlorine, carbon tetrafluoride, or the like has been added.

[0191] The oxide semiconductor film for forming the channel formation region has the above-described semiconductor characteristics. An oxide material having such a property may be used.

[0192] The thickness of the oxide semiconductor film is 10 nm to 300 nm, preferably 20 nm to 100 nm. In this embodiment, an oxide semiconductor target containing In, Ga, and Zn is used. (The mole ratio is In2O3:Ga2O3:ZnO=1:1:1, In2O3:Ga2O3: ZnO=1:1:2) was used, the distance between the substrate and the target was 100 mm, and the pressure was 0. Deposition was performed under an atmosphere of 6 Pa, direct current (DC) power supply of 0.5 kW, and oxygen (oxygen flow rate of 100%). In addition, if a pulsed direct current (DC) power supply is used, dust can be reduced and the film thickness distribution becomes uniform. In this embodiment, an In-Ga-Zn-O based oxide semiconductor film is used as the oxide semiconductor film. Using a ZnO semiconductor target, a 30 nm thick In-Ga-Zn-O sputtering device was used. A non-single crystal film is formed.

[0193] Note that by forming an oxide semiconductor film without exposure to air after the plasma treatment, the gate insulating film can be formed. It is possible to prevent dust and moisture from adhering to the interface between the insulating film 240 and the oxide semiconductor film. A pulsed direct current (DC) power supply is preferable because it reduces dust and makes the film thickness distribution uniform. I wish.

[0194] The relative density of the oxide semiconductor target is 80% or more, preferably 95% or more, and The relative density is preferably 99.9% or more. When a target with a high relative density is used, The impurity concentration in the oxide semiconductor film to be formed can be reduced, and the electrical characteristics or reliability can be improved. Thus, a thin film transistor with high performance can be obtained.

[0195] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0196] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0197] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0198] In addition, the substrate temperature is kept between 100℃ and 700℃ by light or heater during film formation by sputtering. Heating may be performed. By heating during film formation, damage caused by sputtering can be repaired at the same time as film formation. do.

[0199] In addition, before the oxide semiconductor film is formed, the inner wall of the sputtering apparatus, the surface of the target, and the It is advisable to perform a preheat treatment to remove any moisture or hydrogen remaining in the material. The preheating process involves heating the deposition chamber to 200℃ to 600℃ under reduced pressure. There are two methods: preheating, or repeatedly introducing and exhausting nitrogen or inert gas while heating. After the processing is completed, the substrate or sputtering device is cooled and then the oxide semiconductor is In this case, it is better to use oil or fat as the target cooling liquid instead of water. Repeated nitrogen introduction and exhaust without heating can produce a certain effect, but And even better.

[0200] In addition, before, during, or after the formation of the oxide semiconductor film, It is preferable to remove moisture remaining therein using a cryopump.

[0201] The island-shaped oxide semiconductor film 241 is formed by, for example, a mixed solution of phosphoric acid, acetic acid, and nitric acid. The island-shaped oxide semiconductor film 241 is formed on the gate electrode 241. The oxide semiconductor film is etched so as to overlap with the oxide semiconductor film 234. An organic acid such as oxalic acid can be used as an etching agent. By wet etching using 07N (Kanto Chemical Co., Ltd.), unnecessary parts were removed to form islands. The oxide semiconductor film 241 is formed by wet etching. However, the etching method is not limited to this, and dry etching may be used.

[0202] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0203] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0204] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0205] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium or the like contained in the oxide semiconductor film may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0206] In order to process the material into the desired shape, the etching conditions (etching solution, etching Adjust the cooking time, temperature, etc. as appropriate.

[0207] Next, the mixture is heated in a reduced pressure atmosphere, in an inert gas atmosphere such as nitrogen or rare gas, in an oxygen gas atmosphere, or in a vacuum. The dew point was measured using a dew point meter that uses ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy)). The moisture content measured by the method is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. The oxide semiconductor film 241 is heated in an air atmosphere (preferably 10 ppb or less). By performing heat treatment on the oxide semiconductor film 241, the oxide semiconductor film 241 can be formed as shown in FIG. As shown in FIG. 1, an oxide semiconductor film 242 in which the content of impurities such as hydrogen and water is reduced is formed. Specifically, the device is heated under an inert gas atmosphere (nitrogen, helium, neon, argon, etc.). At 300℃ to 750℃ (or a temperature below the distortion point of the glass substrate) for 1 minute RTA (Ra pid Thermal Annealing (RTA) process. Since dehydration or dehydrogenation can be performed in a short time, processing is possible even at temperatures exceeding the distortion point of the glass substrate. Note that the heat treatment can be performed immediately after the island-shaped oxide semiconductor film 241 is formed. The above-mentioned treatment may be performed on the oxide semiconductor film before etching. After the island-shaped oxide semiconductor film 241 is formed, the heat treatment may be performed multiple times.

[0208] In this embodiment, the substrate temperature is set to 600° C. in a nitrogen atmosphere. Heat treatment is performed for 6 minutes in this state. Heat treatment is performed using an electric furnace and a heated gas. GRTA (Gas Rapid Thermal Anneal) method or lamp used LRTA (Lamp Rapid Thermal Anneal) method using light For example, when the heat treatment is performed using an electric furnace, Temperature rise characteristic: 0.1℃ / min to 20℃ / min, temperature fall characteristic: 0.1℃ / min or more It is preferable to set the rate to 15° C. / min or less.

[0209] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain any hydrogen or other elements. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, It is preferable that the concentration of the ion exchange resin is 0.1 ppm or less.

[0210] Next, the insulating film 230, the insulating film 231, the insulating film 232, and the gate insulating film 240 are partially etched. By this switching, the high concentration impurity region 213 of the transistor 220 and the A contact hole is formed that reaches the high concentration impurity region 216 of the capacitor 221 and the wiring 233. Then, a thin film used as a source electrode or a drain electrode is formed over the oxide semiconductor film 242. A conductive film is formed by a sputtering method or a vacuum deposition method, and then the conductive film is etched or the like. By turning the gate, as shown in FIG. 12(B), the gate is turned into a source electrode or a drain electrode. The conductive films 245 to 249 functioning as the conductive film are formed.

[0211] Specifically, the conductive films 245 and 246 are a pair of high-concentration impurity ions included in the transistor 220. The conductive film 246 is also connected to the wiring 233. The conductive film 247 and the conductive film 248 are connected to a pair of high-resistance transistors included in the transistor 221. The conductive film 248 is connected to the conductive film 2 49 and also connected to the oxide semiconductor film 242.

[0212] The conductive films 245 to 249 may be made of, for example, aluminum, chromium, tantalum, or titanium. , manganese, magnesium, molybdenum, tungsten, zirconium, beryllium, The alloy contains one or more of the above elements. In addition, when a heat treatment is performed after the conductive film is formed, a resistance to the heat treatment may be increased. It is preferable to provide the conductive film with heat resistance that can withstand such a temperature rise. Therefore, if heat treatment is performed after the conductive film is formed, a heat-resistant conductive material must be used. Conductive film is formed by combining with conductive materials. Heat-resistant conductive material is combined with aluminum. Materials include titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium, or an alloy containing one or more of the above elements; Nitrides containing the above elements as components are preferred.

[0213] The thickness of the conductive film 245 to the conductive film 249 is 10 nm to 400 nm, preferably 100 nm to In this embodiment, a titanium film, a titanium nitride film, and an alumina film are formed by sputtering. Conductive layer for source and drain electrodes obtained by stacking aluminum and titanium films in order The film is processed (patterned) into a desired shape by etching to form a conductive film 245 to A conductive film 249 is formed.

[0214] The etching for forming the conductive films 245 to 249 may be wet etching or Dry etching can be used. When forming the conductive film 249, gas containing chlorine (Cl2), boron chloride (BCl3), etc. is used. In this etching step, the exposed region of the oxide semiconductor film 241 is also partially etched. The conductive film 248 and the conductive film 249 are separated into an island-shaped oxide semiconductor film 250. The oxide semiconductor film 250 has a small thickness in the region between the oxide semiconductor film 250 and the first insulating film 250 .

[0215] As shown in FIG. 12C, after the conductive films 245 to 249 are formed, the conductive film 245 An insulating film 251 is formed so as to cover the conductive film 249 and the oxide semiconductor film 250. 251 should be as free of impurities as possible, such as moisture, hydrogen, and oxygen, and should be a single layer of insulation. The insulating film 25 may be a single insulating film, or may be composed of a plurality of insulating films stacked together. It is desirable to use a material with high barrier properties for the insulating film 1. For example, The silicon nitride film, the silicon oxynitride film, the aluminum nitride film, or the aluminum oxynitride film In the case where a plurality of laminated insulating films are used, the above-mentioned high barrier properties can be used. Insulating films such as silicon oxide films and silicon oxynitride films, which have a lower nitrogen ratio than insulating films, are called oxide semi-insulating films. The insulating film having a low nitrogen ratio is formed on the side closer to the conductive film 250. The insulating film 245 to the conductive film 249 and the oxide semiconductor film 250 are provided so as to overlap with each other. By using an insulating film having a barrier property, the oxide semiconductor film 250 and the gate insulating film are formed. In the gate insulating film 240, or at the interface between the oxide semiconductor film 250 and another insulating film and in the vicinity thereof, Impurities such as moisture or hydrogen can be prevented from entering the oxide semiconductor film. Form an insulating film such as silicon oxide film or silicon oxynitride film with a low nitrogen ratio so that it is in contact with 250. In this way, the insulating film using a material with high barrier properties is in direct contact with the oxide semiconductor film 250. This can be prevented.

[0216] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 251 has a structure in which a silicon nitride film having a thickness of 100 nm formed by a method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. in this embodiment. The temperature is 100°C.

[0217] An exposed region of the oxide semiconductor film 250 provided between the conductive film 248 and the conductive film 249 and an insulating film The insulating film 251 is in contact with the silicon oxide that constitutes the insulating film 251. The region of the oxide semiconductor film 250 becomes highly resistive, and the oxide semiconductor film 250 having a highly resistive channel formation region is A compound semiconductor film 250 can be formed.

[0218] Next, after the insulating film 251 is formed, heat treatment may be performed. or in an inert gas atmosphere (nitrogen, helium, neon, argon, etc.), The heating is preferably performed at a temperature of 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. For example, Heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. Similar to the previous heat treatment, a high-temperature short-time RTA treatment may be performed. When the above-mentioned process is performed, the oxide semiconductor film 250 is heated in a state where the oxide semiconductor film 250 is in contact with the silicon oxide that constitutes the insulating film 251. The oxide semiconductor film 250 is then made highly resistive, and the electrical characteristics of the transistor are improved. This heat treatment improves the thermal stability of the insulating film and reduces the variation in electrical properties. There is no particular limitation as long as it is after the formation of 251, and other processes, such as heat treatment during resin film formation, This process also serves as a heat treatment to reduce the resistance of the transparent conductive film, so there is no need to increase the number of processes. It is possible to do so.

[0219] Through the above steps, a transistor 260 using the oxide semiconductor film 250 as an active layer is fabricated. It can be manufactured.

[0220] Next, a conductive film is formed on the insulating film 251, and then the conductive film is patterned to form an oxide film. A back gate electrode may be formed at a position overlapping the nitride semiconductor film 250. The electrode is made of the same material and structure as the gate electrode 234 or the conductive films 245 to 249. It is possible to form the

[0221] The thickness of the back gate electrode is 10 nm to 400 nm, preferably 100 nm to 200 nm. For example, a conductive film having a structure in which a titanium film, an aluminum film, and a titanium film are stacked is used. After forming the insulating film, a resist mask is formed by photolithography, and then the insulating film is etched. The unnecessary parts are removed and the conductive film is processed (patterned) into a desired shape to form a backplane. A gate electrode may be formed on the insulating film.

[0222] When forming a back gate electrode, an insulating film is formed so as to cover the back gate electrode. The insulating film is preferably formed by removing moisture, hydrogen, oxygen, etc. from the atmosphere, which may affect the characteristics of the transistor 260. It is desirable to use a material with high barrier properties that can prevent the material from being affected by the For example, insulating films with high barrier properties include silicon nitride films, silicon oxynitride films, aluminum nitride films, Alternatively, an aluminum oxide nitride film or the like is formed by plasma CVD or sputtering. The insulating film may be formed as a single layer or a laminate. For example, it is preferable to form the film with a thickness of 15 nm to 400 nm.

[0223] The back gate electrode may be formed so as to cover the entire oxide semiconductor film 250. However, the oxide semiconductor film 250 at least partially overlaps with a channel formation region of the oxide semiconductor film 250. Good.

[0224] The back gate electrode may be in an electrically insulated floating state, or may be in an electrically insulated floating state. In the latter case, the back gate electrode may be provided with a gate electrode 2. It may be given the same potential as 34, or a fixed potential such as ground may be given. By controlling the level of the potential applied to the back gate electrode, the transistor 2 The threshold voltage of 60 can be controlled.

[0225] In addition, by partially etching the insulating film 251, the conductive films 245 to 249 are After forming a contact hole reaching either of the insulating films 251, a conductive film is formed on the insulating film 251. By patterning the film, a wiring connected to any one of the conductive films 245 to 249 is formed. It is also possible to form

[0226] In this embodiment, after a transistor using silicon is formed, However, the present invention is not limited to this structure. A transistor using a semiconductor film and a transistor using an oxide semiconductor film are formed on the same insulating surface. Alternatively, a transistor using an oxide semiconductor film may be formed, and then a transistor using silicon may be formed. However, in the case where a transistor using an oxide semiconductor film is formed, When a silicon-based transistor is stacked after the formation of the silicon, the silicon is microcrystalline silicon. Silicon or polycrystalline silicon is used.

[0227] This embodiment mode can be implemented in combination with the above embodiment modes.

[0228] (Embodiment 3) In this embodiment, the structure of a transistor including an oxide semiconductor film is different from that in Embodiment 2. The configuration of the transistor will be described.

[0229] The semiconductor device shown in FIG. 13A is an n-channel semiconductor device using crystalline silicon, similar to the second embodiment. The transistor 220 has a p-channel transistor 221. In FIG. 13A, an n-channel transistor 220 and a p-channel transistor 2 21, a bottom-gate transistor having a channel protection structure using an oxide semiconductor film 310 is formed.

[0230] The transistor 310 includes a gate electrode 311 formed on the insulating film 232 and a gate electrode 313. 11, and a gate insulating film 312 overlapping with the gate electrode 311 on the gate insulating film 312. The oxide semiconductor film 313 overlaps with the gate electrode 311. A channel protective film 314 formed on the semiconductor film 313 and a The transistor 310 further includes a conductive film 315 and a conductive film 316. The insulating film 317 formed on the semiconductor film 313 may be included as a component thereof.

[0231] By providing the channel protective film 314, the channel formation region of the oxide semiconductor film 313 Damage to the part that will be damaged during subsequent processes (plasma during etching and etching) This prevents the film from shrinking due to adhesives, thus improving the reliability of the transistor. It is possible.

[0232] The channel protection film 314 is made of an inorganic material containing oxygen (silicon oxide, silicon nitride oxide, silicon oxynitride, etc.). Aluminum oxide, aluminum oxynitride, etc.) can be used. The protective film 314 is formed by vapor deposition such as plasma CVD or thermal CVD, or sputtering. The channel protection film 314 can be formed by etching after the film formation. Here, a silicon oxide film is formed by sputtering, and then photolithography is used to process the silicon oxide film. The channel protective film 314 is formed by etching using the mask.

[0233] In addition, an oxygen film is formed in contact with the island-shaped oxide semiconductor film 313 by a sputtering method, a PCVD method, or the like. When the channel protective film 314, which is an insulating film containing At least the region in contact with the channel protection film 314 becomes highly resistive, and the high-resistance oxide semiconductor By forming the channel protective film 314, the oxide semiconductor film 313 becomes a channel region. A high-resistance oxide semiconductor region can be provided in the vicinity of the interface with the protective film 314 .

[0234] The transistor 310 further includes a back gate electrode on the insulating film 317. The back gate electrode may be formed so as to overlap with a channel formation region of the oxide semiconductor film 313. The back gate electrode can be formed even in an electrically insulated floating state. In the latter case, the back gate electrode may be in a state where a potential is applied. The potential may be the same as that of the ground electrode 311, or may be a fixed potential such as ground. By controlling the level of the potential applied to the back gate electrode, The threshold voltage of the transistor 310 can be controlled.

[0235] The semiconductor device shown in FIG. 13B is an n-channel semiconductor device using crystalline silicon, similar to the second embodiment. The transistor 220 has a p-channel transistor 221. In FIG. 13B, an n-channel transistor 220 and a p-channel transistor 2 A bottom-contact transistor 320 using an oxide semiconductor film is formed on the semiconductor substrate 21. is.

[0236] The transistor 320 includes a gate electrode 321 formed on the insulating film 232 and a gate electrode 323. 21, a gate insulating film 322, a conductive film 323 and a conductive film 324 on the gate insulating film 322, The transistor further includes an oxide semiconductor film 325 overlapping with the gate electrode 321. The photodiode 320 includes an insulating film 326 formed on an oxide semiconductor film 325 as one of its components. You can also do so.

[0237] In the case of the bottom-contact type transistor 320, the conductive film 323 and the conductive film 324 The thickness of the oxide semiconductor film 325 is set to a value in order to prevent a step from being generated in the oxide semiconductor film 325 to be formed later. It is preferable to make it thinner than the bottom gate type shown in form 2. Specifically, it is 10 nm to The thickness is set to 200 nm, and preferably 50 nm to 75 nm.

[0238] The transistor 320 further includes a back gate electrode on the insulating film 326. The back gate electrode may be formed so as to overlap with a channel formation region of the oxide semiconductor film 325. The back gate electrode can be formed even in an electrically insulated floating state. In the latter case, the back gate electrode may be in a state where a potential is applied. The potential may be the same as that of the ground electrode 321, or may be a fixed potential such as ground. By controlling the level of the potential applied to the back gate electrode, The threshold voltage of the transistor 320 can be controlled.

[0239] The semiconductor device shown in FIG. 13C is an n-channel semiconductor device using crystalline silicon, similar to the second embodiment. The transistor 220 has a p-channel transistor 221. In FIG. 13C, an n-channel transistor 220 and a p-channel transistor 2 A top-gate transistor 330 using an oxide semiconductor film is formed on the semiconductor substrate 21. do.

[0240] The transistor 330 includes a conductive film 331 and a conductive film 332 formed over an insulating film 232. The oxide semiconductor film 333 is formed on the conductive film 331 and the conductive film 332. 3, and a gate insulating film 334 overlapping the oxide semiconductor film 333 on the gate insulating film 334. The transistor 330 further includes a gate electrode 335. The insulating film 336 formed on the insulating film 335 may be included in the components.

[0241] In the case of the top-gate transistor 330, the thicknesses of the conductive films 331 and 332 are In order to prevent the oxide semiconductor film 333 to be formed later from being cut off, It is desirable to make it thinner than the bottom gate type shown in 2. Specifically, it is 10 nm to 20 0 nm, preferably 50 nm to 75 nm.

[0242] In the semiconductor device shown in FIG. 13C, the gate electrode 335 and the transistor 220 A contact hole reaching the conductive film 338 functioning as a source electrode or a drain electrode is formed. After forming the insulating film 336 and the gate insulating film 334, the gate electrode 335 and the conductive film 338 are A wiring 337 connected to the

[0243] This embodiment mode can be implemented in combination with the above embodiment modes.

[0244] (Embodiment 4) In this embodiment, a display device called electronic paper or digital paper according to one embodiment of the present invention will be described. The configuration of the semiconductor display device will be described.

[0245] Electronic paper is a type of display that can control the gradation by applying voltage and has a memory function. Specifically, the display element used in the electronic paper is a non-aqueous electrophoretic display element. A dynamic display element in which liquid crystal droplets are dispersed in a polymer material between two electrodes. LC (polymer dispersed liquid crystal) method table Display element, display having chiral nematic liquid crystal or cholesteric liquid crystal between two electrodes The element has charged particles between two electrodes, and the particles are moved through the powder by an electric field. A powder migration type display element can be used. A non-aqueous electrophoretic display element can also be used. The display element is a liquid dispersion in which charged particles are dispersed between two electrodes. A display element having a dispersion liquid in which fine particles are dispersed, on two electrodes sandwiching an insulating film, A twisting ball with two different colored hemispheres, each charged with a different electric charge, is placed between two electrodes. a display element in which a plurality of charged particles are dispersed in a solvent; This includes a display element having a black capsule between two electrodes.

[0246] FIG. 14A shows a pixel portion 700 of electronic paper, a signal line driver circuit 701, and a scanning line driver circuit 702. A top view of the circuit 702 is shown.

[0247] The pixel portion 700 has a plurality of pixels 703. A signal line 707 is routed to the inside of the pixel portion 700. The scanning lines 708 are routed to within the pixel section 700 .

[0248] Each pixel 703 includes a transistor 704, a display element 705, and a storage capacitor 706. The gate electrode of the transistor 704 is connected to one of the scanning lines 708. The source electrode and drain electrode of the transistor 704 are connected to one of the signal lines 707 and the other It is connected to the pixel electrode of the display element 705 .

[0249] In FIG. 14A, the voltage applied between the pixel electrode and the counter electrode of the display element 705 is maintained. A storage capacitor 706 is connected in parallel to the display element 705 to maintain the display. If the memory capacity of 05 is high enough to maintain the display, the retention capacity of 70 It is not necessary to provide 6.

[0250] In FIG. 14A, each pixel has one transistor functioning as a switching element. The structure of the active matrix type pixel portion in which the pixel electrode is provided has been described. The electronic paper to be used is not limited to this configuration. Alternatively, elements such as capacitors, resistors, and coils may be connected in addition to the transistors. stomach.

[0251] FIG. 14(B) shows an example of electrophoretic electronic paper with microcapsules. 7 is a cross-sectional view of a display element 705 provided in a substrate 703 and a signal line driver circuit 701 or a scanning line driver circuit 702. 7A and 7B are cross-sectional views of semiconductor elements used in driving circuits such as a driving circuit 702.

[0252] In the pixel, the display element 705 includes a pixel electrode 710, a counter electrode 711, and a pixel electrode 71 0 and a microcapsule 712 to which a voltage is applied by a counter electrode 711. Either the conductive film 713 functioning as a source electrode or a drain electrode of the transistor 704 One of them is connected to the pixel electrode 710 .

[0253] The transistor 704 uses an oxide semiconductor film for an active layer. The off-state current when the voltage between the source electrodes is almost zero, that is, the leakage current, is This is significantly lower than that of silicon-based transistors.

[0254] Inside the microcapsule 712, positively charged white pigment such as titanium oxide and carbon Negatively charged black pigments such as lanthanum black are enclosed together with a dispersion medium such as oil. According to the voltage of the video signal applied to the pixel electrode 710, the pixel electrode and the counter electrode By applying a voltage between them, the black pigment is attracted to the positive electrode side and the white pigment is attracted to the negative electrode side. , it is possible to perform gradation display.

[0255] In FIG. 14B, the microcapsules 712 are disposed between the pixel electrode 710 and the counter electrode 711. However, the present invention uses this structure. The structure is not limited to the above, and may be formed by a microcapsule 712, a pixel electrode 710, and a counter electrode 711. The space formed may be filled with a gas such as air or an inert gas. In this case, the microcapsules 712 are attached to the pixel electrodes 710 and the counter electrodes 711 by adhesive or the like. It is desirable to fix both or either one of them.

[0256] The number of microcapsules 712 included in the display element 705 is as shown in FIG. A single display element 705 may have multiple microcapsules 712. Alternatively, multiple display elements 705 may have one microcapsule 712. For example, two display elements 705 may share one microcapsule 712. A positive voltage is applied to the pixel electrode 710 of the display element 705, and a positive voltage is applied to the pixel electrode 710 of the other display element 705. Suppose a negative voltage is applied to the pixel electrode 710. In this case, a positive voltage is applied to In the area overlapping with the pixel electrode 710 to which the voltage is applied, a black face is formed within the microcapsule 712. The white pigment is attracted to the pixel electrode 710 side, and the white pigment is attracted to the counter electrode 711 side. Conversely, in the area overlapping with the pixel electrode 710 to which a negative voltage is applied, the microcapsule In the cell 712, the white pigment is attracted to the pixel electrode 710 side, and the black pigment is attracted to the counter electrode 71 It gravitates towards one side.

[0257] The driver circuit includes a transistor 720 including an oxide semiconductor film as an active layer and a silicon A transistor 721 is formed in the active layer. A transistor 720 is used as a switching element that controls the supply of a power supply voltage to the circuit. This can be done.

[0258] During the non-operating period, the supply of the power supply voltage to the circuit is stopped by the switching element. This reduces the dynamic standby power consumed by the circuit. Since the active layer of the transistor 720 is an oxide semiconductor film, the potential between the gate electrode and the source electrode is The off-state current at almost zero voltage, that is, the leakage current, is the This is significantly lower than that of the transistor 721 used in the present embodiment. By using it as a switching element, the static standby current that depends on leakage current, etc., generated in the switching element can be eliminated. Therefore, the supply of power supply voltage to non-operating circuits can be stopped, and the non-operating circuits can be By reducing both the static and dynamic standby power consumed by the operating circuit, It is possible to provide a semiconductor device capable of reducing the overall power consumption.

[0259] In particular, electronic paper has a smaller memory capacity than other semiconductor display devices such as liquid crystal displays and light-emitting devices. Since the display element has high storage stability, the signal line driver circuit 701 or The period during which the operation of the driving circuits such as the scanning line driving circuit 702 can be stopped tends to be long. By applying the configuration of the present invention, standby power can be more effectively used than with other semiconductor display devices. This can be effectively reduced.

[0260] The transistor 721 using crystalline silicon is a transistor having an oxide semiconductor. The mobility and on-current of the transistor 720 are higher than those of the transistor 720. By forming a circuit using 21, it is possible to achieve high integration and high speed operation of an integrated circuit using the circuit. It is possible to achieve this.

[0261] Next, regarding a specific method for driving electronic paper, the above-mentioned electrophoretic electronic paper will be Let me explain with an example.

[0262] The operation of electronic paper can be explained by dividing it into an initialization period, a writing period, and a retention period. Yes, it is possible.

[0263] Before switching the image to be displayed, the grayscale of each pixel in the pixel area is first reset during the initialization period. By unifying the display elements, the display elements are initialized. By initializing the display elements, afterimages are prevented from remaining. Specifically, in the electrophoretic type, each pixel is displayed in either white or black. , the gray scale displayed by the microcapsules 712 of the display element 705 is adjusted.

[0264] In this embodiment, an initialization video signal for displaying black is input to the pixels, and then a video signal for displaying white is input to the pixels. The initialization operation will be described when an initialization video signal such as that shown in the figure is input to a pixel. For example, in the case of an electrophoretic electronic paper in which an image is displayed facing the counter electrode 711 side, In this case, first, the black pigment in the microcapsule 712 is placed on the counter electrode 711 side, and the white pigment is placed on the image side. A voltage is applied to the display element 705 so that it faces the base electrode 710. The white pigment in the cell 712 faces the counter electrode 711 side, and the black pigment faces the pixel electrode 710 side. Then, a voltage is applied to the display element 705 .

[0265] Also, if the initialization video signal is input to the pixel only once, the image displayed before the initialization period Depending on the gradation, the movement of the white pigment and the black pigment in the microcapsule 712 may be incomplete. Even after the initialization period ends, the gradation displayed between the pixels remains the same. Therefore, a negative voltage - Vp is applied to the pixel electrode 710 multiple times to display black. It is desired to display white by applying a positive voltage Vp to the pixel electrode 710 multiple times. I wish.

[0266] If the gray scale displayed by the display element of each pixel before the initialization period is different, The minimum number of times that the video signal must be input for display before the initialization period also differs. The number of times the initialization video signal is input between pixels is changed according to the gray scale that was set. In this case, the pixels that no longer need to input the initialization video signal may be It is a good idea to input the supply voltage Vcom.

[0267] In addition, the voltage Vp or voltage −Vp of the initialization video signal is applied to the pixel electrode 710 multiple times. In order to achieve this, during the period in which the selection signal pulse is applied to each scanning line, the scanning line is A series of operations in which an initialization video signal is input to the pixels of the line having the By applying the voltage Vp or voltage −Vp of the initialization video signal to the pixel electrode 710 multiple times, Thus, the movement of the white pigment and the black pigment in the microcapsule 712 is converged to form a gap between pixels. It is possible to prevent a difference in gray scale from occurring in the pixel portion and initialize the pixels in the pixel portion.

[0268] In the initialization period, each pixel does not first display black and then display white. Alternatively, in the initialization period, each pixel may display black after the first pixel displays white. It is also possible to display white, then black, and then white again.

[0269] The timing at which the initialization period starts is the same for all pixels in the pixel section. For example, it is not necessary to do it pixel by pixel, or pixel by pixel that belongs to the same line. The timing at which the initialization period starts may be made different.

[0270] Next, in the writing period, a video signal having image information is input to the pixels.

[0271] When displaying an image using the entire pixel area, power is applied to all the scanning lines in sequence during one frame period. A selection signal with a shifted voltage pulse is input. Then, a pulse appears in the selection signal. During one line period, video signals having image information are input to all signal lines. do.

[0272] The white light in the microcapsule 712 changes in response to the voltage of the video signal applied to the pixel electrode 710. The color pigment and the black pigment move to the pixel electrode 710 side or the counter electrode 711 side, forming a display element. The child 705 displays the gray scale.

[0273] In addition, during the writing period, the voltage of the video signal is applied to the pixel electrode 710 multiple times, as in the initialization period. Therefore, during the period when the selection signal pulse is applied to each scanning line, A series of operations of inputting a video signal to pixels of a line having the scanning line is described below. Do this multiple times.

[0274] Next, in the retention period, a common voltage Vcom is input to all pixels via the signal lines, and then the scanning No selection signal is input to the line or no video signal is input to the signal line. The white and black pigments in the microcapsules 712 of 705 correspond to the pixel electrodes 710. The arrangement is maintained unless a positive or negative voltage is applied between the opposing electrodes 711. Therefore, the gray scale displayed by the display element 705 is maintained. The displayed image is maintained during the retention period.

[0275] The display element used in electronic paper requires a voltage to change the gradation of the liquid crystal. For light emitting elements such as liquid crystal elements used in display devices and organic light emitting elements used in light emitting devices Therefore, the transistors in the pixels used as switching elements tend to be In the write period, the potential difference between the source electrode and the drain electrode of the transistor 704 becomes large. Therefore, the off current becomes high, and the potential of the pixel electrode 710 fluctuates, which tends to cause display disturbance. However, as described above, in one embodiment of the present invention, the oxide semiconductor film is Therefore, the transistor 704 has a voltage between the gate electrode and the source electrode. The off-state current when the gate insulating layer is almost zero, that is, the leakage current, is Therefore, during the write period, the transistor 70 Even if the potential difference between the source electrode and the drain electrode of 4 becomes large, the off-current is suppressed, and the pixel electrode This makes it possible to prevent display disturbances caused by fluctuations in the potential of 710.

[0276] In the present embodiment, electronic paper is taken as an example of the semiconductor display device of the present invention. The semiconductor display device of the present invention is a light-emitting device represented by a liquid crystal display device or an organic light-emitting device (OLED). DMD (Digital Micromirror Display), a light-emitting device with an element for each pixel device), PDP (Plasma Display Panel), FED (Fie LD Emission Display, etc., and driving circuits using semiconductor elements Other semiconductor display devices that use the same technology are included in this category.

[0277] For example, the power supply voltage is not supplied to the semiconductor display device, such as a screen saver. However, when image display is temporarily stopped, the standby power consumption is reduced. It is possible.

[0278] This embodiment mode can be implemented in combination with the above embodiment modes.

[0279] (Embodiment 5) A structure of a liquid crystal display device according to one embodiment of the present invention will be described.

[0280] Fig. 15 is a perspective view showing an example of the structure of a liquid crystal display device of the present invention. The display device includes a liquid crystal panel 1601 having a liquid crystal element formed between a pair of substrates, and a first diffusion plate 1602. 602, a prism sheet 1603, a second diffusion plate 1604, a light guide plate 1605, and a reflector It has a reflector 1606 , a light source 1607 , and a circuit board 1608 .

[0281] A liquid crystal panel 1601, a first diffusion plate 1602, a prism sheet 1603, and a second diffusion plate 1604 are arranged in a liquid crystal panel 1601. The scattering plate 1604, the light guide plate 1605, and the reflector plate 1606 are laminated in this order. A light source 607 is provided at the end of the light guide plate 1605 and diffused inside the light guide plate 1605. The light from 1607 passes through the first diffusion plate 1602, the prism sheet 1603, and the second diffusion plate The liquid crystal panel 1601 is uniformly irradiated by the light 1604 .

[0282] In this embodiment, a first diffusion plate 1602 and a second diffusion plate 1604 are used. However, the number of the diffusion plates is not limited to this, and may be one or more than two. The scattering plate may be provided between the light guide plate 1605 and the liquid crystal panel 1601. Even if a diffusion plate is provided only on the side closer to the liquid crystal panel 1601 than the reflective sheet 1603, It is preferable that the diffusion plate is provided only on the side closer to the light guide plate 1605 than the prism sheet 1603. It's fine if it is.

[0283] The cross section of the prism sheet 1603 is not limited to the sawtooth shape shown in FIG. It is only necessary that the shape be such that the light from the plate 1605 can be condensed onto the liquid crystal panel 1601 side.

[0284] The circuit board 1608 includes a circuit for generating various signals to be input to the liquid crystal panel 1601, In FIG. 15, a circuit board 16 is provided with circuits for processing these signals. 08 and the LCD panel 1601 are connected by FPC (Flexible Printed Circuit The above circuit is connected via a COG (Chip ON The liquid crystal panel 1601 may be connected using the MOS transistor (Glass) method, or one of the above circuits may be connected using the MOS transistor (Glass) method. Even if the part is connected to FPC1609 using the COF (Chip on Film) method good.

[0285] In FIG. 15, a control circuit for controlling the driving of a light source 1607 is provided on a circuit board 1608. The control circuit and the light source 1607 are connected via an FPC 1610. However, the control circuit may be formed in the liquid crystal panel 1601. In this case, the liquid crystal panel 1601 and the light source 1607 are connected by an FPC or the like. do.

[0286] FIG. 15 shows an edge-light type light source in which a light source 1607 is disposed at the edge of a liquid crystal panel 1601. In the liquid crystal display device of the present invention, the light source 1607 is directly below the liquid crystal panel 1601. The liquid crystal display device according to one aspect of the present invention may be a direct type in which the light emitting diode is disposed in a transmissive manner. It may be of a transflective or reflective type.

[0287] The liquid crystal display device may be of the TN (Twisted Nematic) type. VA (Vertical Alignment) type, OCB (optically co mpensated birefringence) type, IPS (In-Plane S witching type, etc.

[0288] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so chiral dopants and purple dopants are not suitable for this purpose. Add UV-curable resin to improve the temperature range. Blue phase liquid crystal and chiral agent or UV The liquid crystal composition containing the cured resin has a response speed of 10 μsec or more and 100 μsec or less. It is preferable because it is short, optically isotropic, does not require alignment treatment, and has small viewing angle dependency. stomach.

[0289] This embodiment mode can be implemented in appropriate combination with the above embodiment modes. EXAMPLES

[0290] By using a semiconductor device according to one embodiment of the present invention, an increase in power consumption can be prevented and high performance can be achieved. In particular, it is difficult to constantly receive a power supply. In the case of portable electronic devices, a semiconductor device according to one embodiment of the present invention can be added to the components thereof. This also has the advantage of extending the continuous usage time.

[0291] The semiconductor device according to one embodiment of the present invention is applicable to a display device, a notebook personal computer, a recording medium, Image playback device equipped with a medium (typically DVD: Digital Versatile (Devices with a display that can play back recording media such as discs and display the images) In addition, a semiconductor device according to one embodiment of the present invention can be used in a power As child devices, mobile phones, portable game consoles, personal digital assistants, electronic books, video cameras, Digital still camera, goggle-type display (head-mounted display), navigation systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, printer-combination machines, automated teller machines (A TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 16.

[0292] FIG. 16A shows an electronic book having a housing 7001, a display portion 7002, and the like. The semiconductor display device according to the embodiment can be used for the display portion 7002. By using a semiconductor display device according to one embodiment of the present invention, a display device with low power consumption and high functionality can be obtained. In addition, the semiconductor device according to one embodiment of the present invention can provide a digital book. The present invention can be used in an integrated circuit for controlling the driving of an electronic book. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit, the integrated circuit can have low power consumption and high functionality. In addition, by using a flexible substrate, it is possible to provide an electronic book that can read electronic books. Since it is possible to give flexibility to the semiconductor display device, it is flexible and lightweight. It is possible to provide an easy-to-use e-book.

[0293] FIG. 16B shows a display device, which includes a housing 7011, a display portion 7012, a support 7013, etc. The semiconductor display device according to one embodiment of the present invention can be used for the display portion 7012. By using a semiconductor display device according to one embodiment of the present invention for the display portion 7012, it is possible to realize high-performance display with low power consumption. In addition, a display device having a function similar to that of the semiconductor device according to one embodiment of the present invention can be provided. The device can be used in an integrated circuit for controlling the driving of a display device. By using a semiconductor device according to one embodiment of the present invention in an integrated circuit for controlling It is possible to provide a display device having high functionality with a high level of power. This includes all information display devices such as those for mobile computers, TV broadcast reception, and advertising displays. can be.

[0294] FIG. 16C shows a display device, which includes a housing 7021, a display portion 7022, and the like. The semiconductor display device according to this embodiment can be used for the display portion 7022. By using a semiconductor display device according to one embodiment of the present invention, a display device with low power consumption and high functionality can be achieved. In addition, the semiconductor device according to one embodiment of the present invention can provide a display device. The present invention can be used in an integrated circuit for controlling the driving of a display device. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit, the integrated circuit can have low power consumption and high functionality. In addition, by using a flexible substrate, a display device can be provided. Since it is possible to give flexibility to the semiconductor display device, it is flexible and lightweight. It is possible to provide a display device that is easy to use. Therefore, as shown in FIG. The display device can be fixed to fabric and used, greatly expanding the range of applications for the display device. do.

[0295] FIG. 16D shows a portable game machine. The portable game machine includes a housing 7031, a housing 7032, a display portion 7033, A display unit 7034, a microphone 7035, a speaker 7036, an operation key 7037, a star The semiconductor display device according to one embodiment of the present invention includes a display portion 7033, The display portion 7033 and the display portion 7034 can be used as an embodiment of the present invention. By using the semiconductor display device, a portable game machine having low power consumption and high functionality can be realized. In addition, the semiconductor device according to one embodiment of the present invention can be used as a It can be used in an integrated circuit for controlling the driving of a portable game machine. By using a semiconductor device according to one embodiment of the present invention in an integrated circuit for a semiconductor device, the semiconductor device can achieve high performance with low power consumption. It is possible to provide a portable game machine having the above functions. The game machine has two display units 7033 and 7034. However, the number of display units is not limited to this.

[0296] FIG. 16E shows a mobile phone. The mobile phone includes a housing 7041, a display unit 7042, an audio input unit 7043, The device has a voice output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The semiconductor display device according to one embodiment of the present invention can be used for the display portion 7042. By using a semiconductor display device according to one embodiment of the present invention, a high level of functionality can be achieved with low power consumption. In addition, a semiconductor device according to one embodiment of the present invention can be provided. The present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using a semiconductor device according to one embodiment of the present invention in an integrated circuit for It is possible to provide a mobile phone having the functionality.

[0297] FIG. 16F shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 16(F) has a modem built in a housing 7051. The semiconductor display device according to one embodiment of the present invention can be used for the display portion 7052. By using a semiconductor display device according to one embodiment of the present invention for the display portion 7052, power consumption can be reduced. In addition, a highly functional portable information terminal according to one embodiment of the present invention can be provided. The semiconductor device can be used in an integrated circuit for controlling the operation of a portable information terminal. A semiconductor device according to one embodiment of the present invention is used in an integrated circuit for controlling the operation of a portable information terminal. This makes it possible to provide a portable information terminal that consumes low power and has high functionality.

[0298] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0299] 100 circuits 101 Switching element 101a Switching element 101b Switching element 101c Switching element 101d Switching element 102 Control circuit 110 Transistor 111 Transistor 112 Load 120 Transistor 121 Transistor 122 Transistor 123 Transistor 124 Load 130 Transistor 131 Transistor 132 Transistor 133 Transistor 134 Load 140 NAND 141 NAND 142 NAND 143 NAND 200 Bonded Board 201 Insulating film 202 Brittle layer 203 Base Board 204 Semiconductor Film 205 Semiconductor Film 206 Semiconductor Film 207 Semiconductor Film 208 Gate insulating film 209 Electrode 210 Impurity region 211 Impurity region 212 Sidewall 213 High concentration impurity region 214 Low concentration impurity region 215 Channel formation region 216 High concentration impurity region 217 Low concentration impurity region 218 Channel formation region 220 Transistor 221 Transistor 230 Insulating film 231 Insulating Film 232 Insulating film 233 Wiring 234 Gate electrode 240 Gate insulating film 241 Oxide Semiconductor Film 242 Oxide Semiconductor Film 245 Conductive Film 246 Conductive Film 247 Conductive Film 248 Conductive Film 249 Conductive Film 250 Oxide Semiconductor Film 251 Insulating film 260 Transistors 310 Transistor 311 Gate electrode 312 Gate insulating film 313 Oxide Semiconductor Film 314 Channel protection film 315 Conductive Film 316 Conductive Film 317 Insulating Film 320 Transistor 321 Gate electrode 322 Gate insulating film 323 Conductive Film 324 Conductive Film 325 Oxide Semiconductor Film 326 Insulating Film 330 Transistor 331 Conductive Film 332 Conductive Film 333 Oxide Semiconductor Film 334 Gate insulating film 335 Gate electrode 336 Insulating Film 337 Wiring 338 Conductive Film 700 pixels 701 Signal line driver circuit 702 Scanning line driver circuit 703 pixels 704 Transistor 705 Display element 706 Holding capacity 707 Signal Line 708 scan lines 710 Pixel electrode 711 Counter Electrode 712 Microcapsules 713 Conductive Film 714 Resin 720 Transistor 721 Transistor 1601 Liquid crystal panel 1602 First diffuser 1603 Prism sheet 1604 Second diffuser 1605 Light guide plate 1606 Reflector 1607 Light source 1608 Circuit Board 1609 FPC 1610 FPC 7001 Case 7002 Display section 7011 Case 7012 Display section 7013 Support stand 7021 Case 7022 Display section 7031 Case 7032 Case 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Case 7042 Display section 7043 Audio input section 7044 Audio output section 7045 Operation key 7046 Light receiving section 7051 Case 7052 Display section 7053 Operation key

Claims

1. a first transistor having silicon in a channel formation region; a second transistor having silicon in a channel formation region; a third transistor having an oxide semiconductor in a channel formation region, a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a second conductive layer having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a first insulating layer having a region located above the first conductive layer and a region located above the second conductive layer; a third conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate electrode of the third transistor; a fourth conductive layer having a region in contact with an upper surface of the first insulating layer and having the same material as the third conductive layer; a second insulating layer having a region located above the third conductive layer and a region located above the fourth conductive layer; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the third transistor; a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a source region or a drain region of the first transistor; a sixth conductive layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with a source region or a drain region of the second transistor, the sixth conductive layer having the same material as the fifth conductive layer; a third insulating layer having a region in contact with an upper surface of the fifth conductive layer and a region in contact with an upper surface of the sixth conductive layer; The fourth conductive layer has a region that functions as a wiring.

2. a first transistor having silicon in a channel formation region; a second transistor having silicon in a channel formation region; a third transistor having an oxide semiconductor in a channel formation region, a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a second conductive layer having a region located above a channel formation region of the second transistor and functioning as a gate electrode of the second transistor; a first insulating layer having a region located above the first conductive layer and a region located above the second conductive layer; a third conductive layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate electrode of the third transistor; a fourth conductive layer having a region in contact with an upper surface of the first insulating layer and having the same material as the third conductive layer; a second insulating layer having a region located above the third conductive layer and a region located above the fourth conductive layer; an oxide semiconductor layer having a region located above the second insulating layer and including a channel formation region of the third transistor; a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a source region or a drain region of the first transistor; a sixth conductive layer having a region in contact with an upper surface of the fourth conductive layer and a region in contact with a source region or a drain region of the second transistor, the sixth conductive layer having the same material as the fifth conductive layer; a third insulating layer having a region in contact with an upper surface of the fifth conductive layer and a region in contact with an upper surface of the sixth conductive layer; the fourth conductive layer has a region that functions as a wiring; the fourth conductive layer has a region overlapping with a semiconductor layer having a channel formation region of the second transistor.

Images