Semiconductor device and manufacturing method for the same

Abstract

To provide a semiconductor device that mitigates the effects of thermal stress generated on both the front and back surfaces of a semiconductor element during use in the semiconductor device having a structure in which both the front and back surfaces of the semiconductor element are connected to a rigid body via a solder alloy.SOLUTION: A semiconductor device includes a semiconductor element, a lead frame, an insulating substrate, a first bonding material for bonding the semiconductor element to the lead frame, a second bonding material for bonding the semiconductor element to the insulating substrate, and a third bonding material for bonding the insulating substrate to the lead frame. The solid phase line temperature of the first bonding material is lower than the solid phase line temperature of the second bonding material. The solid phase line temperature of the third bonding material is equal to or higher than the solid phase line temperature of the second bonding material.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a structure in which both the front and back sides of a semiconductor element are connected to a rigid body via a solder alloy, and to a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor power module described in Patent Document 1 is known as a semiconductor device having a structure in which both the front and back sides of a semiconductor element are connected to a rigid body via a solder alloy.

[0003] For example, in paragraph 0088 of Patent Document 1, it is stated that "In the semiconductor module (semiconductor power module) 19 shown in FIG. 10, a bonding material such as solder alloy 2b or solder alloy 2b is bonded to both the front and back sides of a semiconductor chip 1, a lead frame 28 is bonded to the bonding materials on both sides of the semiconductor chip 1, and a heat dissipation metal plate 12 is further bonded to the lead frame 28 via an insulating heat dissipation grease 27." It is explained that the semiconductor power module in FIG. 10 of the same document has a structure in which the front and back sides of the semiconductor chip are connected to a lead frame, which is a rigid body, via solder alloys arranged on both the front and back sides of the semiconductor chip. In addition, the abstract and paragraph 0029 of the same document indicate that the solder alloy is made of Sn-Cu-Sb. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2016 / 079881 Summary of the Invention [Problem to be solved by the invention]

[0005] In general, a solder alloy made of Sn-Cu-Sb has a characteristic of being highly resistant to thermal fatigue, and therefore, by using a solder alloy made of Sn-Cu-Sb on both sides of a semiconductor element, as shown in FIG. 10 of Patent Document 1, it is possible to bond the semiconductor element with high reliability.

[0006] However, while solder made of Sn-Cu-Sb has high thermal fatigue resistance, it tends to be harder than normal Sn-based solder. Patent Document 1 does not particularly consider the configuration in which both sides of a semiconductor element are bound by a hard solder alloy as a problem, and does not give any special consideration to the thermal stress that occurs on both sides of a semiconductor element when the temperature rises during use of the semiconductor device.

[0007] Therefore, an object of the present invention is to provide a semiconductor device having a structure in which both the front and back surfaces of a semiconductor element are connected to a rigid body via a solder alloy, which mitigates the effects of thermal stress generated on both the front and back surfaces of a semiconductor element during use of the semiconductor device, and a manufacturing method thereof. [Means for solving the problem]

[0008] In order to solve the above problems, the semiconductor device of the present invention is a semiconductor device having a semiconductor element, a lead frame, an insulating substrate, a first bonding material bonding the semiconductor element to the lead frame, a second bonding material bonding the semiconductor element to the insulating substrate, and a third bonding material bonding the insulating substrate to the lead frame, wherein the solidus temperature of the first bonding material is lower than the solidus temperature of the second bonding material, and the solidus temperature of the third bonding material is higher than or equal to the solidus temperature of the second bonding material.

[0009] Further, a method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device by heating a semiconductor element, a lead frame, an insulating substrate, a first bonding material bonding the semiconductor element and the lead frame, a second bonding material bonding the semiconductor element and the insulating substrate, and a third bonding material bonding the insulating substrate and the lead frame in a heating furnace, the method including the steps of: placing an insulating substrate on a jig; placing the second bonding material on a metal wiring portion of the insulating substrate; placing the semiconductor element on the second bonding material; placing the first bonding material on the semiconductor element; The method includes the steps of: arranging a plurality of the third bonding materials on a metal wiring portion; arranging the lead frame so as to straddle the plurality of the third bonding materials to provide a gap between the lead frame and the first bonding material; melting the first bonding material and adhering it to the upper surface of the semiconductor element; melting the second bonding material and adhering the lower surface of the semiconductor element and the metal wiring portion; and melting the third bonding material to adhere the lead frame and the metal wiring portion and to adhere the upper surface of the semiconductor element and the lead frame via the melted first bonding material. Effect of the Invention

[0010] According to the present invention, in a semiconductor device having a structure in which both the front and back surfaces of a semiconductor element are connected to a rigid body via a solder alloy, the effects of thermal stress generated on both the front and back surfaces of the semiconductor element during use of the semiconductor device can be mitigated. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2A] 1 is a perspective view of a manufacturing process of a semiconductor device according to a first embodiment (before being put into a heating furnace). [Figure 2B] 1 is a perspective view of a manufacturing process of a semiconductor device according to a first embodiment (before being put into a heating furnace). [Diagram 3] FIG. 2 is a schematic cross-sectional view showing a simplified manufacturing process of Example 1 (before being placed in a heating furnace). [Figure 4]1 is a schematic cross-sectional view showing a simplified manufacturing process of Example 1 (after being placed in a heating furnace). [Diagram 5] FIG. 2 is a schematic cross-sectional view showing a simplified manufacturing process of the comparative example (after being placed in a heating furnace). [Figure 6] FIG. 11 is a cross-sectional view of a lead frame of a semiconductor device according to a second embodiment. [Figure 7] 13 is a cross-sectional view of another example of the lead frame of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the semiconductor device of the present invention will be described with reference to the drawings. EXAMPLES

[0013] A semiconductor device 1 according to a first embodiment of the present invention will be described with reference to Figures 1 to 5. In the following description, the semiconductor device 1 will be described as a semiconductor power module for supplying large power to a drive motor of a train or an electric vehicle, but the semiconductor device 1 of the present invention may be another type of semiconductor device.

[0014] <Components of Semiconductor Device 1> First, the components of the semiconductor device 1 of this embodiment will be described using the cross-sectional view of Fig. 1. As shown therein, the semiconductor device 1 of this embodiment includes an insulating substrate 11, a semiconductor element 12, a lead frame 13, a first bonding material 14, a second bonding material 15, a third bonding material 16, a heat dissipation material 17, a fourth bonding material 18, and a sealing material 19. Each of these will be briefly described below. In the following, the up-down direction is defined as shown in Fig. 1.

[0015] The insulating substrate 11 is a rigid body in which a desired number and shape of metal wiring portions 11b are arranged on the upper surface (front surface) of a ceramic insulating plate 11a.

[0016] The semiconductor element 12 is a chip according to the function of the semiconductor device 1. For example, if the semiconductor device 1 is a semiconductor power module, the semiconductor element 12 is a chip with a built-in IGBT 12a or a chip with a built-in diode 12b.

[0017] The lead frame 13 is a rigid copper body for carrying a large current, and has multiple terminals 13a protruding laterally to electrically connect to the upper surface of the metal wiring portion 11b of the insulating substrate 11, and a convex portion 13b protruding downward to electrically connect to the upper surface of the semiconductor element 12.

[0018] The first bonding material 14 is a solder alloy for bonding the upper surface of the semiconductor element 12 to the lower surface of the protruding portion 13b of the lead frame 13, and is, for example, Sn-Cu solder having a solidus temperature T1 of 227° C. Note that since the Sn-Cu solder is a relatively soft solder and has excellent stress relaxation properties, even if thermal stress occurs due to heat generation during use of the semiconductor device 1, the Sn-Cu solder on the upper surface of the semiconductor element 12 can absorb the thermal stress, and damage to the semiconductor element 12 caused by the thermal stress can be suppressed.

[0019] The second bonding material 15 is a solder alloy for bonding the lower surface of the semiconductor element 12 to the upper surface of the metal wiring portion 11b, and is, for example, a Sn-Cu-Sb solder having a solidus temperature T2 exceeding 227° C. and less than 240° C. As described above, the Sn-Cu-Sb solder has a characteristic of high thermal fatigue resistance, and therefore the semiconductor element 12 can be firmly bonded to the upper surface of the metal wiring portion 11b.

[0020] The third bonding material 16 is a solder alloy for bonding the lower surface of the terminal 13a of the lead frame 13 to the upper surface of the metal wiring portion 11b, and is, for example, a Sn-Cu-Sb solder having a solidus temperature T3 exceeding 227° C. and less than 240° C. The solidus temperature T3 may be any temperature as long as it is higher than the solidus temperature T1 and equal to or higher than the solidus temperature T2.

[0021] The heat dissipation material 17 is a metal plate equipped with heat dissipation fins 17a for dissipating heat generated during use of the semiconductor device 1. Although the heat dissipation material 17 equipped with the heat dissipation fins 17a is illustrated in Fig. 1, the heat dissipation fins 17a may be omitted.

[0022] The fourth bonding material 18 is a solder alloy for bonding the lower surface of the insulating substrate 11 and the upper surface of the heat dissipation material 17, and may be, for example, a Sn-Cu solder having a solidus temperature T4 of 227°C, or a Sn-Cu-Sb solder having a solidus temperature T4 of more than 227°C and less than 240°C, or a solder alloy containing Sn as its main component and having a solidus temperature of less than 232°C.

[0023] The sealing material 19 is a heat-resistant resin mold that seals the above-mentioned components.

[0024] <Manufacturing process of semiconductor device 1> Next, a manufacturing process for the main parts of the semiconductor device 1 will be described with reference to the perspective views (also a flow chart) of Figures 2A and 2B, and Figure 3, which is a schematic diagram showing the cross sections of both figures. Note that a well-known chip mounter may be used to arrange the components shown in the figures.

[0025] Step S1 is a procedure for placing insulating substrate 11 on a jig (not shown) with metal wiring portion 11b facing upward. The jig used here is a carbon plate processed to fit the shape of insulating substrate 11. Below, a procedure for placing components on the front side of the upper surface of insulating substrate 11 will be described on the assumption that placement of components on the rear side of the upper surface of insulating substrate 11 has been completed.

[0026] Step S2 is a procedure for placing a sheet-like second bonding material 15 on the upper surface of the metal wiring portion 11b (front side) of the insulating substrate 11. In this example, a relatively large rectangular second bonding material 15a and a relatively small rectangular second bonding material 15b are placed on the upper surface of the metal wiring portion 11b (front side).

[0027] Step S3 is a procedure for arranging the semiconductor element 12 on the upper surface of the second bonding material 15. In this example, a relatively large IGBT-built-in chip 12a is arranged on the upper surface of a relatively large second bonding material 15a, and a relatively small diode-built-in chip 12b is arranged on the upper surface of a relatively small second bonding material 15b.

[0028] Step S4 is a procedure for arranging a sheet-like first bonding material 14 on the upper surface of the semiconductor element 12. In this example, a relatively large first bonding material 14a is arranged on the upper surface of a relatively large IGBT-built-in chip 12a, and a relatively small second bonding material 15b is arranged on the upper surface of a relatively small diode-built-in chip 12b.

[0029] Step S5 is a procedure for placing a sheet-like third bonding material 16 on the upper surface of the metal wiring portion 11b. In this example, the third bonding material 16 is placed on each of the two metal wiring portions 11b on which the two terminals 13a of the lead frame 13 are to be placed.

[0030] Step S6 is a procedure for arranging the lead frame 13 so as to straddle the two third bonding materials 16. In this example, the two terminals 13a of the lead frame 13 are supported by the two third bonding materials 16a, thereby forming a gap between the protrusions 13b of the lead frame 13 and the first bonding material 14.

[0031] Next, step S7 will be described using Fig. 4, which follows the representation in Fig. 3. This step is a procedure in which the components stacked on the jig in steps S1 to S6 (hereinafter referred to as the "element mounting jig") are transferred into a heating furnace and heated, and each bonding material is melted and solidified in sequence to fix each component. If the lead frame 13 is light, a procedure may be added in which a weighting weight is placed on the lead frame 13 prior to heating in the heating furnace.

[0032] Step S7a: Immediately after the element mounting jig is placed into the heating furnace, during the period when the temperature of the element mounting jig is lower than the solidus temperature T1, the terminal 13a of the lead frame 13 is supported by the third bonding material 16, which is solid, and therefore a gap exists between the convex portion 13b and the first bonding material 14.

[0033] Step S7b: During the period when the temperature of the element mounting jig is higher than the solidus temperature T1 of the first bonding material 14 and lower than the solidus temperature T2 of the second bonding material 15, the first bonding material 14 melts and adheres to the upper surface of the semiconductor element 12. However, since there is still a gap above the first bonding material 14, the molten first bonding material 14 does not adhere to the convex portion 13b of the lead frame 13 at this point.

[0034] Step S7c: When the temperature of the element mounting jig becomes higher than the solidus temperature T3 of the third bonding material 16, the terminal 13a of the lead frame 13 loses support as the third bonding material 16 melts and moves downward. Then, the already melted first bonding material 14 comes into contact with the convex portion 13b. At this time, the melted first bonding material 14 is attracted to the convex portion 13b by the wetting force, and an upward force due to the wetting force of the first bonding material 14 also acts on the semiconductor element 12 below the first bonding material 14.

[0035] On the other hand, since the second bonding material 15, which has already melted, is attracted toward the insulating substrate 11 by its wetting force, a downward force caused by the wetting force of the second bonding material 15 also acts on the semiconductor element 12 above the second bonding material 15. Therefore, the upward force caused by the wetting force of the first bonding material 14 and the downward force caused by the wetting force of the second bonding material 15 cancel each other out, so that the semiconductor element 12 does not rise up more than necessary.

[0036] Step S7d: When the heating is stopped and the temperature of the element mounting jig becomes lower than the solidus temperature T1 of the first bonding material 14, each of the components of the semiconductor device 1 is fixed at a desired position.

[0037] As in step S7 above, by successively melting and solidifying the first bonding material 14 to the third bonding material 16, the amount of wetting of the first bonding material 14 to the third bonding material 16 can be appropriately controlled, and the upper surface of the semiconductor element 12 and the convex portion 13b of the lead frame 13, the lower surface of the semiconductor element 12 and the metal wiring portion 11b of the insulating substrate 11, and the terminal 13a of the lead frame 13 and the metal wiring portion 11b of the insulating substrate 11 can be suitably connected.

[0038] Needless to say, after step S7, the heat dissipation material 17 is attached using a fourth bonding material 18 by a well-known method, and the semiconductor element 12 and the like are resin-molded using a sealing material 19, thereby manufacturing the semiconductor device 1 having the structure illustrated in FIG. 1.

[0039] <Comparative Example> Here, to supplement the explanation of the effectiveness of step S7 in Fig. 4, a problem with step S7' in the manufacturing method of the semiconductor device 1' of the comparative example will be pointed out. The semiconductor device 1' of the comparative example is equivalent to the semiconductor device 1 of this embodiment, except that the first bonding material 14 and the third bonding material 16 are of the same quality and their solidus temperatures T13 are lower than the solidus temperature T2 of the second bonding material 15. In step S7' of the semiconductor device 1' of the comparative example, the following phenomenon occurs in the heating furnace.

[0040] Step S7a': Immediately after the element mounting jig is placed into the heating furnace, during the period when the temperature of the element mounting jig is lower than the solidus temperature T13 of the first bonding material 14 and the third bonding material 16, the terminal 13a of the lead frame 13 is supported by the solid third bonding material 16, and therefore a gap exists between the convex portion 13b and the first bonding material 14.

[0041] Step S7b': During the period when the temperature of the element mounting jig is higher than the solidus temperature T13 of the first bonding material 14 and the third bonding material 16 and lower than the solidus temperature T2 of the second bonding material 15, the first bonding material 14 melts and adheres to the upper surface of the semiconductor element 12, while the terminal 13a of the lead frame 13, which has lost support due to the melting of the third bonding material 16, moves downward.

[0042] Then, when the gap above the first bonding material 14 disappears and the upper surface of the molten first bonding material 14 comes into contact with the convex portion 13b of the lead frame 13, the molten first bonding material 14 is attracted toward the convex portion 13b due to its wetting force, and an upward force due to the wetting force of the first bonding material 14 also acts on the semiconductor element 12 below the first bonding material 14.

[0043] 4, the second bonding material 15 is still solid, so that the downward force caused by the wetting force of the second bonding material 15 does not act on the semiconductor element 12. Therefore, as shown in the figure, an undesirable phenomenon occurs in which the semiconductor element 12 is separated from the second bonding material 15, that is, chip lift. Furthermore, the chip lift also causes the following problems.

[0044] First, since the downward force caused by the wetting force of the second bonding material 15 does not act on the first bonding material 14, the molten first bonding material 14 rises to an area not intended by the design (for example, the side surface of the convex portion on the lower surface of the lead frame 13). As a result, the amount of first bonding material 14 remaining between the convex portion 13b of the lead frame 13 and the semiconductor element 12 decreases, and there is a risk of poor connection occurring between the convex portion 13b and the semiconductor element 12.

[0045] Secondly, when chip lift occurs, the weight of the semiconductor element 12 is also applied to the melted third bonding material 16 via the terminal 13a of the lead frame 13. As a result, the third bonding material 16 below the terminal 13a protrudes to an unintended extent in the design, and the amount of the third bonding material 16 remaining between the terminal 13a of the lead frame 13 and the insulating substrate 11 decreases, which may cause a connection failure between the terminal 13a and the insulating substrate 11.

[0046] Step S7c': When the temperature of the element mounting jig becomes higher than the solidus temperature T2 of the second bonding material 15, a downward force caused by the wetting force of the molten second bonding material 15 also acts on the semiconductor element 12. However, since the problem generated in step S7b' is irreversible, the downward force caused by the wetting force of the second bonding material 15 does not resolve the various problems described above.

[0047] Furthermore, if the height of the semiconductor element 12 becomes higher than the design height due to chip floating, there is a risk of poor connection between the semiconductor element 12 and the insulating substrate 11 due to a shortage of the second bonding material 15.

[0048] Step S7d': When the heating is stopped and the temperature of the element mounting jig becomes lower than the solidus temperature T13 of the first bonding material 14 and the third bonding material 16, each component of the semiconductor device 1' is fixed. That is, the various problems that occurred in steps S7b' and S7c' are also fixed.

[0049] According to the manufacturing method of the comparative example described above, chip floating and various problems resulting therefrom occur, but according to the manufacturing method of this embodiment, chip floating does not occur and problems resulting therefrom do not occur.

[0050] Furthermore, in the semiconductor device of this embodiment, a relatively soft Sn-Cu solder is placed on the upper surface of the semiconductor element, and an Sn-Cu-Sb solder with high thermal fatigue resistance is placed on the lower surface of the semiconductor element, thereby mitigating the effects of thermal stress generated on both the front and back surfaces of the semiconductor element during use of the semiconductor device. EXAMPLES

[0051] Second Embodiment Next, a semiconductor device 1 according to a second embodiment of the present invention will be described with reference to Figures 6 and 7. Note that a duplicated description of points common to the first embodiment will be omitted.

[0052] 4 of Example 1, there is no configuration for controlling the amount of wetting of first bonding material 14 when melted first bonding material 14 touches the lower surface of lead frame 13, so even if the order of melting of each bonding material can be appropriately controlled, there is a risk that melted first bonding material 14 will diffuse to an area not intended by the design. Therefore, in this example, a configuration for limiting the diffusion range of melted first bonding material 14 to the area intended by the design is added.

[0053] For example, as shown in Fig. 6, a wetting-up prevention material 13c made of a resin material or a resist material is applied to the side surface of the protruding portion 13b of the lead frame 13. Since this wetting-up prevention material 13c has a low affinity with the dissolved first bonding material 14, even if a chip lift occurs as shown in Fig. 5(b), the diffusion of the dissolved first bonding material 14 into the region where the wetting-up prevention material 13c is applied (i.e., a region where the first bonding material 14 is not designed to protrude) can be suppressed, and the diffusion range of the first bonding material 14 can be limited to the underside of the protruding portion 13b.

[0054] 7, a wetting prevention material 13c made of a resin material or a resist material may be applied to the outer periphery of the lower surface of the protrusion 13b of the lead frame 13. With this configuration, the same effect as that of FIG. [Explanation of symbols]

[0055] 1 Semiconductor device 11 Insulating substrate 11a Insulating plate 11b Metal wiring section 12 Semiconductor elements 13 Lead frame 13a Terminal 13b Convex part 13c Wetting prevention material 14 First bonding material 15 Second bonding material 16 Third bonding material 17 Heat dissipation material 18 Fourth bonding material 19 Encapsulating materials 20 Metal Wire

Claims

1. A semiconductor element; A lead frame; An insulating substrate; a first bonding material that bonds the semiconductor element and the lead frame; A second bonding material that bonds the semiconductor element and the insulating substrate; a third bonding material that bonds the insulating substrate and the lead frame; A semiconductor device having a solidus temperature of the first bonding material is lower than a solidus temperature of the second bonding material; A semiconductor device, characterized in that the solidus temperature of the third bonding material is higher than or equal to the solidus temperature of the second bonding material.

2. 2. The semiconductor device according to claim 1, The first bonding material is a Sn—Cu based solder containing Sn and Cu, The semiconductor device is characterized in that the second bonding material is a Sn-Cu-Sb based solder containing Sn, Cu and Sb.

3. 2. The semiconductor device according to claim 1, the lead frame has terminals protruding laterally and a protrusion protruding downward; the protrusion is bonded to an upper surface of the semiconductor element via the first bonding material, The semiconductor device is characterized in that the terminal is joined to a metal wiring portion of the insulating substrate via the third bonding material.

4. 4. The semiconductor device according to claim 3, A semiconductor device, characterized in that a resin material or a resist material is applied to the side surface of the protrusion.

5. 4. The semiconductor device according to claim 3, The semiconductor device is characterized in that a resin material or a resist material is applied to the outer periphery of the lower surface of the convex portion.

6. A method for manufacturing a semiconductor device, comprising the steps of: heating a semiconductor element, a lead frame, an insulating substrate, a first bonding material bonding the semiconductor element and the lead frame, a second bonding material bonding the semiconductor element and the insulating substrate, and a third bonding material bonding the insulating substrate and the lead frame in a heating furnace, the method comprising the steps of: placing an insulating substrate on a jig; disposing a second bonding material on the metal wiring portion of the insulating substrate; placing the semiconductor element on the second bonding material; disposing the first bonding material on the semiconductor element; disposing a plurality of the third bonding materials on the metal wiring portion; disposing the lead frame across a plurality of the third bonding materials to provide a gap between the lead frame and the first bonding material; melting the first bonding material and bonding it to a top surface of the semiconductor element; dissolving the second bonding material to bond the lower surface of the semiconductor element and the metal wiring portion; melting the third bonding material to bond the lead frame and the metal wiring portion, and bonding an upper surface of the semiconductor element and the lead frame via the melted first bonding material; 1. A method for manufacturing a semiconductor device comprising the steps of:

Images