Semiconductor device

Abstract

To provide a high-reliability semiconductor device which seals a power semiconductor chip-loaded insulation circuit board with a high heat-resistance epoxide resin, and which can inhibit separation between the high heat-resistance epoxide resin and wiring of the insulation circuit board.SOLUTION: A semiconductor device comprises: a power semiconductor chip; an insulation circuit board that is loaded with the power semiconductor chip; and a sealing resin for sealing at least a joint between the power semiconductor chip and the power semiconductor chip of the insulation circuit board. The insulation circuit board has a ceramic board and a surface wiring layer that is formed on a surface of the ceramic board. The surface wiring layer has a first roughened layer on a surface on the opposite side of a surface joined to the ceramic board.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a structure of a semiconductor device, and more particularly to a power module in which an insulating circuit board on which a power semiconductor chip is mounted is sealed with a high heat-resistant epoxy resin, and a method for manufacturing the same. [Background technology]

[0002] A potting technology has been developed as a method for insulating and sealing power modules, which does not require a mold and allows sealing with high heat-resistant epoxy resin. High heat-resistant epoxy resin has an elastic modulus of over 100 GPa at room temperature, and by mechanically binding it, it is possible to reduce thermal stress caused by the difference in linear expansion coefficients of the circuit formation parts formed on the semiconductor chip and insulating substrate, and it is expected to extend the life of the power cycle.

[0003] Background art in this technical field includes, for example, technology such as Patent Document 1. Patent Document 1 discloses "a power module including a semiconductor element arranged on a substrate, a plate-shaped electrode plate having two or more connection parts for connecting the semiconductor elements to each other, the semiconductor element and an external terminal, or the substrate and the external terminal, a resin molding part having a convex shape and a slope on the substrate surface side between adjacent connection parts of the electrode plate, and a sealing resin part for sealing the periphery of the connection part." [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-197842 A Summary of the Invention [Problem to be solved by the invention]

[0005] The insulating substrates of the insulating circuit boards used in the power modules for power devices are made of ceramics such as alumina (aluminum oxide: Al2O3), silicon nitride (Si3N4), and aluminum nitride (AlN), while copper (Cu) or aluminum (Al) is used for the wiring.

[0006] Traditionally, silver solder has been used to connect the ceramic substrate and wiring of an insulated circuit board, but recently, DCB substrates (Direct Bonded Copper), which bond copper material directly to the ceramic substrate, and AMB substrates (Active Metal Braze), which use active metals such as titanium (Ti) to bond the copper to the insulator, have been developed, which are lower cost and have high temperature cycle reliability.

[0007] The linear expansion coefficient of ceramics is 7.2 x 10 for alumina. -6 / K, silicon nitride is 2.8×10 -6 / K, aluminum nitride is 4.6×10 -6 / K. On the other hand, the linear expansion coefficient of copper is 16.5×10 -6 / K, the linear expansion coefficient of aluminum is 23.9 x 10 -6 / K.

[0008] The linear expansion coefficient of high heat resistant epoxy resin encapsulation varies depending on the resin material or the amount of filler added, but is generally in the range of 10 to 20 x 10 -6 / K. Due to the difference in the linear expansion coefficient of the ceramic and high heat resistant epoxy resin sealing, thermal stress occurs between the high heat resistant epoxy resin and the wiring. This thermal stress may cause peeling between the high heat resistant epoxy resin and the wiring. When peeling occurs, the mechanical restraint force of the high heat resistant epoxy resin decreases, increasing thermal stress and reducing the power cycle.

[0009] Incidentally, silicon nitride (Si3N4) is used for the insulating substrates of power modules for power devices with a voltage rating of 750V and 1200V, which are used in inverters for electric vehicles (EVs). This is because silicon nitride has a lower thermal conductivity than alumina (Al2O3), and because its high flexural strength allows the substrate thickness to be made thinner, thereby lowering thermal resistance.

[0010] On the other hand, silicon nitride (Si3N4) has a small linear expansion coefficient among ceramics, and the thermal stress between the high heat resistant epoxy resin and the wiring is large.

[0011] In the above Patent Document 1, the thermal stress between the highly heat-resistant epoxy resin and the wiring of the insulating circuit board is not taken into consideration, and there is room for improvement.

[0012] Therefore, an object of the present invention is to provide a highly reliable semiconductor device in which an insulating circuit board on which a power semiconductor chip is mounted is sealed with a high heat-resistant epoxy resin, and which is capable of suppressing peeling between the high heat-resistant epoxy resin and the wiring of the insulating circuit board. [Means for solving the problem]

[0013] In order to solve the above problems, the present invention provides a semiconductor device comprising: a power semiconductor chip; an insulating circuit board on which the power semiconductor chip is mounted; and a sealing resin that seals at least a joint between the power semiconductor chip and the power semiconductor chip of the insulating circuit board, the insulating circuit board having a ceramic substrate and a surface wiring layer formed on a surface of the ceramic substrate, the surface wiring layer having a first roughened layer on a surface opposite to a joint surface with the ceramic substrate. Effect of the Invention

[0014] According to the present invention, in a semiconductor device in which an insulating circuit board on which a power semiconductor chip is mounted is sealed with a high heat-resistant epoxy resin, it is possible to realize a highly reliable semiconductor device in which peeling between the high heat-resistant epoxy resin and the wiring of the insulating circuit board can be suppressed.

[0015] This makes it possible to extend the power cycle life of the power module.

[0016] Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is an external perspective view of a power module according to a first embodiment of the present invention. [Diagram 2] 2A and 2B are diagrams showing the rear and side surfaces of the power module in FIG. [Diagram 3] 2 is a top view showing a state where high heat-resistant epoxy resin 3 of the power module of FIG. 1 has been removed. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA′ of FIG. [Diagram 5] 5 is a diagram showing a state in which a part of FIG. 4 is sealed with a high heat-resistant epoxy resin 3. FIG. [Figure 6A] 6A to 6C are diagrams illustrating a part of a manufacturing process for a power module according to Example 2 of the present invention. [Figure 6B] FIG. 6B is a diagram showing a manufacturing process subsequent to FIG. 6A. [Figure 7A] FIG. 11 is a partial cross-sectional view of a power module according to a third embodiment of the present invention. [Figure 7B] 7B is a view (plan view) of roughened layer 30 in FIG. 7A taken along the line BB'. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted. EXAMPLES

[0019] First Embodiment A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

[0020] Fig. 1 is an external perspective view of a power module 100 of this embodiment. Fig. 2 is a diagram showing the back and side of the power module 100 of Fig. 1. Fig. 3 is a top view showing a state in which the high heat resistant epoxy resin 3 of the power module 100 of Fig. 1 has been removed. Fig. 4 is a cross-sectional view of the A-A' portion of Fig. 3. Fig. 5 is a diagram showing a state in which a part of Fig. 4 has been sealed with the high heat resistant epoxy resin 3.

[0021] 1, in the power module 100 of this embodiment, a case 2 is bonded to a metal base 1 with an adhesive. The case 2 is filled with a high heat-resistant epoxy resin 3 by potting.

[0022] 2, the power module 100 of this embodiment has a plurality of fins 4 provided on the metal base 1. The fins 4 are provided on the back side of the metal base 1, i.e., on the surface opposite to the front side on which the power semiconductor chips are mounted. By mounting a water-cooling device such as a water jacket or an air-cooling device on the back side of the metal base 1, heat generated from the power semiconductor chips due to the operation of the power module 100 is dissipated via the fins 4.

[0023] 3, this embodiment uses an IGBT (Insulated Gate Bipolar Transistor) and a diode connected in parallel to the IGBT as a power device. This embodiment is a 6-in-1 type power module in which a total of six arms, including the U, V, and W phases and the upper and lower arms, are mounted on one power module 100.

[0024] An insulating circuit board 10 is provided on a metal base 1. An IGBT 11 and a diode 12 are provided on the insulating circuit board 10, and the IGBT 11 and the diode 12 are connected by a lead frame 13.

[0025] As shown in Fig. 4, an insulating circuit board 10 is provided on the metal base 1 to which the fins 4 are connected. The insulating circuit board 10 is composed of a ceramic substrate 14, a back surface wiring layer 21, and a front surface wiring layer 22. The insulating circuit board 10 is connected to the metal base 1 by solder 20 provided between the back surface wiring layer 21 and the metal base 1. The back surfaces of the IGBT 11 and the diode 12 are connected to the front surface wiring layer 22 and solder 23, respectively.

[0026] As a result, the heat generated from the IGBT 11 and the diode 12 is transferred through the solder 23, the surface wiring layer 22, the ceramic substrate 14, the back wiring layer 21, the solder 20, the metal base 1, and the fins 4 to a cooling medium such as cooling water or air (not shown in this figure), thereby cooling the IGBT 11 and the diode 12.

[0027] The IGBT 11 and the diode 12 are insulated from the metal base 1 by a ceramic substrate 14. The surfaces of the IGBT 11 and the diode 12 are connected to a lead frame 13 via solder 24.

[0028] 5, in the power module 100 of this embodiment, a roughened layer 30 is provided on the surface of the surface wiring layer 22. By providing the roughened layer 30, the anchor effect can improve the mechanical binding force between the high heat-resistant epoxy resin 3 and the surface wiring layer 22, and peeling due to thermal stress can be prevented.

[0029] The roughened layer 30 on the surface of the surface wiring layer 22 is formed, for example, by etching the surface of the surface wiring layer 22. Alternatively, when the surface wiring layer 22 is made of copper (Cu), a roughened nickel plating layer may be formed on the surface wiring layer 22 as the roughened layer 30.

[0030] As described above, the power module 100 of this embodiment includes power semiconductor chips (IGBT 11, diode 12), an insulating circuit board 10 on which the power semiconductor chips are mounted, and a sealing resin (high heat resistant epoxy resin 3) that seals at least the joint between the power semiconductor chips and the power semiconductor chip of the insulating circuit board 10, and the insulating circuit board 10 has a ceramic substrate 14 and a surface wiring layer 22 formed on the surface of the ceramic substrate 14, and the surface wiring layer 22 has a roughened layer 30 on the surface opposite to the joint surface with the ceramic substrate 14.

[0031] The roughened layer 30 is formed on the surface of the surface wiring layer 22 that comes into contact with the sealing resin (high heat-resistant epoxy resin 3).

[0032] The ceramic substrate 14 is, for example, a silicon nitride ceramic substrate.

[0033] By providing the roughened layer 30, the high heat-resistant epoxy resin 3 penetrates into the gaps between the projections and recesses of the roughened layer 30 during potting and solidifies there, thereby improving the mechanical binding force through an anchor effect (also called mechanical bonding, anchoring effect, or fastener effect) in which the barbs of the hooks dig in, thereby preventing peeling due to thermal stress. EXAMPLES

[0034] Second Embodiment A semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to FIGS. 6A and 6B.

[0035] Fig. 6A is a diagram showing a part of the manufacturing process of the power module 100 of this embodiment. Fig. 6B is a diagram showing the manufacturing process subsequent to Fig. 6A.

[0036] In forming the insulating circuit board 10, as shown in FIG. 6A, the back wiring layer 21 and the front wiring layer 22 are bonded to the ceramic substrate 14, and then each wiring layer is passed through an etching solution to form a roughened layer 30 on the surfaces of both the back wiring layer 21 and the front wiring layer 22, as shown in FIG. 6B.

[0037] When the roughened layer 30 is formed only on the front surface wiring layer 22, it is necessary to mask the back surface wiring layer 21. However, in this embodiment, no mask is necessary, and the number of steps is reduced, allowing for low-cost production.

[0038] The roughened layer 30 does not affect soldering, and the bonding strength between the back surface wiring layer 21 and the metal base 1 by the solder 20 is the same as when the roughened layer 30 is not present.

[0039] Furthermore, when the back surface wiring layer 21 and the front surface wiring layer 22 are made of copper (Cu), the roughened layer 30 can be formed by subjecting the surfaces to roughened nickel plating.

[0040] As described above, in the power module 100 of this embodiment, the insulating circuit board 10 has a back surface wiring layer 21 formed on the back surface of the ceramic substrate 14, and the back surface wiring layer 21 has a roughened layer 30 on the surface opposite to the bonding surface with the ceramic substrate 14. EXAMPLES

[0041] Third Embodiment A semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 7A and 7B.

[0042] Fig. 7A is a partial cross-sectional view of power module 100 of this embodiment, and corresponds to Fig. 5 of Example 1. Fig. 7B is a view (plan view) of roughened layer 30 in the direction of arrows BB' in Fig. 7A.

[0043] In Example 1 (Figure 5), an example was described in which a roughened layer 30 was provided on the entire surface of the surface wiring layer 22, including the bonding surface with the IGBT 11. However, in this example (Figures 7A and 7B), the roughened layer 30 is not provided on the bonding surface of the surface wiring layer 22 with the IGBT 11, but is provided only on the contact surface with the high heat-resistant epoxy resin 3 on the surface of the surface wiring layer 22, which is different from Example 1 (Figure 5).

[0044] As in the present embodiment, by providing a roughened layer 30 in areas other than the joint between the surface wiring layer 22 and the IGBT 11, the anchor effect can be used to mechanically improve the binding force between the high heat-resistant epoxy resin 3 and the surface wiring layer 22, as in the first embodiment, and peeling due to thermal stress can be prevented.

[0045] In addition to power semiconductor chips using silicon substrates, the present invention can also be applied to power modules using power semiconductor chips such as silicon carbide (SiC) and gallium nitride (GaN).

[0046] Furthermore, the present invention is not limited to the above-mentioned embodiment, and various modifications are included. For example, the above-mentioned embodiment has been described in detail to clearly explain the present invention, and is not necessarily limited to those having all of the configurations described. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. [Explanation of symbols]

[0047] 1: metal base, 2: case, 3: high heat resistant epoxy resin, 4: fin, 10: insulating circuit board, 11: IGBT, 12: diode, 13: lead frame, 14: ceramic substrate, 20 solder, 21: back surface wiring layer, 22: front surface wiring layer, 23: solder, 24: solder, 30: roughened layer, 100: power module.

Claims

1. A power semiconductor chip; an insulating circuit board on which the power semiconductor chip is mounted; a sealing resin that seals at least a joint between the power semiconductor chip and the insulating circuit board, The insulating circuit board has a ceramic substrate and a surface wiring layer formed on a surface of the ceramic substrate, The semiconductor device according to claim 1, wherein the surface wiring layer has a first roughened layer on a surface opposite to a surface to be bonded to the ceramic substrate.

2. 2. The semiconductor device according to claim 1, The semiconductor device according to claim 1, wherein the first roughened layer is formed on a contact surface of the surface wiring layer with the sealing resin.

3. 2. The semiconductor device according to claim 1, the insulating circuit board has a back surface wiring layer formed on a back surface of the ceramic substrate, The semiconductor device according to claim 1, wherein the back wiring layer has a second roughened layer on a surface opposite to a surface bonded to the ceramic substrate.

4. 4. The semiconductor device according to claim 1, The semiconductor device is characterized in that the sealing resin is a highly heat-resistant epoxy resin.

5. 4. The semiconductor device according to claim 1, The semiconductor device is characterized in that the ceramic substrate is a silicon nitride ceramic substrate.

6. 4. The semiconductor device according to claim 1, The semiconductor device according to claim 1, wherein the first roughened layer is formed by etching the surface of the surface wiring layer.

7. 4. The semiconductor device according to claim 3, The semiconductor device according to claim 1, wherein the second roughened layer is formed by etching the surface of the back wiring layer.

8. 4. The semiconductor device according to claim 1, The surface wiring layer is formed of copper, The semiconductor device according to claim 1, wherein the first roughened layer is a roughened nickel plating layer formed on the surface wiring layer.

9. 4. The semiconductor device according to claim 3, The back wiring layer is formed of copper, The semiconductor device according to claim 1, wherein the second roughened layer is a roughened nickel plating layer formed on the back surface wiring layer.

10. 2. The semiconductor device according to claim 1, The semiconductor device according to claim 1, wherein the first roughened layer is formed in an area of ​​the surface wiring layer other than a bonding portion with the power semiconductor chip.

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