Switching element and manufacturing method thereof

Abstract

To suppress interdiffusion between a silicide layer and an electrode layer.SOLUTION: A switching element includes a semiconductor substrate having a trench on its upper surface, a gate electrode disposed in the trench, an interlayer insulating film covering an upper surface of the gate electrode, a sidewall insulating film extending upward from the interlayer insulating film along a side surface of the trench, a silicide layer covering the upper surface of the semiconductor substrate and in contact with the sidewall insulating film, a barrier metal layer covering an area spanning a surface of the silicide layer, a surface of the sidewall insulating film and a surface of the interlayer insulating film, and an electrode layer covering the surface of the barrier metal layer on top of the silicide layer, the sidewall insulating film and the interlayer insulating film.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a switching element and a manufacturing method thereof.

[0002] The switching element disclosed in Patent Document 1 has a semiconductor substrate with a trench provided on its upper surface. A gate electrode is provided in the trench. The upper surface of the gate electrode is covered with an interlayer insulating film. A silicide layer, a barrier metal layer, and an electrode layer are provided on the upper part of the semiconductor substrate as electrodes. The silicide layer covers the upper surface of the semiconductor substrate. The barrier metal layer covers an area spanning the surface of the silicide layer and the surface of the interlayer insulating film. The electrode layer covers the surface of the barrier metal layer on the silicide layer and the upper part of the interlayer insulating film. The barrier metal layer suppresses interdiffusion of materials between the silicide layer and the electrode layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-163580 A Summary of the Invention [Problem to be solved by the invention]

[0004] Since the surface of the silicide layer is located above the surface of the interlayer insulating film, a step exists between the surface of the silicide layer and the surface of the interlayer insulating film. Therefore, when a barrier metal layer is formed in an area spanning the surface of the silicide layer and the surface of the interlayer insulating film, a step also forms on the surface of the barrier metal layer. In this case, the barrier metal layer may not grow properly at the step, and a slit may form on the surface of the barrier metal layer. As a result, interdiffusion occurs between the silicide layer and the electrode layer through the slit in the barrier metal layer, causing the electrode to deteriorate. This specification proposes a technology for suppressing interdiffusion between the silicide layer and the electrode layer. [Means for solving the problem]

[0005] The switching element disclosed in this specification has a semiconductor substrate, a gate insulating film, a gate electrode, an interlayer insulating film, a sidewall insulating film, a silicide layer, a barrier metal layer, and an electrode layer. A trench is provided on the upper surface of the semiconductor substrate. The gate insulating film is disposed in the trench. The gate electrode is disposed in the trench and is insulated from the semiconductor substrate by the gate insulating film. The interlayer insulating film is disposed in the trench and covers the upper surface of the gate electrode. The sidewall insulating film extends upward from the interlayer insulating film along the side surface of the trench and covers the side surface of the trench above the interlayer insulating film. The silicide layer covers the upper surface of the semiconductor substrate and is in contact with the sidewall insulating film. The barrier metal layer covers an area spanning the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film. A step exists on the surface of the barrier metal layer along a step formed by the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film. The electrode layer covers the surface of the barrier metal layer on the silicide layer, the sidewall insulating film, and the interlayer insulating film.

[0006] In this switching element, the side surface of the trench is covered with a sidewall insulating film above the interlayer insulating film. Therefore, the barrier metal layer is formed so as to cover an area spanning the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film. Therefore, a step is formed on the surface of the barrier metal layer along the step formed by the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film. Since the side insulating layer is present below the step in the barrier metal layer, interdiffusion between the silicide layer and the electrode layer can be suppressed even if a slit is formed in the step portion of the barrier metal layer.

[0007] This specification also discloses a method for manufacturing a switching element. The manufacturing method disclosed in this specification includes a semiconductor wafer preparation step, a silicide layer formation step, an etching step, a barrier metal layer formation step, and an electrode layer formation step. In the semiconductor wafer preparation step, a semiconductor wafer is prepared that includes a semiconductor substrate containing silicon and having a trench on its upper surface, a gate insulating film disposed in the trench, a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film, and an insulating layer disposed in the trench and covering the upper surface of the gate electrode. In the silicide layer formation step, a silicide layer made of silicide is formed on the upper surface of the semiconductor substrate by reacting a metal with the semiconductor substrate. In the silicide layer formation step, the silicide layer is formed so that an end of the silicide layer becomes an overhanging portion that extends above the insulating layer. In the etching step, the thickness of the insulating layer is reduced by etching the surface of the insulating layer. In the etching step, the insulating layer is etched so that an interlayer insulating film is formed by the insulating layer remaining along the upper surface of the gate electrode, and a sidewall insulating film extending upward from the interlayer insulating film along the side surface of the trench and covering the side surface of the trench above the interlayer insulating film is formed by the insulating layer remaining under the overhanging portion. In the barrier metal layer forming step, a barrier metal layer is formed to cover an area spanning the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film. In the electrode layer forming step, an electrode layer is formed to cover the surface of the barrier metal layer above the silicide layer, the sidewall insulating film, and the interlayer insulating film.

[0008] In this manufacturing method, in the barrier metal layer formation step, the barrier metal layer is formed so as to cover an area spanning the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film. Since the side insulating layer is present under the step of the barrier metal layer, even if a slit is formed in the step of the barrier metal layer, interdiffusion between the silicide layer and the electrode layer can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a cross-sectional view of a switching element according to an embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view of area X in FIG. 1 . [Diagram 3] FIG. [Figure 4] FIG. [Diagram 5] FIG. [Figure 6] FIG. [Figure 7] FIG. [Figure 8] FIG. [Figure 9] FIG. [Figure 10] FIG. [Figure 11] FIG. 4 is a cross-sectional view of a switching element of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In one example switching element disclosed in this specification, the step of the barrier metal layer may be located closer to the center of the trench than the step formed by the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film.

[0011] In the switching element disclosed in the present specification as an example, at a connection portion between the silicide layer and the sidewall insulating film, the surface of the silicide layer and the surface of the sidewall insulating film may be connected by a smooth curved surface.

[0012] This configuration can suppress the occurrence of slits in the barrier metal layer.

[0013] In the example manufacturing method disclosed in the present specification, the step of etching the insulating layer may include etching the insulating layer by sputter etching, and the step of forming the barrier metal layer may include forming the barrier metal layer by sputtering. Also, the step of etching the insulating layer and the step of forming the barrier metal layer may be performed in a common chamber.

[0014] This configuration allows the switching element to be manufactured more efficiently.

[0015] 1 is a so-called metal-oxide-semiconductor field effect transistor (MOSFET). The switching element 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of single crystal silicon carbide. The semiconductor substrate 12 may be made of another semiconductor material containing silicon (for example, single crystal silicon). A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. A gate insulating film 16, a gate electrode 18, and an interlayer insulating film 20 are arranged inside each trench 14. The gate insulating film 16 covers the inner surface of the trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The interlayer insulating film 20 covers the upper surface of the gate electrode 18. The upper surface of the interlayer insulating film 20 is located lower than the upper surface 12a of the semiconductor substrate 12. That is, the entire interlayer insulating film 20 is arranged in the trench 14. An upper electrode 30 is provided on the upper portion of the semiconductor substrate 12. The upper electrode 30 covers the upper surface 12a of the semiconductor substrate 12 and the upper surface of the interlayer insulating film 20. The upper electrode 30 is insulated from the gate electrode 18 by the interlayer insulating film 20. A lower electrode 40 is provided on the lower portion of the semiconductor substrate 12. The lower electrode 40 covers the lower surface 12 b of the semiconductor substrate 12 .

[0016] A source layer 50, a body layer 52, a drift layer 54, and a drain layer 56 are provided inside the semiconductor substrate 12. The source layer 50 is an n-type layer having a high n-type impurity concentration. The source layer 50 is disposed in a range including the upper surface 12a of the semiconductor substrate 12, and is in ohmic contact with the upper electrode 30. The source layer 50 is in contact with the gate insulating film 16 at the upper end of the side surface of the trench 14. The body layer 52 is a p-type layer having a low p-type impurity concentration. The body layer 52 is in contact with the source layer 50 from below. The body layer 52 is in contact with the gate insulating film 16 at the side surface of the trench 14 below the source layer 50. The body layer 52 is electrically connected to the upper electrode 30 via a p-type layer (for example, a p-type contact layer having a higher p-type impurity concentration than the body layer 52) provided at a position not shown. The drift layer 54 is an n-type layer having a lower n-type impurity concentration than the source layer 50. The drift layer 54 is in contact with the body layer 52 from below. The drift layer 54 is in contact with the gate insulating film 16 on the side surface of the trench 14 below the body layer 52 and on the bottom surface of the trench 14. The drain layer 56 is an n-type layer having a higher n-type impurity concentration than the drift layer 54. The drain layer 56 is in contact with the drift layer 54 from below. The drain layer 56 is disposed in an area including the lower surface 12b of the semiconductor substrate 12, and is in ohmic contact with the lower electrode 40.

[0017] 2 shows an enlarged cross-sectional view of the periphery of the source layer 50 (i.e., range X in FIG. 1). As shown in FIG. 2, a sidewall insulating film 22 is provided at the upper end of the side surface of the trench 14. The sidewall insulating film 22 is connected to the interlayer insulating film 20. The sidewall insulating film 22 extends upward from the interlayer insulating film 20 along the side surface of the trench 14, and covers the side surface of the trench 14 above the interlayer insulating film 20.

[0018] As shown in FIG. 2, the upper electrode 30 includes a silicide layer 32, a barrier metal layer , and an electrode layer .

[0019] The silicide layer 32 is made of nickel silicide. However, the silicide layer 32 may be made of a silicide other than nickel silicide. The silicide layer 32 covers the upper surface 12a of the semiconductor substrate 12. The silicide layer 32 is not provided on the surface of the interlayer insulating film 20. The upper surface 12a of the semiconductor substrate 12 is slightly curved in a direction that is convex upward between the two trenches 14. The silicide layer 32 is curved along the upper surface 12a. Both end faces (i.e., both side faces) of the silicide layer 32 are in contact with the upper end faces of the sidewall insulating film 22. A step S1 is formed by the surface (i.e., the upper surface) of the silicide layer 32, the surface (i.e., the side surface) of the sidewall insulating film 22, and the surface (i.e., the upper surface) of the interlayer insulating film 20. In the step S1, the surface of the silicide layer 32 and the surface of the sidewall insulating film 22 are connected by a smoothly curved surface. The thickness of the sidewall insulating film 22 is thinner than the thickness of the gate insulating film 16. The silicide layer 32 is in ohmic contact with the source layer 50.

[0020] The barrier metal layer 34 is made of Ti, TiN, a titanium alloy, or the like. The barrier metal layer 34 may be made of a plurality of metal layers. The barrier metal layer 34 is distributed in a range spanning a plurality of trenches 14. The barrier metal layer 34 covers a range spanning the surface of the silicide layer 32, the surface of the sidewall insulating film 22, and the surface of the interlayer insulating film 20. That is, the barrier metal layer 34 covers the step S1. A step S2 is provided on the surface (i.e., the upper surface) of the barrier metal layer 34 along the step S1. The step S2 is located closer to the center of the trench 14 than the step S1.

[0021] The electrode layer 36 is made of a metal such as aluminum. The electrode layer 36 is distributed over a range spanning the multiple trenches 14, and covers the upper surface of the barrier metal layer 34. That is, the electrode layer 36 covers the upper surface of the barrier metal layer 34 above the silicide layer 32, the sidewall insulating film 22, and the interlayer insulating film 20. The electrode layer 36 is separated from the silicide layer 32 by the barrier metal layer 34. The barrier metal layer 34 suppresses interdiffusion of materials between the electrode layer 36 and the silicide layer 32.

[0022] Next, a description will be given of a method for manufacturing the switching element 10. First, a semiconductor substrate 12 having a source layer 50, a body layer 52, a drift layer 54, and a drain layer 56 (that is, a semiconductor substrate 12 before electrode processing) is prepared.

[0023] First, as shown in FIG. 3, a plurality of trenches 14 are formed on the upper surface 12a of the semiconductor substrate 12 by selectively etching the upper surface 12a. Since the pitch of the trenches 14 is narrow, the upper surface 12a between the trenches 14 has an upwardly convex curved shape. Next, a gate insulating film 16 is formed on the inner surface of the trench 14 by thermal oxidation or CVD. At this time, the gate insulating film 16 is also formed on the upper surface 12a of the semiconductor substrate 12. Next, a gate electrode 18 is formed in the trench 14. Hereinafter, the semiconductor substrate 12, the electrodes, the insulating layer, etc. are collectively referred to as a semiconductor wafer.

[0024] Next, as shown in FIG. 4, an insulating layer 24 is grown over the entire upper surface of the semiconductor wafer. Next, as shown in FIG. 5, the insulating layer is etched back. In FIG. 5, the insulating layer 24 on the upper part of the gate electrode 18 and the gate insulating film 16 are integrated and shown as an insulating layer 26. Here, the upper surface 12a is exposed from the insulating layer 26, and the insulating layer 26 is left in the trench 14 (i.e., above the gate electrode 18). Since the insulating layer 26 on the upper surface 12a is completely removed, the upper surface 12a protrudes above the remaining insulating layer 26.

[0025] 6, nickel layer 33 is formed over the entire upper surface of the semiconductor wafer. That is, nickel layer 33 is formed so as to cover upper surface 12a of semiconductor substrate 12 and the upper surface of insulating layer .

[0026] Next, the semiconductor wafer is heated to 700° C. or higher in a nitrogen atmosphere, thereby reacting the semiconductor substrate 12 with the nickel layer 33 at their interface. This forms a silicide layer 32 (i.e., a nickel silicide layer) covering the upper surface 12a, as shown in FIG. 7. The silicide layer 32 makes ohmic contact with the semiconductor substrate 12. Since the upper surface 12a is curved so as to be convex upward, the silicide layer 32 grows laterally at its end. Therefore, the end of the silicide layer 32 becomes an overhanging portion 32a that extends above the insulating layer 26. The overhanging portion 32a contacts the insulating layer 26 below it.

[0027] 8, the nickel layer 33 is removed by etching, thereby exposing the silicide layer 32 and the insulating layer 26.

[0028] The semiconductor wafer is then placed in a chamber of a sputtering apparatus, and a sputter etching step and a sputtering step are sequentially performed in the common chamber.

[0029] (Sputter etching process) In the sputter etching process, as shown in FIG. 9, the silicide layer 32 and the insulating layer 26 are sputter-etched from above. This reduces the thickness of the silicide layer 32 and the insulating layer 26. Since the upper surface of the insulating layer 26 is etched, the upper surface of the insulating layer 26 is shifted downward with respect to the upper surface 12a of the semiconductor substrate 12. However, since the insulating layer 26 is not etched below the overhanging portion 32a of the silicide layer 32, the insulating layer 26 remains along the side surface of the trench 14. The insulating layer 26 remaining along the side surface of the trench 14 becomes the sidewall insulating film 22. Moreover, the insulating layer 26 remaining along the upper surface of the gate electrode 18 becomes the interlayer insulating film 20. The upper end surface of the sidewall insulating film 22 is in contact with the side surface of the silicide layer 32. Moreover, a step S1 is formed by the surface of the silicide layer 32, the surface of the sidewall insulating film 22, and the surface of the interlayer insulating film 20. When the sidewall insulating film 22 is formed by sputter etching as described above, the surfaces of the silicide layer 32 and the sidewall insulating film 22 at the boundary between the silicide layer 32 and the sidewall insulating film 22 have a smoothly curved shape.

[0030] (Sputtering process) In the sputtering process, as shown in Fig. 10, a barrier metal layer 34 is formed by sputtering. That is, a barrier metal material is deposited from above on the entire surfaces of the silicide layer 32 and the interlayer insulating film 20 to form the barrier metal layer 34 in contact with the silicide layer 32, the sidewall insulating film 22, and the interlayer insulating film 20. Since a step S1 exists in the lower part of the barrier metal layer 34, a step S2 extending along the step S1 is formed on the surface of the barrier metal layer 34. Since the barrier metal layer 34 covers the step S1, the step S2 is formed at a position closer to the center of the trench 14 than the step S1.

[0031] In this way, by performing the sputter etching process and the sputtering process in the same chamber, throughput is improved.

[0032] Next, as shown in Fig. 2, an electrode layer 36 is formed on the entire surface of the barrier metal layer 34 by sputtering or the like, thereby completing the upper electrode 30. Thereafter, a lower electrode 40 is formed, thereby completing the switching element 10 shown in Fig. 1.

[0033] Next, the slits formed on the surface of the barrier metal layer 34 will be described by comparing the comparative example and the embodiment. FIG. 11 shows a switching element of the comparative example. The barrier metal layer 34 of the comparative example is formed on the semiconductor wafer in the state of FIG. 8 without performing the sputter etching process. Therefore, the shapes of the insulating layer 26 and the silicide layer 32 are the same in FIG. 11 and FIG. 8. As shown in FIG. 11, a step S3 is formed on the base of the barrier metal layer 34 (i.e., the surface of the silicide layer 32 and the insulating layer 26) by the overhang portion 32a. Therefore, when the barrier metal layer 34 is formed, a step S4 is formed on the surface of the barrier metal layer 34. In addition, since the barrier metal layer 34 is difficult to grow at the step S3, a slit 90 is formed on the surface of the barrier metal layer 34 (particularly at the position of the step S4). In the comparative example, since the overhang portion 32a protrudes laterally, the barrier metal layer 34 is particularly difficult to grow at the step S3, and the slit 90 is easily formed. The slit 90 extends in the depth direction from the step S4 toward the lower end of the step S3 (i.e., the boundary between the silicide layer 32 and the insulating layer 26). Therefore, the lower end of the slit 90 is located near the silicide layer 32. When the electrode layer 36 is formed on the barrier metal layer 34 in which the slit 90 exists as shown in FIG. 11, interdiffusion occurs between the silicide layer 32 and the electrode layer 36 through the slit 90. For example, nickel diffuses from the silicide layer 32 to the electrode layer 36. In this case, when alkaline etching is performed for plating the electrode layer 36, a galvanic corrosion effect occurs in the electrode layer 36, causing the electrode layer 36 to be damaged.

[0034] In the manufacturing method of the embodiment, as shown in FIG. 10, a slit 90 may be formed on the surface of the barrier metal layer 34 (particularly at the position of the step S2). In that case, the slit 90 extends in the depth direction from the step S2 toward the lower end of the step S1. In the embodiment, the lower end of the step S1 is the boundary between the sidewall insulating film 22 and the interlayer insulating film 20. The silicide layer 32 does not exist at the lower end of the step S1. Therefore, even if the electrode layer 36 is formed on the barrier metal layer 34 in the state where the slit 90 exists, there is almost no interdiffusion between the silicide layer 32 and the electrode layer 36 through the slit 90. In addition, in the manufacturing method of the embodiment, the surface of the silicide layer 32, which is the base of the barrier metal layer 34, and the surface of the sidewall insulating film 22 form a smooth curved surface. Therefore, it is difficult to form a deep slit 90 in the barrier metal layer 34. This also suppresses interdiffusion between the silicide layer 32 and the electrode layer 36. In this way, according to the technology of the embodiment, interdiffusion between the silicide layer 32 and the electrode layer 36 can be suppressed.

[0035] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0036] 12: semiconductor substrate, 14: trench, 18: gate electrode, 20: interlayer insulating film, 22: sidewall insulating film, 32: silicide layer, 34: barrier metal layer, 36: electrode layer

Claims

1. A semiconductor substrate (12) having a trench (14) formed on an upper surface thereof; a gate insulating film (16) disposed in the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; an interlayer insulating film (20) disposed in the trench and covering an upper surface of the gate electrode; a sidewall insulating film (22) extending upward from the interlayer insulating film along a side surface of the trench and covering the side surface of the trench above the interlayer insulating film; a silicide layer (32) covering the upper surface of the semiconductor substrate and in contact with the sidewall insulating film; a barrier metal layer (34) covering an area spanning a surface of the silicide layer, a surface of the sidewall insulating film, and a surface of the interlayer insulating film, the barrier metal layer having a step (S2) on the surface of the barrier metal layer that follows a step (S1) formed by the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film; an electrode layer (36) covering the surface of the barrier metal layer on the silicide layer, the sidewall insulating film, and the interlayer insulating film; A switching element having

2. 2. The switching element according to claim 1, wherein the step of the barrier metal layer is located closer to the center of the trench than the step formed by the surface of the silicide layer, the surface of the sidewall insulating film, and the surface of the interlayer insulating film.

3. 3. The switching element according to claim 1, wherein at a connection portion between said silicide layer and said sidewall insulating film, said surface of said silicide layer and said surface of said sidewall insulating film are connected by a smoothly curved surface.

4. A method for manufacturing a switching element, comprising the steps of: A semiconductor wafer, comprising: A semiconductor substrate containing silicon and having a trench on an upper surface thereof; a gate insulating film disposed in the trench; a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; an insulating layer (26) disposed in the trench and covering an upper surface of the gate electrode; providing the semiconductor wafer having a step of forming a silicide layer made of silicide on the upper surface of the semiconductor substrate by reacting a metal with the semiconductor substrate, the silicide layer being formed such that an end of the silicide layer forms an overhanging portion that extends above an upper portion of the insulating layer; a step of reducing a thickness of the insulating layer by etching a surface of the insulating layer, the step of etching the insulating layer so that an interlayer insulating film is formed by the insulating layer remaining along the upper surface of the gate electrode, and a sidewall insulating film is formed by the insulating layer remaining under the overhang portion, the sidewall insulating film extending upward from the interlayer insulating film along a side surface of the trench and covering the side surface of the trench above the interlayer insulating film; forming a barrier metal layer covering an area spanning a surface of the silicide layer, a surface of the sidewall insulating film, and a surface of the interlayer insulating film; forming an electrode layer covering a surface of the barrier metal layer on the silicide layer, the sidewall insulating film, and the interlayer insulating film; The manufacturing method comprising the steps of:

5. In the step of etching the insulating layer, the insulating layer is etched by sputter etching; In the step of forming the barrier metal layer, the barrier metal layer is formed by sputtering, The step of etching the insulating layer and the step of forming the barrier metal layer are performed in a common chamber. The method according to claim 4.

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