Printed circuit board

Abstract

To provide a printed circuit board in which a semiconductor element, such as a power element, is built in, power loss can be improved by reducing parasitic resistance of the power element, and heat dissipation characteristics are improved by smoothing heat dissipation of the power element.SOLUTION: The present disclosure relates to a printed circuit board including: a substrate having a cavity; a semiconductor element at least partially disposed in the cavity, with a first metal pad and a gate being disposed on a lower side of the semiconductor element and a second metal pad being disposed on an upper side thereof; a metal block at least partially disposed in the cavity and connected to the second metal pad; and a first insulating layer covering at least a portion of each of the substrate, the semiconductor element, and the metal block, and filling at least a portion of the cavity.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to printed circuit boards. [Background technology]

[0002] Recently, electronic components used in electrical equipment are becoming lighter, thinner, shorter, and smaller as I / O increases. For this reason, there is a demand to embed semiconductor elements, such as power elements, in printed circuit boards. Summary of the Invention [Problem to be solved by the invention]

[0003] Among the various objects of the present disclosure is to provide a printed circuit board having embedded semiconductor devices, such as power devices.

[0004] Another of the various objects of the present disclosure is to provide a printed circuit board capable of reducing parasitic resistance of a power element to improve power loss.

[0005] Another of the various objects of the present disclosure is to provide a printed circuit board having improved heat dissipation characteristics by facilitating heat dissipation from power elements. [Means for solving the problem]

[0006] One of the various solutions proposed throughout this disclosure is to connect a metal block to a semiconductor element, for example a power element, and to place and embed the semiconductor element in a cavity in a substrate.

[0007] For example, a printed circuit board according to one example may include a substrate having a cavity, a semiconductor element at least partially disposed within the cavity, a first metal pad disposed on a lower side and a second metal pad disposed on an upper side, a metal block at least partially disposed within the cavity and connected to the second metal pad, and a first insulating layer covering at least a portion of the substrate, the semiconductor element, and the metal block, and filling at least a portion of the cavity.

[0008] For example, a printed circuit board according to one example may include a substrate having a through cavity, a power element having a first metal pad and a gate on one side and a second metal pad on the other side, and a metal block disposed on the power element and in contact with the second metal pad, a laminate having at least a portion disposed within the through cavity, and an insulating layer covering at least a portion of each of the substrate and the laminate and filling at least a portion of the through cavity. Effect of the Invention

[0009] Among the various advantages of the present disclosure, one advantage is that it provides a printed circuit board having a semiconductor device, such as a power device, embedded therein.

[0010] Another advantage of the present disclosure, among other advantages, is that it is possible to provide a printed circuit board capable of reducing the parasitic resistance of a power element and improving power loss.

[0011] Among the various effects of the present disclosure, yet another effect is that it is possible to provide a printed circuit board having improved heat dissipation characteristics by facilitating heat dissipation from a power element. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a printed circuit board. [Figure 4a] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 4b] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 4c] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 4d] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Figure 4e] 4A to 4C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3. [Diagram 5] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 6a] 6A to 6C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 5. [Figure 6b] 6A to 6C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 5. [Figure 6c] 6A to 6C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 5. [Figure 6d] 6A to 6C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 5. [Figure 6e] 6A to 6C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 5. [Figure 6f] 6A to 6C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 5. [Figure 6g] 6A to 6C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 5. [Figure 6h] 6A to 6C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 5. [Figure 7] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 8a] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 7. [Figure 8b] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 7. [Figure 8c] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 7. [Figure 8d] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 7. [Figure 8e] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 7. [Figure 8f] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 7. [Figure 8g] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 7. [Figure 8h] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 7. [Figure 9] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 10a] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 10b] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 10c] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 10d] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 10e] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 10f] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 10g] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 10h] 10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 10i]10A to 10C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. [Figure 11] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 12a] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. [Figure 12b] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. [Figure 12c] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. [Figure 12d] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. [Figure 12e] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. [Figure 12f] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. [Figure 12g] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. [Figure 12h] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. [Figure 12i] 12A to 12C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 11. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for a clearer description.

[0014] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0015] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0016] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with each other. The chip-related components 1020 can also be in the form of a package including the above-mentioned chips and electronic components.

[0017] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, and may include any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with each other along with the chip-related components 1020.

[0018] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may include passive elements in the form of chip components used for various other applications. The other components 1040 may also be combined with the chip-related components 1020 and / or the network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0020] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0021] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0022] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built in. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0023] Printed Circuit Board FIG. 3 is a cross-sectional view that illustrates an example of a printed circuit board.

[0024] Referring to the drawing, a printed circuit board 100A according to an example may include a substrate 111 having a cavity H, a semiconductor element 150 at least partially disposed in the cavity H, a metal block 160 at least partially disposed in the cavity H and connected to the semiconductor element 150, and a first insulating layer 112 covering at least a portion of each of the substrate 111, the semiconductor element 150, and the metal block 160 and filling at least a portion of the cavity H. The semiconductor element 150 and the metal block 160 may be disposed in the cavity H penetrating between the upper surface and the lower surface of the substrate 111 in the form of a laminate, and embedded in the first insulating layer 112. A first metal pad P1 and a second metal pad P2 may be disposed on the lower side and the upper side of the semiconductor element 150, respectively. The metal block 160 may be attached to and / or in contact with the second metal pad P2 of the semiconductor element 150. For example, the metal block 160 may be directly connected to the second metal pad P2. A gate G may be further disposed on the lower side of the semiconductor element 150. The semiconductor device 150 may be a power device, for example, a power MOSFET, in which the first and second metal pads P1 and P2 may include a source pad and a drain pad, respectively.

[0025] Meanwhile, a power element, for example, a power MOSFET, may have a vertical structure in which a source and a gate are arranged on one side and a drain is arranged on the other side. In this case, even if only a small parasitic resistance occurs in the region where a large current flows between the drain and the source, it may reduce efficiency and generate a lot of heat. Therefore, shortening this path may be effective in improving the performance of the power MOSFET. Meanwhile, when attempting to embed a power MOSFET structure in a cavity of a substrate, if the thickness of the substrate is made very thin, problems may occur during the substrate manufacturing process, and therefore, a certain level of substrate thickness may be ensured. In this state, if only the power MOSFET is manufactured thin, various problems such as non-filling and undulation may occur during the embedding process in the substrate. Therefore, it may be necessary to manufacture and embed the power MOSFET with a considerable thickness, but in this case, the parasitic resistance may increase, the power loss may increase, and more heat may be generated.

[0026] Meanwhile, the printed circuit board 100A according to one example can easily incorporate a semiconductor element 150, for example, a power element such as a power MOSFET, which is processed to be thin so that parasitic resistance can be reduced even when the thickness of the board 111 is thick. Specifically, in one example, the semiconductor element 150 can be disposed in the cavity H of the board 111 in a form in which a metal block 160 is attached on the semiconductor element 150. In this case, even when the thickness of the semiconductor element 150 is thin, the metal block 160 can be made relatively thick to correspond to the thickness of the board 111. For example, the metal block 160 may be thicker than the semiconductor element 150. Therefore, when a power element such as a power MOSFET is incorporated, not only can the system be made smaller, but also the parasitic resistance component can be reduced to improve power loss and improve system efficiency. In addition, the heat dissipation of the power element can be facilitated, and the heat dissipation characteristics can be improved. In addition, problems such as non-filling and undulation can be improved.

[0027] Meanwhile, the semiconductor element 150 and the metal block 160 may be disposed in the cavity H of the substrate 111 in the form of one laminate. For example, the semiconductor element 150 and the metal block 160 may be adjusted to have similar sizes and then bonded to form a laminate. Alternatively, a semiconductor wafer and a metal plate may be bonded and then diced to form a laminate. In this case, the metal block 160 may be directly connected to the second metal pad P2 of the semiconductor element 150. For example, the second metal pad P2 and the metal block 160 may each include copper (Cu). For example, the second metal pad P2 may be a drain pad made of copper (Cu), and the metal block 160 may be a copper block (Cu Block). Therefore, they may be directly connected to each other through a copper (Cu)-copper (Cu) bond. In this case, a separate adhesive may not be required, and the bonding reliability may be superior.

[0028] 1, a printed circuit board 100A according to an example includes a first wiring layer 121 disposed on a lower surface of a substrate 111, a second wiring layer 122 disposed on an upper surface of the substrate 111, a first via layer 131 penetrating the substrate 111 and connecting the first and second wiring layers 121, 122, a third wiring layer 123 disposed on a lower surface of a first insulating layer 112, a second via layer 132 penetrating at least a portion of the lower side of the first insulating layer 112 and connecting the third wiring layer 123 to the first wiring layer 121, the first metal pad P1, and the gate G, a fourth wiring layer 124 disposed on an upper surface of the first insulating layer 112, and a fourth wiring layer 124 penetrating at least a portion of the upper side of the first insulating layer 112 and connecting the third wiring layer 123 to the first wiring layer 121, the first metal pad P1, and the gate G. The wiring layer 124 may further include a third via layer 133 connecting the second wiring layer 122 and the second metal pad P2, a second insulating layer 113 disposed on the lower surface of the first insulating layer 112, a fifth wiring layer 125 disposed on the lower surface of the second insulating layer 113, a fourth via layer 134 penetrating at least a portion of the second insulating layer 113 and connecting the fifth wiring layer 125 to the third wiring layer 123, a third insulating layer 114 disposed on the upper surface of the first insulating layer 112, a sixth wiring layer 126 disposed on the upper surface of the third insulating layer 114, and / or a fifth via layer 135 penetrating at least a portion of the third insulating layer 114 and connecting the sixth wiring layer 126 to the fourth wiring layer 124. The second via layer 132 may include a first metal via connected to the first metal pad P1 and a second metal via connected to the gate G. The third via layer 133 may include a third metal via coupled to the metal block 160 .

[0029] For example, the printed circuit board 100A according to an embodiment may have a multi-layer wiring structure. In this case, the first metal pad P1 and the gate G of the semiconductor element 150 may be electrically connected to the wiring through the first and second metal vias. In addition, the second metal pad P2 of the semiconductor element 150 may be electrically connected to the wiring through the third metal via and the metal block 160, and a more excellent heat dissipation effect may be obtained. Meanwhile, the metal via may be deeper than the second metal via, but is not limited thereto.

[0030] The components of the printed circuit board 100A according to an example will be described in more detail below with reference to the drawings.

[0031] The substrate 111 may be a core layer. For example, it may include an organic core layer, a glass core layer, a metal core layer, a silicon core layer, or a ceramic core layer. The organic core layer may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as copper clad laminate (CCL), Ajinomoto build-up film (ABF), prepreg (PPG), etc., but is not limited thereto, and other polymer materials may be used. The glass core layer may include glass. For example, the glass may include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc. However, alternative glass materials such as, but not limited to, fluoroglass, phosphate glass, chalcogenide glass, etc., may be used as the material of the glass layer. In addition, other additives may be included to form glass with specific physical properties. Such additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of such elements and other elements. Glass may be distinguished from glass fibers as described above. The metal core layer may include a metal. The metal may include, but is not limited to, copper (Cu), Invar, etc. The silicon core layer may include pure silicon (Si). If necessary, the silicon core layer may include an oxide layer formed on silicon (Si). It may also include a nitride layer formed on the oxide layer. The oxide layer may include a silicon oxide film, and the nitride layer may include a silicon nitride film, but is not limited to these.The ceramic core layer may include a ceramic material, such as, but not limited to, alumina (Al2O3), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si3N4), and the like.

[0032] The first to third insulating layers 112, 113, and 114 may include an organic insulating material. As described above, the organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as CCL (Copper Clad Laminate), ABF (Ajinomoto Build-up Film), PPG (Prepreg), etc., but is not limited thereto, and other polymer materials may be used. The first to third insulating layers 112, 113, and 114 may include the same or different organic insulating materials. Each of the first to third insulating layers 112, 113, and 114 may be composed of a plurality of layers as necessary.

[0033] Each of the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited to this. Each of the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 may perform various functions according to the design. For example, the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the first to sixth wiring layers 121, 122, 123, 124, 125, and 126 may include a seed layer and a plating layer formed on the seed layer. The seed layer can be an electroless plating layer (or chemical copper) and / or a sputtering layer, and the plating layer can be an electrolytic plating layer (or electrolytic copper), but is not limited thereto.

[0034] Each of the first to fifth via layers 131, 132, 133, 134, and 135 may include a metal material. As described above, the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include, but is not limited to, copper (Cu). The first via layer 131 may include a through metal via. The through metal via may include a metal layer including the above-mentioned metal material disposed on the inner wall of a through hole, and the inside may be filled with a filler. The filler may be an insulating ink including an insulating resin such as epoxy, but is not limited to this, and may include a conductive ink as necessary. Each of the second to fifth via layers 132, 133, 134, and 135 may include a micro metal via. The micro metal vias may include filled vias that fill the via holes, but may also include conformal vias that are arranged along the walls of the via holes. The second and third via layers 132, 133 may be tapered in opposite directions. The fourth and fifth via layers 134, 135 may be tapered in opposite directions. The second and fourth via layers 132, 134 may be tapered in the same direction. The third and fifth via layers 133, 135 may be tapered in the same direction. The first to fifth via layers 131, 132, 133, 134, 135 may each perform various functions according to the design. For example, they may include ground vias, power vias, signal vias, etc. The first to fifth via layers 131, 132, 133, 134, 135 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtered layer may be included instead of the electroless plating layer (or chemical copper), or all of them may be included.

[0035] The semiconductor device 150 may be an integrated circuit (IC) die in which hundreds to millions of elements are integrated in one chip. The integrated circuit die may be formed on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a base material forming each body. Various circuits may be formed on the body. First and second metal pads P1 and P2 and a gate G for connection to an external circuit, for example, a signal, an electric, a ground, etc. may be formed on the body. The first and second metal pads P1 and P2 may include a conductive material such as aluminum (Al) or copper (Cu), respectively. The first and second metal pads P1 and P2 may be pads for connecting a source and a drain, respectively. For example, the semiconductor device 150 may be preferably a power device, and more preferably a power MOSFET, but is not limited thereto.

[0036] The metal block 160 may include a metal material. As described above, the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal block 160 may include copper (Cu), and may be, for example, a copper block, but is not limited thereto. The metal block 160 may be, but is not limited to, a block having a rectangular shape on a cross section.

[0037] 4a to 4e are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG.

[0038] Referring to FIG. 4a, a substrate 111 is prepared, and first and second wiring layers 121 and 122 and a first via layer 131 are formed on the substrate 111. The substrate 111 may have various types of materials as described above, and may be selected as necessary. A through via hole for forming the first via layer 131 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and a blasting process, depending on the material of the substrate 111. The first and second wiring layers 121 and 122 may be formed by a plating process. The first via layer 131 may be formed through a plating process and, if necessary, a plugging process.

[0039] 4b, a cavity H is formed in the substrate 111. The cavity H may be a through cavity penetrating between the upper and lower surfaces of the substrate 111. The cavity H may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, or a blasting process depending on the material of the substrate 111.

[0040] 4c, a stack is first formed in which metal blocks 160 are stacked on semiconductor elements 150, and then the stack is placed in cavity H. An adhesive such as DAF (Die Attach Film) may be used to place the stack. For example, the stack can be placed in cavity H by attaching an adhesive to the lower surface of substrate 111 and attaching the stack onto the adhesive exposed through cavity H.

[0041] 4d, the substrate 111 and the laminate are embedded with a first insulating layer 112. For example, a first layer of the first insulating layer 112 may be laminated on the adhesive described above to cover the top of the substrate 111 and the laminate, and then after removing the adhesive, a second layer of the first insulating layer 112 may be laminated in the area where the adhesive was removed to cover the bottom of the substrate 111 and the laminate.

[0042] Referring to FIG. 4e, the third and fourth wiring layers 123, 124 and the second and third via layers 132, 133 are formed in the first insulating layer 112. The via holes for forming the second and third via layers 132, 133 can be formed by laser processing, mechanical drilling, or the like. The third and fourth wiring layers 123, 124 and the second and third via layers 132, 133 can be formed by a plating process. In addition, a build-up process is performed as necessary to form the second and third insulating layers 113, 114, the fifth and sixth wiring layers 125, 126, and the fourth and fifth via layers 134, 135.

[0043] The printed circuit board 100A according to the above-described embodiment can be manufactured through a series of processes, and other overlapping descriptions will be omitted.

[0044] FIG. 5 is a cross-sectional view that illustrates a schematic diagram of another example of a printed circuit board.

[0045] Referring to the drawings, the printed circuit board 100B according to another example may include a first cavity H1 that penetrates at least a portion of the substrate 111 from a lower surface of the substrate 111 in a thickness direction and a second cavity H2 that penetrates at least another portion of the substrate 111 from an upper surface of the substrate 111 in a thickness direction in the printed circuit board 100A according to the above example. The first and second cavities H1 and H2 may be connected to each other in a thickness direction. At least a portion of the semiconductor element 150 may be disposed in the first cavity H1. At least a portion of the metal block 160 may be disposed in the second cavity H2. If necessary, the first and second cavities H1 and H2 may have different widths on a cross section. For example, the second cavity H2 may have a larger width on a cross section than the first cavity H1. Correspondingly, the semiconductor element 150 and the metal block 160 may also have different widths on a cross section. For example, the metal block 160 may have a greater width in cross section than the semiconductor element 150. The metal block 160 may be directly connected to the second metal pad P2 of the semiconductor element 150, but is not limited thereto, and an adhesive such as a DAF may be disposed between the semiconductor element 150 and the metal block 160 as necessary. As such, the first and second cavities H1 and H2 may be separately formed, and then the semiconductor element 150 and the metal block 160 may be separately disposed and connected, and in this case, all of the above-mentioned effects may be obtained. Other redundant descriptions will be omitted.

[0046] 6a to 6h are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG.

[0047] Referring to FIG. 6a, a substrate 111 is prepared, and first and second wiring layers 121 and 122 and a first via layer 131 are formed on the substrate 111. The substrate 111 may have various types of materials as described above, and may be selected as necessary. A through via hole for forming the first via layer 131 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and a blasting process, depending on the material of the substrate 111. The first and second wiring layers 121 and 122 may be formed by a plating process. The first via layer 131 may be formed through a plating process and, if necessary, a plugging process.

[0048] 6b, a second cavity H2 is formed in the substrate 111. The second cavity H2 may be a blind cavity that partially penetrates the upper surface of the substrate 111. The second cavity H2 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, or a blasting process depending on the material of the substrate 111.

[0049] 6c, a metal block 160 is placed in the second cavity H2. For example, the metal block 160 can be attached to the bottom surface of the second cavity H2 using an adhesive 165 such as DAF.

[0050] 6d, the first layer of the first insulating layer 112 is embedded over the substrate 111 and the metal block 160. For example, the first layer of the first insulating layer 112 may be laminated over the substrate 111 to cover the substrate 111 and the metal block 160.

[0051] Referring to Fig. 6e, a first cavity H1 is formed in the substrate 111. The first cavity H1 may be a blind cavity that penetrates from the lower surface of the substrate 111 to another part. If necessary, the adhesive 165 may be removed. The first cavity H1 may be connected to a second cavity H2. The second cavity H2 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and a blasting process depending on the material of the substrate 111.

[0052] 6f, the semiconductor element 150 is disposed in the first cavity H1. For example, the semiconductor element 150 may be disposed in the first cavity H1 such that the second metal pad P2 of the semiconductor element 150 is coupled to the metal block 160.

[0053] 6g, the second layer of the first insulating layer 112 is formed to embed the substrate 111 and the semiconductor device 150. For example, the second layer of the first insulating layer 112 may be laminated on the substrate 111 to cover the substrate 111 and the semiconductor device 150.

[0054] 6h, the third and fourth wiring layers 123, 124 and the second and third via layers 132, 133 are formed in the first insulating layer 112. The via holes for forming the second and third via layers 132, 133 may be formed by laser processing, mechanical drilling, or the like. The third and fourth wiring layers 123, 124 and the second and third via layers 132, 133 may be formed by a plating process. In addition, a build-up process is performed as necessary to form the second and third insulating layers 113, 114, the fifth and sixth wiring layers 125, 126, and the fourth and fifth via layers 134, 135.

[0055] The printed circuit board 100B according to the above-mentioned embodiment can be manufactured through a series of processes, and other overlapping descriptions will be omitted.

[0056] FIG. 7 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0057] Referring to the drawings, in the printed circuit board 100C according to another example, the first cavity H1 may have a larger cross-sectional width than the second cavity H2 in the printed circuit board 100B according to the above-mentioned example. Correspondingly, the semiconductor element 150 may have a larger cross-sectional width than the metal block 160. For example, the sizes of the first and second cavities H1 and H2 may be variously formed according to the sizes of the semiconductor element 150 and the metal block 160. In this case, all of the above-mentioned effects can be obtained. Other overlapping descriptions will be omitted.

[0058] 8a to 8h are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG.

[0059] Referring to the drawings, in the above-mentioned Figures 6a to 6h, a printed circuit board 100C according to another example can be manufactured through substantially the same processes as those described above, except that the sizes of the first and second cavities H1, H2 and the sizes of the semiconductor element 150 and metal block 160 placed therein are made different.

[0060] The printed circuit board 100C according to the above-mentioned further example can be manufactured through a series of processes, and other overlapping descriptions will be omitted.

[0061] FIG. 9 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0062] Referring to the drawings, the printed circuit board 100D according to another example may include a first cavity H1 that penetrates at least a portion of the substrate 111 from a lower surface of the substrate 111 in the thickness direction of the cavity H in the printed circuit board 100A according to the above example, and a second cavity H2 that penetrates at least another portion of the substrate 111 from an upper surface of the substrate 111 in the thickness direction. The substrate 111 may be disposed between the first and second cavities H1 and H2 to separate the first and second cavities H1 and H2. The metal block 160 may include a first metal block 161 at least partially disposed in the first cavity H1 and connected to the second metal pad P2, a second metal block 162 at least partially disposed in the second cavity H2 and attached to the substrate 111 disposed between the first and second cavities H1 and H2 via an adhesive 165, and a metal via 163 penetrating the substrate 111 disposed between the first and second cavities H1 and H2 and the adhesive 165 to connect the first and second metal blocks 161 and 162 to each other. The first metal block 161 and the second metal pad P2 may be directly connected to each other via a copper (Cu)-copper (Cu) joint, or may be connected by solder joint as necessary. If necessary, the first and second cavities H1 and H2 may have different widths on a cross section. For example, the second cavity H2 may have a larger width on a cross section than the first cavity H1. Correspondingly, the semiconductor element 150 and the metal block 160 may also have different widths on the cross section. For example, the metal block 160 may have a larger width on the cross section than the semiconductor element 150. As such, the first and second cavities H1 and H2 may be separately formed, and then the semiconductor element 150 and the metal block 160 may be disposed and connected using metal via connections, and in this case, all of the above-mentioned effects may be obtained. Other redundant descriptions will be omitted.

[0063] 10a to 10i are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG.

[0064] Referring to FIG. 10a, a substrate 111 is prepared, and first and second wiring layers 121 and 122 and a first via layer 131 are formed on the substrate 111. The substrate 111 may have various types of materials as described above, and may be selected as necessary. A through via hole for forming the first via layer 131 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and a blasting process, depending on the material of the substrate 111. The first and second wiring layers 121 and 122 may be formed by a plating process. The first via layer 131 may be formed through a plating process and, if necessary, a plugging process.

[0065] 10b, a second cavity H2 is formed in the substrate 111. The second cavity H2 may be a blind cavity that partially penetrates the upper surface of the substrate 111. The second cavity H2 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, or a blasting process depending on the material of the substrate 111.

[0066] 10c, a second metal block 162 is placed in the second cavity H2. For example, the second metal block 162 can be attached to the bottom surface of the second cavity H2 using an adhesive 165 such as DAF.

[0067] 10d, the substrate 111 and the second metal block 162 are embedded in a first layer of the first insulating layer 112. For example, the first layer of the first insulating layer 112 may be laminated on the substrate 111 to cover the substrate 111 and the second metal block 162.

[0068] 10e, a first cavity H1 is formed in the substrate 111. The first cavity H1 may be a blind cavity that penetrates from the bottom surface of the substrate 111 to a portion of the substrate. The first cavity H1 and the second cavity H2 may be separated from each other by the substrate 111. The second cavity H2 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and a blasting process depending on the material of the substrate 111.

[0069] 10f, a first metal block 161 is formed in the first cavity H1, and a metal via 163 is formed in the substrate 111 between the first and second cavities H1 and H2 to connect the first and second metal blocks 161 and 162. The metal via 163 may penetrate the substrate 111 and the adhesive 165 all at once. A via hole for the metal via 163 may be formed by various processes such as laser drilling and mechanical drilling. The first metal block 161 and the metal via 163 may be formed by a plating process. For example, the first metal block 161 and the metal via 163 may include a seed metal layer and a plated metal layer formed on the seed metal layer.

[0070] 10g, the semiconductor element 150 is disposed in the first cavity H1. For example, the semiconductor element 150 may be disposed in the first cavity H1 such that the second metal pad P2 of the semiconductor element 150 is coupled to the first metal block 161.

[0071] 10h, the substrate 111, the first metal block 161, and the semiconductor element 150 are embedded in the second layer of the first insulating layer 112. For example, the second layer of the first insulating layer 112 may be laminated on the substrate 111 to cover the substrate 111, the first metal block 161, and the semiconductor element 150.

[0072] Referring to FIG. 10i, the third and fourth wiring layers 123, 124 and the second and third via layers 132, 133 are formed in the first insulating layer 112. The via holes for forming the second and third via layers 132, 133 can be formed by laser processing, mechanical drilling, or the like. The third and fourth wiring layers 123, 124 and the second and third via layers 132, 133 can be formed by a plating process. In addition, a build-up process is performed as necessary to form the second and third insulating layers 113, 114, the fifth and sixth wiring layers 125, 126, and the fourth and fifth via layers 134, 135.

[0073] The printed circuit board 100D according to the above-mentioned further example can be manufactured through a series of processes, and other overlapping descriptions will be omitted.

[0074] FIG. 11 is a cross-sectional view that diagrammatically shows still another example of a printed circuit board.

[0075] Referring to the drawings, in the printed circuit board 100E according to another example, the first cavity H1 may have a larger cross-sectional width than the second cavity H2 in the printed circuit board 100D according to the above-mentioned another example. Correspondingly, the semiconductor element 150 may have a larger cross-sectional width than the metal block 160. For example, the sizes of the first and second cavities H1 and H2 may be variously formed according to the sizes of the semiconductor element 150 and the metal block 160. In this case, all of the above-mentioned effects can be obtained. Other redundant descriptions will be omitted.

[0076] 12a to 12i are cross-sectional views illustrating steps in a process for manufacturing the printed circuit board of FIG.

[0077] Referring to the drawings, in the above-mentioned Figures 10a to 10i, a printed circuit board 100E according to another example can be manufactured through substantially the same processes as those described above, except that the sizes of the first and second cavities H1, H2 and the sizes of the semiconductor element 150 and the first and second metal blocks 161, 162 arranged therein are made different.

[0078] The printed circuit board 100E according to the above-mentioned further example can be manufactured through a series of processes, and other overlapping descriptions will be omitted.

[0079] In the present disclosure, the term "cover" can include not only the case of covering entirely, but also the case of covering at least a part, and can include not only the case of covering directly, but also the case of covering indirectly. The term "fill" can include not only the case of filling completely, but also the case of filling at least a part, and can also include the case of filling roughly. For example, it can include the case where there are some gaps or voids. The term "surround" can include not only the case of surrounding completely, but also the case of surrounding partially and the case of surrounding roughly.

[0080] In the present disclosure, being placed within a cavity does not only include a case where an object is placed completely within the cavity, but also a case where a part of the object protrudes upward or downward on a cross section. For example, a case where an object is placed within a cavity on a plane can be judged in a broader sense.

[0081] In the present disclosure, the term "substantially" can be determined by including process errors and positional deviations that occur in the manufacturing process, errors during measurement, and the like.

[0082] In the present disclosure, the same insulating material may mean not only the completely same insulating material, but also the same type of insulating material. Thus, the compositions of the insulating materials are substantially the same, but the specific composition ratios thereof may vary slightly.

[0083] In the present disclosure, "on a cross section" may refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from a side, and "on a plane" may refer to the planar shape of an object cut horizontally or the planar shape of an object when viewed from a top or bottom.

[0084] In this disclosure, for convenience, the terms lower, bottom, and lower surface are used to mean the downward direction based on the cross section of the drawing, and the terms upper, top, and upper surface are used to mean the opposite direction. However, this is merely a definition of the direction for convenience of explanation, and the scope of the claims is not particularly limited by the description of the direction, and the concepts of up / down can be changed at any time.

[0085] In the present disclosure, the term "connected" refers not only to a direct connection but also to an indirect connection via an adhesive layer or the like. The term "electrically connected" refers to a physical connection and a non-connection. Furthermore, the terms "first" and "second" are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the right.

[0086] The expression "one example" used in the present disclosure does not mean the same embodiment as the other, but is provided to emphasize and describe the unique features that are different from each other. However, the above-mentioned one example does not exclude being realized in combination with the features of another example. For example, even if the matter described in a particular example is not described in another example, it can be understood as being related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0087] In the present disclosure, the thickness, width, length, depth, etc. can be measured using a scanning microscope, optical microscope, etc. based on a cross section obtained by polishing or cutting the printed circuit board. The cut section can be a vertical section or a horizontal section, and each value can be measured based on the required cut section. If the value is not constant, the value can be determined as the average value of values ​​measured at any five points. The width of the upper end and / or lower end of the via can be measured on a cross section obtained by cutting the central axis of the via in the thickness direction of the board. The depth of the via can be measured as the distance from the upper end to the lower end of each object on a cross section obtained by cutting the central axis of each object in the thickness direction of the board.

[0088] The average thickness, average diameter, average depth, etc. can be calculated as the average value of the values ​​measured at any five points. If each opening has a tapered shape, the diameter of each opening can be calculated as the average value of the diameters of the uppermost and lowermost sides of each opening.

[0089] The terms used in the present disclosure are merely used to describe an example and are not intended to limit the present disclosure. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0090] 1000 electronic equipment 1010 Mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 Camera 1060 Antenna 1070 display 1080 Battery 1090 Signal Line 1100 Smartphone 1110 Motherboard 1120 parts 1121 Parts Package 1130 Camera Module 1140 Speaker 100A, 100B, 100C, 100D, 100E Printed Circuit Boards 111 Substrate 112, 113, 114 Insulating layer 121, 122, 123, 124, 125, 126 wiring layer 131, 132, 133, 134, 135 Via layers 150 Semiconductor elements P1, P2 metal pads G Gate 160, 161, 162 Metal blocks 163 Metal Via 165 Adhesive H, H1, H2 cavities

Claims

1. A substrate having a cavity; a semiconductor element at least partially disposed within the cavity, the semiconductor element having a first metal pad disposed on a lower side thereof and a second metal pad disposed on an upper side thereof; a metal block at least partially disposed within the cavity and connected to the second metal pad; a first insulating layer covering at least a portion of each of the substrate, the semiconductor device and the metal block and filling at least a portion of the cavity.

2. The semiconductor element includes a power MOSFET, the first metal pad comprises a source pad; the second metal pad comprises a drain pad; The printed circuit board of claim 1 , further comprising a gate disposed below the semiconductor element.

3. The printed circuit board of claim 1 , wherein the metal block is directly coupled to the second metal pad.

4. The printed circuit board of claim 3 , wherein the second metal pad and the metal block each include copper, and the coppers are bonded to each other to directly connect to each other.

5. the cavity extends through the substrate in a thickness direction between the upper and lower surfaces; The printed circuit board of claim 1 , wherein the metal block is attached to an upper side of the semiconductor element and is at least partially disposed within the cavity together with the semiconductor element.

6. the cavities include a first cavity penetrating at least a portion of the substrate from a lower surface of the substrate in a thickness direction and a second cavity penetrating at least another portion of the substrate from an upper surface of the substrate in a thickness direction; the semiconductor element is at least partially disposed within the first cavity; The printed circuit board of claim 1 , wherein the metal block is at least partially disposed within the second cavity.

7. The first cavity and the second cavity have different widths in cross section, The printed circuit board according to claim 6 , wherein the semiconductor element and the metal block have different widths in cross section.

8. The printed circuit board of claim 6 , wherein the first cavity and the second cavity are connected to each other in a thickness direction.

9. The printed circuit board of claim 6 , wherein the first cavity and the second cavity are separated from each other by the substrate being disposed between the first cavity and the second cavity.

10. 10. The printed circuit board of claim 9, wherein the metal blocks include: a first metal block at least partially disposed within the first cavity and coupled to the second metal pad; a second metal block at least partially disposed within the second cavity and attached to the substrate disposed between the first cavity and the second cavity via an adhesive; and a metal via penetrating the substrate disposed between the first cavity and the second cavity and the adhesive, coupling the first metal block and the second metal block to each other.

11. a first wiring layer disposed on a lower surface of the substrate; a second wiring layer disposed on the upper surface of the substrate; The printed circuit board according to claim 1 , further comprising: a first via layer penetrating the substrate and connecting the first wiring layer and the second wiring layer.

12. a third wiring layer disposed on a lower surface of the first insulating layer; a second via layer penetrating at least a portion of a lower side of the first insulating layer and connecting the third wiring layer to the first wiring layer and the first metal pad; a fourth wiring layer disposed on an upper surface of the first insulating layer; 12. The printed circuit board of claim 11, further comprising: a third via layer penetrating at least a portion of an upper side of the first insulating layer and connecting the fourth wiring layer to the second wiring layer and the second metal pad, respectively.

13. The printed circuit board of claim 1 , wherein the substrate comprises an organic core layer, a glass core layer, a metal core layer, a silicon core layer, or a ceramic core layer.

14. a substrate having a through cavity; a power element having a first metal pad and a gate disposed on one side and a second metal pad disposed on the other side, and a metal block disposed on the power element and in contact with the second metal pad, the stack being at least partially disposed within the through cavity; an insulating layer covering at least a portion of each of the substrate and the laminate and filling at least a portion of the through cavity.

15. a first metal pattern layer and a second metal pattern layer disposed on one side and the other side of the insulating layer, respectively; a first metal via penetrating at least a portion of the insulating layer and connecting at least a portion of the first metal pattern layer to the first metal pad; a second metal via penetrating at least a portion of the insulating layer and connecting at least a portion of the first metal pattern layer to the gate; 15. The printed circuit board of claim 14, further comprising: a third metal via penetrating at least another portion of the insulating layer and connecting at least a portion of the second metal pattern layer to the metal block.

16. The printed circuit board of claim 14 , wherein the metal block is thicker than the power element.

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