Semiconductor device

Abstract

To form an oxide semiconductor film with a low defect level density, to form an oxide semiconductor film with a low concentration of impurities, and to improve electrical properties in a semiconductor device using an oxide semiconductor film.SOLUTION: The semiconductor device includes: a capacitive element, a resistance element, or a transistor which have a metal oxide film including a region where a rate of probability at which a diffraction pattern having bright spots indicating orientation is observed is 70% or more and less than 100% when an observation location is changed in a one-dimensional range within 300 nm, using a transmission electron diffraction measurement device.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The present invention relates to a method, manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. In particular, the present invention relates to a capacitor element having an oxide semiconductor film, a driving method thereof, and a manufacturing method thereof. The present invention relates to a semiconductor device including a semiconductor element, a resistor element, or a transistor, and a method for manufacturing the same. [Background technology]

[0002] It is used in many flat panel displays, such as liquid crystal displays and light-emitting displays. The transistors used are amorphous silicon and single crystal silicon formed on a glass substrate. The silicon semiconductor is made of silicon semiconductor such as polycrystalline silicon or polysilicon. Transistors using semiconductors are also used in integrated circuits (ICs).

[0003] In recent years, metal oxides that exhibit semiconducting properties have been used in transistors instead of silicon semiconductors. In this specification, the term "oxide" refers to a metal oxide that exhibits semiconductor properties. Let us call them semiconductors.

[0004] For example, as an oxide semiconductor, InGaO3(ZnO) having a homologous phase m (m: Natural numbers) are known (see Non-Patent Document 1 and Non-Patent Document 2).

[0005] In addition, Patent Document 1 describes a homologous compound InMO3(ZnO) m (M=In, Fe, Transparent thin-film field-effect transistor using Ga, Al, m = an integer of 1 or more and less than 50 The data is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2004-103957 A [Non-patent literature]

[0007] [Non-Patent Document 1] M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃”, J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 2] Masaki Nakamura, Noboru Kimizuka, Takahiko Mouri, Mitsumasa Isobe, "Synthesis and crystal structure of homologous phase, InFeO3(ZnO)m (m: natural number) and its isomorphic compounds", Solid State Physics, 1993, Vol.28, No.5, pp.317-327 Summary of the Invention [Problem to be solved by the invention]

[0008] However, when the crystallinity of an oxide semiconductor film is low, oxygen vacancies and dung may occur in the oxide semiconductor film. Defects such as ring bonds are likely to occur.

[0009] In addition, when oxide semiconductor films are stacked using sputtering targets having different compositions, When the crystallinity of each oxide semiconductor film is different, the boundary between the stacked oxide semiconductor films may be Defects will occur on the surface.

[0010] The oxide semiconductor film is filled with hydrogen and other elements due to defects in the film or due to bonds between the defects and hydrogen or the like. In addition, the oxide semiconductor film may have a tendency to have a high electrical characteristic. Impurities contained in the semiconductor film may become carrier traps or carrier generation sources. These results lead to poor electrical characteristics of transistors and also to deterioration over time and stress testing ( For example, BT (Bias-Temperature) stress test, optical BT stress test In the case of the above, the amount of change in the electrical characteristics of the transistor, typically the threshold voltage, increases. This causes the reliability to decrease.

[0011] In view of this, one embodiment of the present invention is to form an oxide semiconductor film having a low density of defect states. Another embodiment of the present invention is a method for forming an oxide semiconductor film having a low impurity concentration. Another object of one embodiment of the present invention is to provide a semiconductor device including an oxide semiconductor film. Another object of the present invention is to improve electrical characteristics in a semiconductor device or the like. An object of the present invention is to improve the reliability of a semiconductor device including an oxide semiconductor film. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Note that it is not necessary for one embodiment of the present invention to solve all of these problems. Furthermore, the description of these problems does not preclude the existence of other problems. The problem is self-evident from the description, drawings, claims, etc. Other issues can be extracted from the descriptions in the drawings, claims, etc. [Means for solving the problem]

[0012] In one embodiment of the present invention, a transmission electron diffraction measurement device is used to perform one-dimensional observation in a range of 300 nm. When the observation point was changed, the percentage of diffraction patterns with bright spots indicating orientation increased by 70%. A capacitance element or a resistance element having a metal oxide film including an area in which the ratio is 0% or more and less than 100%. The semiconductor device is provided with

[0013] The metal oxide film is in contact with the nitride insulating film. Degrees are 8 x 10 19 atoms / cm 3 More preferably, it is equal to or greater than this.

[0014] Alternatively, in one embodiment of the present invention, a transmission electron diffraction measurement device is used to measure a one-dimensional area of ​​300 nm. When the observation point is changed in the range, a diffraction pattern with bright spots indicating orientation is observed. A transistor including an oxide semiconductor film including a region in which the ratio is 70% or more and less than 100% is The semiconductor device is provided with

[0015] Note that the hydrogen concentration in the oxide semiconductor film is 5×10 19 atoms / cm 3 is less than It is preferable.

[0016] Alternatively, one embodiment of the present invention is a semiconductor device having a transistor and a capacitor provided over an insulating surface. The transistor is a semiconductor device having a gate electrode provided on an insulating surface and a gate An oxide semiconductor film that at least partially overlaps with an electrode, and a gate electrode and an oxide semiconductor film a gate insulating film provided on the first insulating film and a pair of electrodes in contact with the oxide semiconductor film; An oxide insulating film covering at least a part of the pair of electrodes and a nitride insulating film are provided in the transistor. The capacitance element is made of a metal oxide film in contact with the gate insulating film and a thin film formed of a metal oxide film. a conductive film having a light-transmitting property, the conductive film having a light-transmitting property being overlapped with the metal oxide film at least partially; and a nitride insulating film provided between the oxide semiconductor film and the metal oxide film. Using a transmission electron diffraction measurement device, the observation area was changed one-dimensionally within a range of 300 nm. When the diffraction pattern has bright spots indicating orientation, the ratio of the area in which the diffraction pattern has bright spots indicating orientation is 70% or more. Includes areas where the percentage is less than 0.00%.

[0017] Alternatively, one embodiment of the present invention is a semiconductor device having a transistor and a capacitor provided over an insulating surface. The transistor is a semiconductor device having an oxide semiconductor layer having an opening on an insulating surface. an oxide semiconductor film in contact with an insulating film; a pair of electrodes in contact with the oxide semiconductor film; a gate insulating film in contact with the oxide semiconductor film; and a gate electrode overlapping the oxide semiconductor film via the gate insulating film. The capacitor element has an insulating surface and an oxide insulating film having an opening. a nitride insulating film; a metal oxide film in contact with the nitride insulating film at an opening; and The oxide semiconductor film and the conductive film are in contact with each other. In the case of metal oxide films, a transmission electron diffraction measurement device was used to measure the one-dimensional area of ​​300 nm. When the observation point is changed, a diffraction pattern with bright spots showing orientation is observed. This includes areas where the ratio is 70% or more but less than 100%.

[0018] Note that the oxide semiconductor film and the metal oxide film are formed of the same metal element.

[0019] In addition, the above diffraction pattern was observed using a nano-beam electron beam with a probe diameter of 1 nm. do. Effect of the Invention

[0020] According to one embodiment of the present invention, an oxide semiconductor film with a low density of defect states can be formed. Alternatively, according to one embodiment of the present invention, an oxide semiconductor film with a low impurity concentration can be formed. According to one embodiment of the present invention, in a semiconductor device including an oxide semiconductor film, According to one embodiment of the present invention, the oxide semiconductor film can have improved electrical characteristics. In a semiconductor device using the same, the reliability can be improved. This makes it possible to provide a novel semiconductor device.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Diagram 2] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Diagram 3] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 4] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Diagram 5] 1A and 1B are diagrams showing a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. [Figure 6] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Figure 7] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Figure 8] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 10] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 14] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Figure 15] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a transistor. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 18] 1A and 1B are diagrams illustrating band structures of transistors. [Figure 19] 1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 20] FIG. 1 is a top view illustrating one embodiment of a semiconductor device. [Figure 21] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 22] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 23] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 24] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 25] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 26] FIG. 4 is a circuit diagram illustrating a protection circuit portion. [Figure 27] 1A and 1B are a top view and a cross-sectional view of a resistor element. [Figure 28] FIG. 4 is a circuit diagram illustrating a protection circuit portion. [Figure 29] 1A and 1B are a circuit diagram and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 30] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 31] FIG. 2 shows the crystal structures of In-Sn-Zn oxide and In-Ga-Zn oxide. [Diagram 32] FIG. 1 is a block diagram of an RFID tag according to one embodiment of the present invention. [Diagram 33] 1A to 1C are diagrams illustrating examples of use of an RFID tag according to one embodiment of the present invention. [Diagram 34] FIG. 2 is a block diagram showing a CPU according to an embodiment of the present invention. [Diagram 35] FIG. 2 is a diagram illustrating a display module. [Diagram 36] 1A and 1B are diagrams illustrating external views of an electronic device according to an embodiment. [Figure 37] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 38] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Figure 39] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Diagram 40] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a transistor. [Diagram 41] Cs-corrected high-resolution TEM image of a cross section of a CAAC-OS film, and a schematic cross-sectional diagram of the CAAC-OS film. [Diagram 42] Cs-corrected high-resolution TEM image in the plane of the CAAC-OS film. [Diagram 43] 1A and 1B illustrate structural analyses of a CAAC-OS film and a single crystal oxide semiconductor by XRD. [Diagram 44] FIG. 1 shows electron diffraction patterns of a CAAC-OS film. [Diagram 45] FIG. 2 is a diagram showing changes in crystalline parts of an In-Ga-Zn oxide film due to electron irradiation. [Figure 46] Schematic diagram illustrating a formation model of a CAAC-OS film and an nc-OS film. [Figure 47] A diagram explaining InGaZnO4 crystals and pellets. [Figure 48] Schematic diagram illustrating a deposition model of a CAAC-OS film. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0024] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0025] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. This will be described with reference to the following.

[0026] 1A to 1C are top views and cross-sectional views of a transistor 10 included in a semiconductor device. FIG. 1A is a top view of a transistor 10, and FIG. 1B is a cross-sectional view of the transistor 10. FIG. 1(C) is a cross-sectional view taken along dashed line AB in FIG. 1(A), and FIG. 1(C) is a cross-sectional view taken along dashed line CD in FIG. In FIG. 1(A), for clarity, a substrate 11, a gate insulating film 15, and an oxide The oxide insulating film 23, the oxide insulating film 25, the nitride insulating film 27, etc. are omitted.

[0027] The transistor 10 shown in FIG. 1B and FIG. 1C is a channel etch type transistor. A gate electrode 13 is provided on a substrate 11, and the substrate 11 and the gate electrode 13 A gate insulating film 15 is formed on the gate electrode 13. The gate insulating film 15 is formed on the gate electrode 13. The oxide semiconductor film 17 is connected to the oxide semiconductor film 17, and a pair of electrodes 19 and 20 are in contact with the oxide semiconductor film 17. In addition, an oxide semiconductor film is formed on the gate insulating film 15, the oxide semiconductor film 17, and the pair of electrodes 19 and 20. The insulating film includes a nitride insulating film 23, an oxide insulating film 25, and a nitride insulating film 27. One of the electrodes 19 and 20, in this case the electrode 32 connected to the electrode 20, is formed on the nitride insulating film 27. The electrode 32 functions as a pixel electrode.

[0028] The oxide semiconductor film 17 is formed of a metal oxide film containing at least In or Zn, Representative examples include In-Ga oxide film, In-Zn oxide film, and In-M-Zn oxide film (M is , Al, Ti, Ga, Y, Zr, Sn, La, Ce, or Nd).

[0029] When the oxide semiconductor film 17 is an In-M-Zn oxide film, the components other than Zn and O are The atomic ratio of In and M in the above-mentioned alloy is preferably 25 atomic % or more of In and 75 atomic % or less of M. atomic %, more preferably In is more than 34 atomic %, and M is 66 atomic %. tomic% or less.

[0030] The oxide semiconductor film 17 is an In-M-Zn oxide film (wherein M is Al, Ti, Ga, Y, Zr, or S In, La, Ce, or Nd), used to deposit In-M-Zn oxide films The atomic ratio of the metal elements in the sputtering target must satisfy the following conditions: In≧M, Zn≧M. The atomic ratio of the metal elements in such a sputtering target is preferably In:M :Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2 It is preferable that the atomic ratio of the oxide semiconductor film 17 to be formed is determined by the above-mentioned error. The atomic ratio of metal elements contained in the sputtering target can vary by ±40%. Includes movement.

[0031] The oxide semiconductor film 17 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, the energy gap is 3 eV or more. By using such a material, the off-state current of the transistor 10 can be reduced.

[0032] The oxide semiconductor film 17 is made of CAAC-OS (C Axis Aligned Cr It is formed using a crystalline oxide semiconductor film. In addition, the oxide semiconductor film 17 is one-dimensionally measured using a transmission electron diffraction measurement device, as described later. When the observation point was changed within a range of 300 nm, the CAAC conversion rate was 70% or more and 100% or more. %, preferably 80% or more and less than 100%, preferably 90% or more and less than 100%, more preferably The impurity concentration in the oxide semiconductor film 17 is preferably 95% or more and 98% or less. and the defect level density is low.

[0033] Here, the CAAC-OS film will be described. The CAAC-OS film is made up of multiple c-axis oriented The oxide semiconductor film has crystal parts (also referred to as pellets).

[0034] Transmission Electron Microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of the CAAC-OS film was obtained by a microscope. (also called high-resolution TEM image) allows multiple crystals to be identified. On the other hand, high-resolution TEM images also show clear boundaries between crystal parts (also called pellets). In other words, it is not possible to confirm the grain boundaries. Therefore, it can be said that the CAAC-OS film is less susceptible to the decrease in electron mobility caused by the grain boundaries. In addition, it is possible to reduce the variation in electrical characteristics and improve reliability. This can be done.

[0035] For example, as shown in FIG. 41(A), the CAAC-OS film is A high-resolution TEM image of the cross section of the sample is observed. Observe the TEM image using the Aberration Corrector function. In the following, we will refer to high-resolution TEM images using the spherical aberration correction function, especially Cs-corrected high-resolution TEM. The Cs-corrected high-resolution TEM image is obtained using, for example, an atomic This can be done using a high-resolution analytical electron microscope such as the JEM-ARM200F.

[0036] A Cs-corrected high-resolution TEM image of the enlarged area (1) in Figure 41(A) is shown in Figure 41(B). From Figure 41(B), it can be seen that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is formed on the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed) or The shape reflects the unevenness of the top surface, and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface. do.

[0037] In FIG. 41(B), the CAAC-OS film has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 41(B) and Figure 41(C). Therefore, the size of each crystal part is about 1 nm to 3 nm, and the inclination between the crystal parts is The size of the gap caused by this is about 0.8 nm. , they can also be called nanocrystals (nc).

[0038] Here, from the Cs-corrected high-resolution TEM image, the pellet of the CAAC-OS film on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 41(D)). The inclination between the pellets observed in FIG. 41(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0039] Also, for example, as shown in FIG. 42(A), the CAAC- Observe the Cs-corrected high-resolution TEM image of the OS film. The Cs-corrected high-resolution TEM images of the enlarged regions (2) and (3) are shown in Figure 42(B), respectively. , as shown in Fig. 42(C) and Fig. 42(D). D) The crystal part has metal atoms arranged in a triangular, quadrangular or hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different crystal parts. .

[0040] Figure 2(A) is a high-resolution TEM image of the cross section of the CAAC-OS film. is a high-resolution TEM image of a cross section of the area b enclosed by the dashed line in Fig. 2(A) and enlarged. In order to facilitate understanding of the high-resolution TEM image of the cross section of Fig. 2(B), Fig. 2(C) is FIG. 11 shows a diagram highlighting the atomic arrangement.

[0041] FIG. 2(D) shows the area surrounded by a circle (diameter approximately 4n m). From Fig. 2(D), the c-axis orientation is confirmed in each region. In addition, the orientation of the c-axis is different between A1-O and O-A2, so it is considered that the crystal structure is different. In addition, the c-axis angles between A1 and O are 14.3° and 16.6°. 26.4°, and gradually changes from 0 to 26.4°. The c-axis angle changes gradually and continuously from -18.3° to -17.6° to -15.9°. It is clear that this is the case.

[0042] In the high-resolution TEM image of the cross section shown in FIG. 3(A), a region different from region b shown in FIG. 2(A) is The area surrounded by the dashed line is a region slightly shifted from area b. The surface in the vicinity of the area is curved. A high-resolution TEM image is shown in FIG. 3(B).

[0043] Figure 3(C) shows the area circled between B1 and B2 in Figure 3(B) (diameter: about 4 nm). From Fig. 3(C), the c-axis orientation can be confirmed in each region. In addition, between B1 and B2, the c-axis angles are -6.0°, -6.1°, and -1.2°. It can be seen that the change is continuous and gradual.

[0044] In the cross-sectional TEM image shown in FIG. 4(A), the region different from region b shown in FIG. 2(A) is indicated by a dashed line. The area surrounded by the dashed line is a region slightly shifted from area b. The surface is flat. A cross-sectional TEM image of the area enclosed by the dashed line is shown in Fig. 4( As shown in B).

[0045] FIG. 4(C) shows the area surrounded by a circle (diameter approximately 4n Fig. 4(C) shows that the c-axis orientation is confirmed in each region. In addition, the c-axis angles between C1 and O are -7.9°, -5.6°, and -4.1°. Similarly, between O and C2, the c-axis angle It can be seen that the angle changes gradually and continuously: -10.0°, -10.0°, -6.8°. do.

[0046] In addition, when electron diffraction is performed on the CAAC-OS film, spots (bright points) indicating orientation are observed. For example, a thickness of 1 nm to 30 nm is observed on the top surface of the CAAC-OS film. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, spots are observed. (See FIG. 5(A)).

[0047] The high-resolution TEM images of the cross section and the plane show that the CAAC-OS film is crystalline. It can be seen that the part has orientation.

[0048] Most of the crystals in the CAAC-OS film are cubic with a side length of less than 100 nm. The size is small enough to fit inside the body. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This includes sizes that fit within a cube of less than 3 nm, 5 nm, or 5 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a high-resolution TEM image of a plane, 2 Below Top, 5 μm 2 More than or equal to 1000μm 2 In some cases, crystal regions having more than this amount may be observed.

[0049] For example, X-ray diffraction (XRD) of a CAAC-OS film having InGaZnO4 crystals : Using an X-Ray Diffraction (X-Ray Diffraction) device, the out-of-plane method was used. When the structure was analyzed, a peak was observed at a diffraction angle (2θ) of about 31°, as shown in FIG. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0050] In addition, the out-of-plane crystal structure of the CAAC-OS film with InGaZnO4 crystals In the structural analysis by the method, in addition to the peak at 2θ near 31°, a peak at 2θ near 36° was also found. The peak at 2θ of around 36° may appear due to the c-axis in some parts of the CAAC-OS film. This indicates that the crystals include those without orientation, typically those with a spinel structure. At the interface between the Pinel structure crystal and other regions, metal elements, typically copper elements, diffuse. As a result, the CAAC-OS film is It is preferable that the CAAC-OS film does not contain crystals with a crystalline structure, and the CAAC-OS film has a crystalline structure with a 2θ of about 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0051] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. When structural analysis is performed using the lane method, a peak appears at 2θ of approximately 56°. , which is attributed to the (110) plane of the InGaZnO4 crystal. In the case of the CAAC-OS film, The angle θ is fixed at about 56°, and the sample is rotated around the normal vector of the sample surface as the axis (φ axis). Even if analysis (φ scan) is performed from the sample, no clear peak appears, as shown in FIG. 43(B). In contrast, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56°. When the φ scan is performed, as shown in Figure 43(C), the crystal plane is returned to the equivalent of the (110) plane. Six peaks that belong to CAAC were observed. It can be seen that the a-axis and b-axis orientations of the -OS film are irregular.

[0052] Next, the CAAC-OS film, In-Ga-Zn oxide, was subjected to a dipping method in the direction parallel to the sample surface. The diffraction pattern (selected area transmission electron microscope) when an electron beam with a probe diameter of 300 nm is incident from the The diffraction pattern is shown in FIG. 44(A). Spots due to the (009) plane of the ZnO4 crystal are confirmed. In this way, the crystal parts included in the CAAC-OS film have a c-axis orientation, and the c-axis extends to the surface on which the film is formed. On the other hand, for the same sample, the direction perpendicular to the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident from a perpendicular direction is shown in Fig. 44. As shown in FIG. 44(B), a ring-shaped diffraction pattern is observed. Therefore, Electron diffraction also revealed that the a- and b-axes of the crystals in the CAAC-OS film have an orientation. It can be seen that the first ring in FIG. 44(B) is a crystal of InGaZnO4. This is thought to be due to the (010) and (100) planes of the crystal. The second ring in the figure is thought to be due to the (110) plane, etc.

[0053] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, it is clear that the direction of the lattice is the same as that confirmed by the high-resolution TEM observation of the cross section mentioned above. Each layer of metal atoms arranged in a layered fashion is parallel to the ab plane of the crystal.

[0054] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. For example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the face or top surface normal vector.

[0055] In this way, the c-axis of each crystal part (nanocrystal) is approximately perpendicular to the surface on which it is formed or the upper surface. Because the CAAC-OS membrane is oriented in the C-Axis Alignment (CANC) direction, In addition, the oxide semiconductor film may be referred to as an oxide semiconductor film having nanocrystals (d nanocrystals).

[0056] In addition, the distribution of the c-axis oriented crystal parts in the CAAC-OS film may not be uniform. For example, the crystals in the CAAC-OS film grow from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has more c-axis oriented crystals than the region near the surface on which the crystal is formed. In addition, the proportion of the impurity part may increase in the CAAC-OS film. The region where the ZnO was added was altered, and regions with different proportions of c-axis oriented crystals were formed. This may also occur.

[0057] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is preferably made of silicon or a transition metal element other than the main component of the oxide semiconductor film. The elements that bond to oxygen stronger than the metal elements that form the oxide semiconductor film, such as Zn, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Since the diameter (or molecular radius) of the ions is large, when the ions are contained inside the oxide semiconductor film, the oxide semiconductor film The impurities contained in the oxide semiconductor film are disturbed, which causes a decrease in crystallinity. Pure materials may act as carrier traps or carrier generation sources.

[0058] For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor film 17 be reduced as much as possible. Specifically, the oxide semiconductor film 17 was analyzed by secondary ion mass spectrometry (SIMS). The hydrogen concentration obtained by 2D ion mass spectrometry was , 5×10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 Less than 5×10 18 atoms / cm 3 Less than 1 x 10 18 atoms / c m 3 less than 5×10 17 atoms / cm 3 Less than 1×, more preferably 10 16 atoms / cm 3 As a result, transistor 10 has a threshold voltage is positive (also called normally-off characteristic).

[0059] In addition, the oxide semiconductor film 17 contains silicon or carbon, which is one of the Group 14 elements. If the oxide semiconductor film 17 is exposed to the oxygen, oxygen vacancies increase in the oxide semiconductor film 17, causing the oxide semiconductor film 17 to become n-type. The concentrations of silicon and carbon in the oxide semiconductor film 17 (obtained by secondary ion mass spectrometry) The concentration of 18 atoms / cm 3 Less than 2 x 10 17 atoms / cm 3 As a result, the transistor 10 is electrically This characteristic is also called a normally-off characteristic.

[0060] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0061] Here, a microcrystalline oxide semiconductor film will be described.

[0062] In the microcrystalline oxide semiconductor film, crystal parts can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor has a region where a crystal part is not clearly observed, and a region where a crystal part is not clearly observed. The crystal parts contained in the film are large, with sizes ranging from 1 nm to 100 nm, or from 1 nm to 10 nm. In particular, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals, which are microcrystals, is called nc-OS (nanocrystal-semiconductor film). The nc-OS film is called a line oxide semiconductor (nc-OS) film. For example, in high-resolution TEM images, it may not be possible to clearly identify grain boundaries. It is possible that the nanocrystals have the same origin as the pellets in the CAAC-OS film. Therefore, hereinafter, the crystalline part of the nc-OS film may be referred to as a pellet.

[0063] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film. For example, an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part for an nc-OS film may be used. When the structure was analyzed using the out-of-plane method, the crystal plane was not shown. In addition, the probe diameter ( For example, electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 50 nm or more. On the other hand, for the nc-OS film, Probe diameter close to or smaller than the size of the crystal part (for example, 1 nm to 30 nm) When nanobeam electron diffraction is performed using an electron beam of nc-O, spots are observed. When nanobeam electron diffraction is performed on an S film, a circular (ring-shaped) area of ​​high brightness is observed. In addition, nanobeam electron diffraction of the nc-OS film shows that phosphorus In some cases, multiple spots may be observed within a cluster-like region (see FIG. 5(B)).

[0064] In this way, the crystal orientation of each pellet (nanocrystal) is not regular. , the nc-OS membrane is RANC (Random Aligned nanocrystals) ) in the oxide semiconductor film.

[0065] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, the crystal orientation is not regular between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0066] Next, the amorphous oxide semiconductor will be described.

[0067] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and does not have crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0068] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0069] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductor, a halo pattern is observed. When nanobeam electron diffraction is performed on the body, no spots are observed, but a halo pattern is observed. will be done.

[0070] There are various views on amorphous structures. For example, A structure that does not have this property is called a completely amorphous structure. In addition, the distance between the nearest neighboring atoms or the second nearest neighboring atoms is called the structure. A structure that has order at the interface and no long-range order is sometimes called an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called a non-crystalline oxide semiconductor. In addition, it cannot be called an crystalline oxide semiconductor. Amorphous oxide semiconductors cannot be called amorphous oxide semiconductors. For example, CAAC-OS and nc-OS can be used as amorphous oxide semiconductors or completely amorphous It cannot be called an oxide semiconductor.

[0071] Note that the oxide semiconductor has a structure that exhibits physical properties between the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor. Body(a-like OS:amorphous-like Oxide Semicon The ductor is called a

[0072] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may not be clearly visible in high-resolution TEM images. There are regions where crystals are visible and regions where no crystals can be seen.

[0073] The following describes how the effect of electron irradiation differs depending on the structure of the oxide semiconductor.

[0074] A-like OS membrane, nc-OS membrane and CAAC-OS membrane were prepared. The material is also an In-Ga-Zn oxide film.

[0075] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0076] In addition, the size of the crystal part of each sample is measured. Figure 45 shows the crystal part of each sample (22 places). This is an example of investigating the change in the average size of a-like O It can be seen that the crystal part of the S film grows larger according to the cumulative amount of electron irradiation. As shown by (1) in Figure 45, in the early stages of TEM observation, the size of the particles was approximately 1.2 nm. The crystal part (also called the initial nucleus) that was the same size as the initial nucleus was irradiated with a cumulative dose of 4.2 × 10 8 e - / nm 2 To In the case of the nc-OS film, the size of the nanocrystals grows to about 2.6 nm. The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 No change in the size of the crystals was observed regardless of the cumulative electron irradiation dose until Specifically, as shown in (2) in Figure 45, the TEM observation Regardless of the size, the size of the crystals is about 1.4 nm. As shown in Fig. 1, the size of the crystals was about 2.1 nm regardless of the TEM observation process. I realize something.

[0077] Thus, the a-like OS film can be observed by irradiating it with a small amount of electrons, which is the same as that observed by a TEM. In some cases, crystallization occurs and the growth of crystals can be seen. In the case of CAAC-OS films, crystallization by electron irradiation of a small amount, which is comparable to that observed by TEM, was observed. is found to be almost invisible.

[0078] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution This can be done using TEM images. For example, InGaZnO4 crystals have a layered structure. InGaZnO4, there are two Ga-Zn-O layers between the In-O layers. The device has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned along the c-axis. It has a layered structure. Therefore, the spacing between adjacent layers is (009) The lattice spacing (also called the d value) of m. Therefore, focusing on the lattice fringes in the high-resolution TEM image, In the area where the spacing is 0.28 nm or more and 0.30 nm or less, each lattice fringe is In It corresponds to the ab plane of the GaZnO4 crystal.

[0079] In addition, the density of oxide semiconductors may differ depending on the structure. Once the composition of the crystal is known, it can be determined by comparing it with the density of a single crystal of the same composition. For example, the density of a single crystal can be estimated by The density of the ke OS film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film is 92.3% or more and 100% or less. Note that an oxide semiconductor having a density of less than 78% of that of a single crystal can be formed by deposition. It is difficult to do so.

[0080] The above will be explained using a specific example. For example, In the oxide semiconductor that satisfies the [atomic ratio], single crystal InGaZnO4 with a rhombohedral crystal structure The density of is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1 In the case of an oxide semiconductor that satisfies the atomic ratio, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1:1 In oxide semiconductors that satisfy the [atomic ratio], the density of the nc-OS film and the CAAC-OS The density of the film is 5.9g / cm 3 More than 6.3g / cm 3 It will be less than.

[0081] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density corresponding to the single crystal of the desired composition can be calculated. The density of a single crystal of a desired composition varies with the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate the above in combination.

[0082] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a micro- The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film. .

[0083] When an oxide semiconductor film has multiple structures, the structures can be resolved by using nanobeam electron diffraction. In some cases, analysis may be possible.

[0084] FIG. 5C shows an electron gun chamber 310, an optical system 312 below the electron gun chamber 310, and an optical system 313 below the electron gun chamber 310. 2, a sample chamber 314 under the sample chamber 314, an optical system 316 under the sample chamber 314, and an observation under the optical system 316. a room 320, a camera 318 installed in the observation room 320, and a film room below the observation room 320. The transmission electron diffraction measurement apparatus shown in FIG. 3 has a camera 318 inside an observation chamber 320. The film chamber 322 does not necessarily have to be provided.

[0085] FIG. 5(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. Inside the electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 310 The light is irradiated onto a substance 328 disposed in a sample chamber 314 via an optical system 312. The electrons passing through the optical system 316 are projected onto a fluorescent screen 332 installed inside the observation chamber 320. On the fluorescent screen 332, a pattern appears according to the intensity of the incident electrons. Electron diffraction patterns can be measured.

[0086] The camera 318 is installed facing the fluorescent screen 332 and captures the pattern that appears on the fluorescent screen 332. The center of the lens of the camera 318 and the center of the fluorescent screen 332 are The angle between the straight line passing through the center and the upper surface of the fluorescent screen 332 is, for example, 15° to 80°. , 30° to 75° or 45° to 70°. The smaller the angle, the The transmission electron diffraction pattern taken by MERA 318 is highly distorted. If the angle is known, it is possible to correct distortions in the obtained transmission electron diffraction pattern. There are cases where the camera 318 may be installed in the film chamber 322. For example, The camera 318 is installed in the film chamber 322 so as to face the direction of incidence of the electrons 324. In this case, a transmission electron diffraction pattern with little distortion is captured from the rear surface of the fluorescent screen 332. It is possible.

[0087] In the sample chamber 314, a holder for fixing a substance 328 which is a sample is installed. The holder is constructed to be transparent to electrons passing through the material 328. For example, the holder may have a function of moving the substance 328 in the X-axis, Y-axis, Z-axis, etc. The movement function may be, for example, 1 nm to 10 nm, 5 nm to 50 nm, or 10 nm or more. In ranges such as 100nm or less, 50nm to 500nm, 100nm to 1μm, etc. These ranges are optimal ranges depending on the structure of the substance 328. Just set it as:

[0088] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0089] For example, as shown in FIG. 5(D), the irradiation position of the electron 324, which is a nanobeam, in the material By changing (scanning) the temperature, it is possible to observe how the structure of a substance changes. In this case, if the material 328 is a CAAC-OS film, the following can be obtained: If the material 328 is an nc-OS film, the diffraction pattern is shown in Fig. 5(B). The diffraction pattern shown is observed.

[0090] By the way, even if the material 328 is a CAAC-OS film, it is partially an nc-OS film. Therefore, the quality of the CAAC-OS film can be evaluated. It may be possible to express it as the CAAC ratio. The ratio of the area where the diffraction pattern of the OS film is observed, i.e., the transmittance as shown in Fig. 5(A), is This refers to the percentage of the area where spots (bright points) showing orientation can be seen in electron diffraction measurements. The oxide semiconductor film 17 shown in the embodiment is one-dimensionally measured by a transmission electron diffraction measurement device. When the observation point was changed in the range of 0 nm, the CAAC conversion rate was 70% or more but less than 100%, Preferably, the ratio is 80% or more and less than 100%, more preferably 90% or more and less than 100%, and even more preferably That is, the oxide semiconductor film shown in this embodiment has a region in which the oxide semiconductor film has a conductivity of 95% or more and 98% or less. The oxide semiconductor film 17 has a low impurity concentration and a low density of defect states. The ratio of the area in which a diffraction pattern different from that of the CAAC-OS film was observed was defined as the ratio of the area in which a diffraction pattern different from that of the non-CAAC-OS film was observed. This is expressed as C rate.

[0091] As the oxide semiconductor film 17, an oxide semiconductor film with low carrier density is used. For example, The oxide semiconductor film 17 has a carrier density of 1×10 17 pieces / cm 3 Less than 1x1 0 15 pieces / cm 3 less than 1×10 13 pieces / cm 3 Less than 100%, more preferably 1×10 11 pieces / cm 3 An oxide semiconductor film having a thickness of less than 100 nm is used.

[0092] The oxide semiconductor film 17 is an oxide semiconductor film having a low impurity concentration and a low density of defect states. By using this, a transistor having excellent electrical characteristics can be manufactured. Here, the low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or substantially high purity intrinsic. Conductors have fewer carrier generation sources, so the carrier density can be reduced. The -OS film and the nc-OS film are more excellent than the a-like OS film and the amorphous oxide semiconductor film. The impurity concentration is low and the defect level density is low. Therefore, the CAAC-OS film or the nc-OS film is used. The transistors used in this study have electrical characteristics in which the threshold voltage is negative (also called normally-on). In addition, the oxide semiconductors that are high purity intrinsic or substantially high purity intrinsic are The membrane has few carrier traps and is pure or substantially pure. The oxide semiconductor film has a remarkably small off-state current and a large voltage between the source and drain electrodes (the drain The off-state current is measured at a voltage between 1V and 10V. below the measurement limit, i.e. 1×10 -13 A characteristic of less than A can be obtained. The transistors using the CAAC-OS film or the nc-OS film have small fluctuations in electrical characteristics. In addition, when the carrier is trapped in the carrier trap in the oxide semiconductor film, the transistor has high reliability. The charge that is stored in the electrode takes a long time to be discharged and behaves like a fixed charge. Therefore, the channel is formed in an oxide semiconductor film having a high impurity concentration and a high density of defect states. The transistor in which the region is formed may have unstable electrical characteristics.

[0093] The thickness of the oxide semiconductor film 17 is 3 nm to 200 nm, preferably 3 nm to 10 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0094] The configuration of the transistor 10 will be described in detail below.

[0095] There is no particular restriction on the material of the substrate 11, but it should be at least strong enough to withstand the subsequent heat treatment. It is necessary to have heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, surface treatment substrate, etc. A fiber substrate or the like may be used as the substrate 11. In addition, silicon, silicon carbide, etc. may be used. A single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound of silicon germanium, etc. It is also possible to use a semiconductor substrate, an SOI substrate, etc., on which a semiconductor element is formed. The substrate 11 may be a glass substrate. When used, 6th generation (1500mm x 1850mm), 7th generation (1870mm x 22 00mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 28 By using large area substrates such as 1000mm and 10th generation (2950mm x 3400mm), Therefore, a large display device can be manufactured.

[0096] In addition, a flexible substrate is used as the substrate 11, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 11 and the transistor 10. The layer is separated from the substrate 11 after a semiconductor device is partially or completely completed thereon, and then the layer is removed. In this case, the transistor 10 is placed on a substrate having poor heat resistance. It can also be transferred to a plate or flexible substrate.

[0097] The gate electrode 13 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above-mentioned metal elements, It can be formed by using an alloy of a combination of metal elements. The metal element may be selected from one or more of the following: The electrode 13 may have a single-layer structure or a laminated structure of two or more layers. Single layer structure of aluminum film, double layer structure of aluminum film laminated on titanium film, titanium nitride Two-layer structure with a titanium film laminated on a titanium nitride film, and two-layer structure with a tungsten film laminated on a titanium nitride film. A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. A two-layer structure in which a copper film is laminated on a titanium film, and a titanium film and an aluminum film are laminated on the titanium film. There are three-layer structures, such as a titanium film on top of the laminated aluminum. Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film containing one or more of the above elements or a nitride film may be used.

[0098] The gate electrode 13 is made of indium tin oxide (hereinafter, also referred to as ITO), tungsten oxide, etc. Indium oxide with tungsten oxide, indium zinc oxide with tungsten oxide, Indium oxide containing titanium, indium tin oxide containing titanium oxide, indium zinc Conductive materials with light transmission properties such as indium tin oxide or silicon oxide doped indium tin oxide are suitable. In addition, a laminate structure of the conductive material having light transmitting properties and the metal element may be used. It can also be written as:

[0099] The gate insulating film 15 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn metal An oxide, a silicon nitride, or the like may be used, and the insulating film is provided as a laminated layer or a single layer.

[0100] The gate insulating film 15 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium minate (HfAlx O y N z ), hafnium oxide, yttrium oxide and other high- The use of k-materials can reduce the gate leakage of transistors.

[0101] The thickness of the gate insulating film 15 is 5 nm or more and 400 nm or less, and more preferably 10 nm or more. It is preferably 300 nm or less, and more preferably 50 nm or more and 250 nm or less.

[0102] The pair of electrodes 19, 20 is made of aluminum, titanium, chromium, nickel, copper, yttrium, elemental metals consisting of aluminum, zirconium, molybdenum, silver, tantalum, or tungsten; Or an alloy containing this as a main component is used as a single layer structure or a laminate structure. A single-layer structure of an aluminum film containing titanium, a two-layer structure of an aluminum film laminated on a titanium film, Two-layer structure with aluminum film laminated on tungsten film, copper-magnesium-aluminum Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, tungsten A two-layer structure in which a copper film is laminated on a titanium film, a titanium film or titanium nitride film, and a titanium film or In the method, an aluminum film or a copper film is laminated on a titanium nitride film, and a titanium film is further laminated on the aluminum film or a copper film. Or a three-layer structure forming a titanium nitride film, a molybdenum film or a molybdenum nitride film, and An aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and There is also a three-layer structure in which a molybdenum film or a molybdenum nitride film is formed on top of the above. Transparent conductive materials including indium oxide, tin oxide or zinc oxide may also be used.

[0103] The gate insulating film 28 is formed by stacking the oxide insulating film 23 and the oxide insulating film 2 3 and a nitride insulating film 27 in contact with the oxide insulating film 25. The gate insulating film 28 is made of an oxide film containing more oxygen than the oxygen required for the stoichiometric composition. Here, the oxide insulating film 23 is preferably an oxygen-permeable insulating film. The oxide insulating film 25 is formed by using an oxide insulating film having a stoichiometric composition. An oxide insulating film containing a large amount of oxygen is formed, and hydrogen and oxygen are removed as the nitride insulating film 27. In this embodiment, the gate insulating film 28 is formed as a three-layer structure. However, it may be one layer, two layers, or four or more layers. At least, the oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. is preferred.

[0104] The oxide insulating film 23 is an oxide insulating film that transmits oxygen. The oxygen desorbed from the oxide insulating film 25 provided on the oxide insulating film 23 is absorbed through the oxide insulating film 23. The oxide insulating film 23 can be moved to the oxide semiconductor film 17. It also functions as a film for reducing damage to the oxide semiconductor film 17 when the oxide insulating film 25 is formed. do.

[0105] The oxide insulating film 23 has a thickness of 5 nm to 150 nm, preferably 5 nm or more. A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 50 nm or less can be used. In the present specification, a silicon oxynitride film is a film having a higher oxygen content than nitrogen as a composition. A silicon nitride oxide film is a film that contains more nitrogen than oxygen. Refers to a large amount of membrane.

[0106] In addition, it is preferable that the oxide insulating film 23 has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 3×10 17 spins / cm 3 This is because the oxide insulation If the film 23 contains a large number of defects, oxygen will be bonded to the defects, and the oxide insulating film 2 This is because the amount of oxygen permeating through 3 decreases.

[0107] In addition, the number of defects at the interface between the oxide insulating film 23 and the oxide semiconductor film 17 is small. Preferably, typically, the g value derived from defects in the oxide semiconductor film 17 is determined by ESR measurement. The spin density of the signal appearing between 1.89 and 1.96 is 1×10 17 spins / cm 3 It is preferably less than the lower limit of detection.

[0108] Note that in the oxide insulating film 23, all of the oxygen that has entered the oxide insulating film 23 from the outside is In some cases, the oxide insulating film 23 may move to the outside. In some cases, part of the oxygen remains in the oxide insulating film 23. As oxygen enters the oxide insulating film 23, the oxygen contained in the oxide insulating film 23 flows out of the oxide insulating film 23. The movement of oxygen may cause the movement of oxygen in the oxide insulating film 23 in some cases.

[0109] An oxide insulating film 25 is formed so as to be in contact with the oxide insulating film 23. The fifth embodiment is formed using an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is heated to remove the oxygen. A part of the element is released. The oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. TDS (Thermal Desorption Spectroscopy) analysis The amount of oxygen released is 1.0×10 18 atoms / cm 3 Below Above, preferably 3.0 x 10 20 atoms / cm 3 The oxide insulating film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower, or The range of 100°C or more and 500°C or less is preferred.

[0110] The oxide insulating film 25 has a thickness of 30 nm to 500 nm, preferably 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or more and 400 nm or less can be used.

[0111] In addition, it is preferable that the oxide insulating film 25 has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the oxide insulating film 25 has a thickness smaller than that of the oxide insulating film 23. Since the oxide semiconductor film 17 is away from the oxide insulating film 23, the defect density may be higher than that of the oxide insulating film 23. stomach.

[0112] The nitride insulating film 27 has at least a blocking effect against hydrogen and oxygen. In particular, it is preferable to use a material having a blocking effect against oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the nitride insulating film 27 on the gate insulating film 28, the oxide semiconductor film 17 Prevents the diffusion of oxygen from the inside to the outside and prevents the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 17. It is possible.

[0113] The nitride insulating film 27 has a thickness of 50 nm to 300 nm, preferably 100 nm. m or more and less than 200 nm, silicon nitride, silicon oxynitride, aluminum nitride, and oxynitride Examples include aluminum oxide.

[0114] In place of the nitride insulating film 27, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be used. An oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples include aluminum oxide, aluminum oxynitride, gallium oxide, and gallium oxynitride. , yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. be.

[0115] The electrode 32 is formed using a light-transmitting conductive film. The light-transmitting conductive film is an indium tin film. Oxide, indium zinc oxide, indium oxide with tungsten oxide, tungsten oxide Indium zinc oxide containing tin, indium oxide containing titanium oxide, titanium oxide Indium tin oxide containing silicon oxide, indium tin oxide containing silicon oxide, etc.

[0116] Next, a method for manufacturing the transistor 10 shown in FIG. 1 will be described with reference to FIGS. 6 to 8, the cross-sectional view in the channel length direction shown by AB in FIG. 1 and 2 show cross-sectional views in the channel width direction shown in FIG.

[0117] Films constituting the transistor 10 (insulating film, oxide semiconductor film, metal oxide film, conductive film, etc.) The methods include sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulsed laser deposition ( It can be formed by using the PLD method. Alternatively, it can be formed by coating or printing. The deposition method includes sputtering and plasma enhanced chemical vapor deposition (PECVD). is a typical example, but thermal CVD may also be used. An example of the thermal CVD method is MOCVD (metal organic chemical vapor deposition). Chemical vapor deposition (CVD) and ALD (Atomic Layer Deposition) methods may also be used.

[0118] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0119] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating the gas introduction sequence. For example, By switching between the switching valves (also called high-speed valves), two or more types of raw materials can be mixed. The gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the multiple source gases. At the same time or after this, an inert gas (argon, nitrogen, etc.) is introduced to If an inert gas is introduced at the same time, the inert gas acts as a carrier gas. In addition, an inert gas may be introduced at the same time as the second raw material gas is introduced. In addition, instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first monoatomic layer. The second monolayer is formed on the first monolayer by reacting with the second source gas introduced later. A thin film is formed by laminating the above.

[0120] This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. This allows precise film thickness adjustment, making it possible to fabricate minute transistors. It is suitable for fabrication.

[0121] As shown in FIG. 6(A), a conductive film 12 that will later become a gate electrode 13 is formed on a substrate 11. Complete.

[0122] Here, a glass substrate is used as the substrate 11.

[0123] The conductive film 12 can be formed by a sputtering method, a vacuum deposition method, a pulsed laser deposition (PLD) method, or a thermal It is formed by the CVD method or the like.

[0124] In addition, a tungsten film can be formed using a film formation device that uses ALD. In this case, WF6 gas and B2H6 gas are introduced in sequence to form the initial tungsten film. Then, WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. SiH4 gas may be used in place of B2H6 gas.

[0125] Here, a tungsten film having a thickness of 100 nm is formed as the conductive film 12 by sputtering. More forming.

[0126] Next, a mask is formed on the conductive film 12 by a photolithography process using a first photomask. Next, a part of the conductive film 12 is etched using the mask to form a gate electrode. 13 is formed. After that, the mask is removed (see FIG. 6(B)).

[0127] The method for etching a part of the conductive film 12 may be a wet etching method or a dry etching method. One or both of these methods can be used.

[0128] Here, a mask is formed by a photolithography process, and the conductive film is The gate electrode 13 is formed by dry etching the film 12 .

[0129] The gate electrode 13 may be formed by electrolytic plating, printing, ink jet printing, or the like instead of the above-mentioned method. It may be formed by a jet method or the like.

[0130] Next, as shown in FIG. 6(C), a gate insulating film is formed on the substrate 11 and the gate electrode 13. An insulating film 14 that will become an insulating film 15 is formed, and a layer that will later become an oxide semiconductor film 17 is formed on the insulating film 14. An oxide semiconductor film 16 is formed.

[0131] The insulating film 14 can be formed by sputtering, CVD, vacuum deposition, pulsed laser deposition (PL D) method, thermal CVD method, etc.

[0132] The insulating film 14 is a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. When forming the film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and tetrasilane. Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and Nitric oxide, etc.

[0133] When a gallium oxide film is formed as the insulating film 14, MOCVD (Metal Orga The film is formed using the NIC Chemical Vapor Deposition method. This can be done.

[0134] The insulating film 14 is formed by a thermal CVD method such as MOCVD or ALD. To form a hafnium film, a liquid containing a solvent and a hafnium precursor compound (hafnium Alkoxide solution, typically tetrakisdimethylamidohafnium (TDMAH) Two types of gases are used: vaporized raw gas and ozone (O3) as an oxidizing agent. The chemical formula for trachysdimethylamidohafnium is Hf[N(CH3)2]4. Other liquid materials include tetrakis(ethylmethylamido)hafnium.

[0135] The insulating film 14 is formed by depositing an oxidized aluminum film using a thermal CVD method such as MOCVD or ALD. When forming an aluminum film, a liquid containing a solvent and an aluminum precursor compound (trimethylsilyl) is used. Two types of gas are used: vaporized ethyl aluminum (TMA) and H2O as an oxidizer. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionato) Examples include:

[0136] The insulating film 14 is formed by a thermal CVD method such as MOCVD or ALD. When forming a silicon film, hexachlorodisilane is adsorbed onto the surface to be filmed, and the adsorbed material contains It removes chlorine contained in the adsorbent and supplies radicals of oxidizing gases (O2, nitrous oxide) to the adsorbent. Make it react.

[0137] The oxide semiconductor film 16 is formed by sputtering, pulsed laser deposition, laser ablation, or the like. The film can be formed by a deposition method, a thermal CVD method, or the like.

[0138] When the oxide semiconductor film 16 is formed by a sputtering method, a plasma generating device is used. The power supply may be an RF power supply, an AC power supply, a DC power supply, or the like.

[0139] The sputtering gas is a rare gas (typically argon), oxygen gas, or a rare gas and oxygen. In the case of a mixed gas of rare gas and oxygen, the amount of oxygen relative to the rare gas is appropriately adjusted. It is preferable to increase the ratio of the nitrogen gas to the nitrogen gas.

[0140] The target may be appropriately selected depending on the composition of the oxide semiconductor film 16 to be formed. good.

[0141] In addition, the oxide semiconductor film 16 is preferably formed while the substrate is heated. 120°C or more and less than 600°C, preferably 150°C or more and less than 450°C, preferably 150 C. or higher and lower than 350.degree. C., preferably 150.degree. C. or higher and lower than 250.degree. C., while heating the oxide semiconductor film 1 By forming the CAAC-OS 6, the oxide semiconductor film 16 includes a plurality of crystal parts. This is preferable because it forms a film.

[0142] In order to obtain a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film 16, Not only is it necessary to evacuate the inside of the chamber to a high vacuum, but it is also necessary to highly purify the sputtering gas. The oxygen gas and argon gas used as the gas source have a dew point of -40°C or less, preferably -80°C or less. More preferably, the temperature is reduced to below -100°C, and even more preferably to below -120°C. By using the gas, it is possible to prevent moisture and the like from being taken into the oxide semiconductor film 16 as much as possible. This can be done.

[0143] The deposition equipment using ALD can be used to form oxide semiconductor films, such as InGaZnO X (X>0) When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form InO Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gas are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, the InGaO2 layer InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. It is also possible to use H obtained by bubbling an inert gas such as Ar instead of O3 gas. Although O gas may be used, it is preferable to use O gas that does not contain H. Instead of the CH3)3 gas, In(C2H5)3 gas may be used. Ga(C2H5)3 gas may be used instead of Zn(CH3)2 gas. A suction cup may also be used.

[0144] Here, an In-Ga-Zn oxide target (In:Ga:Zn=3:1:2) was used. The oxide semiconductor film 16 was formed by sputtering with a thickness of 35 nm. The n-oxide film is formed by evaporating the gas at a substrate temperature of 170° C. under argon gas containing 50 vol% oxygen. The gas is used as a sputtering gas.

[0145] Next, a photolithography process using a second photomask is performed on the oxide semiconductor film 16. After forming a mask, a part of the oxide semiconductor film 16 is etched using the mask. By this, an oxide semiconductor film 17 with isolated elements is formed. After that, the mask is removed ( See Figure 6(D).

[0146] The method for etching a part of the oxide semiconductor film 16 may be a wet etching method, a dry etching method, or the like. One or both of these methods can be used.

[0147] Here, a mask is formed by a photolithography process, and the mask is used to form an oxide The semiconductor film 16 is wet etched to form an oxide semiconductor film 17 .

[0148] After this, heating is performed at a temperature higher than 350°C and lower than 650°C, preferably at a temperature higher than 450°C and lower than 600°C. As a result, a transmission electron diffraction measurement device was used to measure the one-dimensional area of ​​300 nm. When the observation point is changed, the CAAC conversion rate is 70% or more but less than 100%, preferably 80% or less. % or more and less than 100%, preferably 90% or more and less than 100%, more preferably 95% or more and less than 90%. In addition, the oxide semiconductor film 17 can be obtained with a low content of hydrogen, water, or the like. In other words, it is possible to obtain the oxide semiconductor film 17 having a low impurity concentration and a low defect density. An oxide semiconductor film with a low density of defect states can be formed.

[0149] Note that the heat treatment is performed after the oxide semiconductor film 16 is formed and after the second phototransistor is formed. This may be performed before the photolithography process using a mask.

[0150] Next, as shown in FIG. 7(A), a conductive film 18 which will later become a pair of electrodes 19 and 20 is formed. do.

[0151] The conductive film 18 can be formed by sputtering, vacuum deposition, pulsed laser deposition (PLD), or thermal deposition. It is formed by the CVD method etc.

[0152] Here, a 50 nm thick tungsten film and a 300 nm thick copper film are sputtered in sequence. The conductive film 18 is formed by laminating the layers using a ring method.

[0153] Next, a mask is formed on the conductive film 18 by a photolithography process using a third photomask. Next, the conductive film 18 is etched using the mask to form a pair of electrodes 19 and 20 is formed. After that, the mask is removed (see FIG. 7(B)).

[0154] Here, a mask is formed over the conductive film 18 by a photolithography process. The tungsten film and the copper film are dry-etched using the mask to form a pair of electrodes 19, First, the copper film is etched using a wet etching method, Next, the tungsten film is etched by dry etching using SF6. During the etching, fluoride is formed on the surface of the copper film. The diffusion of copper elements from the oxide semiconductor film 17 is reduced, and the copper concentration in the oxide semiconductor film 17 is reduced. can.

[0155] Next, as shown in FIG. 8A, a semiconductor layer 17 and a pair of electrodes 19 and 20 are The oxide insulating film 22 which will later become the oxide insulating film 23 and the oxide insulating film 25 which will later become the oxide insulating film 26 are A compound insulating film 24 is formed.

[0156] After the oxide insulating film 22 is formed, the oxide insulating film 2 is continuously removed without being exposed to the air. After the oxide insulating film 22 is formed, the source gas The oxide insulating film 24 is continuously formed by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature. By forming the oxide insulating film 22 and the oxide insulating film 24 in a non-uniform manner, the air components at the interface between the oxide insulating film 22 and the oxide insulating film 24 are prevented from In addition, the concentration of impurities derived from the oxide insulating film 24 can be reduced. The amount of oxygen vacancies in the oxide semiconductor film 17 can be reduced. It can be reduced.

[0157] The oxide insulating film 22 is placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is maintained at a temperature of 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber. The pressure in the chamber is set to 20 Pa or more and 250 Pa or less, and more preferably 100 Pa or more and 250 Pa or less. Under the conditions below, a silicon oxide film is formed by supplying high frequency power to an electrode provided in the processing chamber. Alternatively, a silicon oxynitride film can be formed.

[0158] The source gas for the oxide insulating film 22 is a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane and disilane. , trisilane, fluorinated silane, etc. Oxidizing gases include oxygen, ozone, dinitrogen monoxide, etc. Examples include nitrogen dioxide and nitrogen oxide.

[0159] By using the above conditions, an oxide insulating film that transmits oxygen is formed as the oxide insulating film 22. In addition, by providing the oxide insulating film 22, the oxide insulating film to be formed later can be formed. In the formation process of 25, damage to the oxide semiconductor film 17 can be reduced.

[0160] The oxide insulating film 22 is placed in a processing chamber of a plasma CVD apparatus that has been evacuated to a vacuum. The substrate is maintained at a temperature of 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber. The pressure in the treatment chamber is set to 20 Pa or more and 250 Pa or less, and high frequency power is applied to the electrode installed in the treatment chamber. Depending on the conditions of supply, the oxide insulating film 22 may be a silicon oxide film or a silicon oxynitride film. A film can be formed.

[0161] Under the film formation conditions, by setting the substrate temperature to the above temperature, the bond between silicon and oxygen As a result, the oxide insulating film 22 is oxygen-permeable, dense, and hard. A thin oxide insulating film, typically etched using 0.5% by weight hydrofluoric acid at 25°C. A silicon oxide film having a chipping rate of 10 nm / min or less, preferably 8 nm / min or less. A silicon oxynitride film can be formed.

[0162] In addition, in order to form the oxide insulating film 22 while heating, hydrogen, When water or the like is contained in the oxide semiconductor film 17, hydrogen, water, or the like is released from the oxide semiconductor film 17 in this step. The hydrogen contained in the oxide semiconductor film 17 can be converted into oxygen generated in the plasma. The oxide insulating film 22 is formed by heating the substrate. Therefore, water generated by the bond between oxygen and hydrogen is released from the oxide semiconductor film 17. That is, by forming the oxide insulating film 22 by the plasma CVD method, the oxide semiconductor film The water and hydrogen content in 17 can be reduced.

[0163] In addition, since heating is performed in the process of forming the oxide insulating film 22, the oxide semiconductor film 17 The heating time in an exposed state is short, and oxygen is released from the oxide semiconductor film by heat treatment. That is, the amount of oxygen vacancies in the oxide semiconductor film 17 can be reduced. It is possible.

[0164] In addition, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film 22 When forming the oxide semiconductor film 17, damage to the oxide semiconductor film 17 can be reduced. In particular, the amount of oxygen vacancies in the oxide insulating film 22 can be reduced. Alternatively, the deposition temperature of the oxide insulating film 24 to be formed later is increased, typically to 220° C. or higher. By setting the temperature at a low level, part of oxygen contained in the oxide semiconductor film 17 is released, and oxygen vacancies are formed. In addition, in order to improve the reliability of the transistor, the oxide insulating film 2 to be formed later is By using the film formation conditions for reducing the amount of defects in 4, the amount of oxygen desorption is easily reduced. As a result, it may be difficult to reduce oxygen vacancies in the oxide semiconductor film 17. The pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less during the formation of the oxide insulating film 22. By reducing damage to the oxide semiconductor film 17 caused by the oxidation of the oxide insulating film 24, the oxide semiconductor film 17 can be easily oxidized. The oxygen vacancies in the oxide semiconductor film 17 can be reduced by the amount of oxygen desorption.

[0165] In addition, by increasing the amount of oxidizing gas to 100 times or more the amount of deposition gas containing silicon, It is possible to reduce the hydrogen content in the oxide insulating film 22. Since the amount of hydrogen mixed into the semiconductor film 17 can be reduced, the threshold voltage of the transistor can be reduced. The shift can be suppressed.

[0166] Here, the oxide insulating film 22 is formed by using silane at a flow rate of 30 sccm and SiO2 at a flow rate of 4000 s. The source gas was nitrous oxide (N2O) at 1.0 ccm, the pressure in the processing chamber was 200 Pa, and the substrate temperature was 220° C. A 27.12 MHz high-frequency power source was used to supply 150 W of high-frequency power to the parallel plate electrodes. A silicon oxynitride film with a thickness of 50 nm is formed by the plasma CVD method using the above conditions. In this way, a silicon oxynitride film through which oxygen is transmitted can be formed.

[0167] The oxide insulating film 24 is placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at a temperature of 180° C. or higher and 280° C. or lower, more preferably 200° C. or higher and 240° C. or lower. The raw material gas is introduced into the processing chamber to set the pressure in the processing chamber at 100 Pa or more and 250 Pa or less. More preferably, the pressure is set to 100 Pa or more and 200 Pa or less. .17W / cm 2 More than 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 End 0.35W / cm 2 Under the following conditions of high frequency power supply, silicon oxide film or oxide A silicon nitride film is formed.

[0168] The source gas for the oxide insulating film 24 is a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane and disilane. , trisilane, fluorinated silane, etc. Oxidizing gases include oxygen, ozone, dinitrogen monoxide, etc. Examples include nitrogen dioxide and nitrogen oxide.

[0169] The oxide insulating film 24 is formed under the conditions of high frequency irradiation with the above power density in a reaction chamber with the above pressure. Supplying microwave power increases the efficiency of decomposing the source gas in the plasma, and oxygen radicals are increased. As the source gas is added, the oxidation of the source gas proceeds, so that the oxygen content in the oxide insulating film 24 becomes stoichiometric. On the other hand, in the film formed at the substrate temperature, the composition of silicon and oxygen is Since the bonding strength is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. It contains more oxygen than the stoichiometric composition, and some of the oxygen is released by heating. In addition, the oxide insulating film 2 can be formed over the oxide semiconductor film 17. Therefore, in the process of forming the oxide insulating film 24, the oxide insulating film 2 2 serves as a protective film for the oxide semiconductor film 17. As a result, damage to the oxide semiconductor film 17 is prevented. Therefore, the oxide insulating film 24 can be formed by using high-frequency power with high power density while reducing the Cut.

[0170] Here, the oxide insulating film 24 is made of silane at a flow rate of 200 sccm and SiO2 at a flow rate of 4000 The source gas was dinitrogen monoxide at a flow rate of 200 sccm. The pressure in the reaction chamber was set at 200 Pa and the substrate temperature at 220 ℃, and a 27.12MHz high-frequency power source was used to apply 1500W of high-frequency power to parallel plate electrodes. A silicon oxynitride film having a thickness of 400 nm is formed by plasma CVD using a gas supplied to the substrate. The plasma CVD device has an electrode area of ​​6000 cm 2 Parallel plate plasma CV D equipment, and the power supplied is converted to power per unit area (power density) of 0.25 W / cm 2 It is.

[0171] Next, a heat treatment is performed. The temperature of the heat treatment is typically 150° C. or higher and 400° C. or lower. The temperature is preferably 300°C or higher and 400°C or lower, and more preferably 320°C or higher and 370°C or lower.

[0172] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0173] Heat treatment is carried out in a vacuum of nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably 1 ppm). pm or less, preferably 10 ppb or less air), or rare gases (argon, helium, etc.) In addition, the above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas may be mixed with hydrogen, water, or the like. It is preferable that the above is not included.

[0174] By the heat treatment, part of oxygen contained in the oxide insulating film 24 is transferred to the oxide semiconductor film 17. By moving the oxygen vacancies, the amount of oxygen vacancies in the oxide semiconductor film 17 can be further reduced.

[0175] When the oxide insulating film 22 and the oxide insulating film 24 contain water, hydrogen, or the like, After forming the nitride insulating film 26 having the function of blocking elements, etc., a heat treatment is performed. The water, hydrogen, and the like contained in the oxide insulating film 22 and the oxide insulating film 24 are 7, and defects are generated in the oxide semiconductor film 17. By performing this before the formation of the nitride insulating film 26, the oxide insulating film 22 and the oxide insulating film 24 It is possible to remove water, hydrogen, etc. contained in the semiconductor material, and the electrical characteristics of the transistor 10 are improved. This can reduce the variation in the threshold voltage and suppress the fluctuation in the threshold voltage.

[0176] The oxide insulating film 24 is formed on the oxide insulating film 22 while being heated. By moving oxygen to the oxide semiconductor film 17, oxygen vacancies contained in the oxide semiconductor film 17 are reduced. Therefore, the heat treatment may not be performed.

[0177] Here, a heat treatment is performed using nitrogen and oxygen at 350° C. for 1 hour.

[0178] In addition, when forming the pair of electrodes 19 and 20, the conductive film is etched to form an oxide semiconductor. The oxide semiconductor film 17 is damaged, and the back channel of the oxide semiconductor film 17 ( In this case, oxygen vacancies occur on the surface opposite to the surface facing the gate electrode 13. The oxide insulating film 24 contains more oxygen than the oxygen that satisfies the stoichiometric composition. By applying this method, it is possible to reduce the oxygen vacancies that occur on the back channel side due to heat treatment. This makes it possible to improve the reliability of the transistor 10.

[0179] Next, sputtering, CVD, thermal CVD, vacuum deposition, pulsed laser deposition ( A nitride insulating film 26, which will later become a nitride insulating film 27, is formed by a photolithography (PLD) method or the like.

[0180] When the nitride insulating film 26 is formed by the plasma CVD method, the The substrate placed in the evacuated processing chamber is heated to 300° C. or higher and 400° C. or lower, more preferably A temperature of 320° C. or higher and 370° C. or lower is preferable because a dense nitride insulating film can be formed. stomach.

[0181] When a silicon nitride film is formed as the nitride insulating film 26 by the plasma CVD method, the silicon It is preferable to use a deposition gas containing carbon, nitrogen, and ammonia as a source gas. By using a small amount of ammonia as the source gas compared to nitrogen, the amount of ammonia in the plasma is reduced. The monium oxide dissociates and generates active species. The active species are contained in the deposition gas containing silicon. This breaks the silicon and hydrogen bonds and the nitrogen triple bonds. The bonding of silicon and nitrogen is promoted, resulting in fewer silicon and hydrogen bonds, fewer defects, and a dense structure. On the other hand, the amount of ammonia in the source gas is small compared to that of nitrogen. If the amount of silicon is large, the decomposition of the deposition gas containing silicon and nitrogen does not proceed well, and silicon is The silicon nitride film is rough and has many defects due to the residual hydrogen bonds and the residual densities. For these reasons, the flow rate ratio of nitrogen to ammonia in the raw gas is set at 5. It is preferable to set the value to 50 or less, and more preferably to 10 or more and 50 or less.

[0182] Here, silane at a flow rate of 50 sccm and 5000 The raw gases were nitrogen at a flow rate of 100 sccm and ammonia at a flow rate of 100 sccm. The pressure in the processing chamber was The pressure was set to 100 Pa, the substrate temperature was set to 350°C, and a 27.12 MHz high frequency power supply was used for 100 A nitride insulating film was formed by plasma CVD using a 1000W high-frequency power supplied to parallel plate electrodes. A silicon nitride film with a thickness of 50 nm is formed by the plasma CVD apparatus. The height is 6000cm 2 It is a parallel plate type plasma CVD device, and the supplied power is expressed as a unit. This translates to 1.7 x 10 power per area (power density). -1 W / cm 2 It is.

[0183] Through the above steps, the oxide insulating film 22, the oxide insulating film 24, and the nitride insulating film 26 are formed. It can be formed.

[0184] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher and 40° C. or lower. 0°C or lower, preferably 300°C or higher and 400°C or lower, preferably 320°C or higher and 370°C or lower Let us assume that.

[0185] Next, a fourth photomask is used to form a photoresist film on the nitride insulating film 26. After forming a mask, the oxide insulating film 22, the oxide insulating film 24, and The oxide insulating film 23 and the nitride insulating film 26 are partially etched to form the oxide insulating film 23 and the nitride insulating film 26. The oxide insulating film 23, the oxide insulating film 25, and the nitride insulating film 27 are formed. , and the nitride insulating film 27 has an opening 41, as shown by AB in FIG. 8(B).

[0186] Next, as shown in FIG. 8(B), a conductive film 30 which will later become an electrode 32 is formed.

[0187] The conductive film 30 is formed by a sputtering method, a CVD method, a vapor deposition method, or the like.

[0188] Here, a 100 nm thick ITO film is formed as the conductive film 30 by sputtering. do.

[0189] Next, a mask is formed on the conductive film 30 by a photolithography process using a fifth photomask. Next, a part of the conductive film 30 is etched using the mask to form an electrode 32. After that, the mask is removed.

[0190] Through the above steps, the transistor 10 can be manufactured. The oxide semiconductor film has a high CAAC ratio, so it has excellent electrical properties. is high.

[0191] <Variation 1> In the method for manufacturing the transistor 10, a pair of electrodes 19 and 20 and an oxide semiconductor film 1 7, using a halftone mask (or a graytone mask, a phase difference mask, etc.) By forming the masks, the number of masks and the number of process steps can be reduced. The resist mask for forming the oxide semiconductor film 17 is removed by ashing, etc. A resist mask is formed for forming a pair of electrodes 19 and 20. An oxide semiconductor film 17 is always provided under the electrodes 19 and 20. FIG. 38(A) shows a plan view of a transistor 10 produced using halftone. The cross-sectional views are shown in Fig. 38(B) and Fig. 38(C). In other embodiments, By using halftone, an oxide semiconductor film and a pair of electrodes can be formed.

[0192] <Variation 2> In the method for manufacturing the transistor 10, the oxide semiconductor film 17 and the pair of electrodes 19 and 20 An insulating film 29 may be provided between the opening 44 and the insulating film 29 as shown in FIG. In the opening 45, the oxide semiconductor film 17 and the pair of electrodes 19 and 20 are connected. The insulating film 29 is the same as any one of the gate insulating film 15, the oxide insulating film 25, and the nitride insulating film 27. The insulating film 29 can be formed using the above-mentioned material. It may be provided only on the panel area.

[0193] <Modification 3> In the transistor 10 of this embodiment, the oxide semiconductor film 17 and the pair of electrodes 19 In addition, this embodiment mode may be applied to other transistors as appropriate. can be applied.

[0194] The pair of electrodes 19 and 20 provided in the transistor are made of tungsten, titanium, aluminum, etc. Aluminum, copper, molybdenum, chromium, or tantalum alone or in alloys, etc. As a result, the oxygen contained in the oxide semiconductor film 17 and the conductive material that is easy to be used can be The conductive material contained in the pair of electrodes 19 and 20 is bonded to the oxide semiconductor film 17. A pair of electrodes 19 and 20 are formed on the oxide semiconductor film 17. In some cases, some of the constituent elements of the conductive material may be mixed in. As a result, the oxide semiconductor film 17 may have a low conductivity. In this case, a low resistance region is formed in the vicinity of the region in contact with the pair of electrodes 19 and 20. The region is in contact with the pair of electrodes 19 and 20, and is a region between the gate insulating film 15 and the pair of electrodes 19 and 20. The low resistance region is formed between the oxide semiconductor film 17 and the pair of electrodes 1 because of its high conductivity. 9, 20, it is possible to reduce the contact resistance with the It is possible.

[0195] The ends of the low resistance regions 21a and 21b are substantially aligned with the ends of the pair of electrodes 19 and 20. Alternatively, the end of the low resistance region may be located inside the ends of the pair of electrodes 19 and 20. In the case where a low resistance region is formed in the oxide semiconductor film 17, the channel length is This is the distance between the low resistance regions at the interface between the semiconductor film 17 and the gate insulating film 28.

[0196] The pair of electrodes 19 and 20 are made of the conductive material that easily bonds with oxygen, titanium nitride, and nitrogen. Alternatively, the layer structure may be a laminate structure with a conductive material that is difficult to bond with oxygen, such as tantalum chloride or ruthenium. With such a stacked structure, the oxide insulating film 23 and the pair of electrodes 19 and 20 are In this way, it is possible to prevent the pair of electrodes 19 and 20 from being oxidized, and the pair of electrodes 19 and 20 can be highly It is possible to suppress the development of resistance.

[0197] <Film formation model> An example of a deposition model for a CAAC-OS film and an nc-OS film is described below. .

[0198] FIG. 46A shows how a CAAC-OS film is formed by sputtering. FIG.

[0199] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130 through the magnets. The magnetic field is generated by a number of magnets. The magnetic field of the magnets is used to increase the deposition speed. The sputtering method used is called magnetron sputtering.

[0200] The target 5130 has a polycrystalline structure, with each grain including a cleavage plane.

[0201] As an example, the cleavage surface of target 5130 having In-Ga-Zn oxide is described. FIG. 47(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In FIG. 47(A), the c-axis is oriented upward, and the InGaZn This is the structure of an O4 crystal.

[0202] As shown in FIG. 47(A), in two adjacent Ga-Zn-O layers, It can be seen that the oxygen atoms are arranged close to each other. And the oxygen atoms have a negative charge. By this, the two adjacent Ga-Zn-O layers repel each other. A ZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0203] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the deposition chamber is 0.02m or more and 0.5m or less. Most of the deposition gas (e.g., oxygen, argon, or a mixture containing 5% or more by volume of oxygen) and The pressure is controlled to be 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, a discharge starts and a plasma is generated. It is confirmed that a high density plasma region is generated near the target 5130 by the magnetic field. In the high-density plasma region, the deposition gas is ionized, and ions 5101 The ion 5101 is, for example, an oxygen cation (O + ) and argon cations ( Ar + ) etc.

[0204] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually At this time, flat or pellet-shaped sputtered particles are ejected from the cleavage surface. The pellets 5100a and 5100b are peeled off and knocked out. The pellet 5100a and the pellet 5100b are deformed by the impact of the ion 5101. Distortion may occur.

[0205] The pellet 5100a is a flat plate or pellet having a triangular, for example equilateral, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles having a plate-like or pellet-like shape. The term pellets refers to flat or pellet-shaped sputter particles such as pellet 5100b. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon, but may be any shape, e.g. For example, a shape may be formed by combining multiple triangles. In some cases, the shape may be a quadrilateral (for example, a rhombus) made up of two joined sides.

[0206] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason will be explained later. It is preferable that the thickness of the pellet 5100 is uniform. A pellet shape with no lumps is preferable to a thick cube shape. The thickness of the 5100 is 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less. The diameter of the pellet 5100 is 1.2 nm or more and 2.5 nm or less. For example, the target 5 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are collided with the Ga-Zn-O A pellet 5100 having three layers, a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer, pops out. FIG. 47(C) shows the structure of the pellet 5100 when observed from a direction parallel to the c-axis. Therefore, the pellet 5100 has two Ga-Zn-O layers and an In-O layer. , which can also be called a nano-sized sandwich structure.

[0207] The pellet 5100 receives a charge as it passes through the plasma, causing the sides to become negative or The pellet 5100 has oxygen atoms on the side, and the oxygen atoms In this way, the sides can be charged with the same polarity, The loads repel each other, allowing the flat shape to be maintained. When the S film is an In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. It may become electrically charged or may bond with indium, gallium or zinc atoms. The oxygen atoms may become negatively charged. Also, the pellet 5100 may become charged by passing through the plasma. When the compound is bonded to indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc., The difference in size between (2) and (1) in Figure 45 above is the Here, when the substrate 5120 is at room temperature, the pellet 5100 Since the film does not grow any further, it becomes an nc-OS film (see FIG. 46(B)). Since the temperature is about 100°C, it is possible to form an nc-OS film even if the substrate 5120 has a large area. In order to grow the pellet 5100 in plasma, a sputtering method is used. It is effective to increase the film formation power in the pellet 5. 100 structures can be stabilized.

[0208] As shown in FIG. 46(A) and FIG. 46(B), for example, a pellet 5100 is a plasma It flies like a kite through the air and flutters up to the top of the board 5120. Since the pellet 100 is electrically charged, it will be attracted to the area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, a vertical magnetic field (also called a horizontal magnetic field) is generated between the substrate 5120 and the target 5120. Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is on the upper surface of the substrate 5120. Due to the action of the magnetic field and the electric current, a force (Lorentz force) is exerted on the object. This can be understood using Greg's left-hand rule.

[0209] The pellet 5100 has a large mass compared to a single atom. In order to move the surface, it is important to apply some kind of force from the outside. One of these forces is It is possible that the force is generated by the action of a magnetic field and an electric current. In order to increase the force, the upper surface of the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably Alternatively, a region having a resistance of 50 G or more may be provided on the upper surface of the substrate 5120. A magnetic field oriented parallel to the top surface of the plate 5120 is 1. 5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is advisable to provide an area where

[0210] At this time, the magnet unit and the substrate 5120 are not moved relative to each other, and are not rotated. By this, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. Thus, on the upper surface of the substrate 5120, the pellet 5100 is subjected to forces in various directions and is moved in various directions. It can move in various directions.

[0211] Also, when the substrate 5120 is heated as shown in FIG. 0 and the substrate 5120, the resistance due to friction is small. The pellet 5100 glides over the top surface of the substrate 5120. The transfer occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches its side surface, the sides of the pellet 5100 are joined together. The oxygen atoms on the side of 00 are released. The released oxygen atoms cause the Since the oxygen vacancies in the CAAC-OS film may be filled, the CAAC-OS film has a low density of defect states. The temperature of the upper surface of the substrate 5120 is, for example, 100° C. or more and less than 500° C., 150° C. or more and less than 45° C. The temperature may be less than 0° C., or 170° C. or more and less than 400° C. That is, when the substrate 5120 has a large area Even in this case, it is possible to form a CAAC-OS film.

[0212] In addition, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relieved. The pellet 51 with the distortion relieved is shown in FIG. Pellet 5100 is almost a single crystal. Pellet 5100 is almost a single crystal. Even if the 5100 pellets are heated after bonding, the 5100 pellets themselves hardly expand or contract. Therefore, the gaps between the pellets 5100 are widened, and the grain boundaries and other No defects or crevasses will form.

[0213] In addition, the CAAC-OS film is not a single crystal oxide semiconductor plate. The aggregates of Pellet 5100 (Nano Crystals) are like bricks or blocks stacked on top of each other. In addition, there are no grain boundaries between them. Even if the CAAC-OS film shrinks or deforms due to heating or bending after film formation, It is therefore possible to relieve local stress or release distortion. This structure is suitable for semiconductor devices. nc-OS is pellet 5100 (nano crystal). The result is an arrangement that looks like they are stacked in a disorderly manner.

[0214] When the target is sputtered with ions, not only pellets but also zinc oxide and other substances fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And it reaches 0.1nm to 10nm, 0.2nm to 5nm, or 0. A zinc oxide layer 5102 having a thickness of 5 nm or more and 2 nm or less is formed. A schematic cross-sectional view is shown in FIG.

[0215] As shown in FIG. 48(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are deposited. The pellets 5105c and 5105c are arranged so that their sides are in contact with each other. After being deposited on the pellet 5105b, the pellet 510 slides on the pellet 5105b. In another aspect of FIG. 05a, a plurality of particles 51 ejected from the target along with zinc oxide. The substrate 5120 is heated to crystallize the SiO 2 film 5103, forming a region 5105a1. Particles 5103 may include oxygen, zinc, indium, gallium, and the like.

[0216] Then, as shown in FIG. 48(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a2. It is arranged so as to be in contact with another side surface of 105b.

[0217] Next, as shown in FIG. 48(C), a pellet 5105d is further added to the pellet 5105a2. After being deposited on pellet 5105a2 and pellet 5105b, It slides on the pellet 5105b. It also slides toward the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0218] As shown in FIG. 48(D), the pellet 5105d has a side surface similar to that of the pellet 51. The pellet 5105e is placed so that its side is in contact with the pellet 5105a2. Also, the other side of the pellet 5105d is placed in contact with the other side of the pellet 5105c. At the surface, a plurality of particles 5103 that have come out of the target together with zinc oxide are deposited on the substrate 51. By heating at 20, it is crystallized and a region 5105d1 is formed.

[0219] As described above, the piled pellets are arranged so that they come into contact with each other, and the pellets are The growth occurs to form a CAAC-OS film on the substrate 5120. The AAC-OS membrane has larger individual pellets than the nc-OS membrane. The difference in size between (3) and (2) corresponds to the growth that occurred after deposition.

[0220] In addition, the gaps between the pellets 5100 become extremely small, so that one large pellet is formed. The large pellets may have a single crystal structure. The size of the particles is 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, as viewed from the top. Or it may be 20 nm or more and 50 nm or less. When the channel formation region is smaller than the large pellet, a single crystal structure is formed as the channel formation region. In addition, the pellet can be enlarged, so that the size of the transistor can be increased. A region having a single crystal structure is used as the channel forming region, the source region, and the drain region. It may be possible.

[0221] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0222] Based on the above model, it is considered that the pellet 5100 is deposited on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is formed does not have a crystal structure, It can be seen that the CAAC-OS film can be formed even in the case of the substrate 512. Even if the structure of the top surface (formation surface) of C0 is amorphous (e.g., amorphous silicon oxide), It is possible to form an AAC-OS film.

[0223] In addition, the CAAC-OS film can be formed even if the upper surface of the substrate 5120 on which the film is formed is uneven. It can be seen that the pellets 5100 are aligned along the shape of the substrate 5120. If the top surface is atomically flat, the pellet 5100 will have a flat surface that is parallel to the ab plane. If the pellet 5100 has a uniform thickness, it is flat and has a uniform thickness. A layer with high crystallinity is formed. Then, the layer is stacked in n steps (n is a natural number). By this, a CAAC-OS film can be obtained.

[0224] On the other hand, even if the upper surface of the substrate 5120 has an uneven surface, the CAAC-OS film can be formed on the pellet 5 The structure is made up of n layers (n is a natural number) of 100 layers arranged along the unevenness. Since the pellets 5120 have unevenness, the CAAC-OS film is prone to gaps between the pellets 5100. However, the intermolecular forces act between the pellets, so the pellets will stick even if they are uneven. The gaps between the holes are arranged as small as possible. It is possible to obtain a CAAC-OS film having excellent anti-reflection properties.

[0225] Therefore, the CAAC-OS film does not require laser crystallization and can be used on large-area glass substrates. Regardless of the material, a uniform film can be formed.

[0226] Since the CAAC-OS film is formed by this model, the sputtered particles It is preferable that the sputtered particles are in a pellet shape without any thick cubes. In this case, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. There is a match.

[0227] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface having an amorphous structure. Therefore, a CAAC-OS film having excellent optical properties can be obtained.

[0228] Note that the configurations and methods described in this embodiment may be the same as those described in other embodiments. The method can be used in combination with other methods.

[0229] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. Note that the transistor described in this embodiment is the same as the transistor described in Embodiment 1. The transistor is different from the transistor in that it has two gate electrodes with an oxide semiconductor film interposed therebetween.

[0230] 9A to 9C are top views and cross-sectional views of a transistor 40 included in a semiconductor device. 9A is a top view of transistor 40, and FIG. FIG. 9(C) is a cross-sectional view taken along dashed line AB in FIG. 9(A), and FIG. 9(C) is a cross-sectional view taken along dashed line CD in FIG. 9A, for clarity, the substrate 11, the gate insulating film 15, and the oxide film 16 are not shown. The oxide insulating film 23, the oxide insulating film 25, the nitride insulating film 27, etc. are omitted.

[0231] The transistor 40 shown in FIG. 9B and FIG. 9C is a channel etch type transistor. A gate electrode 13 is provided on a substrate 11, and the substrate 11 and the gate electrode 13 A gate insulating film 15 is formed on the gate electrode 13. The gate insulating film 15 is formed on the gate electrode 13. The oxide semiconductor film 17 is connected to the oxide semiconductor film 17, and a pair of electrodes 19 and 20 are in contact with the oxide semiconductor film 17. In addition, an oxide semiconductor film is formed on the gate insulating film 15, the oxide semiconductor film 17, and the pair of electrodes 19 and 20. A gate insulating film composed of a nitride insulating film 23, an oxide insulating film 25, and a nitride insulating film 27. 28 and a gate electrode 31 formed on the gate insulating film 28. The gate electrode 31 is In the gate insulating film 15 and the gate insulating film 28, the gate insulating film 15 is provided with openings 42 and 43. The electrode 13 is connected to the first electrode 19. The electrode 20 is connected to the second electrode 20. An electrode 32 is formed on the nitride insulating film 27. The electrode 32 functions as a pixel electrode. do.

[0232] In the transistor 40 according to this embodiment, the gate electrode 13 and and the gate electrode 31, an oxide semiconductor is formed between the gate insulating film 15 and the gate insulating film 28. A conductive film 17 is provided. As shown in FIG. 9A, the gate electrode 31 is From the viewpoint of the gate insulating film 28, the gate insulating film 28 overlaps with an end of the oxide semiconductor film 17. The length is 0.5 μm or more and 6.5 μm or less, more preferably 1 μm or more and 2.5 μm or less. It is preferable that there is.

[0233] The gate insulating film 15 and the gate insulating film 28 have a plurality of openings. As shown in FIG. 9(B), the electrode 19 has an opening 41 through which one of the pair of electrodes 19 and 20 is exposed. As shown in FIG. 9C, an opening sandwiching the oxide semiconductor film 17 in the channel width direction is formed. That is, the oxide semiconductor film 17 has openings 42 and 43 on the outer side of the side surface thereof. In the opening 41, one of the pair of electrodes 19 and 20, here the electrode 20 and the electrode 32 In addition, the gate electrode 13 and the gate electrode 31 are connected in the openings 42 and 43. That is, in the channel width direction, the gate electrode 13 and the gate electrode 31 are The oxide semiconductor film 17 is surrounded by the gate insulating film 15 and the gate insulating film 28. In the panel width direction, the side surface of the oxide semiconductor film 17 and the opening 42 are interposed between the gate insulating film 28 and , 43, a gate electrode 31 is provided.

[0234] The gate electrode 13 and the gate electrode 31 are provided. 1 is set to the same potential and the side surface of the oxide semiconductor film 17 faces the gate electrode 31. Furthermore, in the channel width direction, the gate electrode 13 and the gate electrode 31 are formed as a gate insulator. The oxide semiconductor film 17 is surrounded by the film 15 and the gate insulating film 28. In the film 17, carriers flow only at the interfaces between the gate insulating films 15 and 28 and the oxide semiconductor film 17. Since the current flows over a wide area of ​​the oxide semiconductor film 17, the current in the transistor 40 The amount of carrier movement increases. As a result, the on-current of the transistor 40 increases. , the field effect mobility is high, typically 10 cm 2 / V s or more, 20cm 2 / V s or more. Note that the field-effect mobility here is The current drive in the saturation region of the transistor is the mobility approximation, not the film's physical property. This is an index of the apparent field effect mobility. L is also called the length. By making the channel length 0.5 μm or less, the increase in field effect mobility is remarkable. By making it small, between 0.5μm and 6.5μm, the channel width can also be made small. Therefore, even if there are a plurality of connection parts between the gate electrode 13 and the gate electrode 31, the transistor It is possible to reduce the area of ​​the transistor.

[0235] In addition, at the end of the oxide semiconductor film 17 that has been processed by etching or the like, Damage causes defects and contamination due to impurity adhesion. In the case where only one of the gate electrode 13 and the gate electrode 31 is formed in the transistor, Even if the compound semiconductor film 17 is intrinsic or substantially intrinsic, it may be subject to stress such as an electric field. As a result, the end portion of the oxide semiconductor film 17 is activated and tends to become an n-type region (low resistance region). In addition, the n-type end portion is connected to a pair of electrodes 19, as shown by the dashed lines 33 and 34 in FIG. If the n-type region is placed between the n-type and n-type MOSFETs, the n-type region becomes a carrier path, and a parasitic channel is formed. As a result, the drain current increases stepwise near the threshold voltage and However, in Figure 9(C), As shown in the figure, the gate electrodes 13 and 31 have the same potential, and In the above, the gate electrode 31 is connected to the oxide semiconductor via the gate insulating film 28. In the transistor in which the side of the film 17 is located, the electric field of the gate electrode 31 is applied to the oxide semiconductor film As a result, the parasitic channel at the end of the oxide semiconductor film 17 is As a result, the drain current increases stepwise near the threshold voltage. This results in a transistor with excellent electrical characteristics.

[0236] In addition, by having the gate electrode 13 and the gate electrode 31, each of them can receive an electric current from the outside. In order to have a function of shielding the magnetic field, As a result, the fixed charges present in the oxide semiconductor film 17 do not affect the oxide semiconductor film 17. For example, a negative potential is applied to the gate electrode (Gate Bias-Temperature Transistor). The degradation of the drain voltage at different drain voltages is suppressed. Fluctuations in the rising voltage of the on-current can be suppressed.

[0237] The BT stress test is a type of accelerated test that detects the transitions that occur during long-term use. It is possible to evaluate the characteristic changes (i.e., aging) of the transistor in a short time. The amount of change in the threshold voltage of a transistor before and after stress testing is used to examine reliability. This is an important indicator. The smaller the change in threshold voltage before and after the BT stress test, the Therefore, it can be said that this is a highly reliable transistor.

[0238] The gate electrode 31 is made of the same material as the electrode 32 shown in the first embodiment and is formed at the same time as the electrode 32. It can be formed into.

[0239] Next, a method for manufacturing the transistor 40 shown in FIG. 9 will be described with reference to FIGS. 6 to 8 and 10, the line AB in FIG. 1A and 1B show cross-sectional views in the channel length direction and the channel width direction, respectively.

[0240] 6 to 8A in the same manner as in the first embodiment, a gate electrode, 13, insulating film 14, oxide semiconductor film 17, a pair of electrodes 19, 20, oxide insulating film 22, The nitride insulating film 24 and the nitride insulating film 26 are formed. In the above, a photolithography process is performed using the first photomask to the third photomask. We are carrying out the following.

[0241] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher and 40° C. or lower. 0°C or lower, preferably 300°C or higher and 400°C or lower, preferably 320°C or higher and 370°C or lower Let us assume that.

[0242] Next, a fourth photomask is used to form a photoresist film on the nitride insulating film 26. After forming a mask, the insulating film 14, the oxide insulating film 22, and the oxide insulating film 23 are formed using the mask. The gate insulating film 15 and the nitride insulating film 26 are each partially etched. The gate insulating film is made up of an oxide insulating film 23, an oxide insulating film 25, and a nitride insulating film 27. The gate insulating film 28 is formed as shown in FIG. The gate insulating film 15 and the gate insulating film 28 have an opening 41. As shown in (A) CD, it has openings 42 and 43.

[0243] Next, as shown in FIG. 10(B), a conductive film 3 which will later become a gate electrode 31 and an electrode 32 is Form 0.

[0244] Next, a mask is formed on the conductive film 30 by a photolithography process using a fifth photomask. Next, a part of the conductive film 30 is etched using the mask to form a gate electrode. The mask 31 and the electrode 32 are then formed. After this, the mask is removed.

[0245] As shown in FIG. 10C, the gate insulating film 15 and A gate electrode 31 and an oxide semiconductor film 17 are provided in an opening in the gate insulating film 28. The gate electrode 31 is formed so that the side surface of the gate insulating film 28 is located therebetween.

[0246] Through the above steps, the transistor 40 can be manufactured.

[0247] In the transistor described in this embodiment, the gate electrode 31 is In the openings 42 and 43 provided in the gate insulating film 15 and the gate insulating film 28, an oxide By facing the side surface of the semiconductor film 17, the electric field of the gate electrode 31 is applied to the edge of the oxide semiconductor film 17. This affects the end portion of the oxide semiconductor film 17, and the occurrence of a parasitic channel at the end portion of the oxide semiconductor film 17 is suppressed. As a result, a transistor with excellent electrical characteristics was obtained, in which the drain current rises sharply at the threshold voltage. In addition, the side surface of the oxide semiconductor film 17 is also affected by the electric field of the gate electrode 31. As a result, carriers flow over a wide area of ​​the oxide semiconductor film 17. As the field effect mobility increases, the on-current increases.

[0248] From the above, it is possible to obtain electrical characteristics of a semiconductor device including a transistor having an oxide semiconductor film. In addition, a semiconductor device having an oxide semiconductor film can be obtained. In a semiconductor device provided with the above, a highly reliable semiconductor device can be obtained.

[0249] Note that the configurations and methods described in this embodiment may be the same as those described in other embodiments. The method can be used in combination with other methods.

[0250] <Variation 1> A transistor having a structure different from those shown in FIGS. 1 and 9 will be described with reference to FIG. 11. The transistor 50 shown in FIG. 1 is a transistor having an oxide semiconductor film 17 on one side in the channel width direction. On the outer side of the surface, the gate electrode 13 and the gate electrode 51 are connected to each other, but the oxide semiconductor film On the outside of the other side surface of 17, via the gate insulating film 15 and the gate insulating film 28, The point where the gate electrode 13 and the gate electrode 51 face each other is the same as that of the other transistor shown in the second embodiment. Different from Sta.

[0251] 11A to 11C are top views and 11A is a top view of a transistor 50, and FIG. 11B is a cross-sectional view of the transistor 50. 11(A) is a cross-sectional view taken along the dashed line AB in FIG. 11(A), and FIG. 11(C) is a cross-sectional view taken along the dashed line AB in FIG. 11A is a cross-sectional view taken along line CD. For clarity, in FIG. 11A, the substrate 11 and the gate The insulating film 15, the oxide insulating film 23, the oxide insulating film 25, the nitride insulating film 27, and the like are omitted. do.

[0252] The transistor 50 shown in FIGS. 11A to 11C is a channel-etched transistor. The oxide insulating film 23, the oxide insulating film 25, and the nitride insulating film 27 are The gate electrode 51 formed on the nitride insulating film 27 functions as the nitride insulating film 28. The gate electrode 51 is formed through an opening provided in the gate insulating film 15 and the gate insulating film 28. At the portion 42, the gate electrode 13 is connected. An electrode 32 connected to the electrode 20 is formed on the gate insulating film 28. It functions as a base electrode.

[0253] The gate electrode 51 is formed at the same time as the electrode 32 shown in the first embodiment using the same material. It is possible.

[0254] The transistor 50 according to the present embodiment has a gate electrode 13 and a gate electrode 51 between them. An oxide semiconductor film 17 is provided. In addition, the gate electrode 51 is formed as shown in FIG. When viewed from above, the gate insulating film 28 overlaps with an end of the oxide semiconductor film 17 .

[0255] As shown in FIG. 11C, on the outside of one side surface of the oxide semiconductor film 17, In the opening 42 provided in the gate insulating film 15 and the gate insulating film 28, the gate electrode The electrode 51 is connected to the gate electrode 13. The gate electrode 51 is also connected to a gate electrode provided in the opening 42. The side surfaces of the gate electrode 51 and the oxide semiconductor film 17 are located via the gate insulating film 28. On the outside of the other side surface of the oxide semiconductor film 17, the gate electrode 51 is in contact with the gate electrode 13. The end of the gate electrode 51 is located outside the side surface of the oxide semiconductor film 17. .

[0256] Next, a manufacturing process of the transistor 50 will be described.

[0257] 6 to 8A, a gate electrode 13, an insulating film 14, an oxide A semiconductor film 17, a pair of electrodes 19 and 20, an oxide insulating film 23, an oxide insulating film 24, and a nitride In this step, the first to third photomasks are used to form a photo-etched insulating film 26. A photolithography process is carried out using a photomask.

[0258] Next, a photolithography process using a fourth photomask is performed on the nitride insulating film 26. After forming a mask, the insulating film 14, the oxide insulating film 23, the oxide insulating film 24, and the nitride A part of the insulating film 26 is etched to form an opening 4 shown in FIG. 11(A) and FIG. 11(B). 1, and the gate insulating film 15 is also etched to form the opening shown in FIG. 11(A) and FIG. 11(C). A mouth portion 42 is formed.

[0259] Next, the conductive film 30 is formed in the same manner as in the process shown in FIG. After forming a mask on the conductive film 30 by a photolithography process using a mask, A part of the film 30 is etched to form the gate electrode 51 and the gate electrode 52 shown in FIGS. 11(A) to 11(C). And the electrode 32 is formed.

[0260] Through the above steps, the transistor 50 can be manufactured.

[0261] <Variation 2> A transistor with a structure different from those in Figures 1, 9, and 11 is explained using Figure 12. In the transistor 60 shown in FIG. The point where the transistor is connected via the film 62 is the same as the other transistors shown in the first and second embodiments. Different from Sta.

[0262] 12A to 12C are top views and 12A is a top view of a transistor 60, and FIG. 12B is a cross-sectional view of the transistor 60. FIG. 12(C) is a cross-sectional view taken along the dashed line AB in FIG. 12(A), and FIG. 12(C) is a cross-sectional view taken along the dashed line AB in FIG. 12A is a cross-sectional view taken along line CD. For clarity, in FIG. 12A, the substrate 11 and the gate The insulating film 15, the oxide insulating film 23, the oxide insulating film 25, the nitride insulating film 27, and the like are omitted. do.

[0263] The transistor 60 shown in FIG. 12B and FIG. 12C is a channel etch type transistor. The oxide insulating film 23, the oxide insulating film 25, and the nitride insulating film 27 are gate insulating films. The gate electrode 64 formed on the nitride insulating film 27 functions as the nitride insulating film 28. The gate electrode 64 is connected to the gate electrode 13 via the conductive film 62. One of the pair of electrodes 19 and 20, in this case the electrode 32 connected to the electrode 20, is disposed on the gate insulating film 28. The electrode 32 functions as a pixel electrode.

[0264] The conductive film 62 is formed using the same material and method as the pair of electrodes 19 and 20 described in the first embodiment. The conductive film 62 can be formed by simultaneously forming the pair of electrodes 19 and 20. The gate electrode 64 is formed using the same material as the electrode 32 shown in the first embodiment. can be formed at times.

[0265] The transistor 60 shown in this embodiment has a gate electrode 13 and a gate electrode 64. An oxide semiconductor film 17 is provided. In addition, a gate electrode 64 is formed as shown in FIG. When viewed from above, the gate insulating film 28 overlaps with an end of the oxide semiconductor film 17 .

[0266] As shown in FIG. 12C, in an opening 61 provided in the gate insulating film 15, The conductive film 62 is connected to the gate electrode 13. Also, an opening provided in the gate insulating film 28 At 63, the gate electrode 64 is connected to the conductive film 62. The gate electrode 13 and the gate electrode 64 are electrically connected to each other. The conductive film 62 , which has the same potential as the back electrode 64 , faces the side surface of the oxide semiconductor film 17 .

[0267] In addition, the transistor 60 is oxidized in the channel width direction as shown in FIG. The gate electrode 13 and the gate electrode 64 are disposed only on the outer side of one side of the semiconductor film 17. The oxide semiconductor film 17 is connected to the gate electrode 61 through the conductive film 62. The port electrode 13 and the gate electrode 64 may be connected via a conductive film 62 .

[0268] Next, a manufacturing process of the transistor 60 will be described.

[0269] Through the process of FIG. 6, a gate electrode 13, an insulating film 14, and an oxide semiconductor In this process, a first photomask and a second photomask are used to form a film 17. A photolithography process is performed using the above method.

[0270] Next, a mask is formed on the insulating film 14 by a photolithography process using a third photomask. After the formation of the mask, a part of the insulating film 14 is etched to form the insulating film 14 shown in FIG. 12(A) and FIG. 12(C). An opening 61 shown in FIG.

[0271] Next, in the same manner as in the steps shown in FIGS. 7(A) and 7(B), a fourth photomask was used. After forming a mask on the conductive film 18 by a photolithography process, a part of the conductive film 18 is A pair of electrodes 19, 20 and a conductive film 62 are formed by etching.

[0272] Next, similarly to the step shown in FIG. 8(A), the oxide insulating film 23, the oxide insulating film 24, and A nitride insulating film 26 is formed. Next, a photolithography process is performed using a fifth photomask. After forming a mask on the nitride insulating film 26 by the process, a part of the nitride insulating film 26 is etched. By this, the openings 41 and 63 shown in FIG. 12(A) and FIG. 12(C) are formed.

[0273] Next, the conductive film 30 is formed in the same manner as in the process shown in FIG. After forming a mask on the conductive film 30 by a photolithography process using a mask, A portion of the film 30 is etched to expose the gate electrode 64 and And the electrode 32 is formed.

[0274] Through the above steps, the transistor 60 can be manufactured.

[0275] <Modification 3> For transistors with structures different from those shown in Figs. 1, 9, 11, and 12, Fig. 13 is used. A transistor 80 shown in FIG. An electrode 92 is formed on the nitride insulating film 87. On the electrodes 19 and 20, an oxide insulating film 83 and an oxide insulating film 84 are formed. The oxide insulating film 83 and the oxide insulating film 84 are formed on the electrodes 19 and 20 ... The transistor differs from the other transistors shown in the first and second embodiments in that the transistor has a film 85. .

[0276] 13A to 13C are top views and 13A is a top view of a transistor 80, and FIG. 13B is a cross-sectional view of the transistor 80. FIG. 13(C) is a cross-sectional view taken along the dashed line AB in FIG. 13(A), and FIG. 13(C) is a cross-sectional view taken along the dashed line AB in FIG. 13A is a cross-sectional view taken along line CD. For clarity, in FIG. 13A, the substrate 11 and the gate The insulating film 15, the oxide insulating film 83, the oxide insulating film 85, the nitride insulating film 87, and the like are omitted. do.

[0277] The transistor 80 shown in FIG. 13B and FIG. 13C is a channel etch type transistor. A gate electrode 13 is provided on a substrate 11, and the substrate 11 and the gate electrode A gate insulating film 15 is formed on the gate electrode 13. The semiconductor device has an oxide semiconductor film 17 overlapping the oxide semiconductor film 17 and a pair of electrodes 19 and 20 in contact with the oxide semiconductor film 17. In addition, on the gate insulating film 15, the oxide semiconductor film 17, and the pair of electrodes 19 and 20, , an oxide insulating film 83, an oxide insulating film 85, and a gate insulating film 87. The gate electrode 91 is formed on the gate insulating film 88. 1 is a gate insulating film 15 and an opening 94 provided in the nitride insulating film 87. It is connected to the electrode 13. It is also connected to one of the pair of electrodes 19 and 20, in this case the electrode 20. An electrode 92 is formed on the nitride insulating film 87. The electrode 92 is provided on the nitride insulating film 87. The electrode 92 is connected to the electrode 20 through the opening 93. The electrode 92 functions as a pixel electrode. .

[0278] The gate insulating film 15 is formed of a nitride insulating film 15a and an oxide insulating film 15b. The oxide insulating film 15b is formed by covering the oxide semiconductor film 17, the pair of electrodes 19 and 20, and the oxide It is formed in a region overlapping with the insulating film 83 .

[0279] The nitride insulating film 15a is formed using a silicon nitride film. The oxides listed for the gate insulating film 15 in the first embodiment are appropriately used for the film 5b. The nitride insulating film 15a and the oxide insulating film 15b are formed by the same process as the insulating film 14. The oxide insulating film 83 can be formed by any of the methods described in the embodiment modes. The oxide insulating film 23 can be formed by using a material and a method similar to those of the oxide insulating film 23 shown in FIG. The oxide insulating film 85 can be formed using the same material as the oxide insulating film 25 in Embodiment 1. The nitride insulating film 87 can be formed by using an appropriate method and formation method. The insulating film 27 can be formed by using the same material and method as those for the nitride insulating film 27. The gate electrode 91 and the electrode 92 are the same as the gate electrode 31 and the electrode 3 shown in the first embodiment. It can be formed by appropriately using the same materials and manufacturing methods as those of 2.

[0280] The oxide insulating film 83 and the oxide insulating film 85 are separated for each transistor. 13B. In the direction of the oxide insulating film 83, the end portions of the oxide insulating film 85 are formed on the pair of electrodes 19 and 20. In the channel width direction shown in FIG. 13C, an oxide semiconductor film 17 is formed on the outside of the oxide semiconductor film 17. The nitride insulating film 87 is located at the end of the nitride insulating film 83 and the end of the oxide insulating film 85. The oxide insulating film 83 and the oxide insulating film 85 are formed so as to cover the upper and side surfaces thereof, and are nitrided. The oxide insulating film 83 and the oxide insulating film 85 are in contact with each other. In the channel length direction, the insulating film 15a is not provided on the pair of electrodes 19 and 20, but is provided on the nitride insulating film 15a. It may be possible to do so.

[0281] In addition, in the channel width direction shown in FIG. 13(C), the oxide insulating film 83 and the oxide insulating film The side surfaces of the gate electrode 91 and the oxide semiconductor film 17 are located via the side surfaces of the insulating film 85 .

[0282] In the transistor 80 according to this embodiment, the gate electrode 13 and and the gate electrode 91, an oxide semiconductor is formed between the gate insulating film 15 and the gate insulating film 88. A conductive film 17 is provided. As shown in FIG. 13A, the gate electrode 91 has an upper surface 8, the gate insulating film 88 overlaps with an end of the oxide semiconductor film 17.

[0283] As shown in FIG. 13C, the gate electrode is formed on the outer side of one side surface of the oxide semiconductor film 17. In the opening 94 provided in the nitride insulating film 15 and the nitride insulating film 87, the gate electrode 91 is connected to the gate electrode 13. In addition, the oxide insulating films 83 and 85 and the nitride insulating film 87 The gate electrode 91 and the side surface of the oxide semiconductor film 17 are located through the side surface. On the other side of the semiconductor film 17, the gate electrode 91 is connected to the gate electrode 13. In addition, the end of the gate electrode 91 is located outside the side surface of the oxide semiconductor film 17.

[0284] In addition, the transistor 80 is oxidized in the channel width direction as shown in FIG. The gate electrode 13 and the gate electrode 91 are disposed only on the outer side of one side of the semiconductor film 17. However, on the outer side of both sides of the oxide semiconductor film 17, the gate electrode 13 and The gate electrode 91 may be connected.

[0285] In the transistor 80 described in this embodiment, the oxide semiconductor film 17 and the oxide insulating film The film 85 is surrounded by the nitride insulating film 15a and the nitride insulating film 87. The nitride insulating film 15a and the nitride insulating film 87 have a low oxygen diffusion coefficient and act as a barrier against oxygen. Therefore, part of oxygen contained in the oxide insulating film 85 can be efficiently absorbed into the oxide semiconductor film 17 Therefore, the amount of oxygen vacancies in the oxide semiconductor film 17 can be reduced. In addition, the nitride insulating film 15a and the nitride insulating film 87 have a low diffusion coefficient for water, hydrogen, and the like. Since the oxide semiconductor film 17 has a barrier property against water, hydrogen, and the like, water and hydrogen can be prevented from entering the oxide semiconductor film 17 from the outside. As a result, the transistor 80 has high reliability. It becomes a transistor.

[0286] Next, a manufacturing process of the transistor 80 will be described.

[0287] The transistor 80 is formed on a substrate through the same processes as those shown in FIGS. A gate electrode 13, a nitride insulating film 14a, an oxide insulating film 14b, an oxide semiconductor film 17, a pair of In this process, the first photomask to the third photomask are used. A photolithography process is performed using a photomask.

[0288] Next, as shown in FIG. 14(A), an oxide insulating film 22 and an oxide insulating film 24 are formed. Next, heat treatment is performed to oxidize part of oxygen contained in the oxide insulating film 24 to the oxide semiconductor film 24. By this, the amount of oxygen vacancies in the oxide semiconductor film 17 can be reduced.

[0289] Next, a fourth photomask is used in a photolithography process to form an oxide insulating film 24 After forming a mask on the oxide insulating film 22, a part of the oxide insulating film 24 is etched. Then, oxide insulating films 83 and 85 are formed, which are separated for each transistor. In addition, part of the oxide insulating film 14b is also etched together with the etching of the oxide insulating film 83. As a result, as shown in FIG. 14(B), an etched oxide insulating film 15b That is, the gate insulating film 15 having a step is formed later.

[0290] Next, the nitride insulating film 86 shown in FIG. 14(C) is formed. In the channel width direction shown in FIG. That is, the oxide semiconductor film 17 and the oxide insulating film 85 are the nitride insulating film 15a and the nitride insulating film 15b. It is surrounded by a membrane 86 .

[0291] Next, a nitride insulating film 86 is formed by a photolithography process using a fifth photomask. After forming a mask on the nitride insulating film 86, a part of the nitride insulating film 86 is etched to form an opening 93. Furthermore, the nitride insulating film 14a and the nitride insulating film 86 are partially etched to form openings. The portion 94 is formed, and the nitride insulating film 15a and the nitride insulating film 87 are also formed (FIG. 14 (See (D)).

[0292] Thereafter, as shown in FIG. 15(A), a conductive film that will later become a gate electrode 91 and an electrode 92 is The conductive film 90 can be formed in the same manner as the conductive film 30 described in the first embodiment. can.

[0293] Next, a mask is formed on the conductive film 90 by a photolithography process using a sixth photomask. Next, a part of the conductive film 90 is etched using the mask to form a gate electrode. Then, the mask 91 and the electrode 92 are formed. After that, the mask is removed (see FIG. 15(B)).

[0294] As shown in FIG. 15B, the oxide semiconductor film 17 and the oxide The insulating film 83 is formed on the side of the oxide insulating film 85, and the insulating film 87 is formed on the side of the oxide insulating film 83. The gate electrode 91 is formed as shown in FIG.

[0295] After that, heat treatment may be performed. The nitride insulating film 15a and the nitride insulating film 15b are formed of an oxide insulating film containing more oxygen than the nitride insulating film 15c. The oxide insulating film 87 has a high barrier property against oxygen. It is possible to reduce the diffusion of oxygen contained in the oxide insulating film 85 to the outside. The diffusion of oxygen contained in the semiconductor film 17 to the outside can be reduced. It is possible to reduce oxygen vacancies in the semiconductor film 17. Furthermore, the nitride insulating film 15a and the nitride The oxide insulating film 87 has a high barrier property against hydrogen, water, and the like, and prevents the oxide semiconductor film 17 from being damaged by the outside. Therefore, the diffusion of hydrogen, water, and the like into the oxide semiconductor film 17 can be reduced. As a result, highly reliable transistors can be manufactured. Cut.

[0296] Through the above steps, the transistor 80 can be manufactured.

[0297] <Modification 4> In the transistor described in this embodiment, a pair of In the method for manufacturing the electrodes 19 and 20 and the oxide semiconductor film 17, The oxide semiconductor film 17 is masked with a half-tone mask (or a gray-tone mask, By forming the semiconductor device using a mask (e.g., a differential mask), the number of masks and process steps can be reduced. In FIG. 9, a plan view of a transistor fabricated using halftone is shown in FIG. 0(A), and cross-sectional views are shown in FIG. 40(B) and FIG. 40(C).

[0298] (Embodiment 3) In this embodiment, a semiconductor device according to one embodiment of the present invention having a different structure from that of the above embodiment will be described. The body device will now be described with reference to FIG.

[0299] 16A and 16B are top views of a transistor 450 included in the semiconductor device. 16A is a top view of the transistor 450, and FIG. 16(A) is a cross-sectional view taken along dashed line AB and dashed line CD in FIG. In FIG. 16B, for clarity, the substrate 400, the insulating film 402, the insulating film 414, etc. are omitted. is doing.

[0300] The transistor 450 shown in FIG. 16A and FIG. 16B has a protruding portion on the substrate 400. an insulating film 402 having a protrusion; an oxide semiconductor film 406 on a protrusion of the insulating film 402; A pair of electrodes 408a, 408b in contact with the side and top surfaces of the membrane 406; A gate insulating film 410 in contact with the oxide semiconductor film 406 on the gate insulating film 408a and the gate insulating film 408b. A gate electrode that is in contact with the upper surface of the insulating film 410 and faces the side and upper surfaces of the oxide semiconductor film 406. The pair of electrodes 408a and 408b and the gate electrode 412 Insulating film 414 may be included as an element of transistor 450 .

[0301] As shown in FIG. 16B, in the transistor 450, a pair of electrodes 408a and 40 The region 8b is in contact with a side surface of the oxide semiconductor film 406 in which a channel is formed. In the cross section in the axial direction, the gate electrode 412 faces the top surface and the side surface of the oxide semiconductor film 406. The oxide semiconductor film 406 is electrically connected to the gate electrode 412 by an electric field of the gate electrode 412. Here, the electric field of the gate electrode 412 causes the channel (or channel The structure of the transistor that electrically surrounds the oxide semiconductor film 406) on which the panel is formed is This is called a surrounded channel (s-channel) structure. The oxide semiconductor film 406 has an s-channel structure, and thus the entire oxide semiconductor film 406 (bulk In the s-channel structure, the transistor This allows a large current to flow between the source and drain of the transistor, resulting in a high on-state current.

[0302] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. For example, The channel length of the transistor is preferably 40 nm or less, more preferably 30 nm or less. , more preferably 20 nm or less, and the channel width of the transistor is preferably 4 0 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less.

[0303] The channel length is the length in a region where the semiconductor film and the gate electrode overlap in a top view. The source (source region or source electrode) and the drain (drain region or drain electrode) 16A, the channel length is the distance from the oxide semiconductor film 40 The distance between the pair of electrodes 408a and 408b in the region where the gate electrode 412 overlaps with the electrode 6 The channel width is the width between the source and drain in the region where the semiconductor film and the gate electrode overlap. In other words, in FIG. 16(A), The width of the channel is determined by dividing the width of a pair of electrodes in a region where the oxide semiconductor film 406 and the gate electrode 412 overlap with each other. This refers to the length over which the poles 408a and 408b face each other in parallel.

[0304] The components included in the transistor 450 will be described in detail below. The substrate 400, the oxide semiconductor film 406, the gate insulating film 410, and the gate insulating film 410 are included in the gate electrode 450. The gate electrode 412 is formed by the substrate 11, the oxide semiconductor film 17, the gate insulating film 15, and the Since the description of the gate electrode 13 can be referred to, a detailed description thereof will be omitted. The oxide semiconductor film 406 was observed one-dimensionally within a range of 300 nm by transmission electron diffraction measurement. The ratio of observed diffraction patterns with bright spots showing orientation when the observation point is changed (i.e. That is, the CAAC ratio is 70% or more and less than 100%, preferably 80% or more and less than 100%. It has a certain area.

[0305] The gate insulating film 410 included in the transistor 450 is a mask film of the gate electrode 412. In the embodiment of the present invention, however, the semiconductor device is processed in a self-aligning manner. The embodiment is not limited to this, and the upper surfaces of the pair of electrodes 408a and 408b are covered with the gate insulating film 410. It may be configured to cover the

[0306] In the transistor 450, the insulating film 402 is made of aluminum oxide, magnesium oxide, or the like. Sium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide An insulating film containing oxydimium oxide, hafnium oxide or tantalum oxide is used in a single layer or a laminated layer. However, the insulating film 402 has a function of preventing diffusion of impurities from the substrate 400. In addition, the oxide semiconductor film 406 in which a channel is formed is supplied with oxygen. Therefore, an insulating film containing oxygen is preferably used as the insulating film 402. It is more preferable to use an insulating film containing more oxygen than in the stoichiometric composition. In the case where the insulating film 402 has a stacked structure, at least a region in contact with the oxide semiconductor film 406 In this case, it is preferable to use an insulating film containing oxygen. For example, the insulating film 402 is made of silicon nitride. The silicon oxynitride film is a laminated structure of a silicon film and a silicon oxynitride film. It is only necessary that the semiconductor film 406 is in contact with the insulating film 404 .

[0307] In addition, when the substrate 400 is a substrate on which other elements are formed, the insulating film 402 is an interlayer insulating film. In this case, the surface of the insulating film 402 may be planarized. For example, the insulating film 402 may be subjected to CMP (Chemical Mechanical Polishing). A flattening process may be performed using a flattening method or the like.

[0308] Note that the projections of the insulating film 402 are formed by dividing the oxide semiconductor film 406 in contact with the insulating film 402 into islands. In the etching process for processing, the insulating film exposed from the island-shaped oxide semiconductor film 406 The insulating film 402 is etched, and the thickness of the insulating film 402 in the corresponding area is reduced. However, depending on the etching conditions of the oxide semiconductor film 406, the insulating film 402 may not have a protrusion. There may not be.

[0309] The pair of electrodes 408a and 408b has a property of extracting oxygen from the oxide semiconductor film. It is preferable to use a conductive film. For example, a conductive film having a property of extracting oxygen from an oxide semiconductor film is used. The conductive film is made of aluminum, titanium, chromium, nickel, molybdenum, tantalum, and tungsten. Examples of conductive films include those containing stainless steel.

[0310] The conductive film has a property of extracting oxygen from the oxide semiconductor film. Oxygen in the oxide semiconductor film 406 is released, and oxygen vacancies may be formed in the oxide semiconductor film. The higher the temperature at which the transistor is heated, the more likely it is to be pulled out. Since the heating step is performed, the pair of electrodes 408 a and 408 b of the oxide semiconductor film 406 There is a high possibility that oxygen vacancies will be formed in the area near the contact. Hydrogen may enter the loss site, causing the oxide semiconductor film 406 to become n-type. The pair of electrodes 408a and 408b function to form a pair of oxide semiconductor film 406 and The resistance of the region where 408a and 408b contact each other is reduced, and the on-resistance of the transistor 450 is reduced. can be reduced.

[0311] In addition, transistors with small channel lengths (e.g., 200 nm or less, or 100 nm or less) When fabricating a MOSFET, the source and drain may be short-circuited due to the formation of an n-type region. Therefore, when forming a transistor with a small channel length, the source electrode and and a conductive film having a property of appropriately extracting oxygen from the oxide semiconductor film 406 as a drain electrode. As a conductive film having a property of appropriately extracting oxygen, for example, nickel , conductive films containing molybdenum or tungsten, and the like.

[0312] In addition, transistors with very small channel lengths (40 nm or less, or 30 nm or less) In this case, the pair of electrodes 408a and 408b are formed by using the oxide semiconductor film 406. In this case, a conductive film that does not extract oxygen from the oxide semiconductor film 406 may be used. Examples of conductive films that do not extract oxygen include tantalum nitride, titanium nitride, or A conductive film containing ruthenium, etc. Note that a plurality of types of conductive films may be stacked.

[0313] When the channel length of the transistor 450 is made very small, the conductive film is etched. When the ends of the pair of electrodes 408a and 408b formed by the above are rounded (have curved surfaces), In addition, when the conductive film is etched, the portion exposed from the pair of electrodes 408a and 408b may be The insulating film 402 may be etched, resulting in a decrease in the thickness of the insulating film 402 in that region. do.

[0314] The insulating film 414 provided over the transistor 450 includes the oxide semiconductor film 406 and and the gate insulating film 410 has a lower oxygen permeability (has a barrier property against oxygen). It is preferable to provide an insulating film having a barrier property against oxygen in contact with the gate insulating film 410. By providing the insulating film 414 having the gate insulating film 410 and the oxide semiconductor This can suppress the desorption of oxygen from the insulating film 406. Alternatively, an aluminum oxide film, a silicon nitride film, or a silicon nitride oxide film may be provided. .

[0315] Note that in order to prevent hydrogen from entering the oxide semiconductor film 406, Specifically, the hydrogen concentration in the insulating film 414 is preferably reduced. , 5×10 19 atoms / cm 3 It is preferable that the number of times the number of times is less than 5 × 10 18 atoms / cm 3 It is more preferable that the thickness of the aluminum oxide film is less than 100 nm. Therefore, the insulating film 414 is preferably used as an oxide film. It is preferable to use an aluminum nitride film. The insulating film 414 may also have a stacked structure. In the case where the insulating film 414 has a layered structure, the pair of electrodes 408a and 408b and the gate The insulating film having a barrier property against oxygen is in contact with the gate electrode 412. is preferred.

[0316] The configuration, method, etc. of this embodiment described above may be appropriately combined with the configurations, methods, etc. of other embodiments. They can be used in combination.

[0317] (Embodiment 4) In this embodiment, compared with Embodiments 1 to 3, defects in an oxide semiconductor film can be reduced. A semiconductor device having a transistor capable of further reducing the amount of The transistor described in this embodiment will be described in the following. In comparison, the difference is that the semiconductor device has a multilayer film including a plurality of oxide semiconductor films.

[0318] 17A to 17C are top views and FIG. 17A is a top view of a transistor 95a, and FIG. 17(A) is a cross-sectional view taken along the dashed line AB in FIG. 17(A), and FIG. 17(C) is a cross-sectional view taken along the dashed line AB in FIG. 17A is a cross-sectional view taken along dashed lines CD. For clarity, in FIG. 17A, the substrate 11 and the gate The gate insulating film 15, the oxide insulating film 23, the oxide insulating film 25, the nitride insulating film 27, etc. are omitted. is.

[0319] The transistor 95a shown in FIG. 17A has a gate electrode 1 The multilayer film 96 overlaps the electrode 3, and a pair of electrodes 19 and 20 contact the multilayer film 96. An oxide insulating film 23 is formed on the gate insulating film 15, the multilayer film 96, and the pair of electrodes 19 and 20. , an oxide insulating film 25, and a nitride insulating film 27 are formed.

[0320] In the transistor 95a described in this embodiment, the multilayer film 96 includes an oxide semiconductor film 17 and an oxide semiconductor film 97. That is, the multilayer film 96 has a two-layer structure. A part of the semiconductor film 17 functions as a channel region. The oxide insulating film 23 is formed, and the oxide insulating film 25 is formed so as to be in contact with the oxide insulating film 23. That is, an oxide semiconductor layer is formed between the oxide semiconductor film 17 and the oxide insulating film 23. A membrane 97 is provided.

[0321] The oxide semiconductor film 97 is composed of one or more elements that constitute the oxide semiconductor film 17. Therefore, at the interface between the oxide semiconductor film 17 and the oxide semiconductor film 97, Therefore, the movement of carriers is not hindered at the interface. This results in a high field effect mobility of the transistor.

[0322] The oxide semiconductor film 97 is formed of a metal oxide film containing at least In or Zn. Representative examples include In-Ga oxide film, In-Zn oxide film, and In-M-Zn oxide film (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, or Nd) and oxide semiconductor The energy of the lower end of the conduction band is closer to the vacuum level than that of the semiconductor film 17, and is typically an oxide semiconductor. The energy of the bottom of the conduction band of the oxide semiconductor film 17 The difference between the or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the oxide semiconductor film 97 and the electron affinity of the oxide semiconductor film 17 is 0 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

[0323] The oxide semiconductor film 97 contains In, and thus has high carrier mobility (electron mobility). Therefore, it is preferable.

[0324] The oxide semiconductor film 97 is made of Al, Ti, Ga, Y, Zr, Sn, La, Ce, or Having Nd in a higher atomic ratio than In may have the following effects: (1) Acid (2) Enlarging the energy gap of the oxide semiconductor film 97 (3) To reduce the diffusion of impurities from the outside. (4) To form an oxide semiconductor film. Compared to 17, it has higher insulation properties. (5), Al, Ti, Ga, Y, Zr, Sn, La , Ce, and Nd are metal elements with strong bonding strength with oxygen, so oxygen deficiency is unlikely to occur. It becomes.

[0325] When the oxide semiconductor film 97 is an In-M-Zn oxide, In is The atomic ratio of In and M is less than 50 atomic % and M is more than 50 atomic %. More preferably, In is less than 25 atomic % and M is more than 75 atomic %. Let us assume that.

[0326] In addition, the oxide semiconductor film 17 and the oxide semiconductor film 97 are In-M-Zn oxide M (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, or Nd), oxide semiconductor Compared with the film 17, the M (M is Al, Ti, Ga, Y, Zr , Sn, La, Ce, or Nd) is in a large atomic ratio, and typically, the oxide semiconductor film 1 7, 1.5 times or more, preferably 2 times or more, more preferably is more than three times higher than the atomic ratio.

[0327] In addition, the oxide semiconductor film 17 and the oxide semiconductor film 97 are In-M-Zn oxide (M is In the case of Al, Ti, Ga, Y, Zr, Sn, La, Ce, or Nd), an oxide semiconductor film 97 is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor film 17 is In:M If Zn=x2:y2:z2 [atomic ratio], then y1 / x1 is greater than y2 / x2. Preferably, y1 / x1 is 1.5 times or more larger than y2 / x2. More preferably, y1 / x1 is more than twice as large as y2 / x2, and more preferably, y1 / x1 is more than y2 / x In this case, in the oxide semiconductor film, when y2 is equal to or larger than x2, is preferable because stable electrical characteristics can be imparted to the transistor using the oxide semiconductor film. Yes.

[0328] When the oxide semiconductor film 17 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, S n, La, Ce, or Nd), in the target used to form the oxide semiconductor film 17, when the atomic ratio of the metal elements is In:M:Zn = x1:y1:z1 then 、 x 1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, which is preferable. Note that by setting z1 / y1 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed as the oxide semiconductor film 17. Typical examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:1:1, In :M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, etc.

[0329] When the oxide semiconductor film 97 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, S n, La, Ce, or Nd), in the target used to form the oxide semiconductor film 97, when the atomic ratio of the metal elements is In:M:Zn = x2:y2:z2 then 、 x 2 / y2 < x1 / y1, and z2 / y2 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, which is preferable. Note that by setting z2 / y2 to 1 or more and 6 or less, the oxide semiconductor film 97 is likely to be formed as a CAAC-OS film. Typical examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In: M:Zn = 1:3:6, In:M:Zn = 1:3:8, In:M:Zn = 1:4:4, I Examples include n:M:Zn=1:4:5, In:M:Zn=1:4:6, etc.

[0330] The atomic ratios of the oxide semiconductor film 17 and the oxide semiconductor film 97 are each determined with an error. The atomic ratios listed above may vary by ±40%.

[0331] The oxide semiconductor film 97 is a film formed by forming the oxide insulating film 25 later. It also functions as a film for reducing damage to the film 17. For this reason, the oxide insulating film 23 is not provided. An oxide insulating film 25 may be formed over the oxide semiconductor film 97 .

[0332] The thickness of the oxide semiconductor film 97 is 3 nm to 100 nm, preferably 3 nm to 50 nm. nm or less.

[0333] In addition, like the oxide semiconductor film 17, the oxide semiconductor film 97 may have a non-single crystal structure. The non-single crystal structure is, for example, CAAC-OS (C Axis Aligned-Cr ystalline oxide semiconductor), polycrystalline structure, described later The oxide semiconductor film 97 has a microcrystalline structure or an amorphous structure. It is preferable to use an oxide semiconductor film having a high CAAC ratio, similarly to the oxide semiconductor film 17 shown in FIG. An oxide semiconductor film with a high CAAC ratio has a low impurity concentration and a low defect state density. Therefore, it is possible to fabricate transistors with excellent electrical characteristics. In the oxide semiconductor film having a high crystal grain boundary, the crystal grain boundary is not observed, the c-axis is oriented, and the c-axis is not formed. As a result, the oxide semiconductor film 97 By using an oxide semiconductor film with a high CAAC ratio as a pair of electrodes 19 and 20, It is possible to prevent the metal element from diffusing into the oxide semiconductor film 17.

[0334] The oxide semiconductor film 97 may have, for example, an amorphous structure. For example, the atomic arrangement is disordered and does not have crystalline components. Or, the oxide film has an amorphous structure. For example, it has a completely amorphous structure and does not have any crystalline parts.

[0335] In the oxide semiconductor film 17 and the oxide semiconductor film 97, Two or more types of regions are available: a crystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystalline structure region. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, and a mixed film having a crystal structure. A region of a polycrystalline structure, a region of a CAAC-OS, or a region of a single crystal structure. The mixed film may have a single layer structure having an amorphous structure region, The region may be a microcrystalline region, a polycrystalline region, a CAAC-OS region, or a single crystal region. The film may have a laminated structure of two or more types of regions.

[0336] In place of the multilayer film 96, a multilayer transistor 95b shown in FIG. It may have a membrane 98 .

[0337] The multilayer film 98 includes an oxide semiconductor film 99, an oxide semiconductor film 17, and an oxide semiconductor film 97. That is, the multilayer film 98 has a three-layer structure. serves as a channel region.

[0338] In addition, the gate insulating film 15 and the oxide semiconductor film 99 are in contact with each other. An oxide semiconductor film 99 is provided between the oxide semiconductor film 17 and the oxide semiconductor film 17 .

[0339] In addition, the oxide semiconductor film 97 and the oxide insulating film 23 are in contact with each other. An oxide semiconductor film 97 is provided between the first insulating film 7 and the oxide insulating film 23.

[0340] The oxide semiconductor film 99 is formed using a material and a method similar to those of the oxide semiconductor film 97. It is possible.

[0341] The oxide semiconductor film 99 is preferably thinner than the oxide semiconductor film 17. The thickness of the body film 99 is set to 1 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less. Therefore, it is possible to reduce the amount of variation in the threshold voltage of the transistor.

[0342] Note that the oxide semiconductor film 9 7 is a film that prevents damage to the oxide semiconductor film 17 when forming the oxide insulating film 25 that is to be formed later. The oxide insulating film 23 is not provided, and the oxide semiconductor film 97 is provided with the oxide insulating film 23. An oxide insulating film 25 may be formed on the insulating film 24 .

[0343] In the transistor described in this embodiment, Therefore, the oxide semiconductor film 97 and the oxide insulating film 97 are Even if carrier traps are formed between the films 23 due to impurities and defects, the There is a gap between the region in which carrier traps are formed and the oxide semiconductor film 17. As a result, electrons flowing through the oxide semiconductor film 17 are less likely to be captured by carrier traps, and the transistor It is possible to increase the on-current of the semiconductor device and to enhance the field effect mobility. In addition, when an electron is captured in a carrier trap, the electron behaves as a negative fixed charge. This results in a shift in the threshold voltage of the transistor. Since there is a gap between the conductive film 17 and the region where the carrier traps are formed, the carrier traps It is possible to reduce the trapping of electrons in the trap, thereby reducing the variation in the threshold voltage. It is possible.

[0344] In addition, the oxide semiconductor film 97 can block impurities from the outside. It is possible to reduce the amount of impurities that move from the oxide semiconductor film 17 to the oxide semiconductor film 17. The oxide semiconductor film 97 is less likely to form oxygen vacancies. It is possible to reduce the impurity concentration and oxygen vacancy amount.

[0345] In addition, an oxide semiconductor film 99 is provided between the gate insulating film 15 and the oxide semiconductor film 17. An oxide semiconductor film 97 is provided between the oxide semiconductor film 17 and the oxide insulating film 23. Therefore, the silicon in the vicinity of the interface between the oxide semiconductor film 99 and the oxide semiconductor film 17 is the concentration of silicon or carbon in the oxide semiconductor film 17, or the concentration of silicon or carbon in the oxide semiconductor film 18. The concentration of silicon or carbon in the vicinity of the interface between the oxide semiconductor film 97 and the oxide semiconductor film 17 is reduced. This can be done.

[0346] The transistor 95b having such a structure includes a multilayer film 98 including an oxide semiconductor film 17. Since there are very few defects in the semiconductor, it is possible to improve the electrical characteristics of the transistor. Typically, it is possible to increase the on-current and improve the field effect mobility. The threshold voltage in the BT stress test and the optical BT stress test, which are examples of the non-linear stress test, The fluctuation is small and the reliability is high.

[0347] <Band structure of transistor> Next, the multilayer film 9 provided in the transistor 95a shown in FIGS. 6, and the band structure of the multilayer film 98 provided in the transistor 95b shown in FIG. This will be explained with reference to FIG.

[0348] Here, as an example, the oxide semiconductor film 17 has an energy gap of 3.15 eV. The In-Ga-Zn oxide, which has an energy gap of 3 The energy gap of the In-Ga-Zn oxide is 0.5 eV. Measure using a meter (HORIBA JOBIN YVON UT-300) can be done.

[0349] Vacuum level and valence band top energy of the oxide semiconductor film 17 and the oxide semiconductor film 97 The differences (also called ionization potentials) were 8 eV and 8.2 eV, respectively. The energy difference between the vacuum level and the top of the valence band was measured using ultraviolet photoelectron spectroscopy (UPS). Traviolet Photoelectron Spectroscopy ( Measurements can be performed using a VersaProbe (PHI Corporation).

[0350] Therefore, the vacuum level and the conduction band minimum of the oxide semiconductor film 17 and the oxide semiconductor film 97 are The energy difference (also called electron affinity) is 4.85 eV and 4.7 eV, respectively. do.

[0351] FIG. 18(A) shows a schematic diagram of a part of the band structure of the multilayer film 96. The gate insulating film 15 and the oxide insulating film 23 are silicon oxide films, and the multilayer film 96 and the silicon oxide The case where a silicon oxide film is provided in contact with the silicon oxide film will be described. EcS1 is the energy of the conduction band minimum of the oxide semiconductor film 17. EcS2 represents the energy of the bottom of the conduction band of the oxide semiconductor film 97, EcI2 indicates the energy of the bottom of the conduction band of the silicon oxide film. 17(B), and EcI2 corresponds to the oxide insulating film 2 shown in FIG. Equivalent to 3.

[0352] As shown in FIG. 18A, in the oxide semiconductor film 17 and the oxide semiconductor film 97, The energy at the bottom of the conduction band changes smoothly without any barrier. In other words, it changes continuously. This is because the multilayer film 96 contains elements common to the oxide semiconductor film 17. In addition, oxygen is transferred between the oxide semiconductor film 17 and the oxide semiconductor film 97. This can be said to be due to the formation of a mixed layer.

[0353] As shown in FIG. 18A, the oxide semiconductor film 17 of the multilayer film 96 serves as a well. In the transistor using the semiconductor device 96, a channel region is formed in the oxide semiconductor film 17. In addition, since the energy of the conduction band minimum changes continuously in the multilayer film 96, In other words, the oxide semiconductor film 17 and the oxide semiconductor film 97 are in continuous contact with each other.

[0354] As shown in FIG. 18A, the interface between the oxide semiconductor film 97 and the oxide insulating film 23 Although carrier traps due to impurities and defects may be formed in the vicinity, the oxide semiconductor The oxide semiconductor film 17 is separated from the carrier traps by the provision of the oxide film 97. However, if the energy difference between EcS1 and EcS2 is small, the oxide semiconductor Electrons in the conductive film 17 may exceed the energy difference and reach the carrier trap. When electrons are captured by the rear trap, a negative fixed charge is generated on the surface of the insulating film, causing a transistor. The threshold voltage of the transistor is shifted in the positive direction. Therefore, EcS1 and Ec When the energy difference with S2 is set to 0.1 eV or more, preferably 0.15 eV or more, the This is preferable because it reduces the fluctuation in the threshold voltage of the transistor and provides stable electrical characteristics.

[0355] FIG. 18B shows a schematic diagram of a part of the band structure of the multilayer film 98. The gate insulating film 15 and the oxide insulating film 23 are silicon oxide films, and the multilayer film 98 and the silicon oxide The case where a silicon oxide film is provided in contact with the silicon oxide film will be described. EcS1 is the energy of the conduction band minimum of the oxide semiconductor film 17. EcS2 represents the energy of the bottom of the conduction band of the oxide semiconductor film 97, EcS3 indicates the energy of the bottom of the conduction band of the oxide semiconductor film 99, and EcI2 indicates the energy of the silicon oxide EcI1 is the energy of the bottom of the conduction band of the silicon film. 17(D)。 EcI2 corresponds to the insulating film 15, and EcI3 corresponds to the insulating oxide film 23 shown in FIG.

[0356] As shown in FIG. 18B, the oxide semiconductor film 99, the oxide semiconductor film 17, and the oxide In the semiconductor film 97, the energy of the conduction band minimum changes smoothly without any barrier. In this case, it can be said that the change is continuous. This is because the multilayer film 98 is made of oxide semiconductors. The oxide semiconductor film 17 and the oxide semiconductor film 99 contain the same elements, and In addition, oxygen moves between the oxide semiconductor film 17 and the oxide semiconductor film 97, causing mixing. This can be said to be because a composite layer is formed.

[0357] As shown in FIG. 18B, the oxide semiconductor film 17 of the multilayer film 98 serves as a well. In the transistor using the semiconductor device 98, a channel region is formed in the oxide semiconductor film 17. In addition, since the energy of the conduction band minimum changes continuously in the multilayer film 98, The oxide semiconductor film 99, the oxide semiconductor film 17, and the oxide semiconductor film 97 are continuously joined together. It could also be said that there are.

[0358] In addition, in the vicinity of the interface between the multilayer film 98 and the oxide insulating film 23, and in the vicinity of the interface between the multilayer film 98 and the gate insulating film 1 Although carrier traps due to impurities or defects may be formed near the interface with 5, As shown in FIG. 18B, the oxide semiconductor films 97 and 99 are provided. The semiconductor film 17 can be spaced apart from the region where the carrier traps are formed. , the energy difference between EcS1 and EcS2, and the energy difference between EcS1 and EcS3 are When the energy difference is small, electrons in the oxide semiconductor film 17 exceed the energy difference and reach the carrier trap. When electrons are captured in the carrier traps, negative charges are generated on the surface of the insulating film. A fixed charge is generated, and the threshold voltage of the transistor shifts in the positive direction. So, the energy difference between EcS1 and EcS2, and the energy difference between EcS1 and EcS3 When the difference is set to 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor This is preferable because it reduces voltage fluctuations and provides stable electrical characteristics.

[0359] <Variation 1> In the transistors 95a and 95b described in Embodiment 4, In-M oxides (where M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, or Nd) However, the oxide semiconductor film 97 may be a metal oxide represented by the formula (I) or (Hf). The material must have a low enough conductivity to prevent it from acting as part of the channel-forming region. Alternatively, the oxide semiconductor film 97 may be formed of a material having a low electron affinity (between the vacuum level and the conduction band). The energy difference between the conduction band minimum and the conduction band minimum is smaller than that of the oxide semiconductor film 17. A material having a difference (band offset) with respect to the conduction band edge energy of the semiconductor film 17 is used. In addition, the difference in threshold voltages depending on the magnitude of the drain voltage (hysteresis) In order to suppress the occurrence of the above phenomenon, the energy of the conduction band minimum of the metal oxide film must be A material having a vacuum level that is 0.2 eV closer to the energy level of the conduction band minimum of the semiconductor film 17 is preferable. It is preferable to use a material having a vacuum level of 0.5 eV or more.

[0360] In addition, by increasing the atomic ratio of element M to In, the energy gap of the metal oxide film is increased. Therefore, the oxide semiconductor film 17 and the This creates a conduction band offset between the two, forming a channel in the metal oxide film. In order to suppress this, the metal oxide film should have a ratio of In:M=x:y (atomic ratio) of y / (x +y) is 0.75 or more and 1 or less, preferably 0.78 or more and 1 or less, more preferably 0. It is preferable that the thickness of the metal oxide film is 80 or more and 1 or less. However, the metal oxide film contains indium, which is the main component. Elements other than M, M, and oxygen may be mixed in as impurities. The ratio of impurities in this case is preferably 0.1% or less.

[0361] Note that the configurations and methods described in this embodiment may be the same as those described in other embodiments. The method can be used in combination with other methods.

[0362] (Embodiment 5) In this embodiment, a semiconductor device which is one embodiment of the present invention will be described with reference to drawings. Note that in this embodiment, a semiconductor device which is one embodiment of the present invention will be described using a display device as an example. do.

[0363] FIG. 19A shows an example of a semiconductor device. The semiconductor device shown in FIG. 101, a scanning line driving circuit 104, and a signal line driving circuit 106 are parallel or approximately parallel to each other. m scanning lines 107, the potentials of which are controlled by a scanning line driving circuit 104; , each are arranged in parallel or approximately in parallel, and the potentials are controlled by a signal line driving circuit 106. The pixel section 101 is arranged in a matrix. The pixel 103 is connected in parallel or approximately parallel to the signal line 109. The capacitance lines 115 are arranged along the scanning lines 107. The scanning line driving circuit 104 and the signal lines may be arranged in parallel or approximately in parallel. The drive circuits 106 may be collectively referred to as a drive circuit section.

[0364] Each scanning line 107 corresponds to one of the pixels 103 arranged in m rows and n columns in the pixel section 101. The signal lines 109 are electrically connected to the n pixels 103 arranged in any one row. is m pixels 103 arranged in m rows and n columns, and m pixels 103 arranged in any one of the columns. 3. m and n are both integers of 1 or more. is n pixels 103 arranged in any one of the rows among the pixels 103 arranged in m rows and n columns. 3. Capacitor lines 115 are arranged parallel to each other along the signal line 109. In the case where the pixels 103 are arranged in m rows and n columns, any one of the pixels 103 may be arranged in a matrix of m rows and n columns. The pixel array 103 is electrically connected to m pixels 103 arranged in a column.

[0365] 19B and 19C show a pixel 103 of the display device shown in FIG. 19A. 1 shows an example of a circuit configuration that can be used.

[0366] The pixel 103 shown in FIG. 19B includes a liquid crystal element 121, a transistor 102, and a capacitor. child 105.

[0367] The potential of one of the pair of electrodes of the liquid crystal element 121 is appropriately set according to the specifications of the pixel 103. The alignment state of the liquid crystal element 121 is set by the written data. A common potential (common potential) is applied to one of a pair of electrodes of the liquid crystal element 121 of each pixel 103. In addition, one of the pair of electrodes of the liquid crystal element 121 for each row of the pixels 103 may be applied. may be given different potentials.

[0368] The liquid crystal element 121 controls the transmission or non-transmission of light by the optical modulation effect of the liquid crystal. The optical modulation effect of liquid crystals is achieved by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field). The liquid crystal element 121 and the liquid crystal element 122 are controlled by a directional electric field or an oblique electric field. These include nematic liquid crystals, cholesteric liquid crystals, smectic liquid crystals, and thermotropic liquid crystals. Examples of such liquid crystals include lyotropic liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals.

[0369] The display device having the liquid crystal element 121 can be driven in, for example, a TN mode or a VA mode. ASM (Axially Symmetric Aligned Micro-ce) ll) mode, OCB (Optically Compensated Birefringence ngence) mode, MVA mode, PVA (Patterned Vertical Alignment mode, IPS mode, FFS mode, or TBA (Tran You can also use the symmetric bend alignment mode. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

[0370] Also, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element may be configured by the liquid crystal that exhibits the blue phase. Since it is short and optically isotropic, it does not require alignment treatment and has small viewing angle dependency.

[0371] In the configuration of the pixel 103 shown in FIG. 19B, the source electrode and One of the drain electrodes is electrically connected to a signal line 109, and the other is connected to one of the liquid crystal elements 121. The gate electrode of the transistor 102 is electrically connected to the other of the pair of electrodes. The transistor 102 is electrically connected to the line 107. The transistor 102 is in an on or off state. By this, it has a function of controlling the writing of data of the data signal. The transistor 102 is a transistor described in any one of Embodiments 1 to 4. can be done.

[0372] In the configuration of the pixel 103 shown in FIG. 19B, one of a pair of electrodes of the capacitor 105 is The other is electrically connected to a pair of the liquid crystal elements 121. The potential value of the capacitance line 115 is determined based on the specifications of the pixel 103. The capacitance element 105 serves as a storage capacitor for storing written data. It has the function of

[0373] For example, in a display device having a pixel 103 shown in FIG. 19B, The pixels 103 in each row are selected in sequence, and the transistors 102 are turned on to output the data signal. Write the data.

[0374] The pixel 103 to which the data has been written is held by turning off the transistor 102. By performing this process row by row, an image can be displayed.

[0375] In addition, a pixel 103 shown in FIG. 19C includes a transistor for switching a display element. 133, a transistor 102 for controlling the driving of the pixel, a transistor 135, and a capacitance element The display panel includes a light-emitting element 105 and a light-emitting element 131.

[0376] A data signal is applied to one of the source and drain electrodes of the transistor 133. The gate electrode of the transistor 133 is electrically connected to a signal line 109. The pixel electrodes 104 are electrically connected to a scanning line 107 to which a port signal is applied.

[0377] The transistor 133 is turned on or off to transmit the data of the data signal. It has the function of controlling the writing of data.

[0378] One of the source and drain electrodes of the transistor 102 serves as an anode line. The source electrode and the drain electrode of the transistor 102 are electrically connected to the wiring 137 that corresponds to the The other electrode is electrically connected to one electrode of the light emitting element 131. The gate electrode of the transistor 102 is connected to the other of the source electrode and drain electrode of the transistor 133. and electrically connected to one electrode of the capacitor 105 .

[0379] The transistor 102 is turned on or off to produce a light emitting element 131. The transistor 102 has a function of controlling a current flow. The transistor shown in any one of the fourth embodiment can be used.

[0380] One of the source and drain electrodes of the transistor 135 is provided with a data reference potential. The source electrode and the drain electrode of the transistor 135 are connected to the wiring 139. The other electrode of the light emitting element 131 is electrically connected to the other electrode of the capacitor 105. Furthermore, the gate electrode of the transistor 135 is connected to the scanning line 1 through which a gate signal is applied. 07.

[0381] The transistor 135 has a function of adjusting a current flowing through the light-emitting element 131. For example, When the internal resistance of the light emitting element 131 increases due to deterioration or the like of the light emitting element 131, the transistor A current flows through the wiring 139 to which one of the source electrode and the drain electrode of the stator 135 is connected. By monitoring the wiring, the current flowing through the light emitting element 131 can be corrected. The potential applied to 139 can be, for example, 0V.

[0382] One of a pair of electrodes of the capacitor 105 is connected to the source electrode and the drain electrode of the transistor 133. The other of the gate electrodes of the transistor 102 is electrically connected to the gate electrode of the capacitor element 1 The other of the pair of electrodes of 05 is the other of the source electrode and drain electrode of the transistor 135. , and is electrically connected to one electrode of the light-emitting element 131 .

[0383] In the configuration of the pixel 103 shown in FIG. 19C, the capacitance element 105 The capacitor functions as a storage capacitor to store data.

[0384] One of the pair of electrodes of the light emitting element 131 is a source electrode and a drain electrode of the transistor 135. the other of the gate electrodes of the capacitor 105, and the source and drain electrodes of the transistor 102. The other of the pair of electrodes of the light emitting element 131 is electrically connected to the other of the pair of electrodes. It is electrically connected to a wiring 141 which functions as a cathode.

[0385] The light-emitting element 131 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light emitting element 131 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0386] A high power supply potential VDD is applied to one of the wiring 137 and the wiring 141, and In the configuration shown in FIG. 19C, the wiring 137 is provided with a low power supply potential VSS. A high power supply potential VDD is applied to the wiring 141, and a low power supply potential VSS is applied to the wiring 142. .

[0387] In a display device having the pixel 103 of FIG. 19C, the scanning line driving circuit 104 drives the The pixels 103 are selected in sequence, the transistors 133 are turned on, and data of the data signal is written. Sink in.

[0388] The pixel 103 to which the data has been written is held by turning off the transistor 133. Furthermore, since the transistor 133 is connected to the capacitor 105, The data stored in the memory can be held for a long time. The amount of current flowing between the source electrode and the drain electrode of the transistor 102 is controlled, and the light-emitting element The element 131 emits light with a luminance according to the amount of current flowing through it. Images can be displayed.

[0389] Next, a specific configuration of the element substrate included in the display device will be described. A specific example of a liquid crystal display device using a liquid crystal element 103 will be described. A top view of the pixel 103 shown in FIG. 9(B) is shown in FIG.

[0390] 20 is a top view of a pixel included in a VA mode liquid crystal display device. The scanning lines 107 extend in a direction substantially perpendicular to the signal lines 109. The scanning lines 107 are arranged to extend in a direction parallel to the signal lines 109. The scanning line driver circuit 104 (see FIG. 19) is electrically connected to the signal line 109 and The capacitance line 115 is electrically connected to the signal line driving circuit 106 (see FIG. 19).

[0391] The transistor 102 is provided in the region where the scanning line 107 and the signal line 109 intersect. The transistor 102 has a structure similar to that of the transistor 80 described in the second embodiment. In the scan line 107, the oxide semiconductor film 17a and The overlapping region functions as a gate electrode of the transistor 102. The gate electrode 13 is a gate electrode that overlaps with the oxide semiconductor film 17a in the signal line 109. The region corresponding to the transistor 102 functions as a source electrode or a drain electrode. 23, the electrode 19 is shown. Also, in FIG. 20, the scanning line 107 is In other words, the end of the scanning line 107 is located outside the end of the oxide semiconductor film 17a. The transistor functions as a light-shielding film that blocks light from a light source such as a backlight. The oxide semiconductor film 17a included in the transistor is not irradiated with light, and thus the electrical characteristics of the transistor are not changed. It can be suppressed.

[0392] The electrode 20 is connected to the electrode 92 through the opening 93. The electrode 92 has a light-transmitting property. The pixel electrode is formed of a conductive film having a thickness of 100 nm and functions as a pixel electrode.

[0393] The capacitance element 105 is connected to a capacitance line 115. The capacitance element 105 has a gate A metal oxide film 17b formed on the insulating film and a dielectric film provided on the transistor 102 The dielectric film is made of a nitride insulating film and an electrode 92. Since the nitride film 17b, the nitride insulating film, and the electrode 92 are each transparent, 05 has translucency.

[0394] Since the capacitor 105 has a light-transmitting property, the capacitor 105 is large in the pixel 103. Therefore, the aperture ratio can be increased, typically by 50%. It is possible to set the electric field strength to 55% or more, preferably 60% or more. It is possible to obtain a semiconductor device with an increased capacitance. For example, a semiconductor device with high resolution, For example, in a liquid crystal display device, the area of ​​a pixel becomes smaller, and the area of ​​a capacitance element also becomes smaller. For this reason, in a semiconductor device with high resolution, the charge capacity stored in the capacitive element is small. However, since the capacitor 105 in this embodiment has a light-transmitting property, By providing a capacitance element in each pixel, it is possible to obtain sufficient charge capacity in each pixel while increasing the aperture ratio. Typically, the pixel density is 200ppi or more, or even 300ppi or more. Furthermore, it can be suitably used in semiconductor devices with a high resolution of 500 ppi or more.

[0395] In addition, according to one embodiment of the present invention, the aperture ratio can be increased even in a high-resolution display device. This allows the light from light sources such as backlights to be used efficiently, and reduces the power consumption of the display device. The force can be reduced.

[0396] Next, a cross-sectional view taken along the dashed line AB and CD in FIG. 20 is shown in FIG. The dashed line AB indicates the channel length direction of the transistor 102 and the distance between the transistor 102 and the pixel electrode. 1 is a cross-sectional view of a connection portion of an electrode 92 that functions as a capacitor, and a capacitance element 105, in the direction of CD. The cross-sectional view is a cross-sectional view of the transistor 102 in the channel width direction, and the gate electrode 13 and 13 is a cross-sectional view of a connection portion of a gate electrode 91. FIG.

[0397] The transistor 102 shown in FIG. 21 is a channel-etched transistor. A gate electrode 13 is provided on the substrate 11, and a gate electrode is formed on the substrate 11 and the gate electrode 13. The gate insulating film 15 and the oxide semiconductor film 1 overlapping the gate electrode 13 via the gate insulating film 15. The gate electrode 17a has a pair of electrodes 19 and 20 in contact with the oxide semiconductor film 17a. An oxide insulating film is formed on the oxide insulating film 15, the oxide semiconductor film 17a, and the pair of electrodes 19 and 20. A film 83 is formed, and an oxide insulating film 85 is formed on the oxide insulating film 83. film 15, oxide semiconductor film 17a, oxide insulating film 83, oxide insulating film 85, electrodes 19, 20 A nitride insulating film 87 is formed on the upper surface of the insulating film 87. An electrode 92 connected to the electrode 20 and a gate electrode 91 are formed on the nitride insulating film 87 . The electrode 92 functions as a pixel electrode.

[0398] The gate insulating film 15 is formed of a nitride insulating film 15a and an oxide insulating film 15b. The oxide insulating film 15b is formed on the oxide semiconductor film 17a, the pair of electrodes 19 and 20, and the oxide It is formed in a region overlapping with the insulating film 83 .

[0399] As shown in the cross-sectional view of CD, the nitride insulating film 15a and the nitride insulating film 87 are provided with In the opening 94, the gate electrode 91 is connected to the gate electrode 13. The base electrode 13 and the gate electrode 91 are at the same potential.

[0400] The transistor 102 shown in this embodiment has an oxide film formed on the surface thereof. The insulating films 83 and 85 are formed. The separated oxide insulating films 83 and 85 are formed on the oxide semiconductor film 1 In addition, in the cross-sectional view in the channel width direction shown in FIG. Ends of the oxide insulating film 83 and the oxide insulating film 85 are located outside the chamfer 17a. In the width direction of the panel, the outer periphery of one side surface and the other side surface of the oxide semiconductor film 17a On the other hand, the gate electrode 91 is formed of an oxide insulating film 83, an oxide insulating film 85, and a nitride insulating film. The nitride insulating film 87 is located on the side of the oxide semiconductor film 17a. The oxide insulating film 83 and the oxide insulating film 85 are formed so as to cover the upper and side surfaces thereof, and are nitrided. It comes into contact with the insulating film 15a.

[0401] The transistor 102 described in this embodiment includes an oxide semiconductor film 17a and an oxide insulating film The nitride insulating film 85 is surrounded by the nitride insulating film 15a and the nitride insulating film 87. The nitride insulating film 15a and the nitride insulating film 87 have a low oxygen diffusion coefficient and act as a barrier against oxygen. Therefore, part of oxygen contained in the oxide insulating film 85 can be efficiently absorbed into the oxide semiconductor film 17 a, and the amount of oxygen vacancies in the oxide semiconductor film 17a can be reduced. In addition, the nitride insulating film 15a and the nitride insulating film 87 have a diffusion coefficient of water, hydrogen, etc. Since the oxide semiconductor film 17a has a low barrier property against water, hydrogen, and the like, It is possible to prevent the diffusion of water, hydrogen, etc. As a result, the transistor 102 is reliable. This results in a highly reliable transistor.

[0402] The capacitance element 105 is formed by a metal oxide film 17b formed on the gate insulating film 15 and a nitride insulating film 17b. The capacitance element 105 is composed of an insulating film 87 and an electrode 92. b is a film formed at the same time as the oxide semiconductor film 17a and contains impurities. Alternatively, the metal oxide film 17b is a film having enhanced electrical conductivity. This film is formed at the same time, contains impurities, and is oxygen deficient due to plasma damage, etc. Losses are formed in the film, increasing its electrical conductivity.

[0403] Both the oxide semiconductor film 17a and the metal oxide film 17b are composed of the same metal element. The oxide semiconductor film 17a and the metal oxide film 17b are both formed on the gate insulating film 15. Specifically, the impurity concentration of the oxide semiconductor film 17a is different from that of the oxide semiconductor film 17b. For example, the hydrogen concentration in the oxide semiconductor film 17a is 5 ×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than, Preferably 1 x 10 18 atoms / cm 3 less than 5×10 17 atom s / cm 3 less than 1×10 16 atoms / cm 3 less than the metal acid The hydrogen concentration in the oxide film 17b is 8×10 19 atoms / cm 3 The above, preferably 1×10 20 atoms / cm 3 More preferably, 5×10 20 atoms / cm 3 In addition, the water content of the metal oxide film 17b is smaller than that of the oxide semiconductor film 17a. The concentration of the element is 2 times, preferably 10 times or more.

[0404] In addition, the oxide semiconductor film formed at the same time as the oxide semiconductor film 17a is exposed to plasma. The oxide semiconductor film can be damaged by the above-mentioned reaction, and oxygen vacancies can be formed. For example, When a film is formed on an oxide semiconductor film by plasma CVD or sputtering, the oxide The oxide semiconductor film is exposed to plasma, and oxygen vacancies are generated. In the etching process for forming the oxide insulating film 85, the oxide semiconductor film is When the oxide semiconductor film is exposed to hydrogen, a rare gas, or an oxygen vacancy is generated. When exposed to plasma of ammonia, oxygen, and hydrogen gas mixture, oxygen vacancies are generated. As a result, the oxide semiconductor film becomes highly conductive and turns into a metal oxide film 17b.

[0405] That is, the metal oxide film 17b can be said to be a highly conductive oxide semiconductor film. The oxide film 17b can also be considered as a highly conductive metal oxide film.

[0406] The nitride insulating film 87 contains hydrogen. In other words, it is an insulating film capable of releasing hydrogen. The nitride insulating film 87 is preferably formed such that the hydrogen concentration in the nitride insulating film 87 is 1 ×10 22 atoms / cm 3 It is preferable that the hydrogen of the nitride insulating film 87 is an oxide. When the fluorine-containing gas diffuses into the oxide semiconductor film formed at the same time as the semiconductor film 17a, the fluorine-containing gas diffuses into the oxide semiconductor film. In this case, hydrogen bonds with oxygen, and electrons, which act as carriers, are generated. When a film is formed by plasma CVD or sputtering, the oxide semiconductor film is exposed to plasma. Hydrogen contained in the nitride insulating film 87 enters the oxygen vacancies. As a result, the oxide semiconductor film has high electrical conductivity. This becomes the metal oxide film 17b.

[0407] The metal oxide film 17b has a lower resistivity than the oxide semiconductor film 17a. The resistivity of the oxide semiconductor film 17a is 1×10 -8 more than 1x10 -1 Less than double It is preferable that the concentration is 1×10 -3 Ωcm or more 1×10 4 Less than Ωcm, and Preferably, the resistivity is 1×10 -3 Ωcm or more 1×10 -1 It is preferable that the resistivity is less than Ωcm.

[0408] The element substrate of the semiconductor device described in this embodiment is The conductive film that functions as a pixel electrode is formed as a capacitor. The other electrode of the element is used. Since the step of forming a film is not required, the manufacturing process can be reduced. As a result, the area occupied by the capacitor element is increased, The aperture ratio of the pixel can be increased.

[0409] Next, a method for manufacturing the transistor 102 and the capacitor 105 shown in FIG. 22 and 23.

[0410] As shown in FIG. 22A, a gate electrode 13 is formed on a substrate 11. can be formed using a photolithography process using a first photomask .

[0411] Next, as shown in FIG. 22(B), a film, which will later become a nitride insulating film 15a, is formed on the gate electrode 13. Then, the nitride insulating film 14a is formed, and the oxide insulating film 14b is formed. Next, an oxide semiconductor film 17a and a metal oxide film 17b (later) are formed on the oxide insulating film 14b. The oxide semiconductor films 17a and 17c are formed by the second photomask. The insulating film can be formed by a photolithography process using a mask.

[0412] After this, the substrate is heated at a temperature higher than 350°C and lower than the substrate distortion point, preferably at a temperature higher than 450°C and lower than 600°C. Heat treatment is performed. As a result, a one-dimensional 300 nm range is observed using a transmission electron diffraction measurement device. When the observation point is changed, the CAAC conversion rate is 70% or more and less than 100%, preferably 8 0% or more and less than 100%, preferably 90% or more and less than 100%, more preferably 95% or more The oxide semiconductor films 17a and 17c can be obtained by using the oxide semiconductor films 17a and 17c with a conductivity of 98% or less. It is possible to obtain the oxide semiconductor films 17a and 17c in which the content of is reduced. In this way, an oxide semiconductor film with a low impurity concentration and a low density of defect states can be formed.

[0413] Next, as shown in FIG. 22(C), a pair of electrodes 19 and 20 and a wiring The pair of electrodes 19 and 20 and the conductive film 21c are formed in the third photoconductor. The insulating film can be formed by a photolithography process using a mask.

[0414] Next, as shown in FIG. 22(D), an oxide insulating film 83 and an oxide insulating film 85 are formed. The oxide insulating film 83 and the oxide insulating film 85 are formed by photolithography using a fourth photomask. It can be formed by using a lithography process.

[0415] As shown in the cross-sectional view of CD, the oxide semiconductor film 17a The oxide insulating film 83 and the oxide insulating film 85 are arranged so that their ends are located outside both side surfaces of the The oxide insulating film 83 and the oxide insulating film 85 are formed so as to be separated from each other. At the same time, a part of the oxide insulating film 14b is also etched, and the oxide insulating film 15b As a result, the nitride insulating film 14a is exposed. In this process, the oxide semiconductor film 17c is damaged by the plasma, and the oxide semiconductor film 17c is An elemental defect is formed.

[0416] Next, a heat treatment is performed. The temperature of the heat treatment is typically 150° C. or higher and 400° C. or lower. The temperature is preferably 300°C or higher and 400°C or lower, and more preferably 320°C or higher and 370°C or lower.

[0417] By this heat treatment, part of oxygen contained in the oxide insulating film 85 is oxidized to the oxide semiconductor film 17a The oxygen vacancies in the oxide semiconductor film 17a can be filled by the oxygen vacancies in the oxide semiconductor film 17a. As a result, the amount of oxygen vacancies in the oxide semiconductor film 17a can be further reduced.

[0418] Next, as shown in FIG. 23(A), a nitride insulating film 26 that will later become a nitride insulating film 87 is formed. Complete.

[0419] The nitride insulating film 26 is formed by a sputtering method, a CVD method, or the like. 6 is formed by a sputtering method, a CVD method, or the like, so that the oxide semiconductor film 17c is Since the oxide semiconductor film 17c is exposed to the interference, oxygen vacancies in the oxide semiconductor film 17c can be increased.

[0420] Through this process, the oxide semiconductor film 17a, the oxide insulating film 83, and the oxide insulating film 85 are formed. The nitride insulating film 15a and the nitride insulating film 26 are in contact with each other by providing an oxide semiconductor layer on the inside. The conductor film 17c becomes the metal oxide film 17b. When a silicon nitride film is formed by the CVD method, hydrogen contained in the silicon nitride film is converted into oxide semi-conductor. Since it diffuses into the conductive film 17c, the conductivity is increased.

[0421] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150° C. or higher and 40° C. or lower. 0°C or lower, preferably 300°C or higher and 400°C or lower, preferably 320°C or higher and 370°C or lower Note that in this heat treatment, the oxide semiconductor film 17a, the oxide insulating film 83, and The oxide insulating film 85 is provided in a region where the nitride insulating film 15a and the nitride insulating film 87 are in contact with each other. Therefore, the oxide semiconductor film 17a, the oxide insulating film 83, and the oxide insulating film 85 This prevents oxygen from diffusing from the semiconductor to the outside. As a result, the threshold voltage shifts negatively. In addition, the amount of variation in the threshold voltage can be reduced.

[0422] Next, a fifth photomask is used to form a photoresist film on the nitride insulating film 26. After forming a mask, the nitride insulating film 14a and the nitride insulating film 26 are formed using the mask. 23(B) to form a nitride film having openings 93 and 94. A nitride insulating film 87 and a nitride insulating film 15a having an opening 94 are formed.

[0423] Next, as shown in FIG. 23(C), the gate electrode 91 and the electrode functioning as the pixel electrode are The gate electrode 91 and the electrode 92 functioning as a pixel electrode are formed in the sixth photodiode. The pattern can be formed by a photolithography process using a photomask. At the opening 93, the electrode 20 and the electrode 92 are connected. The electrode 13 and the gate electrode 91 are connected.

[0424] Through the above steps, the transistor 102 and the capacitor 105 are manufactured. It is possible.

[0425] The element substrate of the semiconductor device described in this embodiment is The conductive film that functions as a pixel electrode is formed as a capacitor. The other electrode of the element is used. Since the step of forming a film is not required, the manufacturing process can be reduced. As a result, the area occupied by the capacitor element is increased, The aperture ratio of the pixel can be increased.

[0426] As described above, a semiconductor device including an oxide semiconductor film has improved electrical characteristics. can be obtained.

[0427] <Variation 1> In the semiconductor device described in this embodiment, as shown in FIG. In addition, the transistor 10 described in Embodiment 1 is used, and a planarization film is formed over the nitride insulating film 87. The capacitor 105a may be provided with a metal oxide film 17b and a nitride insulating film 8 7, a planarizing film 89, and an electrode 92a. As a result, the surface of the electrode 92a is planarized. This makes it possible to reduce uneven alignment of the liquid crystal molecules contained in the liquid crystal layer.

[0428] <Variation 2> The semiconductor device described in this embodiment mode can be an FFS mode liquid crystal display device. The structure of an FFS mode liquid crystal display device will be described with reference to FIG.

[0429] FIG. 25 is a cross-sectional view of the semiconductor device, in which the metal oxide film 17b is in contact with the electrode 20. In the case of the nitride insulating film 87, the metal oxide film 17b functions as a pixel electrode. The common electrode 92b is formed in the same manner as the electrode 92 shown in the present embodiment. The common electrode 92b is provided with a slit. Instead of the common electrode 92b having slits, a striped common electrode may be provided.

[0430] In addition, the area where the metal oxide film 17b, the nitride insulating film 26, and the common electrode 92b overlap each other When a voltage is applied to the metal oxide film 17b, A parabolic electric field is generated between the metal oxide film 17b and the common electrode 92b. As a result, the liquid crystal molecules contained in the liquid crystal layer can be aligned. The display has a high aperture ratio, a wide viewing angle, and improved image contrast. It can be improved.

[0431] In addition, by providing a portion of the common electrode 92b so as to overlap the electrode 20, The nitride insulating film 87 and the common electrode 92b function as a capacitance element, and the metal oxide film 17 The potential of b can be maintained.

[0432] Note that the configurations and methods described in this embodiment may be the same as those described in other embodiments. The method can be used in combination with other methods.

[0433] (Embodiment 6) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Provide an explanation.

[0434] FIG. 26 shows an example of a specific protection circuit portion 196 included in the semiconductor device.

[0435] The protection circuit section 196 shown in FIG. 26 includes a resistor element 114 between the wiring 110 and the wiring 112. and a diode-connected transistor 116.

[0436] The resistor element 114 is connected in series to the transistor 116. Controlling the current flowing through the transistor 116, or as a protective resistor for the transistor 116 itself It can function.

[0437] The wiring 110 may be, for example, a scanning line, a data line, or a line extending from a terminal section to a drive circuit section. The wiring 112 corresponds to, for example, a gate driver or a source The potential of the power supply line (VDD, VSS or GND) is given to supply power to the driver. Alternatively, the wiring 112 corresponds to a wiring to which a common potential is applied. (common line).

[0438] An example of the wiring 112 is a power line for supplying power to a scanning line driving circuit, particularly a low It is preferable to connect the gate signal line to a wiring that supplies a low potential. Therefore, the potential of the wiring 112 is also low. In this case, the current leaking from the gate signal line to the wiring 112 during normal operation is This is because it is possible to reduce the

[0439] Here, an example of the configuration of the resistance element 114 that can be used in the protection circuit unit 196 will be described. This will be explained with reference to FIG.

[0440] FIG. 27(A) shows a top view of the resistance element 114, and FIG. 27(B) shows the FIG. 27(C) is a cross-sectional view taken along the dashed line AB shown in FIG. 27(A). The cross-sectional view corresponds to the cut surface of the dashed line AB. In order to avoid complication, some components are omitted in the illustration.

[0441] The resistor element 114 shown in FIG. 27 includes a substrate 202 and a nitride insulating film 205 on the substrate 202. , an oxide insulating film 206 on the nitride insulating film 205, and a metal oxide film on the oxide insulating film 206 208, a conductive film 210a electrically connected to the metal oxide film 208, and a metal oxide film 2 08, the conductive film 210b electrically connected to the conductive film 210a, and the conductive film 210b and a nitride insulating film 214 over the oxide insulating film 212.

[0442] Note that the resistor element illustrated in FIG. 27B is formed by using the oxide insulating film 206 and the oxide insulating film 21. 2 has an opening 209, whereas the resistor element shown in FIG. 27(C) does not have an opening. Depending on whether or not the portion 209 is present, the insulating film that contacts the upper or lower side of the metal oxide film 208 is The configuration can be changed.

[0443] As shown in FIG. 27, the shape of the metal oxide film 208, specifically, the length or width, is appropriately adjusted. This makes it possible to provide a resistor element having an arbitrary resistance value.

[0444] 27 is a transistor shown in any one of the first to fifth embodiments. The fifth embodiment is taken as an example. I will use this to explain.

[0445] The resistor element shown in FIG. 27(B) is made of a nitride insulating film 205 and a and a metal oxide film 208 formed on the oxide insulating film 206. 27(a) and 27(b), and a nitride insulating film 214 formed on the metal oxide film 208. The resistor element shown in C) is made of a nitride insulating film 205 and a metal film formed on the nitride insulating film 205. An oxide film 208, an oxide insulating film 212 formed on the metal oxide film 208, and an oxide insulating film and a nitride insulating film 214 formed on the insulating film 212.

[0446] In this way, the composition of the insulating film in contact with the lower or upper side of the metal oxide film 208 is changed. In this way, the resistance of the metal oxide film 208 can be controlled. When an oxide semiconductor is used as the material for the metal oxide film 208, the oxide semiconductor Oxygen vacancies in the oxide semiconductor or impurities (hydrogen, water, etc.) in the oxide semiconductor The resistance of the metal oxide film 208 can be controlled. The resistivity of the metal oxide film 208 is preferably , 1×10 -3 Ωcm or more 1×10 4 Less than Ωcm, more preferably less than 1×10 -3 Ωc m or more 1×10 -1 It is preferable that the resistivity is less than Ωcm.

[0447] For example, the nitride insulating films 205 and 214 may be the nitride insulating film 15 shown in the fifth embodiment. As in a and 87, an insulating film that contains hydrogen, in other words, an insulating film that can release hydrogen, Generally speaking, hydrogen is supplied to the metal oxide film 208 by using a silicon nitride film. The nitride insulating film may be a nitride insulating film having a hydrogen concentration of 1× 10 22 atoms / cm 3 By using such an insulating film, Hydrogen can be supplied to the metal oxide film 208. By this, impurities are introduced into the metal oxide film 208, and the resistance of the metal oxide film 208 is reduced. The insulating films 206 and 212 are the oxide insulating films 15b, 83, and 85 described in Embodiment 5. Similarly, an insulating film containing oxygen, in other words, an oxide insulating film capable of releasing oxygen, typically In particular, a silicon oxide film or a silicon oxynitride film is used to form a metal oxide film. By supplying oxygen to the metal oxide film 208, As a result, the amount of oxygen vacancies in the metal oxide film 208 is reduced, and the resistance of the metal oxide film 208 is increased.

[0448] Note that the nitride insulating film 205 and the oxide insulating film 206 are the same as those of the nitride insulating film described in Embodiment 5. The metal oxide film 208 can be formed simultaneously with the oxide insulating film 15a and the oxide insulating film 15b. The conductive film 21 can be formed at the same time as the metal oxide film 17b shown in the fifth embodiment. 0a and 210b function as a pair of electrodes 19 and 20 and a capacitance wiring shown in the fifth embodiment. The oxide insulating film 212 can be formed at the same time as the conductive film 21c which functions as a conductive film. The nitride insulating film 214 can be formed simultaneously with the oxide insulating films 83 and 85 shown in FIG. The insulating film 87 can be formed at the same time as the nitride insulating film 87 shown in the fifth embodiment.

[0449] The resistor element 114 shown in FIG. 27 is a diode-connected transistor in FIG. The above is an example of a case where the capacitor is connected in series with the diode. However, this is not limited to this. It can also be connected in parallel with a transistor.

[0450] The resistor element 114 shown in FIG. 27 is a combination of a plurality of transistors and a plurality of resistor elements. In addition, it may be provided in the display device. Specifically, it can be configured as shown in FIG. .

[0451] The protection circuit unit 196_1 shown in FIG. and resistance elements 171, 172, and 173. Wiring 181 connected to one or more of the scanning line driving circuit, the signal line driving circuit, and the pixel unit , 182, and 183. The transistor 151 has a source electrode A first terminal having a function as a gate electrode is connected to a second terminal having a function as a gate electrode. A third terminal having a function as a drain electrode is connected to the wiring 183. The transistor 152 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. A second terminal having a drain electrode, a third terminal having a drain electrode, and a transistor. The first terminal of the transistor 151 is connected to the source electrode of the transistor 153. A first terminal having a function as a gate electrode is connected to a second terminal having a function as a gate electrode. a third terminal having a function as a drain electrode; a first terminal of the transistor 152; The transistor 154 has a first terminal that functions as a source electrode and A second terminal having a function as a gate electrode is connected to the first terminal having a function as a drain electrode. A third terminal having the transistor 153 is connected to a first terminal of the transistor 153. A first terminal of the resistor 154 is connected to the wiring 183 and the wiring 181. The elements 171 and 173 are provided on the wiring 183. The resistor element 172 is provided on the wiring 183. 82 and the first terminal of the transistor 152 and the third terminal of the transistor 153. It is being done.

[0452] The wiring 181 is used as, for example, a power supply line to which a low power supply potential VSS is applied. The wiring 182 can be used as, for example, a common line. The line 183 can be used, for example, as a power supply line to which a high power supply potential VDD is applied.

[0453] The resistance element 114 shown in FIG. 27 is suitable for the resistance elements 171 to 173 shown in FIG. It can be used.

[0454] In this manner, the protection circuit unit 196_1 includes a plurality of diode-connected transistors, That is, the protection circuit unit 196_1 is configured by a plurality of resistance elements. A parallel combination of a gate-connected transistor and a resistor element can be used.

[0455] By providing a protection circuit in this way, it is possible to reduce the risk of damage caused by ESD, etc. The resistance to overcurrent can be improved, and therefore the reliability of the semiconductor device can be improved. can be provided.

[0456] Furthermore, a resistive element is used as the protection circuit section, and the resistance value of the resistive element can be adjusted arbitrarily. Therefore, it is necessary to protect the diode-connected transistors used as the protection circuit. This becomes possible.

[0457] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0458] (Embodiment 7) In this embodiment, a semiconductor memory device in which no power is supplied using a transistor according to one embodiment of the present invention will be described. A semiconductor device (memory device) that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. An example of the device will be described with reference to FIG.

[0459] FIG. 29A is an example of a circuit diagram of a semiconductor device according to one embodiment of the present invention. The semiconductor device shown in FIG. 1 includes a transistor 470 using a first semiconductor and a transistor 470 using a second semiconductor. A transistor 452, a capacitor 490, a wiring BL, a wiring WL, and a wiring CL, The second semiconductor transistor 452 includes a wiring SL. The transistors described in any of Embodiments 1 to 3 can be used. A transistor having a structure similar to that of the transistor 450 described in Embodiment 3 is used as a second semiconductor device. An example of application to a transistor 452 using a conductor will be described.

[0460] One of the source and drain of the transistor 452 is electrically connected to the wiring BL. The other of the drains is electrically connected to one of the electrodes of the capacitor 490, and the gate is connected to the wiring WL. The other electrode of the capacitor 490 is electrically connected to the wiring CL. The other of the source and drain of the transistor 452 and one electrode of the capacitor 490 The node between these is called a node FN. One of the source and drain is electrically connected to a wiring BL, and the other of the source and drain is electrically connected to a wiring SL. The gate is electrically connected to a node FN.

[0461] Therefore, the semiconductor device shown in FIG. 29A is arranged when the transistor 452 is in a conductive state. A potential corresponding to the potential of the line BL is applied to the node FN. In other words, the semiconductor device shown in FIG. The physical device functions as a memory cell of a memory device.

[0462] The conductive state or non-conductive state of the transistor 452 is selected by the potential applied to the wiring WL. The transistor 452 can be controlled using a transistor with low off-state current. By this, the potential of the node FN in the non-conducting state can be maintained for a long period of time. Therefore, the frequency of refreshing the semiconductor device can be reduced, and power consumption can be reduced. A semiconductor device with low power consumption can be realized. One example of such a transistor is a transistor including an oxide semiconductor.

[0463] A constant potential such as a ground potential is applied to the wiring CL. At this time, the potential of the node FN This causes the apparent threshold voltage of transistor 470 to vary. The transistor 470 changes its conductive or non-conductive state due to the fluctuation of the value voltage. The data can be read out.

[0464] The semiconductor device shown in FIG. 29A is arranged in a matrix, whereby a memory device (memory A cell array) can be formed.

[0465] FIG. 29B shows an example of a cross-sectional view of a semiconductor device corresponding to FIG.

[0466] In the semiconductor device shown in FIG. 29B, a transistor 452 is provided above a transistor 470. A gate insulating film and a capacitor 490 are provided in the transistor 452. The insulating film 420, which functions as a capacitor, is provided in a manner to cover the pair of electrodes. The gate insulating film also functions as a dielectric film for the capacitor 490. The insulating film 420 functions as a The insulating film 420 has the same structure as the transistor 450. It is possible to form the material.

[0467] In FIG. 29B, the capacitance element 490 includes a nitride insulating film 401 and a nitride insulating film 40 1, an insulating film 420 functioning as a dielectric film, and a metal oxide film 405 in contact with the metal oxide film 405. The capacitor element 49 includes a conductive film 411 that at least partially overlaps with the film 405. The metal oxide film 405 included in the transistor 452 is the same as the oxide semiconductor film 406 included in the transistor 452. In the transistor 450, the oxide semiconductor film 4 The insulating film 402 in contact with the metal oxide film 405 is selectively removed in a region overlapping the metal oxide film 405. As a result, the metal oxide film 405 is provided under the insulating film 402. The nitride insulating film 401 is an insulating film containing hydrogen. Since the insulating film is capable of releasing hydrogen when heated, it is preferable to use a mode in which the insulating film is in contact with the metal oxide film 405. Thus, hydrogen is supplied to the metal oxide film 405. By this, the resistance of the metal oxide film 405 is reduced, and the metal oxide film 405 can be used as one of the electrodes of the capacitor 490. In addition, the conductive film which is the other electrode included in the capacitor 490 The gate electrode 411 can be manufactured in the same process as the gate electrode of the transistor 452 .

[0468] In FIG. 29B, a transistor 470 is manufactured using a semiconductor substrate 440. The transistor 470 is formed by a protruding portion of the semiconductor substrate 440, an impurity region 466 in the protruding portion, and a An insulating film 462 having a region in contact with the upper surface and side surface of the protruding portion, and A conductive film 464 facing the upper surface and the side surface, and an insulating film 460 in contact with the side wall of the conductive film 464; Note that the conductive film 464 functions as a gate electrode of the transistor 470. In addition, the impurity region 466 functions as a source region and a drain region of a transistor 470. Note that the transistor 470 does not necessarily have to include the insulating film 460. Since the protruding portion of the semiconductor substrate 440 is used, the FIN type transistor 470 is The protrusions may have an insulating film on them. This functions as a mask when forming protrusions on the substrate 440 .

[0469] Here, an example in which the semiconductor substrate 440 has a protruding portion is described. The semiconductor device is not limited to this. For example, a SOI substrate is processed to form a convex semiconductor. It's okay to do so.

[0470] The transistor 470 may be either an n-channel type or a p-channel type, depending on the circuit. An appropriate transistor is used.

[0471] The semiconductor substrate 440 is made of a semiconductor having a different energy gap from that of an oxide semiconductor. For example, a substrate made of a semiconductor material other than an oxide semiconductor may be used as the semiconductor substrate 440. When single crystal silicon is used as the semiconductor substrate, high speed operation is possible. The transistor 470 may be capable of switching between a first and second inputs.

[0472] In the semiconductor device shown in FIG. 29B, a transistor is provided above a transistor 470 with an insulating film interposed therebetween. The transistor 452 and the capacitor 490 are also included. A plurality of conductive films functioning as wirings are disposed between the capacitor 452 and the substrate 453. The multiple conductive films embedded in the film connect the wiring and electrodes arranged on the upper and lower layers to the are electrically connected.

[0473] In this way, by forming a structure in which a plurality of transistors are stacked, the integration of the semiconductor device can be improved. The degree can be increased.

[0474] When single crystal silicon is used for the semiconductor substrate 440, It is preferable that the insulating film has a high hydrogen concentration. The hydrogen can break down dangling bonds of silicon. By terminating the transistor 470, the reliability of the transistor 470 can be improved. The hydrogen concentration in the insulating film near the oxide semiconductor film included in the transistor 452 is preferably low. The hydrogen is one of the factors that generate carriers in the oxide semiconductor. A high hydrogen concentration in the insulating film near the conductor film reduces the reliability of the transistor 452. Therefore, the transistor 470 using single crystal silicon may In the case where the transistor 452 including an oxide semiconductor is stacked, hydrogen is The insulating film 403 having a blocking function enhances the reliability of both transistors. It is effective for

[0475] The insulating film 403 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Insulating materials include hafnium nitride, yttria-stabilized zirconia (YSZ), silicon nitride, etc. The lamina may be used in a single layer or in a laminate.

[0476] The insulating film 414 covering the transistor 452 using an oxide semiconductor is formed by It is preferable to form an insulating film having a blocking function. It is preferable to provide an aluminum oxide film. The aluminum oxide film is resistant to hydrogen, moisture, etc. The high barrier effect of the film prevents the penetration of both impurities and oxygen, By using an aluminum oxide film as the insulating film 414 covering the transistor 45 The present invention prevents the desorption of oxygen from the oxide semiconductor contained in 2 and prevents water and It is possible to prevent the inclusion of hydrogen.

[0477] It should be noted that the transistor 470 is not limited to a FIN type transistor, but may be of various types. For example, it can be a planar type transistor. Cut.

[0478] Moreover, the transistor 452 and the transistor 470 may be fabricated on the same surface. At this time, the transistor 470 is a transistor in which a channel is formed in an oxide semiconductor. Also, the transistor 452 may be fabricated on the same surface as the transistor 470. When manufacturing a semiconductor device, the components included in each transistor are formed through the same process. That is, the transistor 452 and the transistor 470 are fabricated through different processes. The number of manufacturing steps of the semiconductor device can be reduced compared to the case where the semiconductor device is manufactured by the conventional method. It can improve sexuality.

[0479] In FIG. 29B, one electrode of the capacitor 490 is formed using a metal oxide film 405. However, the configuration of this embodiment is not limited to this. The semiconductor device shown in FIG. 30 is a modified example of the semiconductor device shown in FIG. The transistor 450 described in Embodiment 3 is used instead of the transistor 452. Instead of the capacitance element 490 in the configuration shown in FIG. The electrode 408a, which is one of a pair of electrodes functioning as a source electrode or a drain electrode, is The capacitor 491 is used as an electrode.

[0480] In FIG. 30, the insulating film 417 which also functions as the dielectric film of the capacitance element 491 is The insulating films are formed in the same process as the gate insulating film 410 of the transistor 450. The conductive film 411 and the gate electrode 412 are used as a mask to perform self-aligned etching. Furthermore, when processing the insulating film 417 and the gate insulating film 410, the insulating film 402 is also processed at the same time. By etching the transistor 450 and the capacitor 491 at the outer periphery, In other words, the insulating film 419 and the insulating film 414 are in contact with each other. In the device, the transistor 450 and the capacitor element 491 are disposed between the insulating film 419 and the insulating It has a configuration surrounded by a membrane 414.

[0481] In the configuration shown in FIG. 30, the side surface of the gate insulating film 410 and the side surface and bottom surface of the insulating film 402 are Since the insulating films 414 and 419 are used to cover the insulating film 419 and the insulating film 414, Then, an insulating film having a blocking property against oxygen and hydrogen, such as an aluminum oxide film, is formed. In this way, the insulating film 402 and the gate insulating film 403 in contact with the oxide semiconductor film can be The insulating film 410 is formed of a fluorine-containing oxide semiconductor material. Furthermore, the insulating film 402 and / or the gate insulating film 41 can be prevented from being mixed with the insulating film 402. 0, and an insulating film containing excess oxygen is provided, so that the oxygen contained in the insulating film can be effectively Note that the insulating film 419 can be preferably formed by When an insulating film having a function of blocking hydrogen (e.g., an aluminum oxide film) is provided, The insulating film 403 is not necessarily formed.

[0482] The configuration, method, etc. of this embodiment described above may be appropriately combined with the configurations, methods, etc. of other embodiments. They can be used in combination.

[0483] (Embodiment 8) In the following, as an example of an oxide applicable to an oxide semiconductor film, In-Sn-Zn oxide is used. The crystal structures of In-Ga-Zn oxide and In-Ga-Zn oxide are shown. The effective mass was calculated as follows:

[0484] For the calculation, the crystal structure shown in Figure 31 was assumed. Note that the figure shows the atomic structure of each element except oxygen. The ratio of the number of atoms in the In-Sn-Zn oxide is shown in FIG. The crystal structure may differ from that shown in FIG. 31(C).

[0485] The calculation was performed using the first-principles electronic structure calculation package CASTEP. The calculation conditions are as shown in Table 1 below. As shown in the figure.

[0486] [Table 1]

[0487] The lattice constants in the optimized structure are shown in Table 2 below.

[0488] [Table 2]

[0489] Next, the effective mass of the electron (m e * ) and the effective mass of the hole (m h * ) and Ek dispersion curve The band edge at was derived by fitting with a quadratic function. The results are shown in Table 3 below. .

[0490] [Table 3]

[0491] As shown above, the In-Sn-Zn oxide and In-Ge oxide with the assumed crystal structure were In a-Zn oxide, the effective mass of the hole is very large compared to the effective mass of the electron. This suggests that holes are less likely to move in the oxide.

[0492] Therefore, when the oxide is used for the semiconductor film of a transistor, holes flow from the drain to the By tunneling, leakage current is unlikely to occur. It can be seen that it is a small transistor.

[0493] (Embodiment 9) In this embodiment, a semiconductor device including the transistor described in any of Embodiments 1 to 4 Here, an RFID tag and a CP are described as one type of semiconductor device. Explain using U.

[0494] <RFIDタグ> In the following, regarding the RFID tag including the above-mentioned transistor, resistive element, and capacitive element, This will be explained using Figure 32.

[0495] The RFID tag has a memory circuit inside, stores information in the memory circuit, and is read by a non-contact means, e.g. For example, RFID uses wireless communication to send and receive information from the outside. Tags are an individual authentication system that identifies items by reading their individual information. However, high reliability is required for these applications. can be.

[0496] The structure of the RFID tag will be described with reference to Fig. 32. Fig. 32 shows the structure of the RFID tag. FIG. 1 is a block diagram illustrating an example.

[0497] As shown in FIG. 32, an RFID tag 800 includes a communicator 801 (such as an interrogator or a reader / writer). An antenna 802 connected to the The RFID tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, A demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811 are included. Note that the transistor having a rectifying effect included in the demodulation circuit 807 has a reverse current. A transistor capable of sufficiently suppressing the current, for example, any of the transistors according to the first to fourth embodiments In this way, the rectification caused by the reverse current can be suppressed. This suppresses the degradation of the input of the demodulation circuit and prevents the output of the demodulation circuit from being saturated. The output of the demodulation circuit with respect to the force can be made closer to linear. The data transmission format is as follows: An electromagnetic coupling method in which a pair of coils are placed opposite each other and communicate through mutual induction, using an induced electromagnetic field. RF communication is broadly divided into three types: RF, electromagnetic induction communication, and radio wave communication. The ID tag 800 can be used in either of these methods.

[0498] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is smoothed by a capacitive element in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential. The limiter circuit is a circuit for limiting the amplitude of an input AC signal. When the internally generated voltage is large, the power supply is controlled so that it does not input a certain amount of power to the downstream circuit. This is a circuit for

[0499] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0500] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0501] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds the input information, including a row decoder, a column decoder, a memory area, etc. It has. Also, ROM811 stores a unique number (ID), etc., and outputs according to the process. It is a circuit for performing.

[0502] Note that each of the above circuits can be appropriately selected or discarded.

[0503] Here, the storage device described in Embodiment 7 can be used for the storage circuit 810. The storage device described in Embodiment 7 can hold information even when the power is cut off. Therefore, it is suitable for RFID tags. Furthermore, the storage device described in Embodiment 7 has a lower power (voltage) required for writing data compared to conventional non-volatile memories. Therefore, it is possible not to cause a difference in the maximum communication distance between the read and write times of data. Furthermore, it is possible to suppress the occurrence of malfunction or incorrect writing due to insufficient power during data writing. Furthermore, it is possible to suppress the occurrence of malfunction or incorrect writing due to insufficient power during data writing. It can be.

[0504] Also, since the storage device described in Embodiment 7 can be used as a non-volatile memory, it can also be applied to ROM811. In that case, it is preferable to separately prepare a command for the producer to write data to ROM811 so that the user cannot freely rewrite it. By writing the unique number before shipment and then shipping the product, it is possible to assign the unique number not to all the manufactured RFID tags, but only to the good products. This makes it possible to avoid having discontinuous unique numbers for the products after shipment and facilitates customer management corresponding to the products after shipment.

[0505] <Usage example of RFID tag> ​​​​​An example of how to use an RFID tag according to an embodiment of the present invention will be described below with reference to FIG. RFID tags are used in a wide range of applications, including banknotes, coins, securities, and bearer bonds. Tickets, certificates (driver's licenses, resident's certificates, etc., see Figure 33 (A)), packaging containers (wrapping paper, bottles, see Fig. 33(C), recording media (DVDs, video tapes, see Fig. 33(B) ), vehicles (bicycles, etc., see Figure 33 (D)), personal belongings (bags, glasses, etc.), food Animals, plants, animals, the human body, clothing, daily necessities, medicines and pharmaceuticals, or electronic devices Devices (liquid crystal display devices, EL display devices, television sets, or mobile phones), etc. Or, it is used by attaching it to a tag (see Figure 33 (E) and Figure 33 (F)) to each article. It is possible.

[0506] The RFID tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. For example, in a book, the sensor is embedded in the paper and fixed to the packaging made of organic resin. If so, it is embedded in the organic resin and fixed to each article. The FID tag 4000 is small, thin, and lightweight, so even after it is attached to an item, it remains the same It does not impair the design of the product itself. It can also be used for banknotes, coins, securities, bearer bonds, Alternatively, the RFID tag 4000 according to one embodiment of the present invention may be fixed to a document or the like to perform authentication. By utilizing this authentication function, counterfeiting can be prevented. In addition, packaging containers, recording media, personal belongings, food, clothing, daily necessities, or electronic devices By attaching an RFID tag 4000 according to one aspect of the present invention to a container or the like, an inspection system In addition, the present invention can be applied to vehicles as well. By attaching the RFID tag 4000 to your device, security against theft, etc. It can improve sexuality.

[0507] As described above, the RFID tag according to one embodiment of the present invention can be used for the above-mentioned purposes. It is possible.

[0508] <cpu> Below, we will explain the CPU including the above-mentioned transistors, resistors, capacitors, etc. do.

[0509] FIG. 34 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. It is.

[0510] The CPU shown in FIG. 34 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 34 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 34 is regarded as one core, and the core is divided into multiple The CPU may also be configured to include a processor core and each core may operate in parallel. The number of bits that can be handled by a computing circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0511] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0512] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0513] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0514] In the CPU shown in FIG. 34, a memory cell is provided in the register 1196. The memory device described in the seventh embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0515] In the CPU shown in FIG. 34, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0516] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0517] In addition, a transistor including an oxide semiconductor film has an extremely small off-state current. The off-state current of a transistor having a semiconductor film is determined by the formation of a channel in crystalline silicon. The off-state current of the transistor is significantly lower than that of the transistor By using it as a transistor 1209, a power supply voltage is supplied to the memory element 1200. The signal held in the capacitor 1208 is held for a long period of time even when the memory is not in use. The element 1200 can retain its memory contents (data) even when the supply of power voltage is stopped. It is.

[0518] Although the present embodiment has been described using a CPU as one embodiment of a semiconductor device, In addition, DSP (Digital Signal Processor) and custom LSI , PLD (Programmable Logic Device) and other LSIs, RF- The ID (Radio Frequency Identification) also includes the above A transistor, a resistor, and a capacitor can be used.

[0519] (Embodiment 10) In this embodiment, a structural example of an electronic device to which a semiconductor device of one embodiment of the present invention is applied will be described. In addition, in this embodiment, a display module to which the semiconductor device of one embodiment of the present invention is applied will be described. The rule will be described with reference to FIG.

[0520] The display module 8000 shown in FIG. 35 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003, A display panel 8006, a backlight unit 8007, a frame 8009, a printed circuit board The backlight unit 8007, the battery 8011, and the LCD panel 8012 are also included. The telly 8011, the touch panel 8004, etc. may not be provided.

[0521] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0522] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel. The shape and dimensions can be changed as appropriate to suit the size of the panel 8006.

[0523] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide a touch panel function to the display panel. It is also possible to provide an optical sensor in each pixel of the 8006 to make it into an optical touch panel. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 8006, and a capacitive touch sensor is provided. It may also be a panel.

[0524] The backlight unit 8007 includes a light source 8008. Alternatively, the light diffusing plate may be provided at the end of the light receiving unit 8007.

[0525] The frame 8009 protects the display panel 8006 and also supports the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 8009 may also function as a heat sink.

[0526] The printed circuit board 8010 includes a power supply circuit, a video signal circuit, and a clock signal circuit. The power supply circuit is supplied with power from an external commercial power source. Alternatively, the power source may be a battery 8011 provided separately. 11 can be omitted if commercial power is used.

[0527] The display module 8000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. Additional ones may be provided.

[0528] FIG. 36 is an external view of an electronic device including a semiconductor device of one embodiment of the present invention.

[0529] The electronic device may be, for example, a television device (television or television receiver) (also called "computer monitors"), digital cameras, digital video cameras, etc. digital photo frames, mobile phones (also called mobile phones or mobile phone devices), These include large game machines such as small game machines, portable information terminals, audio playback devices, and pachinko machines. can be.

[0530] FIG. 36A shows a portable information terminal, which includes a main body 1001, a housing 1002, a display unit 1003, and a The display unit 1003b is a touch panel. By touching the keyboard button 1004 displayed on the display unit 1003b, Of course, the display unit 1003a can be configured as a touch panel. The transistor described in the above embodiment may be used as a switching element in a liquid crystal panel. By fabricating a display panel or an organic light-emitting panel and applying it to the display units 1003a and 1003b, It is possible to provide a highly reliable portable information terminal.

[0531] The portable information terminal shown in FIG. 36(A) displays various information (still images, videos, text images, etc.) Functions that display calendars, dates, or times on the display, functions that display Ability to manipulate or edit the information displayed on the The back and sides of the housing can be equipped with external connection terminals. The device may be configured to include terminals (earphone terminal, USB terminal, etc.), a recording medium insertion section, etc. .

[0532] The portable information terminal shown in FIG. 36(A) is configured to be capable of wirelessly transmitting and receiving information. The desired book data can be purchased and downloaded wirelessly from an electronic book server. It is also possible to configure the device to perform this function.

[0533] FIG. 36(B) shows a portable music player. The main body 1021 has a display unit 1023 and an earphone. The device has a fixing part 1022 for mounting to an external device, a speaker, an operation button 1024, and an external memory slot. The transistors described in the above embodiment are switched By preparing a liquid crystal panel or an organic light-emitting panel as an element and applying it to the display unit 1023, This makes it a more reliable portable music player.

[0534] Furthermore, the portable music player shown in FIG. 36(B) is equipped with an antenna, a microphone function, and a wireless function. If you carry it with you and connect it to your mobile phone, you can enjoy wireless hands-free driving while driving a car. Conversation in Lee is also possible.

[0535] FIG. 36(C) shows a mobile phone, which is composed of two housings, housing 1030 and housing 1031. The housing 1031 includes a display panel 1032, a speaker 1033, a microphone, and a microphone array. Phone 1034, pointing device 1036, camera 1037, external connection terminal 10 The housing 1030 also includes a solar cell 104 for charging the mobile phone. 0, an external memory slot 1041, etc. Also, the antenna is provided inside the housing 1031. The transistor described in the above embodiment is applied to the display panel 1032. This makes it possible to provide a highly reliable mobile phone.

[0536] The display panel 1032 is equipped with a touch panel, and an image is displayed on the display panel 1032 as shown in FIG. The operation keys 1035 are indicated by dotted lines. It also implements a boost circuit to boost the voltage supplied to each circuit to the voltage required.

[0537] The display direction of the display panel 1032 changes appropriately depending on the usage mode. The camera 1037 is located on the same surface as the screen 1032, so video calls are possible. The speaker 1033 and microphone 1034 are not limited to voice calls, but can also be used for video calls and recording. Furthermore, the housing 1030 and the housing 1031 can be slid to each other, as shown in FIG. (C) It can be folded from the unfolded state to the folded state, making it easy to carry. It is possible to reduce the size.

[0538] The external connection terminal 1038 can be used to connect various cables such as an AC adapter and a USB cable. It is possible to charge the battery and to communicate with a personal computer, etc. A recording medium can be inserted into the external memory slot 1041 for storing and transferring a larger amount of data. We can handle it.

[0539] In addition to the above functions, it also has infrared communication function, TV reception function, etc. Good too.

[0540] FIG. 36(D) shows an example of a television device. The television device 1050 is A display unit 1053 is built into the housing 1051. The display unit 1053 displays an image. In addition, the CPU is built into the stand 1055 that supports the housing 1051. The transistor described in the above embodiment is provided in the display portion 1053 and the CPU. By applying this, a highly reliable television device 1050 can be obtained.

[0541] The television device 1050 can be operated using an operation switch provided on the housing 1051 or a separate remote control. The remote control can be operated by a remote controller. A display unit for displaying information output from the machine may be provided.

[0542] The television device 1050 includes a receiver, a modem, and the like. This allows reception of general television broadcasts, and can also be used for wired or wireless reception via a modem. By connecting to a network, communication can be one-way (sender to receiver) or two-way It is also possible to communicate information in both directions (between sender and receiver, or between receivers). .

[0543] The television device 1050 also includes an external connection terminal 1054 and a storage medium playback / recording unit 1055. 052, and an external memory slot. The external connection terminal 1054 is a It can be connected to any type of cable, enabling data communication with a personal computer, etc. In the storage medium playback and recording unit 1052, a disk-shaped recording medium is inserted and It is possible to read the stored data and write it to the recording medium. Images and videos stored in the external memory 1056 inserted in the reslot It is also possible to display it on the display unit 1053.

[0544] In addition, when the off-leak current of the transistor described in the above embodiment is extremely small, By applying this transistor to the external memory 1056 and the CPU, power consumption can be reduced sufficiently. This results in a highly reliable television apparatus 1050 with reduced power consumption.

[0545] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done. EXAMPLES

[0546] In this embodiment, the film was formed immediately after deposition (referred to as-sputtered) or in an oxygen-containing atmosphere. After the heat treatment at 450°C in the atmosphere, the top surface of each sample with the CAAC-OS film was Transmission electron diffraction patterns were acquired while scanning the sample for 60 seconds at a speed of 5 nm / second. The diffraction pattern was observed while scanning. That is, the irradiation position of the nano-beam electron beam was one-dimensionally scanned. The diffraction pattern was observed while the wavelength was gradually changed within a range of 300 nm. The CAAC rate was calculated by converting the folding pattern into still images every 0.5 seconds. A nano-beam electron beam with a probe diameter of 1 nm was used as the electron beam. The CAAC conversion rate was calculated using the average value of the six samples. .

[0547] The CAAC ratio in each sample is shown in FIG. The AAC ratio was 75.7% (non-CAAC ratio was 24.3%). The CAAC content of the treated CAAC-OS membrane was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after heat treatment at 450°C than immediately after film formation. That is, the non-CAAC ratio is reduced by heat treatment at a high temperature (e.g., 400°C or higher). In addition, the CAAC content is increased when the temperature is heated below 500°C. It can be seen that a CAAC-OS membrane with a high CAAC content can be obtained even with

[0548] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The pattern was a folded pattern. In addition, the amorphous oxide semiconductor film was not observed in the measurement area. Therefore, the heat treatment could not produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the neighboring domains influences the rearrangement of the CAAC domain. .

[0549] 37(B) and 37(C) show the CAAC- 37(B) and 37(C) are high-resolution TEM images of the planar surface of the OS film. It can be seen that the CAAC-OS film after the 450℃ heat treatment has a more homogeneous film quality. That is, the quality of the CAAC-OS film is improved by heat treatment at high temperatures. I understand.

[0550] Using this measurement method, it is possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.< / cpu>

Claims

[Claim 1] A first nitride insulating film; a first oxide insulating film on the first nitride insulating film; a metal oxide film on the first oxide insulating film; a first conductive film electrically connected to the metal oxide film; a second conductive film electrically connected to the metal oxide film; a second oxide insulating film on the first conductive film and on the second conductive film; a second nitride insulating film on the second oxide insulating film; The metal oxide film is a resistance element including an area in which, when the observation location is changed one-dimensionally within a range of 300 nm using a transmission electron diffraction measurement device, the rate at which a diffraction pattern having bright spots indicating orientation is observed is 70% or more but less than 100%.

Images