Manufacture of membrane device

Abstract

To provide a method for forming a membrane of a semiconductor membrane device.SOLUTION: A method includes providing an active silicon layer 6, an embedded oxide (BOX) layer 8, and a silicon-on-insulator (SOI) substrate 4 including a handle wafer 10, determining a membrane region 12 of the substrate, locally removing the BOX layer 8 in at least a part of the membrane region 12, providing one or more dielectric layers 13 on the active silicon layer 6, etching the substrate, and forming a membrane including the one or more dielectric layers in the membrane region 12, wherein the etching includes an anisotropic etching passing through the handle wafer 10 and the active silicon layer 6, using an etching mask defining an etching region, and the etching region overlaps at least a part of the membrane region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to the manufacture of membrane devices. [Background technology]

[0002] Microfabricated membrane devices are used in a variety of different technologies such as sensor technology (e.g., pressure sensors), microphones, transducers, and actuators. The performance of the membrane is highly sensitive to the effective dimensions of the membrane and its geometry and other design features. Summary of the Invention [Problem to be solved by the invention]

[0003] There is a continuing need to improve the manufacturing processes for providing membrane devices. [Means for solving the problem]

[0004] Aspects of the present invention provide a method of making a membrane device, such as a MEMS membrane device, as claimed in the accompanying claims.

[0005] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 shows a schematic cross-sectional view of a membrane device. [Diagram 2] FIG. 2 shows a schematic cross-sectional view of another membrane device. [Diagram 3] 1 shows a schematic cross-sectional view of a further membrane device; [Figure 4] 1 shows a schematic cross-sectional view of a further membrane device; [Diagram 5] FIG. 1 shows a schematic cross-sectional view of an apparatus comprising an array of membrane devices. [Figure 6A]1 illustrates method steps for forming a membrane device. [Figure 6B] 1 illustrates method steps for forming a membrane device. [Figure 6C] 1 illustrates method steps for forming a membrane device. [Figure 6D] 1 illustrates method steps for forming a membrane device. [Figure 6E] 1 illustrates method steps for forming a membrane device. [Figure 7] 1 shows a schematic cross-sectional view of a further membrane device; [Figure 8A] 5 illustrates steps of another method for forming a membrane device. [Figure 8B] 5 illustrates steps of another method for forming a membrane device. [Figure 8C] 5 illustrates steps of another method for forming a membrane device. [Figure 8D] 5 illustrates steps of another method for forming a membrane device. [Figure 8E] 5 illustrates steps of another method for forming a membrane device. [Figure 8F] 5 illustrates steps of another method for forming a membrane device. [Figure 9A] 1 illustrates some steps in a method of forming a membrane device. [Figure 9B] 1 illustrates some steps in a method of forming a membrane device. [Figure 9C] 1 illustrates some steps in a method of forming a membrane device. [Figure 9D] 1 illustrates some steps in a method of forming a membrane device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] FIG. 1 shows a membrane device 2 including an SOI substrate 4 including an active silicon layer 6, a buried oxide (BOX) layer 8, and a handle wafer 10 (comprising silicon). The membrane 12 is formed from one or more dielectric layers (typically SiO2) 13 and is defined by an opening in the active silicon layer 6. To form the membrane, the type of etch of the BOX layer 8 can be changed to etch the substrate from the backside (the side of the handle wafer 10). It can be difficult to align the backside etch with the frontside features, which increases the tolerance of the membrane location. The dashed line 14 indicates the intended / nominal membrane area, whereby the (actual) membrane 12 is offset from the nominal membrane area due to these tolerances. Furthermore, the handle wafer 10 has a relatively large thickness (e.g., >400 μm), which can have a significant effect on the final membrane dimensions even with small sidewall angles, thereby increasing the tolerances.

[0008] FIG. 2 shows a membrane device 2 with a SOI substrate 4. Similar or equivalent features in different figures are given the same reference numbers to aid understanding and are not intended to limit the illustrated embodiment. Unlike FIG. 1, the membrane 12 coincides with the nominal membrane area. The membrane etch from the backside is still offset, but the BOX layer 8 has been locally removed before the membrane etch and is used as an etch mask to define the membrane area. FIG. 2 shows a cross section of the membrane device 2, where the shape of the membrane 12 is typically circular with the membrane diameter. Other shapes of the membrane 12 are also possible, such as a rectangle with a width and length.

[0009] The BOX layer 8 can be precisely removed from the front side, for example, using a handle wafer contact (HWC) module (e.g., a module including a series of steps such as those shown in Figures 9A-9D below) in a complementary metal oxide semiconductor (CMOS) process. The HWC module can be used when processing SOI substrates to form a small contact area between the active silicon layer 6 and the handle wafer 10 underneath. The HWC module has been used when making high voltage (HV) devices to change the dielectric breakdown behavior across the BOX layer 8. The HWC module is applied at the beginning of the CMOS process, before the active silicon layer 6 is populated (i.e., before the active silicon layer 6 is doped to make the semiconductor device) and before back-end-of-line (BEOL) processing, whereby the active silicon layer 6 is covered by one or more metal layers to provide electrical connections to the active silicon layer 6 and dielectric layers to insulate and separate the metal layers. The HWC module typically includes two etching steps followed by an epitaxial silicon growth step to provide an opening in the BOX layer 8 such that the active silicon layer 6 is in direct contact with the handle wafer 10 in the opening. To fabricate the illustrated membrane device 2, the HWC module is used to create a much larger opening that defines the membrane area. The HWC module does not need to be adapted and can still be used when fabricating one or more HV transistors on the substrate 4.

[0010] Since the BOX layer 8 has been locally removed in the membrane area, a single anisotropic etch that is silicon selective can be used to form the membrane 12. That is, unlike the fabrication of the device shown in FIG. 1, it is not necessary to change the etch after reaching the BOX layer 8 to remove silicon dioxide and then change again to etch the active silicon layer 6. Instead, a single etch (e.g., DRIE, deep reactive ion etching) can be used to etch completely through both the handle wafer 10 and the active silicon layer 6. The etch stops on the membrane 12, which includes one or more dielectric layers (e.g., oxide). In one embodiment, the membrane 12 includes a metal layer that can be used as an etch stop layer. In this case, the SiO2 etch is performed after the Si etch and therefore may be less advantageous.

[0011] The membrane device 2 may also include fiducial markers for aligning the membrane etch (i.e., for aligning an etch mask on the backside). FIG. 3 shows a membrane device 2 with two metal structures 16 that are fiducial markers for aligning a membrane etch mask (not shown). The metal structures 16 may include a portion of a patterned metal top layer formed in a BEOL process of a CMOS process. The position of the membrane etch mask relative to the nominal membrane area can be determined by optically scanning the front side of the wafer. For example, an etching tool (for providing / applying the membrane etch mask and performing the etch) can be fixed in a fixed position relative to the optical scanner. The substrate 4 can then be placed between the optical scanner and the etching tool. The substrate 4 is then moved relative to the optical scanner and the fiducial markers are detected from the reflection. By aligning the fiducial markers relative to the optical scanner on the front side, the substrate 4 is also aligned relative to the etching tool on the back side.

[0012] Metal structures 16 are located on either side of membrane 12 so as not to impede flexure of the membrane in use.

[0013] The use of fiducial markers can improve the accuracy of the position of the etch mask, thus allowing a smaller etch footprint to be used.

[0014] FIG. 4 shows an alternative embodiment in which an etching mask (not shown) defines a membrane area that is smaller than the opening in the BOX layer 8. In this embodiment, the accuracy of the position of the final membrane 12 provided by using fiducial markers 16 to position the membrane etching mask may be sufficient so that the membrane etching mask can be used alone to define the membrane area instead of the (patterned) BOX layer 8. This embodiment still has the advantage that only one membrane etching step is required to form the membrane. For example, a single DRIE can be used to etch through the handle wafer 10 and the active silicon layer 6 down to the membrane 12. Another potential advantage is that there is no edge / ledge between the BOX layer 8 and the handle wafer 10 (as there is in the embodiment of FIGS. 2 and 3).

[0015] FIG. 5 shows a schematic cross-sectional view of an apparatus 18 comprising a plurality of membrane devices 2 in an array. The apparatus 18 can include any one of the membrane devices shown in FIGS. 2-4. Each membrane device 2 is formed simultaneously. The apparatus 18 can be a micro-mechanical systems device (MEMS) array. For example, the apparatus 18 can include an actuation layer 20, such as a piezoelectric layer, for actuating the membrane 12 of the device 2. For example, the apparatus 18 can be an ultrasonic transducer, a micropump, a pressure sensor, or the like. Between the membranes 12 of the device, a metal layer 21 is disposed between the dielectric layers 13 and provides electrical connection to the membrane devices 2.

[0016] 6A-6E show several steps of a method for making a membrane device, which may be used, for example, to form the membrane device 2 described in relation to FIG.

[0017] FIG. 6A shows an SOI substrate 4 (also called an SOI wafer) that includes an active silicon layer 6, a BOX layer 8, and a handle wafer 10.

[0018] FIG. 6B shows the SOI substrate 4 after removing a portion of the BOX layer 8 to form an opening 22 where the active silicon layer 6 contacts the handle wafer 10. The opening 22 may be circular or square or some other shape and may have a diameter or width of at least 30 μm. For example, this method can be used to provide an opening 22 with a width in the range of 30 μm to 200 μm. The portion of the BOX layer 8 can be removed using a HWC module of a CMOS process.

[0019] FIG. 6C shows the SOI substrate 4 after forming a number of dielectric layers 13 on the active silicon layer 6. The dielectric layers 13 may be constituted by a CMOS back-end stack including metallization for connecting to the active silicon layer 6 to form semiconductor devices (e.g., transistors, diodes, etc.). Two fiducial markers 16 are formed in (or between) the dielectric layers 13. The fiducial markers 13 are formed on either side of an opening 22 in the BOX layer 8. That is, the fiducial markers 16 do not overlap the opening 22. The fiducial markers 16 can be used to position an etching mask on the back side (on the handle wafer 10). The fiducial markers 16 can be formed by depositing a metal layer on one of the dielectric layers 13 and patterning the metal layer to form a metal structure that can be used as a fiducial marker. The metal layer may be the top metal layer of the CMOS back-end stack.

[0020] FIG. 6D shows a membrane device 2 including a membrane 12 formed by etching from the backside. The etching involves anisotropic etching through the handle wafer 10, through the openings 22, and through the active silicon layer 6. This etching is anisotropic and has high selectivity to silicon. The etching area (defined by the openings in the membrane etch mask) is larger than the openings 22 and covers the entire openings 22. Thus, the remaining BOX layer 8 limits the width of the etching through the active silicon layer 6, since the etching stops on the BOX layer 8 in the etching areas that do not overlap the openings 22 in the BOX layer 8. The multiple dielectric layers act as an etch stop for the active silicon layer 6. The etching is typically DRIE. The etching mask is positioned using fiducial markers 16. A small offset of the etching mask relative to the substrate 4 does not affect the final membrane 12, which is still laterally defined by the openings 22 in the BOX layer 8.

[0021] FIG. 6E shows the membrane device after providing an actuation layer 20 (eg, a piezoelectric layer) for actuating the membrane to induce bending in the membrane.

[0022] 7 shows a schematic cross-section of the membrane device 2 in use. A voltage is applied across the actuation layer 20 causing it to deflect the membrane 12.

[0023] 8A-8F show steps of a method for making a membrane device, which includes two successive etching steps to release the membrane 12. The method may be particularly suitable for making membrane devices with large membranes (e.g., with a width or diameter of >100 μm).

[0024] FIG. 8A shows an SOI substrate 4 (also referred to as an SOI wafer) that includes an active silicon layer 6, a BOX layer 8, and a handle wafer 10.

[0025] 8B shows the SOI substrate 4 after removing a portion of the BOX layer 8 to form a number of openings 24 where the active silicon layer 6 contacts the handle wafer 10. The portion of the BOX layer 8 can be removed using a HWC module of a CMOS process. The number of openings 24 is located in the membrane area where the membrane is to be formed.

[0026] 8C shows the substrate 4 after forming an isolation structure 26 in the active silicon layer 6. The isolation structure 26 may include a deep trench isolation (DTI). The isolation structure 26 may be a circular wall surrounding the membrane region. The isolation structure 26 extends from the top surface of the active silicon layer 6 to the BOX layer 8.

[0027] FIG. 8D shows the SOI substrate 4 after forming a number of dielectric layers 13 on the active silicon layer 6. The dielectric layers 13 may be constituted by a CMOS back-end stack including metallization for connecting to the active silicon layer 6 to form semiconductor devices (e.g., transistors, diodes, etc.). Two fiducial markers 16 are formed in (or between) the dielectric layers 13. The fiducial markers 16 are formed on either side of the isolation structure 26. The fiducial markers 16 are used to position an etching mask on the back side (on the handle wafer 10). The fiducial markers 16 may be formed by depositing a metal layer on one of the dielectric layers 13 and patterning the metal layer to form a metal structure that can be used as a fiducial marker. The metal layer may be the top metal layer of the CMOS back-end stack.

[0028] FIG. 8E shows the structure after etching from the backside. The etch involves anisotropic etching through the handle wafer 10, through the openings 24, and through the active silicon layer 6 in the areas exposed by the openings 24. This etch is anisotropic and highly selective to silicon. The etched areas (defined by the openings in the membrane etch mask) cover the openings 24. The multiple dielectric layers act as etch stop layers. The etch is typically DRIE. The etch mask is positioned using fiducial markers 16. Other methods of aligning the etch mask may alternatively be used.

[0029] Figure 8F shows the membrane device 2 after an isotropic etching step. The isotropic etching removes the remaining active silicon in the active silicon layer 6 in the membrane area, thereby releasing the membrane 12. The openings 24 in the BOX layer 8 allow the etchant to penetrate into and remove the active silicon layer 6 in the membrane area. The isolation structures 26 act as lateral etch stops and define the lateral membrane dimensions.

[0030] 9A-9D show some steps of a method for forming a membrane device. For example, this method can be used to form the membrane device described in relation to FIGS. 2, 3 and 4 above. 9A-9D show some steps of a method for removing a portion of the BOX layer 8 to form an opening 22 that defines a membrane region. The steps shown can be performed by a HWC module of a CMOS process.

[0031] FIG. 9A shows the SOI substrate 4 after application of an etching mask 28 on the active silicon layer 6. In FIG. 9B, a first etching step is performed to remove the part of the active silicon layer 6 exposed by the etching mask 28. The first etching stops on the BOX layer 8. In FIG. 9C, a second etching step is performed to remove the BOX layer 8 exposed by the etching mask 28, thereby forming the opening 22. The second etching exposes a part of the handle wafer 10. After the local removal of the BOX layer 8, the etching mask 28 is removed and silicon is epitaxially grown on the handle wafer 10 to provide the structure shown in FIG. 9D.

[0032] In general, embodiments described herein provide a method for forming a membrane of a semiconductor membrane device, the method comprising: providing a silicon-on-insulator (SOI) substrate including an active silicon layer, a buried oxide (BOX) layer, and a handle wafer; and determining a membrane area of ​​the substrate. The method further comprises: locally removing the BOX layer in at least a portion of the membrane area; providing one or more dielectric layers on the active silicon layer; and etching the substrate to form a membrane including the one or more dielectric layers in the membrane area, the etching comprising an anisotropic etch through the handle wafer and the active silicon layer using an etch mask that defines an etch area, the etch area overlapping at least a portion of the membrane area.

[0033] The etching area can be larger than the membrane area and overlaps the entire membrane area. The openings in the BOX layer can be used to define the lateral dimensions of the membrane during etching, allowing the etching area to be larger, which allows for increased tolerances in the alignment of the etching mask without affecting the membrane properties. Typically, the membrane area and the etching area are substantially concentric. The membrane can be substantially circular or have, for example, a rectangular shape.

[0034] The method may also include providing a metal layer before or during the step of providing one or more dielectric layers, which may be used as an etch stop layer (to stop the anisotropic etch after passing through the active silicon layer) and may form part of the final membrane.

[0035] Typically, the anisotropic etch is a deep reactive ion etch (DRIE). The etch must be deep enough to penetrate the entire thickness of the handle wafer, which can be >400 μm. The BOX layer can be removed in the entire membrane area, or in parts of the membrane area to provide multiple openings in the membrane area.

[0036] The etching step may further include an isotropic etch to remove silicon contained in the active silicon layer in the membrane area. An isolation structure formed from the front side may be used to stop the etch, thereby defining a lateral dimension of the membrane. For example, the method may further include a deep trench isolation (DTI) step to form an oxide barrier in the active silicon layer around the membrane area, the oxide barrier stopping the isotropic etch.

[0037] The method may further include depositing a piezoelectric layer on the one or more dielectric layers to cover the membrane area. The piezoelectric layer may be used to deflect the membrane.

[0038] The step of locally removing the BOX layer includes:

[0039] applying a mask having openings defining membrane regions;

[0040] and etching through the active silicon layer and the BOX layer down to the handle wafer. The etching typically includes two separate etching steps to remove the active silicon layer and the BOX layer, respectively. The same etch mask can be used for both etching steps.

[0041] The step of locally removing the BOX layer may be part of a complementary metal oxide semiconductor (CMOS) process to provide contact between the handle wafer and the active silicon layer. This part of the CMOS process may be performed using a handle wafer contact (HWC) module. After removing the BOX layer, the method may include providing epitaxial silicon directly on the handle wafer in the membrane area. In one embodiment, a MEMS-dedicated SOI wafer may be used.

[0042] The method may further include forming one or more fiducial markers on or in the one or more dielectric layers and aligning the etching mask using the fiducial markers prior to the etching step. The one or more fiducial markers may include one or more metal structures, and forming the one or more fiducial markers may include depositing a metal layer on one of the one or more dielectric layers and patterning the metal layer.

[0043] The step of providing one or more dielectric layers may comprise a complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process.

[0044] While specific embodiments of the invention have been described above, it should be understood that the invention may be practiced otherwise than as described. The above description is intended to be illustrative and not limiting. It will be apparent to those skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set out below.

[0045] Each feature disclosed or illustrated in this specification may be incorporated into the present invention alone or in any suitable combination with any other feature disclosed or illustrated in this specification.

Claims

1. 1. A method of forming a membrane for a semiconductor membrane device, the method comprising: providing a silicon-on-insulator (SOI) substrate including an active silicon layer, a buried oxide (BOX) layer, and a handle wafer; determining a membrane area of ​​the substrate; locally removing the BOX layer in at least a portion of the membrane area; providing one or more dielectric layers over said active silicon layer; and etching the substrate to form the membrane comprising the one or more dielectric layers in the membrane region, the etching comprising an anisotropic etch through the handle wafer and the active silicon layer using an etch mask that defines an etch region, the etch region overlapping at least a portion of the membrane region.

2. The method of claim 1 , wherein the etched area is larger than the membrane area and overlaps the entire membrane area.

3. The method of claim 1 or 2, wherein the anisotropic etch is a deep reactive ion etch (DRIE).

4. The method of claim 1 , wherein the step of locally removing the BOX layer comprises removing the BOX layer in the entire membrane area.

5. 4. The method of claim 1, wherein the step of locally removing the BOX layer comprises removing the BOX layer from a portion of the membrane area, and the etching step further comprises an isotropic etch to remove silicon contained in the active silicon layer within the membrane area.

6. 6. The method of claim 5, further comprising: deep trench isolation (DTI) for forming an oxide barrier in the active silicon layer around the membrane area, the oxide barrier stopping the isotropic etch.

7. The method of claim 1 , wherein the membrane region and the etch region are substantially concentric.

8. The method of claim 1 , further comprising depositing a piezoelectric layer on the one or more dielectric layers to cover the membrane region.

9. The step of locally removing the BOX layer comprises: applying a mask having openings defining said membrane regions; Etching through the active silicon layer and the BOX layer down to the handle wafer; 9. The method of claim 1 , comprising:

10. 10. The method of claim 9, wherein the etching comprises two separate etching steps to remove the active silicon layer and the BOX layer, respectively.

11. 11. The method of any one of claims 1 to 10, wherein the step of locally removing the BOX layer is part of a complementary metal oxide semiconductor (CMOS) process to provide contact between the handle wafer and the active silicon layer.

12. 12. The method of any one of claims 9 to 11, further comprising providing epitaxial silicon directly on the handle wafer in the membrane region.

13. 13. The method of claim 1, further comprising forming one or more fiducial markers on or in the one or more dielectric layers, and aligning the etching mask using the fiducial markers prior to the etching step.

14. 14. The method of claim 13, wherein the one or more fiducial markers comprise one or more metal structures, and the step of forming the one or more fiducial markers comprises depositing a metal layer on one of the one or more dielectric layers and patterning the metal layer.

15. 15. The method of claim 1, wherein the step of providing one or more dielectric layers comprises a complementary metal oxide semiconductor (CMOS) back-end of line (BEOL) process.

Images