Manufacturing method of ultrathin high-density multilayer interconnection ceramic board

Abstract

To provide a ceramic board which has good heat dissipation, and in which an integration density is high.SOLUTION: According to an embodiment, the present invention discloses a manufacturing method of an ultrathin high-density multilayer interconnection ceramic board, containing steps of: preparing a ceramic wafer, performing a laser punching to the ceramic wafer, and forming a via hole; performing a vacuum magnetron sputtering to the ceramic wafer, and forming a seed titan layer and a copper layer onto a front surface of the ceramic wafer and on a wall of the via hole by the sputtering; manufacturing a ceramic double-layer core plate; manufacturing a multilayer substrate; manufacturing a vertical interconnection multilayer substrate; and manufacturing a high-end multilayer HDI ceramic board. The multilayer ceramic plate manufactured in the above mentioned processing can be easily processed as compared with LTCC and HTCC, and an energy consumption amount for the processing is deteriorated. A heat conductivity of a finished product is improved. A wiring is more accurate; a conductive resistance is low; and a signal transmission loss is low.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to the field of printed circuit board manufacturing, and more particularly to a method for manufacturing ultra-thin, high density, multi-layer interconnect ceramic substrates. [Background technology]

[0002] With the vigorous development of the microelectronics packaging industry, electronic packaging technology is developing toward miniaturization, high density, multiple output, and high reliability. Currently, there are four types of substrate materials in common use: plastic substrates, metal substrates, ceramic substrates, and composite substrates. Due to its good high temperature properties, corrosion resistance, high thermal conductivity, and thermal expansion coefficient, ceramic substrates have become the basic material for the structure and interconnection technologies of high-power electronic circuits.

[0003] Ceramic substrates are mainly divided into DPC, TFC, DBC, AMB, LTCC / HTCC, etc. according to the process. In the manufacturing process of direct copper plated ceramic substrate (DPC: Direct Plated Copper), first, the ceramic wafer is pretreated and cleaned, and a Ti / Cu layer is deposited on the surface of the wafer by vacuum sputtering to form a seed layer. Then, wiring is made by photolithography, development, and etching processes. Finally, the thickness of the wiring is increased by electroplating / electroless plating, and the photoresist is removed to manufacture the substrate. Thick film ceramic substrate (TFC: Thick Film Ceramic) is manufactured by applying metal slurry to the surface of a ceramic wafer using screen printing technology, followed by drying and high-temperature sintering (700-800°C). Metal slurry is generally made of metal powder (Ag-Pd or Ag-Pt), organic resin, glass powder, etc. The resin binder burns off during high-temperature sintering, and most of what remains is pure metal. The glassy binder acts on the surface of the ceramic substrate, so the thickness of the metal layer after sintering is 10 to 20 μm, and the minimum line width is 0.3 mm. Direct bonded copper ceramic substrates (DBC: Direct Bonded Copper) are made by eutectic sintering a ceramic wafer (Al2O3 or AlN) and copper foil at high temperature (1065°C), and finally forming wiring by etching according to the wiring requirements. Copper-clad ceramic substrates (AMB: Active Metal Brazing) are made by adding active elements to the brazing material, forming a reaction layer on the ceramic surface through a chemical reaction, and improving the wettability of the brazing material on the ceramic surface, thereby chemically bonding the ceramic and metal. HTCC (High Temperature Co-fired Ceramic Substrate) is made by adding an organic binder to ceramic powder (Al2O3 or AlN), mixing it uniformly to make a paste-like slurry, then using a doctor blade to cut the slurry into sheets, and turning the sheet-like slurry into green through a drying process. Next, via holes are designed and drilled according to the design of each layer, and wiring and via holes are filled by screen printing metal slurry. Finally, each green is stacked and sintered in a high-temperature furnace (1600℃).The manufacturing process of LTCC (low temperature co-fired ceramic substrate) is similar to that of HTCC, except that Al2O3 powder is mixed with 30-50% low melting point glass frit and the sintering temperature is reduced to 850-900℃.

[0004] In the above manufacturing process, except for LTCC and HTCC, which can be multi-layered, the rest are all single-sided or double-sided wiring. LTCC and HTCC ceramic circuit boards can be multi-layered, but LTCC has limitations due to shrinkage and heat dissipation problems. LTCC is made by sintering slurry and green ceramic tape in an environment of 800-900℃, and the thermal conductivity of the ceramic circuit board is only 2-6W / m·K, which is far lower than the original thermal conductivity of bare ceramic wafers (alumina: 15-25W / m·K, aluminum nitride>170W / m·K, silicon nitride>80W / m·K). The manufacturing process of HTCC is co-firing at a high temperature of 1600℃, and the shrinkage problem during processing affects the line layer, and due to the high processing temperature, the line needs to use high melting point metals such as tungsten, molybdenum, molybdenum, and manganese, and such wiring has high conductor resistivity and large signal transmission loss. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, the object of the present invention is to provide a manufacturing method capable of producing ultra-thin, high-density, multi-layer interconnected ceramic substrates using a low-temperature process (<350°C), which results in ceramic substrates with excellent heat dissipation and high integration density. [Means for solving the problem]

[0006] In order to solve the above problems, the present invention provides providing a ceramic wafer and performing laser drilling on the ceramic wafer to form via holes; performing vacuum magnetron sputtering on the ceramic wafer to sputter a seed titanium layer and a copper layer on the surface of the ceramic wafer and on the walls of the via holes; Producing a ceramic double-layer core board; and b. fabricating a multi-layer substrate.

[0007] Furthermore, the ceramic wafer is a ceramic wafer made of aluminum oxide, aluminum nitride, silicon nitride, or beryllium oxide.

[0008] Furthermore, when the seed titanium layer and copper layer are formed by sputtering on the surface of the ceramic wafer and the wall of the via hole, the thickness of the titanium layer is 0.25 μm or more, and the thickness of the copper layer is 0.8 μm or more.

[0009] Further, the ceramic wafer is subjected to vacuum magnetron sputtering to form a seed titanium layer and a copper layer on the surface of the ceramic wafer and the wall of the via hole by sputtering, and then The method further includes a step of performing electroplating on the ceramic substrate to fill the holes, thereby ensuring that the via holes of the ceramic wafer are filled, and at the same time, increasing the thickness of the surface copper of the ceramic wafer to a thickness of 45 μm or more.

[0010] Furthermore, the step of manufacturing a ceramic two-layer core board includes: polishing the ceramic wafer with the increased thickness of the surface copper by filling the holes by electroplating to make the copper surface flat; performing a first pattern transfer to transfer a desired wiring pattern onto the copper surface; Etching the desired traces on the copper surface by an etching process; and performing titanium removal on the ceramic wafer using a chemical solution to sufficiently remove the seed titanium layer and obtain a ceramic two-layer core board.

[0011] Furthermore, after producing the ceramic two-layer core board, performing AOI inspection and full electrical testing on the ceramic core board; forming a brown oxide thin film on the copper surface of the ceramic core plate by brown oxidation treatment.

[0012] The method further includes a step of manufacturing a multi-layer substrate after manufacturing the two-layer ceramic core board, the step including: A step of assembling and laminating a semi-hardened sheet + copper foil or FPC on the upper and lower surfaces of the ceramic core board after brown oxidation treatment; and laminating the semi-hardened sheet + copper foil or FPC and the ceramic core board together by a lamination method to obtain a laminated multi-layer board.

[0013] Further, after manufacturing the multi-layer board, a step of manufacturing a top-bottom interconnection multi-layer board is included, which step includes: a mark point exposing step of removing the copper and PP dielectric of the outer layer using a laser to expose the mark point of the inner layer; laser processing the blind hole to form a channel of the blind hole in the inner layer and the outer layer through the mark point in the inner layer; a slag removal step of completely removing the slag in the blind hole by plasma microetching; a copper deposition step of depositing a copper seed metal on the walls of the blind holes by chemical copper deposition; A panel plating step in which a seed layer made by chemical copper deposition is electroplated to a thickness of 3 to 5 μm; The blind hole electroplating step involves filling the blind holes completely with electroplating and at the same time electroplating the surface of the board with copper to a thickness of 40μm or more. a polishing step of polishing the copper surface of the substrate after electroplating to a flat surface; a second pattern transfer step of transferring the image onto the copper surface by an image transfer process; and an etching step of forming a wiring pattern by an etching process to obtain a top-bottom interconnection multi-layer board.

[0014] Further, the method includes the step of manufacturing a high-end multi-layer HDI ceramic substrate after manufacturing the upper and lower interconnection multi-layer board, the step including: Drilling trenches in a controlled thickness in the upper and lower interconnect multi-layer board and removing the insulating dielectric with a picosecond laser to expose pads for high power chip welding on the ceramic core board; forming a solder mask / symbol; performing a surface treatment; and using a picosecond laser to scribe and slice to obtain a finished high-end HDI ceramic multi-layer substrate.

[0015] The present invention also provides an ultra-thin, high density, multi-layer interconnect ceramic substrate produced by the above method. Effect of the Invention

[0016] Compared with the prior art, the present invention adopts a thermoelectric separation design, keeps the devices with high heat dissipation in the ceramic layer, and vertically interconnects and integrates the remaining conductors. The present invention manufactures multi-layer wiring based on the traditional two-layer DPC ceramic substrate, and the multi-layer ceramic plate manufactured by this process is easier to process than LTCC and HTCC, consumes less energy for processing, has better thermal conductivity of the finished product, has more precise wiring, lower conductor resistivity, and lower signal transmission loss. In order to more clearly describe the technical solutions of the embodiments of the present application, the following briefly describes the accompanying drawings that need to be used in the description of the embodiments. The drawings in the following description are some embodiments of the present application, and it is obvious that those skilled in the art can derive other drawings from these drawings without any creative efforts. [Brief description of the drawings]

[0017] [Figure 1]1 is an example of a flowchart of an embodiment of a manufacturing method of the present invention. [Diagram 2] FIG. 1 is an example of a stacking schematic diagram of an embodiment of the product of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, but it is clear that the described embodiments are only some of the embodiments of the present application and not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative efforts belong to the scope of protection of the present application.

[0019] It should be noted that the terms "comprise" and "containing," when used in this specification and the appended claims, indicate the presence of described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0020] It should also be understood that the terms used in the specification of this application are used merely for the purpose of describing particular embodiments, and are not intended to limit the scope of the application. As used in the specification and the appended claims, the singular forms "a," "one," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0021] Furthermore, the term "and / or" as used in the specification and appended claims of this application should be understood to mean and include any and all possible combinations of one or more of the associated listed items.

[0022] As shown in Figure 1, Figure 1 is an example of a flow chart of an embodiment of the manufacturing method of the present invention. The present invention specifically provides an embodiment of a manufacturing method of an ultra-thin high-density multi-layer interconnect ceramic substrate, including the following steps: S1: A 0.32 mm thick high strength ceramic wafer (flexural strength >700 MPa) is used to perform laser drilling with a fiber laser, penetrating both the front and back sides. The ceramic wafers used herein include, but are not limited to, ceramic wafers made of aluminum oxide, aluminum nitride, silicon nitride, and beryllium oxide. In this embodiment, a very thin and high-strength silicon nitride ceramic wafer having a thickness of 0.32 mm is used. S2: Chemically remove the slag using hydrofluoric acid + hydrogen peroxide to completely remove the slag caused by the drilling of S1, and then clean the hole walls and ceramic surface by multiple ultrasonic cleaning with pure water. Here, for the laser drilled ceramic rug, the particle slugs are removed by physical scraping, and then the low density layer on the hole wall is etched away using chemicals, thereby ensuring the quality of the product. S3: Metallization of ceramic seed layer: Using vacuum magnetron sputtering, sputter a seed titanium layer and a copper layer on a silicon nitride ceramic wafer, and at the same time, deposit a seed metal thin film layer on the ceramic hole wall, so that the thickness of the titanium layer is 0.25 μm or more, and the thickness of the copper layer is 0.8 μm or more. Here, 6.0 × 10 -4 Using the alternating magnetic and electric fields at a vacuum level of 100 Pa, electrons collide with argon gas to generate ions, which then collide with the target surface under the action of the electric field, transferring and depositing the titanium and copper targets onto the surface of the ceramic wafer. S4: The ceramic wafer with the seed layer is electroplated to fill the via holes and thicken the surface copper. After electroplating, the via holes are filled with copper pillars, and the surface copper is also electroplated to a thickness of 45 μm or more. The ceramic wafer on which the seed layer was formed is electroplated to fill the holes, completely filling the upper and lower via holes and increasing the thickness of the surface copper to 45 μm or more. S5: The entire copper surface of the substrate is polished flat by mechanically polishing the substrate after electroplating, and the copper surface after polishing is controlled to be between 30 and 40 μm. In this embodiment, the substrate after electroplating is mechanically polished to uniformly polish the copper surface, and the copper thickness after polishing is controlled to about 35 μm. S6: The first pattern transfer is performed on the polished substrate through the processes of film drying, exposure, and development to transfer the image onto the copper surface. At this time, the pads to be reserved are protected with a dry film through the panel plating process, and the copper for the wiring intervals to be removed by etching is exposed. S7: Remove the copper in the trend by reducing the copper by etching to obtain a wiring pattern (for example, after removing the film, the pattern plating process uses a micro-etchant to etch and remove the bottom seed copper layer); S8: Using a titanium removal solution, the titanium layer, which is the bottom seed layer, is completely removed to obtain a ceramic two-layer core board. Note that in steps S4 to S8, a pattern plating process may be adopted in which pattern transfer is performed, followed by electroplating, followed by polishing, film removal, and micro-etching of the seed copper. S9: Intermediate Test: The ceramic core board is subjected to AOI, full electrical testing to ensure the core board meets the requirements. S10: After inspection, the ceramic core plate is subjected to a brown oxidation treatment. S11: Combination / Lamination: In this application, 1080 RC67% is laminated on the upper and lower surfaces of the high Tg semi-hardened sheet, respectively, and HOZ is used for the copper foil, or FPC pure adhesive material is used. S12: Using the lamination method, (PP + copper foil) or FPC and ceramic core board are laminated together. S13: Since the ceramic core board is a brittle material, the marking points are exposed by laser, that is, the marking area is designed according to the core board, and the copper and PP of the outer layer are removed by laser to expose the marking points of the inner layer. S14: Through the alignment of the mark points on the core board, the laser is used to form the blind hole channels on the inner and outer layers. S15: The substrate after the laser processing is subjected to a slag removal and micro-etching process using plasma to completely remove the slag in the blind holes. S16: Copper deposition: Deposit seed metal copper on the blind hole walls by chemical copper deposition. S17: Panel plating: The thickness of the chemical copper deposition layer is increased to 3-5 μm by electroplating, thereby avoiding the etching of the copper deposition layer by the pretreatment for filling holes. S18: Blind hole electroplating: The blind hole channel is filled reliably by electroplating, and at the same time, the surface copper of the substrate is electroplated to a thickness of more than 40 μm. S19: Polishing: The copper surface of the substrate after electroplating is polished flat. S20: Second pattern transfer: similar to S6 process, transfer the image onto the copper surface by image transfer process; S21: Etching: Similar to the S7 process, a wiring pattern is formed. S22:AOI / Electrical Test 2:AOI inspection, full electrical test to ensure the product meets the requirements. S23: S10 to S22 are repeated to manufacture many layer wirings. S24: Open trenches with controlled thickness, i.e. remove insulating dielectric with picosecond laser, to expose pads of ceramic core plate for welding high power chips. Here, a picosecond laser is used to burn away the dielectric above the pad to which the core piece is welded, exposing the pad of the ceramic core board layer, and a similar process is used to open trenches on the back side of the heat dissipation pad, or to dissipate heat by densely arranging blind holes in an array, as shown in Figure 1. S25: Solder Mask / Symbol: Follow up the product design and form the solder mask / symbol. S26: Surface treatment: Follow up on product design and perform surface treatment. S27: Forming: Scribing and slicing are performed using a picosecond laser to obtain the finished product.

[0023] The board is made of a composite material of PP / FPC and ceramic, so its formation requires double-sided cutting using a laser. First, the PP / FPC layer is cut, and then a notch is formed in the ceramic by the laser, allowing it to be separated into individual pcs.

[0024] As shown in Fig. 2, Fig. 2 is an example of a lamination schematic diagram of an embodiment of the product of the present invention. The present invention also provides an embodiment of an ultra-thin high-density multi-layer interconnect ceramic substrate, the multi-layer interconnect ceramic substrate including a ceramic wafer, and an inner copper foil is formed on the upper and lower surfaces of the ceramic wafer as an inner copper clad layer. In this case, an outer copper foil is laminated on the inner copper clad layer on the upper and lower surfaces of the ceramic wafer by PP to form an outer copper clad layer.

[0025] The ceramic wafer is provided with through holes that can penetrate the upper and lower inner copper clad layers, and a copper base is formed in the through hole to connect the upper and lower inner copper clad layers (upper and lower layer wiring). On one side of the ceramic substrate, a depth control trench is opened at a position corresponding to the through hole, and a ceramic layer pad for welding a high power chip is formed at the position of this depth control trench. On the other side of the ceramic substrate, a depth control trench is also opened at a position corresponding to the through hole, or blind holes are densely arranged in an array to dissipate heat.

[0026] In this embodiment, the multi-layer interconnect ceramic substrate adopts a thermoelectric isolation design form, which keeps the devices with large heat dissipation in the ceramic layer, and vertically interconnects and integrates the remaining conductors, that is, the pads of the devices with low power and no requirement for heat conduction are designed in another wiring layer, and the design does not wire above the heat dissipation pads, thereby ensuring the advantages of good heat dissipation and high integration density of the ceramic substrate.

[0027] Although the specific embodiment of the invention has been described in detail above, it is merely an example, and the present invention is not limited to the above specific embodiment. For those skilled in the art, any equivalent correction or replacement made to the present invention is included within the scope of the present invention, and therefore any equivalent modification, correction, improvement, etc. made within the scope of the present invention without departing from the spirit and principle of the present invention shall be included within the scope of the present invention.

Claims

1. 1. A method for manufacturing an ultra-thin, high density, multi-layer interconnect ceramic substrate, comprising: providing a ceramic wafer and performing laser drilling on the ceramic wafer to form via holes; performing vacuum magnetron sputtering on the ceramic wafer to sputter a seed titanium layer and a copper layer on the surface of the ceramic wafer and on the walls of the via holes; Producing a ceramic two-layer core board; and b. fabricating a multi-layer substrate.

2. 2. The method of claim 1, wherein the ceramic wafer is made of aluminum oxide, aluminum nitride, silicon nitride, or beryllium oxide.

3. 3. The method for manufacturing an ultra-thin high-density multi-layer interconnect ceramic substrate as claimed in claim 2, wherein when a seed titanium layer and a copper layer are formed by sputtering on the surface of the ceramic wafer and the wall of the via hole, the thickness of the seed titanium layer is 0.25 μm or more, and the thickness of the copper layer is 0.8 μm or more.

4. The ceramic wafer is subjected to vacuum magnetron sputtering to form a seed titanium layer and a copper layer on the surface of the ceramic wafer and on the wall of the via hole by sputtering, and then 4. The method of claim 3, further comprising the step of: electroplating on the ceramic substrate to fill the holes, thereby ensuring that the via holes of the ceramic wafer are filled; and at the same time, increasing the thickness of the surface copper of the ceramic wafer to a thickness of 45 μm or more.

5. The step of manufacturing a ceramic two-layer core board includes: polishing the ceramic wafer with the increased thickness of the surface copper by filling the holes by electroplating to make the copper surface flat; performing a first pattern transfer to transfer a desired wiring pattern onto the copper surface; Etching the desired traces on the copper surface by an etching process; 5. The method of claim 4, further comprising the step of: performing titanium removal on the ceramic wafer using a chemical solution to sufficiently remove the seed titanium layer and obtain a ceramic two-layer core board.

6. After the ceramic two-layer core board is manufactured, performing an AOI inspection and a full electrical test on the ceramic core board; 6. The method for manufacturing an ultra-thin, high-density, multi-layer interconnect ceramic substrate according to claim 5, further comprising the step of: forming a brown oxide thin film on the copper surface of the ceramic core plate by brown oxidation treatment.

7. The step of manufacturing a multi-layer substrate includes: a step of assembling and laminating a semi-hardened sheet + copper foil or FPC on the upper and lower surfaces of the ceramic core plate after brown oxidation treatment; and laminating the semi-hardened sheet + copper foil or FPC and the ceramic core board together by a lamination method to obtain a laminated multi-layer board.

8. The steps of manufacturing a top-bottom interconnect multi-layer board include: a mark point exposing step of removing the copper and PP dielectric of the outer layer using a laser to expose the mark points of the inner layer; a blind hole laser processing step of forming a blind hole channel in the inner layer and the outer layer through the mark point in the inner layer; a slag removal step of completely removing the slag in the blind hole by plasma microetching; a copper deposition step of depositing a copper seed metal on the walls of the blind holes by chemical copper deposition; a panel plating step in which a seed layer of chemically deposited copper is electroplated to a thickness of 3-5 μm; a blind hole electroplating step, which uses an electroplating method to completely fill the blind holes and at the same time electroplats the surface of the substrate to a thickness of 40 μm or more with copper; a polishing step of polishing the copper surface of the substrate after electroplating to a flat surface; a second pattern transfer step of transferring the image onto the copper surface by an image transfer process; 8. The method for manufacturing an ultra-thin, high-density, multi-layer interconnection ceramic substrate according to claim 7, further comprising: an etching step of forming a wiring pattern by an etching process to obtain a top-bottom interconnection multi-layer substrate.

9. The steps of manufacturing a high-end multi-layer HDI ceramic substrate include: Drilling trenches in a controlled thickness in the upper and lower interconnect multi-layer board and removing the insulating dielectric with a picosecond laser to expose pads for high power chip welding on the ceramic core board; forming a solder mask / symbol; performing a surface treatment; 9. The method of claim 8, further comprising the steps of: using a picosecond laser to scribe and slice to obtain a finished high-end HDI ceramic multi-layer substrate.

10. An ultra-thin, high density, multi-layer interconnect ceramic substrate produced by the method of any one of claims 1 to 9.

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