Manufacturing method for circuit member with solder bump, and circuit member with solder bump

Abstract

To provide a manufacturing method for a circuit member with solder bump excelling in both connection reliability and insulation reliability, and a circuit member with solder bump.SOLUTION: A manufacturing method for a circuit member with solder bump includes: a pillar formation process for forming a conductive pillar 3 in an electrode region R provided in a predetermined pattern on a first surface 2a of a substrate 2; a deposition process for depositing a solder corpuscle 5 on a region including a top face 3a of the pillar 3 on the first surface 2a of the substrate 2; and an excessive solder removal process for removing excessive solder 12 from a region excluding the top face 3a of the pillar 3.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a circuit member with solder bumps and a circuit member with solder bumps.

Background Art

[0002] As one of the techniques for mounting electronic components with high density, flip chip mounting is known. In flip chip mounting, for example, solder bumps are previously formed on electrodes provided on one circuit member, and the electrodes of one circuit member and the electrodes of the other circuit member are joined by melting the solder bumps. Thereby, a connection structure of circuit members is formed.

[0003] As a technique for forming solder bumps on electrodes, for example, there is a solder bump forming method described in Patent Document 1. This conventional solder bump forming method includes a step of forming a resist pattern in a conductor groove on a substrate, a step of forming a barrier layer on the substrate using the resist pattern as a mask, a step of forming a solder layer on the substrate using the resist pattern as a mask, and a step of removing the resist pattern from the substrate, and is characterized in that the barrier layer is formed by using a vacuum evaporation method in an inert gas atmosphere.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, miniaturization and sophistication of electronic components have advanced, and miniaturization of circuit members used in electronic components has advanced. Along with the miniaturization of circuit members, the electrode size has also been miniaturized. For this reason, even when the electrode size is miniaturized, a circuit member excellent in both connection reliability and insulation reliability is required.

[0006] The present disclosure has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a circuit member with solder bumps and a circuit member with solder bumps that are excellent in both connection reliability and insulation reliability even when the electrode size is miniaturized.

Means for Solving the Problems

[0007] The gist of the present disclosure is as follows.

[0008] [1] A method for manufacturing a circuit member with solder bumps, the method including a pillar forming step of forming conductive pillars in an electrode region provided in a predetermined pattern on one surface side of a substrate, a deposition step of depositing solder fine particles in a region including the top surface of the pillars on one surface side of the substrate, and an excess solder removing step of removing excess solder from a region excluding the top surface of the pillars.

[0009] In this method for manufacturing a circuit member with solder bumps, conductive pillars are formed in the electrode region of the substrate, solder fine particles are deposited on the top surface of the pillars, and then excess solder is removed to form a circuit member with solder bumps. According to this method, by selectively depositing solder fine particles in a region defined by the top surface of the pillars, solder bumps can be accurately formed in a minute region. Therefore, in the circuit member with solder bumps obtained by this method, both connection reliability and insulation reliability are sufficiently excellent.

[0010] [2] The method for manufacturing a circuit member with solder bumps according to [1], including a reflow step of performing reflow of the solder fine particles deposited on the top surface of the pillars. In this case, by reflowing the solder fine particles, solder bumps having a spherical or nearly spherical shape can be formed on the top surface of the pillars. Therefore, in the obtained circuit member with solder bumps, both connection reliability and insulation reliability can be further enhanced.

[0011] [3] The method for manufacturing a circuit member with solder bumps according to [1] or [2], including a resist forming step of previously forming a resist having a height greater than that of the pillar on a portion excluding the electrode region on one side of the substrate. In this case, solder fine particles of a desired height can be deposited regardless of the height of the pillar. Also, by forming the resist, adhesion of excess solder to the side surface of the pillar can be suppressed. Therefore, in the obtained circuit member with solder bumps, both connection reliability and insulation reliability can be further enhanced.

[0012] [4] The method for manufacturing a circuit member with solder bumps according to any one of [1] to [3], including a resist forming step of previously forming a resist having a height greater than that of the pillar on a portion excluding the electrode region on one side of the substrate, and a reflow step of performing reflow of the solder fine particles deposited on the top surface of the pillar, and performing an excess solder removing step by removing the resist before and after the reflow step. In this case, excess solder can be simultaneously removed by removing the resist. Therefore, the process can be simplified.

[0013] [5] In the pillar forming step, the pillar is formed of Cu, and in the deposition step, fine particles of an Sn - Bi alloy are deposited as the solder fine particles, in the method for manufacturing a circuit member with solder bumps according to any one of [1] to [4]. According to this method, minute solder bumps made of an Sn - Bi alloy, which were difficult to fabricate by conventional methods such as paste printing, plating, or mounting of solder balls, can be realized.

[0014] [6] The particle size of the solder fine particles is 0.01 μm to 10 μm, in the method for manufacturing a circuit member with solder bumps according to any one of [1] to [5]. In this case, the solder fine particles can be densely deposited on the top surface of the pillar. Therefore, in the obtained circuit member with solder bumps, both connection reliability and insulation reliability can be further sufficiently enhanced.

[0015] [7] A circuit member with solder bumps, comprising a substrate having an electrode region of a predetermined pattern provided on one side, and a conductive pillar provided on the electrode region, wherein a solder bump formed by a deposit of solder fine particles is provided on the top surface of the pillar.

[0016] In this circuit member with solder bumps, by selectively depositing solder fine particles in a region defined by the top surface of the pillar, solder bumps can be accurately formed in a minute region. Therefore, in this circuit member with solder bumps, both connection reliability and insulation reliability are sufficiently excellent.

[0017] [8] The circuit member with solder bumps according to [7], wherein the particle size of the solder fine particles is 0.01 μm to 10 μm. In this case, the solder fine particles can be densely deposited on the top surface of the pillar. Therefore, both connection reliability and insulation reliability can be further enhanced sufficiently.

[0018] [9] A circuit member with solder bumps, comprising a substrate having an electrode region of a predetermined pattern provided on one side, and a conductive pillar provided on the electrode region, wherein a solder bump formed by a deposit of reflowed solder fine particles is provided on the top surface of the pillar.

[0019] In this circuit member with solder bumps, by selectively depositing solder fine particles in a region defined by the top surface of the pillar, solder bumps can be accurately formed in a minute region. Therefore, in this circuit member with solder bumps, both connection reliability and insulation reliability are sufficiently excellent. Also, in this circuit member with solder bumps, by reflowing the solder fine particles, a solder bump having a spherical or nearly spherical shape can be formed on the top surface of the pillar. Therefore, both connection reliability and insulation reliability can be further enhanced.

[0020]

[10] The pillar is formed of Cu, and the solder bump is formed of a Sn-Bi alloy, the circuit member with solder bumps according to any one of [7] to [9]. According to such a configuration, it is possible to realize minute solder bumps made of a Sn-Bi alloy, which have been difficult to fabricate by conventional methods such as mounting of paste, plating, or solder balls.

Advantages of the Invention

[0021] According to the present disclosure, even when the electrode size is miniaturized, it is possible to provide a circuit member with solder bumps that is excellent in both connection reliability and insulation reliability.

Brief Description of the Drawings

[0022]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0023] Hereinafter, with reference to the drawings, a method for manufacturing a circuit member with solder bumps and a preferred embodiment of the circuit member with solder bumps according to one aspect of the present disclosure will be described in detail.

[0024] In the following description, the numerical range indicated by "~" indicates a range including the numerical values described before and after "~" as the minimum value and the maximum value, respectively. In the numerical ranges described step by step in this specification, the upper limit value or the lower limit value of a numerical range at a certain step may be replaced with the upper limit value or the lower limit value of a numerical range at another step.

[0025] FIG. 1 is a schematic cross-sectional view showing a circuit member with solder bumps according to the first embodiment of the present disclosure. The circuit member with solder bumps 1A shown in FIG. 1 is a member used, for example, for flip-chip mounting between circuit members. The circuit member with solder bumps 1A is electrically connected to another circuit member via solder bumps 4 to form a connection structure between circuit members. As shown in FIG. 1, the circuit member with solder bumps 1A includes a substrate 2, a conductive pillar 3, and solder bumps 4.

[0026] The substrate 2 has a first surface 2a provided with an electrode region R of a predetermined pattern and a second surface 2b opposite to the first surface a. Specific examples of the substrate 2 include chip components such as IC chips (semiconductor chips), resistor chips, capacitor chips, driver ICs, and rigid package substrates. These substrates generally have a large number of circuit electrodes. Other examples of substrates having a plurality of electrodes on the surface include wiring substrates such as flexible tape substrates having metal wiring, flexible printed wiring boards, and glass substrates vapor-deposited with indium tin oxide (ITO).

[0027] Examples of the constituent material of the electrode region R include electrodes such as copper, copper / nickel, copper / nickel / gold, copper / nickel / palladium, copper / nickel / palladium / gold, copper / nickel / gold, copper / palladium, copper / palladium / gold, copper / tin, copper / silver, and indium tin oxide. The electrodes can be formed, for example, by electroless plating, electrolytic plating, sputtering, or etching of metal foils.

[0028] The pillar 3 is provided on the first surface 2a of the substrate 2 corresponding to the electrode region R. As the constituent material of the pillar 3, for example, the same material as that of the above-described electrode region R can be used. In this embodiment, the pillar 3 is formed of copper (Cu). The pillar 3 generally has a columnar shape. When the diameter of the pillar 3 is r, the height of the pillar 3 may be 1 / 4×r or more, and may be 1 / 2×r or more from the viewpoint of ensuring the reliability of the connection structure and the use of the interlayer sealing material. Also, when the diameter of the pillar 3 is r, the pitch between adjacent pillars 3, 3 may be 1 / 2×r or more, and may be r or more from the viewpoint of preventing a bridge between adjacent pillars 3, 3 during the formation of the solder bump 4. As an example, the height of the pillar 3 may be 1 μm to 200 μm, or may be 5 μm to 150 μm. The diameter of the pillar 3 may be 0.4 μm to 200 μm, or may be 1 μm to 100 μm. The pitch between adjacent pillars 3, 3 may be 0.5 μm or more, or may be 1 μm.

[0029] The solder bump 4 is composed of a deposit of solder fine particles 5 and is provided on the top surface 3a of the pillar 3. The solder fine particles 5 are composed of a tin alloy. Examples of the tin alloy include In-Sn alloy, In-Sn-Ag alloy, Sn-Au alloy, Sn-Bi alloy, Sn-Bi-Ag alloy, Sn-Ag-Cu alloy, Sn-Cu alloy, and the like. In the present embodiment, the solder fine particles 5 are composed of fine particles of Sn-Bi alloy.

[0030] The particle size of the solder fine particles 5 may be 0.01 μm to 10 μm, or may be 0.05 μm to 5 μm. The height of the solder bump 4 from the top surface 3a of the pillar 3 may be 0.005 μm to 200 μm, or may be 0.01 μm to 150 μm. The particle size of the solder fine particles 5 and the height of the solder bump 4 can be measured from an image obtained by, for example, an optical microscope, an electron microscope, or the like. Specific devices include a flow-type particle image analyzer, a Microtrac, a Coulter counter, and the like.

[0031] FIG. 2 is a schematic cross-sectional view showing a circuit member with solder bumps according to the second embodiment of the present disclosure. The circuit member 1B with solder bumps shown in FIG. 2 is different from the circuit member 1A with solder bumps of the first embodiment in that the solder bump 4 is composed of a deposit of solder fine particles 5 that have been reflowed.

[0032] In the circuit member 1B with solder bumps, each solder particle 5 is integrated by the reflow of the deposit of solder particles 5, and the shape of the solder bump 4 is close to a spherical shape such as a spherical shape or a hemispherical shape. The diameter of the solder bump 4 in a plan view may be 0.01 μm to 150 μm, or may be 0.02 μm to 100 μm. The height of the solder bump 4 from the top surface 3a of the pillar 3 may be 0.005 μm to 200 μm, or may be 0.05 μm to 150 μm. The diameter and the height of the solder bump 4 can be measured from an image obtained by, for example, an optical microscope, an electron microscope, or the like, in the same manner as in the first embodiment. Specific devices include a flow-type particle image analyzer, a Microtrac, a Coulter counter, and the like.

[0033] The circuit member 1A with solder bumps of the first embodiment can also be positioned as an intermediate body of the circuit member 1B with solder bumps of the second embodiment. For example, storage and transportation may be performed in the state of the circuit member 1A with solder bumps, and at the manufacturing site of the connection structure, reflow of the deposit of solder particles 5 may be performed to produce the circuit member 1B with solder bumps, and the manufactured circuit member 1B with solder bumps may be used to manufacture the connection structure.

[0034] FIG. 3 is a flowchart showing a method for manufacturing a circuit member with solder bumps according to the first embodiment of the present disclosure. As shown in FIG. 3, the method for manufacturing a circuit member with solder bumps according to the first embodiment includes a resist formation step S01, a pillar formation step S02, a resist removal step S03, a deposition step S04, a reflow step S05, and an excess solder removal step S06.

[0035] The resist formation step S01 is a step of forming a resist 11 on the first surface 2a of the substrate 2. In the resist formation step S01, as shown in FIG. 4(a), a resist 11 is formed on the portion excluding the electrode region R on the first surface 2a side of the substrate 2 by exposure and development using a predetermined mask. The height of the resist 11 from the first surface 2a of the substrate 2 is preferably higher than the height of the pillar 3 formed in the pillar formation step S02.

[0036] As a method for forming the resist 11, for example, a method of applying a positive photoresist by spin coating to an arbitrary film thickness and then applying light to the resist in the portion corresponding to the electrode region R by an exposure process can be mentioned. Thereafter, the resist in the portion corresponding to the electrode region R is removed by a development process, and the resist 11 can be formed by exposing the surface of the electrode region R. Also, a negative type may be used for the photoresist. Further, for forming the resist 11, a film type resist adjusted to the heights of the pillars 3 and solder bumps 4 formed in the electrode region R can also be used. When using a film type resist, a lamination method can be used instead of spin coating.

[0037] The pillar formation step S02 is a step of forming a conductive pillar 3 in the electrode region R on the first surface 2a side of the substrate 2. In the pillar formation step S02, for example, by copper plating, as shown in FIG. 4(b), in the region excluding the resist 11, that is, in the electrode region R, the pillar 3 is formed at a height smaller than that of the resist 11.

[0038] As a method for copper plating, for example, a plating method, a sputtering method, a vapor deposition method, an ion plating method, or a paste method can be used. As the plating method, electroless plating or electroplating can be used. In particular, electroplating is preferable from the viewpoint of productivity because the deposition rate of the metal is faster than other methods. Before forming the pillar 3, a pretreatment for removing residues and oxide films on the surface of the electrode region R may be performed from the viewpoint of ensuring the adhesion between the electrode region R and the pillar 3. For example, the residues and oxide films on the surface of the electrode region R are removed by plasma treatment, desmear treatment, or a combination thereof, and after sufficient cleaning, the pillar 3 is formed. After performing electroless plating to form a thin Cu layer after the pretreatment, Cu may be deposited by electroplating to form the pillar 3.

[0039] In the pretreatment, when performing plasma treatment or desmear treatment using an acid or alkali solution, it is necessary to appropriately set the treatment conditions so that the resist 11 other than the electrode region R does not deteriorate. If the pretreatment is excessive, the resist 11 may be etched, and the pillars 3 and solder bumps 4 may not be formed in the designed shape and size, or the resist 11 may peel off from the substrate 2 during the electrolytic plating process. By adjusting the treatment conditions of the plasma treatment or desmear treatment, the occurrence of such problems can be suppressed, and the pillars 3 and solder bumps 4 can be formed in the designed shape and size.

[0040] The resist removal step S03 is a step of removing the resist 11 from the first surface 2a of the substrate 2. In the resist removal step S03, the resist 11 is removed by, for example, a wet or dry method. In the wet method, large-area treatment is possible. In the wet method, the substrate 2 on which the resist 11 is formed is immersed in a stripping solution for a certain period of time. Thereby, as shown in FIG. 5(a), the resist 11 on the first surface 2a side of the substrate 2 is removed. In the wet method, the shorter the immersion time in the stripping solution, the more the oxidation and deterioration of the pillar 3 are suppressed. By heating the stripping solution to a certain temperature, the peelability is enhanced, and the immersion time can be shortened. By performing rocking during the immersion, peeling in a shorter time becomes possible. After immersion in the stripping solution, a step of washing with pure water is performed to prevent the stripping solution from remaining on the surface of the substrate 2, thereby suppressing the oxidation and deterioration of the pillar 3. As the stripping solution, for example, an aqueous solution of an organic acid ammonium salt, an aqueous solution of an inorganic acid ammonium salt, etc. can be used.

[0041] The deposition step S04 is a step of depositing solder fine particles 5 in a region including the top surface 3a of the pillar 3 on the first surface 2a side of the substrate 2. In the deposition step S04, for example, by a sputtering method, as shown in FIG. 5(b), the solder fine particles 5 are deposited on the top surface 3a of the pillar 3 and the first surface 2a of the substrate 2 excluding the region of the pillar 3. The solder fine particles 5 deposited in the region excluding the region of the pillar 3 become excess solder 12.

[0042] In the deposition process S04, as an example, Sn42-Bi58 (a solder alloy containing 42% tin and 58% bismuth) can be used as the solder fine particles 5, and Ar gas can be used as the process gas for sputtering. As described above, the particle size of the solder fine particles 5 to be used can be 0.01 μm to 10 μm or 0.05 μm to 5 μm. The pressure of the Ar gas can be, for example, 1 Pa. The applied power to the target material can be 60 W. The deposition process S04 is not limited to the sputtering method and may be carried out by other methods such as the evaporation method and the ion plating method.

[0043] After the deposition process S04, when the reflow process S05 is omitted and the surplus solder removal process S06 is carried out, the deposited body of the solder fine particles 5 on the top surface 3a of the pillar 3 directly becomes the solder bump 4, and the circuit member 1A with solder bumps shown in FIG. 1 is obtained.

[0044] The reflow process S05 is a process of performing reflow of the solder fine particles 5 deposited on the top surface 3a of the pillar 3. Due to the reflow of the solder fine particles 5, the solder wets and spreads on the top surface 3a of the pillar 3, and a solder bump 4 having a spherical or nearly spherical shape is formed on the top surface 3a of the pillar 3 as shown in FIG. 6(a). The reflow of the solder fine particles 5 is carried out, for example, by heating in a reducing atmosphere.

[0045] In the reflow process S05, as an example, a hydrogen radical atmosphere or a formic acid atmosphere can be used as the reducing atmosphere. Also, a method of bringing a flux material into contact can be used. When using a formic acid atmosphere, formic acid can be used as the reducing gas, and heating can be carried out under the conditions of a temperature of 130°C for 10 minutes. Also, nitrogen can be used as the gas, and post-heating can be carried out under the conditions of a temperature of 200°C for 4 minutes. In a reducing atmosphere, heating may be carried out to a temperature above the melting point of the solder. For example, in the case of Sn-Bi, the solder may be melted at 139°C or higher in a formic acid atmosphere. The reflow process S05 is not limited to heating in a reducing atmosphere and may be carried out by other methods such as laser reflow.

[0046] The surplus solder removal step S06 is a step of removing surplus solder 12 from the region excluding the top surface 3a of the pillar 3. In the surplus solder removal step S06, for example, by irradiating ultrasonic waves in methanol, as shown in FIG. 6(b), the surplus solder 12 on the first surface 2a of the substrate 2 excluding the region of the pillar 3 is removed. Thereby, the circuit member 1B with solder bumps shown in FIG. 2 is obtained. The surplus solder removal step S06 is not limited to irradiating ultrasonic waves in methanol, and may be carried out by other methods such as dry etching, plasma processing such as oxygen plasma and argon plasma, and laser irradiation.

[0047] As described above, in this method for manufacturing a circuit member with solder bumps, a conductive pillar 3 is formed in the electrode region R of the substrate 2, and after depositing solder fine particles 5 on the top surface 3a of the pillar 3, the surplus solder 12 is removed to form the circuit member 1A with solder bumps or the circuit member 1B with solder bumps. According to this method, by selectively depositing the solder fine particles 5 in the region defined by the top surface 3a of the pillar 3, the solder bumps 4 can be accurately formed in a minute region. Therefore, in the circuit members 1A and 1B with solder bumps obtained by this method, both the connection reliability and the insulation reliability are sufficiently excellent.

[0048] This embodiment includes a reflow step of performing reflow on the solder fine particles 5 deposited on the top surface 3a of the pillar 3. In this case, by reflowing the solder fine particles 5, solder bumps 4 having a spherical or nearly spherical shape can be formed on the top surface 3a of the pillar 3. Therefore, in the obtained circuit member 1B with solder bumps, both the connection reliability and the insulation reliability can be further enhanced.

[0049] This embodiment includes a resist formation step of previously forming a resist 11 having a height greater than that of the pillar 3 on the portion excluding the electrode region R on the first surface 2a side of the substrate 2. In this embodiment, by previously forming a resist 11 having a height greater than that of the pillar 3, it becomes possible to uniformize the shape of the pillar 3 formed by copper plating or the like in the pillar formation step S02.

[0050] In this embodiment, in the pillar formation step, pillar 3 is formed of Cu, and in the deposition step, fine particles of an Sn-Bi alloy are deposited as solder fine particles 5. According to such a method, it is possible to realize minute solder bumps made of an Sn-Bi alloy, which have been difficult to fabricate by conventional methods such as printing of paste, plating, or mounting of solder balls.

[0051] In this embodiment, the particle size of the solder fine particles 5 is 0.01 μm to 5 μm. By using the solder fine particles 5 having such a minute particle size, the solder fine particles 5 can be densely deposited on the top surface 3a of the pillar 3. Therefore, in the obtained circuit members 1A and 1B with solder bumps, both the connection reliability and the insulation reliability can be further sufficiently enhanced.

[0052] FIG. 7 is a flowchart showing a method for manufacturing a circuit member with solder bumps according to the second embodiment of the present disclosure. As shown in FIG. 7, the method for manufacturing a circuit member with solder bumps according to the second embodiment is different from the first embodiment in that a surplus solder removal step is performed before and after the reflow step, and a resist removal step is performed before the deposition step.

[0053] Specifically, the method for manufacturing a circuit member with solder bumps according to the second embodiment includes a resist formation step S11, a pillar formation step S12, a deposition step S12, a resist removal step (surplus solder removal step) S14, and a reflow step S15. That is, in this embodiment, before the reflow step S15, the surplus solder removal step S14 is performed by removing the resist 11.

[0054] The resist formation step S11 and the pillar formation step S12 are the same as the resist formation step S01 and the pillar formation step S02 in the first embodiment (see FIGS. 4(a) and 4(b)). In the deposition step S13, as shown in FIG. 8(a), the solder fine particles 5 are deposited on the top surface 3a of the pillar 3 and the top surface 11a of the resist 11. The solder fine particles 5 deposited on the top surface 11a of the resist 11 become surplus solder 12.

[0055] In the resist removal step S14, as shown in FIG. 8(b), the resist 11 is removed from the first surface 2a of the substrate 2. By removing the resist 11, the excess solder 12 deposited on the top surface 11a of the resist 11 is also removed simultaneously. Therefore, by performing the resist removal step S14, the excess solder removal step is also performed simultaneously.

[0056] After the resist removal step S14, when the reflow step S15 is omitted, the deposit of the solder particles 5 on the top surface 3a of the pillar 3 directly becomes the solder bump 4, and the circuit member 1A with solder bumps shown in FIG. 1 is obtained. In the reflow step S15, as shown in FIG. 8(c), the solder particles 5 are reflowed to form a solder bump 4 having a spherical or nearly spherical shape on the top surface 3a of the pillar 3. Thereby, the circuit member 1B with solder bumps shown in FIG. 2 is obtained.

[0057] Also in such a second embodiment, by selectively depositing the solder particles 5 in the region defined by the top surface 3a of the pillar 3, the solder bump 4 can be accurately formed in a minute region. Therefore, in the circuit members 1A and 1B with solder bumps obtained by this method, both the connection reliability and the insulation reliability are sufficiently excellent. Further, in the present embodiment, the excess solder removal step is performed by removing the resist 11 before the reflow step. Thereby, since the excess solder 12 can be removed simultaneously by removing the resist 11, the process can be simplified.

[0058] Also in the second embodiment, a resist 11 having a height greater than that of the pillar 3 is previously formed on the portion of the first surface 2a side of the substrate 2 excluding the electrode region R. If there is no resist 11, when solder fine particles 5 are deposited at a height exceeding the height of the pillar 3, it is conceivable that the pillar 3 will be buried in the solder fine particles 5. On the other hand, by previously forming a resist 11 having a height greater than that of the pillar 3 on the portion excluding the electrode region R, solder fine particles 5 having a desired height can be deposited regardless of the height of the pillar 3. Further, by forming the resist 11, adhesion of excess solder 12 to the side surface of the pillar 3 can be suppressed. Therefore, in the obtained circuit members 1A and 1B with solder bumps, both connection reliability and insulation reliability can be further enhanced.

[0059] FIG. 9 is a flowchart showing a method for manufacturing a circuit member with solder bumps according to the third embodiment of the present disclosure. As shown in FIG. 9, the method for manufacturing a circuit member with solder bumps according to the third embodiment is different from the first embodiment in that a resist removal step is performed before the deposition step in that an excess solder removal step is performed before and after the reflow step, similar to the second embodiment.

[0060] Specifically, the method for manufacturing a circuit member with solder bumps according to the third embodiment includes a resist formation step S21, a pillar formation step S22, a deposition step S23, a reflow step S24, and a resist removal step (excess solder removal step) S25. That is, in this embodiment, after the reflow step S24, an excess solder removal step S25 is performed by removing the resist 11.

[0061] The resist formation step S21 and the pillar formation step S12 are the same as the resist formation step S01 and the pillar formation step S02 in the first embodiment (see FIGS. 4(a) and 4(b)). Also, the deposition step S23 is the same as the deposition step S13 in the second embodiment (see FIG. 8(a)). The solder fine particles 5 deposited on the top surface 11a of the resist 11 become excess solder 12.

[0062] In the reflow process S24, as shown in Fig. 10(a), solder bumps 4 having a spherical or nearly spherical shape are formed on the top surface 3a of the pillar 3 by the reflow of solder particles 5. In the resist removal process S25, as shown in Fig. 10(b), the resist 11 is removed from the first surface 2a of the substrate 2. Thereby, the circuit member 1B with solder bumps shown in Fig. 2 is obtained. By removing the resist 11, the excess solder 12 deposited on the top surface 11a of the resist 11 is also removed simultaneously. Therefore, by performing the resist removal process S25, the excess solder removal process is also performed simultaneously.

[0063] Also in such a third embodiment, by selectively depositing the solder particles 5 in the region defined by the top surface 3a of the pillar 3, the solder bumps 4 can be accurately formed in a minute region. Therefore, in the circuit member 1B with solder bumps obtained by this method, both the connection reliability and the insulation reliability are sufficiently excellent. Further, in the present embodiment, the excess solder removal process is performed by removing the resist 11 before the reflow process. Thereby, since the excess solder 12 can be removed simultaneously by removing the resist 11, the process can be simplified.

[0064] Also in the third embodiment, by previously forming a resist 11 having a height greater than that of the pillar 3 in a portion excluding the electrode region R, solder particles 5 having a desired height can be deposited regardless of the height of the pillar 3. Further, by forming the resist 11, the adhesion of the excess solder 12 to the side surface of the pillar 3 can be suppressed. Therefore, in the obtained circuit members 1A and 1B with solder bumps, both the connection reliability and the insulation reliability can be further enhanced.

Explanation of Signs

[0065] 1A, 1B... Circuit members with solder bumps, 2... Substrate, 2a... First surface, 3... Pillar, 3a... Top surface, 4... Solder bump, 5... Solder particle, 11... Resist, 12... Excess solder, R... Electrode region.

Claims

1. a pillar forming step of forming conductive pillars in electrode regions provided in a predetermined pattern on one surface of the substrate; a depositing step of depositing solder particles on a region including the top surface of the pillar on one side of the substrate; and a step of removing excess solder from areas other than the top surfaces of the pillars.

2. 2. The method for producing a circuit member having solder bumps according to claim 1, further comprising a reflow step of reflowing the solder particles deposited on the top surface of the pillar.

3. 2. The method for manufacturing a circuit member with solder bumps according to claim 1, further comprising a resist forming step of previously forming a resist having a height greater than that of said pillars on one surface of said substrate except for said electrode regions.

4. a resist forming step of previously forming a resist having a height greater than that of the pillars on a portion of the one surface side of the substrate excluding the electrode region; a reflow process for reflowing the solder particles deposited on the top surface of the pillar, 2. The method for producing a circuit member with solder bumps according to claim 1, wherein the excess solder removing step is carried out by removing the resist before or after the reflow step.

5. In the pillar forming step, the pillar is formed of Cu, 5. The method for producing a circuit member with solder bumps according to claim 1, wherein in the depositing step, fine particles of an Sn--Bi alloy are deposited as the solder fine particles.

6. 5. The method for producing a circuit member with solder bumps according to claim 1, wherein the particle size of the solder particles is 0.01 μm to 10 μm.

7. A substrate having an electrode region of a predetermined pattern on one side thereof; a conductive pillar provided in the electrode region; A circuit member with solder bumps, the top surfaces of the pillars being provided with solder bumps made of a deposit of solder particles.

8. 8. The circuit member with solder bumps according to claim 7, wherein the particle size of said solder particles is 0.01 μm to 10 μm.

9. A substrate having an electrode region of a predetermined pattern on one side thereof; a conductive pillar provided in the electrode region; A circuit member having solder bumps, the pillars each having a top surface provided with a solder bump formed of a deposit of reflowed solder particles.

10. the pillar is formed of Cu; 10. The circuit member with solder bumps according to claim 7, wherein the solder bumps are made of a Sn--Bi alloy.

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