Method of manufacturing display device

Abstract

To provide a method of manufacturing a display device capable of improving yield.SOLUTION: A method of manufacturing a display device includes: forming a lower electrode; forming an insulation layer on the lower electrode; forming a partition wall including a lower part disposed on an upper side of the insulation layer and an upper part including an end protruding from a side face of the lower part; disposing a resist to cover the partition wall on the insulation layer, and removing a portion of the insulation layer that is exposed from the resist by etching, thereby forming a rib and a pixel opening enclosed by the rib; covering the lower electrode through the pixel opening; forming an organic layer which emits light in response to application of a voltage; and forming an upper electrode covering the organic layer. In the middle of the etching, the end of the upper part becomes exposed from the resist.SELECTED DRAWING: Figure 8D

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology that enables improvement of yields in this type of display device is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a method for manufacturing a display device that can improve yield. [Means for solving the problem]

[0005] A method for manufacturing a display device according to one embodiment includes forming a lower electrode, forming an insulating layer on the lower electrode, forming a partition including a lower portion disposed above the insulating layer and an upper portion having an end portion protruding from a side surface of the lower portion, disposing a resist covering the partition on the insulating layer, forming a rib and a pixel opening surrounded by the rib by etching away a portion of the insulating layer exposed from the resist, forming an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage, and forming an upper electrode covering the organic layer, wherein the end portion of the upper portion is exposed from the resist during the etching. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of a layer structure that can be applied to the organic layer. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing an example of a configuration that can be applied to the partition wall. [Figure 6] 6A to 6C are schematic cross-sectional views showing the manufacturing process of the display device according to this embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a step subsequent to that shown in FIG. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a step subsequent to that shown in FIG. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a step subsequent to FIG. 8C. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a step subsequent to FIG. 8D. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a step subsequent to that shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a step subsequent to that shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a step subsequent to that shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a step subsequent to that shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a step subsequent to that shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a step subsequent to that shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0008] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. The third direction Z is the normal direction of a plane that includes the first direction X and the second direction Y. Moreover, viewing various elements parallel to the third direction Z is called planar view.

[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] 1 is a diagram showing an example of the configuration of a display device DSP according to an embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0013] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0014] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example of Fig. 1, the scanning lines GL and the power lines PL extend in a first direction X, and the signal lines SL extend in a second direction Y.

[0015] A gate electrode of the pixel switch 2 is connected to a scanning line GL. A source electrode of the pixel switch 2 is connected to a signal line SL. A drain electrode of the pixel switch 2 is connected to a gate electrode of the driving transistor 3 and a capacitor 4. A source electrode of the driving transistor 3 is connected to a power line PL and a capacitor 4. A drain electrode of the driving transistor 3 is connected to a display element DE.

[0016] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in a first direction X. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in a second direction Y.

[0018] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG.

[0019] A rib 5 is disposed in the display area DA. The rib 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio. Note that the sizes of the pixel apertures AP1, AP2, and AP3 are not limited to this example. For example, the pixel apertures AP2 and AP3 may have the same size.

[0020] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.

[0021] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib 5 surrounds each of these display elements DE1, DE2, and DE3.

[0022] In the display area DA, partition walls 6 are disposed. The partition walls 6 are located above the ribs 5 and entirely overlap the ribs 5. In the example of FIG. 2, the partition walls 6 have the same planar shape as the ribs 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3, respectively. From another perspective, the ribs 5 and the partition walls 6 are lattice-shaped in plan view and surround the display elements DE1, DE2, and DE3, respectively. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0023] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes unevenness caused by the circuit layer 11.

[0024] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 (the drain electrode of the driving transistor 3 shown in FIG. 1) through a contact hole provided in the organic insulating layer 12.

[0025] The partition 6 includes a conductive lower portion 61 disposed on the rib 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition 6 is called an overhang shape.

[0026] In the example of Fig. 3, the lower part 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib 5, and is formed thinner than the axial layer 64. Also, in the example of Fig. 3, both ends of the bottom layer 63 protrude from the side surfaces of the axial layer 64. Furthermore, the ends of the bottom layer 63 are located between the ends of the upper part 62 and the side surfaces of the axial layer 64 in a plan view.

[0027] 3, the upper portion 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the axial layer 64 of the lower portion 61. The second top layer 66 is disposed on the first top layer 65.

[0028] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0029] The display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. The display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. The display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0030] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0031] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located around the partition wall 6 (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located around the partition wall 6 (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located around the partition wall 6 (a part that constitutes the display element DE3).

[0032] The subpixels SP1, SP2, and SP3 are provided with sealing layers SE11, SE12, and SE13 that cover the stacked films FL1, FL2, and FL3, respectively. Specifically, the sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0033] 3, the laminated film FL1 and the sealing layer SE11 on the partition 6 between the subpixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition 6. In addition, the laminated film FL1 and the sealing layer SE11 on the partition 6 between the subpixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition 6.

[0034] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least throughout the entire display area DA, and a part of them extends into the peripheral area SA.

[0035] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0036] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0037] The lower electrodes LE1, LE2, and LE3 each have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. The reflective layer can be made of a metal material with excellent light reflectivity, such as silver. Each conductive oxide layer can be made of a transparent conductive oxide, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0038] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0039] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of, for example, a metal material. The metal material of the bottom layer 63 may be, for example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb). The metal material of the shaft layer 64 may be, for example, aluminum (Al), an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a laminated structure of a plurality of layers. The shaft layer 64 may also include a layer formed of an insulating material.

[0040] For example, the first top layer 65 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. The metal material forming the first top layer 65 can be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the second top layer 66 can be, for example, ITO, IZO, or IGZO. The upper portion 62 may have a single layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0041] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0042] 4 is a diagram showing an example of a layer structure applicable to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including an emitting layer EML. In this embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in this order in the third direction Z. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of emitting layers EML.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in the red wavelength region.

[0045] As another example, the emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the emitting layers EML into light of a color corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the emitting layers EML to generate light of a color corresponding to the subpixels SP1, SP2, and SP3.

[0046] Fig. 5 is a schematic cross-sectional view showing an example of a configuration that can be applied to the partition wall 6. Fig. 5 illustrates a portion of the partition wall 6 located between the subpixels SP1 and SP2. A configuration similar to that shown in Fig. 5 can also be applied to a portion of the partition wall 6 located between the subpixels SP1 and SP3 and a portion of the partition wall 6 located between the subpixels SP2 and SP3.

[0047] The upper part 62 has an end E11 on the subpixel SP1 side and an end E12 on the subpixel SP2 side. The first top layer 65 has a bottom surface L1. The second top layer 66 has an top surface U1. The axis layer 64 has a side surface F21 on the subpixel SP1 side and a side surface F22 on the subpixel SP2 side. The bottom layer 63 has an end E31 on the subpixel SP1 side, an end E32 on the subpixel SP2 side, and an top surface U3.

[0048] In the example of FIG. 5, the end E11 of the upper portion 62 protrudes from the end E31 of the bottom layer 63 and the side surface F21 of the shaft layer 64. Similarly, the end E12 of the upper portion 62 protrudes from the end E32 of the bottom layer 63 and the side surface F22 of the shaft layer 64. Also, the end E31 of the bottom layer 63 protrudes from the side surface F21 of the shaft layer 64. Similarly, the end E32 of the bottom layer 63 protrudes from the side surface F22 of the shaft layer 64. In the example of FIG. 5, the width of the second top layer 66 is the same as the width of the first top layer 65, but the width of the second top layer 66 may be smaller than the width of the first top layer 65. The shaft layer 64 is formed thicker than the bottom layer 63, the first top layer 65, and the second top layer 66.

[0049] The rib 5 has a first portion 51 and second portions 521 and 522. The first portion 51 is a portion of the rib 5 that has a constant thickness. The term "constant" here includes not only the case where there is no variation in the thickness of the rib 5 depending on the position in the XY plane, but also the case where there is a slight variation that is not formed intentionally. In one example, the first portion 51 corresponds to a region that is not exposed to etching, which will be described later with reference to FIGS. 8A to 8D. The second portion 521 is a portion of the rib 5 whose thickness decreases toward the pixel opening AP1. The second portion 522 is a portion of the rib 5 whose thickness decreases toward the pixel opening AP2. The first portion 51 is located between the second portions 521 and 522.

[0050] 5, the boundary B1 between the first portion 51 and the second portion 521 coincides with the end E11 of the upper portion 62 in a planar view. Moreover, the boundary B2 between the first portion 51 and the second portion 522 coincides with the end E12 of the upper portion 62 in a planar view. As another example, the boundary B1 and the end E11 may be misaligned. Moreover, the boundary B2 and the end E12 may be misaligned.

[0051] The first portion 51 has an upper surface U5. The second portion 521 has an inclined surface 531 inclined from the boundary B1 toward the pixel opening AP1. The second portion 522 has an inclined surface 532 inclined from the boundary B2 toward the pixel opening AP2. The lower electrode LE1 has an upper surface Uc1 and an end Ec1. The lower electrode LE2 has an upper surface Uc2 and an end Ec2. The ends Ec1 and Ec2 overlap with the partition wall 6 in a plan view. Specifically, the ends Ec1 and Ec2 overlap with the axis layer 64 in a plan view.

[0052] As shown in Fig. 5, steps ST are generated on the upper surface U5 of the rib 5 due to the ends Ec1, Ec2 of the lower electrodes LE1, LE2. In this embodiment, these steps ST are covered by the bottom layer 63 and the shaft layer 64. As shown in Fig. 5, the upper surfaces of the shaft layer 64, the first top layer 65, and the second top layer 66 may be deformed in accordance with the steps ST.

[0053] 5, the angle θ1 between the inclined surface 531 and the upper surface Uc1 of the lower electrode LE1 and the angle θ2 between the inclined surface 532 and the upper surface Uc2 of the lower electrode LE2 are equal (θ1=θ2). However, the angles θ1 and θ2 may be different. In one example, the angles θ1 and θ2 are 50° or less.

[0054] 5, areas AR1 and AR2 are formed below the upper part 62. The areas AR1 and AR2 are areas surrounded by the lower surface of the upper part 62, the side surface of the lower part 61, and the upper surface of the rib 5. Specifically, the area AR1 is surrounded by the lower surface L1 of the first top layer 65, the side surface F21 of the shaft layer 64, the upper surface U3 of the bottom layer 63, the end E31 of the bottom layer 63, and the upper surface U5 of the first portion 51. The area AR2 is surrounded by the lower surface L1 of the first top layer 65, the side surface F22 of the shaft layer 64, the upper surface U3 of the bottom layer 63, the end E32 of the bottom layer 63, and the upper surface U5 of the first portion 51.

[0055] Next, an example of a manufacturing method of the display device DSP according to this embodiment will be described. Figures 6 to 15 are schematic cross-sectional views showing the manufacturing process of the display device DSP according to this embodiment. In these figures, the substrate 10 and the circuit layer 11 are omitted. Also, in Figures 6, 7, and 9 to 15, the step portion ST due to the end of the lower electrode is omitted.

[0056] In manufacturing the display device DSP, first, the circuit layer 11, the organic insulating layer 12, and the lower electrodes LE1, LE2, and LE3 are formed on the substrate 10. Then, as shown in Fig. 6, an insulating layer L5 for processing into the rib 5 is formed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3, a first layer L63 for processing into the bottom layer 63 is formed on the insulating layer L5, a second layer L64 for processing into the axis layer 64 is formed on the first layer L63, a third layer L65 for processing into the first top layer 65 is formed on the second layer L64, and a fourth layer L66 for processing into the second top layer 66 is formed on the third layer L65.

[0057] Subsequently, the first layer L63, the second layer L64, the third layer L65, and the fourth layer L66 are patterned. This patterning includes a step of disposing a resist having a planar shape of the partition wall 6 on the fourth layer L66, a step of forming a second top layer 66 by etching the fourth layer L66, a step of forming a first top layer 65 by etching the third layer L65, a step of forming an axis layer 64 by etching the second layer L64, and a step of forming a bottom layer 63 by etching the first layer L63. Through these steps, as shown in FIG. 7, the partition wall 6 having a lower portion 61 and an upper portion 62 is formed on the insulating layer L5. The lower portion 61 includes the bottom layer 63 and the axis layer 64 as shown in FIG. 5. Also, the upper portion 62 includes the first top layer 65 and the second top layer 66 as shown in FIG. 5.

[0058] Next, a process of forming the rib 5 will be described with reference to Fig. 8A to Fig. 8D. Note that in Fig. 8A to Fig. 8D, a portion of the insulating layer L5 and the partition wall 6 located between the lower electrodes LE1 and LE2 will be described. The portion of the insulating layer L5 and the partition wall 6 located between the lower electrodes LE1 and LE3 and the portion located between the lower electrodes LE2 and LE3 are also formed in the same manner as in Fig. 8A to Fig. 8D.

[0059] First, as shown in FIG. 8A, a resist R1 covering the partition 6 is disposed on the insulating layer L5. The resist R1 has a lattice-like planar shape like the partition 6. For example, the resist R1 has a cross-sectional shape whose thickness decreases toward both ends. It is desirable that the size of the resist R1 is such that the ends E11 and E12 are not exposed from the resist R1. In the example of FIG. 8A, the ends E11 and E12 of the upper portion 62 are covered with the resist R1.

[0060] Next, as shown in FIG. 8B, anisotropic dry etching is performed on the insulating layer L5 using the resist R1 as a mask. The two-dot chain lines shown in FIG. 8B to FIG. 8D represent the outlines of the insulating layer L5 and the resist R1 before etching. In this etching, the portion of the insulating layer L5 exposed from the resist R1 is eroded. In this etching, the resist R1 is also eroded. Therefore, the width of the resist R1 gradually decreases during the etching. As a result, inclined surfaces L51 and L52 are formed on the insulating layer L5 as shown in FIG. 8B.

[0061] During the etching, the width of the resist R1 gradually decreases, exposing parts of the ends E11, E12 of the upper portion 62 and parts of the upper surface U1. Therefore, the partition wall 6 divides the resist R1 into a resist R1a located on the region AR1 side among the resists located under the upper portion 62, a resist R1b located on the region AR2 side among the resists located under the upper portion 62, and a resist R1c located on the upper portion 62. The second top layer 66 is made of a conductive oxide and is less affected by the etching. Therefore, the parts of the upper surface U1 exposed from the resist R1c and the ends E11, E12 are hardly eroded.

[0062] As the etching progresses, the width of the resist R1 is further reduced, and as shown in FIG. 8C, the ends E11 and E12 of the upper portion 62 are completely exposed. The resist R1a in the region AR1 and the resist R1b in the region AR2 are located directly below the upper portion 62 in the third direction Z. As a result, the upper portion 62 suppresses the erosion of the resist R1a in the region AR1 and the resist R1b in the region AR2 during the etching. On the other hand, the resist R1a outside the region AR1 and the resist R1b outside the region AR2 are eroded by the etching because they do not overlap with the upper portion 62 in a plan view. Therefore, an end Ea that is aligned with the end E11 of the upper portion 62 in the third direction Z is formed in the resist R1a. Similarly, an end Eb that is aligned with the end E12 of the upper portion 62 in the third direction Z is formed in the resist R1b. Note that, during the etching, a protective film may be formed on the ends Ea and Eb to prevent erosion by the etching.

[0063] As the etching proceeds further, the width of the resist R1 is further reduced as shown in FIG. 8D. As a result, the portions of the insulating layer L5 exposed from the resists R1a and R1b are removed by the etching, and the rib 5 and the pixel openings AP1 and AP2 surrounded by the rib 5 are formed. Furthermore, the etching forms in the rib 5 a first portion 51 having a constant thickness, a second portion 521 whose thickness decreases toward the pixel opening AP1, and a second portion 522 whose thickness decreases toward the pixel opening AP2. In the second portion 521, an inclined surface 531 is formed that inclines from the boundary B1 between the first portion 51 and the second portion 521 toward the pixel opening AP1. Similarly, in the second portion 522, an inclined surface 532 is formed that inclines from the boundary B2 between the first portion 51 and the second portion 522 toward the pixel opening AP2. When the rib 5 and the pixel openings AP1 and AP2 are formed, the etching is terminated. After the etching, the resist R1 is removed.

[0064] As shown in FIG. 8D, at the end of the etching, the resist R1a remains in the region AR1, and the resist R1b remains in the region AR2. Also, the resist R1c remains on the upper surface U1 of the upper portion 62. Furthermore, the lower surface L1 of the first top layer 65 in the region AR1, the side surface F21 of the shaft layer 64, the end E31 of the bottom layer 63, and the upper surface U5 of the first portion 51 in the region AR1 are covered with the resist R1a. Similarly, the lower surface L1 of the first top layer 65 in the region AR2, the side surface F22 of the shaft layer 64, the end E32 of the bottom layer 63, and the upper surface U5 of the first portion 51 in the region AR2 are covered with the resist R1b. In the example of FIG. 8D, the end E11 of the upper portion 62, the end Ea of the resist R1a, and the boundary B1 coincide with each other in a plan view. Similarly, the end E12 of the upper portion 62, the end Eb of the resist R1b, and the boundary B2 coincide with each other in a plan view.

[0065] After the formation of the rib 5, a process for forming the display elements DE1, DE2, and DE3 is performed. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0066] In forming the display element DE1, first, a laminated film FL1 and a sealing layer SE11 are formed as shown in Fig. 9. As shown in Fig. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1.

[0067] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by deposition. The sealing layer SE11 is formed by CVD (Chemical Vapor Deposition). The laminated film FL1 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0068] After the laminated film FL1 and the sealing layer SE11 are formed, a resist R2 is disposed on the sealing layer SE11 as shown in Fig. 9. The resist R2 covers the subpixel SP1 and a part of the partition wall 6 around it.

[0069] Then, as shown in FIG. 10, the laminated film FL1 and the sealing layer SE11 are etched using the resist R2 as a mask to remove the exposed portions of the resist R2. This forms a display element DE1 in the subpixel SP1. For example, the etching includes wet etching and dry etching that are sequentially performed on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R2 is removed.

[0070] The display element DE2 is formed in the same manner as the display element DE1. That is, in forming the display element DE2, a laminated film FL2 and a sealing layer SE12 are formed as shown in Fig. 11. As shown in Fig. 3, the laminated film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0071] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by deposition. The sealing layer SE12 is formed by CVD. The laminated film FL2 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE12 continuously covers each divided part of the laminated film FL2 and the partition walls 6.

[0072] After the laminated film FL2 and the sealing layer SE12 are formed, a resist R3 is disposed on the sealing layer SE12 as shown in Fig. 11. The resist R3 covers the subpixel SP2 and a part of the partition wall 6 around it.

[0073] Then, as shown in FIG. 12, the laminated film FL2 and the sealing layer SE12 are etched using the resist R3 as a mask to remove the portions of the laminated film FL2 and the sealing layer SE12 that are exposed from the resist R3. This forms a display element DE2 in the subpixel SP2. For example, the etching includes wet etching and dry etching that are sequentially performed on the sealing layer SE12, the cap layer CP2, the upper electrode UE2, and the organic layer OR2. After these etching processes, the resist R3 is removed.

[0074] The display element DE3 is formed in the same manner as the display elements DE1 and DE2. That is, when the display element DE3 is formed, a laminated film FL3 and a sealing layer SE13 are formed as shown in Fig. 13. As shown in Fig. 3, the laminated film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0075] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by deposition. The sealing layer SE13 is formed by CVD. The laminated film FL3 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the laminated film FL3 and the partition walls 6.

[0076] After the laminated film FL3 and the sealing layer SE13 are formed, a resist R4 is disposed on the sealing layer SE13 as shown in Fig. 13. The resist R4 covers the subpixel SP3 and a part of the partition wall 6 around it.

[0077] Then, as shown in FIG. 14, the laminated film FL3 and the sealing layer SE13 are etched using the resist R4 as a mask to remove the portions of the laminated film FL3 and the sealing layer SE13 that are exposed from the resist R4. This forms a display element DE3 in the subpixel SP3. For example, the etching includes wet etching and dry etching that are sequentially performed on the sealing layer SE13, the cap layer CP3, the upper electrode UE3, and the organic layer OR3. After these etchings, the resist R3 is removed.

[0078] After the display elements DE1, DE2, and DE3 are formed, a resin layer RS1, a sealing layer SE2, and a resin layer RS2 are formed in this order, as shown in Fig. 15. Through these steps, the display device DSP is completed.

[0079] In the present embodiment, as shown in FIGS. 8A to 8D, by anisotropic dry etching performed in the step of forming the rib 5 and the pixel openings AP1 and AP2, the width of the resist R1 decreases, and the ends E11 and E12 of the upper portion 62 are exposed. That is, by the partition wall 6, the resist R1 is divided into resists R1a and R1b located under the upper portion 62 and a resist R1c located above the upper portion 62. Since the portions of the resists R1a and R1b that overlap the upper portion 62 in the third direction Z are shielded from the etching by the upper portion 62, they are hardly eroded. Therefore, by this etching, the end E11 of the upper portion 62 and the boundary B1 between the first portion 51 and the second portion 521 coincide in plan view, and the end E12 of the upper portion 62 and the boundary B2 between the first portion 51 and the second portion 522 coincide in plan view, and the pixel openings AP1 and AP2 are formed in the rib 5. That is, the width of the first portion 51 of the rib 5 is determined by the width of the upper portion 62. The same applies to the first portion 51 located between the pixel openings AP1 and AP3 and between the pixel openings AP2 and AP3.

[0080] On the other hand, when the coating amount of the resist R1 is large, the etching ends before the resist R1 is divided by the partition wall 6. In this case, the width of the first portion 51 of the rib 5 is determined by the width of the resist R1 at the end of the etching. Therefore, due to variations in the coating amount of the resist, there is a possibility that pixel openings with non-uniform sizes and positions are formed for each pixel.

[0081] In contrast, in the present embodiment, as described above, the width of the first portion 51 of the rib 5 is determined by the width of the upper portion 62. Therefore, it is possible to form pixel openings with substantially uniform sizes and positions for each pixel. Furthermore, compared with the case where the coating amount of the resist is large, it is possible to form larger pixel openings.

[0082] Thus, according to the method for manufacturing the display device DSP according to the present embodiment, it is possible to improve the yield during the manufacture of the display device DSP. In addition, various suitable effects can be obtained from the present embodiment.

[0083] All display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display device manufacturing method described above as an embodiment of the present invention fall within the scope of the present invention as long as they include the gist of the present invention.

[0084] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0085] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0086] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, 5...rib, 51...first portion, 521, 522...second portion, 6...partition wall, 61...lower portion, 62...upper portion, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer, R1, R1a, R1b, R1c, R2, R3, R4...resist.

Claims

1. Forming a lower electrode; forming an insulating layer on the lower electrode; forming a partition wall including a lower portion disposed above the insulating layer and an upper portion having an end portion protruding from a side surface of the lower portion; a resist for covering the partition wall is disposed on the insulating layer; a rib and a pixel opening surrounded by the rib are formed by removing a portion of the insulating layer exposed from the resist by etching; forming an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; forming an upper electrode covering the organic layer; Including, During the etching, the end of the upper portion is exposed from the resist. A method for manufacturing a display device.

2. The etching gradually reduces the width of the resist. The method for manufacturing the display device according to claim 1 .

3. When the etching is completed, the resist remains in an area surrounded by a lower surface of the upper portion, the side surface of the lower portion, and an upper surface of the rib. The method for manufacturing the display device according to claim 1 .

4. When the etching is completed, the end of the upper portion and an end of the resist remaining in the region are aligned in a plan view. The method for manufacturing the display device according to claim 3 .

5. Upon completion of the etching, the resist remains on a top surface of the upper portion. The method for manufacturing the display device according to claim 1 .

6. forming the rib including a first portion having a constant thickness and a second portion having a thickness decreasing toward the pixel opening by the etching; The method for manufacturing the display device according to claim 1 .

7. When the etching is completed, the end of the upper portion and a boundary between the first portion and the second portion coincide with each other in a plan view. The method for manufacturing the display device according to claim 6 .

8. the second portion has an inclined surface that is inclined from the boundary toward the pixel aperture, an angle between the inclined surface and the upper surface of the lower electrode is 50° or less; The method for manufacturing the display device according to claim 7 .

9. An end portion of the lower electrode overlaps with the partition wall in a plan view. The method for manufacturing the display device according to claim 1 .

10. the upper portion has a first top layer disposed over the lower portion and a second top layer disposed over the first top layer; The second top layer is formed of a conductive oxide. The method for manufacturing the display device according to claim 1 .

11. At the end of the etching, the lower surface of the first top layer is covered by the resist. The method for manufacturing the display device according to claim 10 .

12. The lower portion has an axis layer and a bottom layer disposed between the axis layer and the rib, The end of the bottom layer is located between the end of the upper portion and the side surface of the axial layer in a plan view. The method for manufacturing the display device according to claim 1 .

13. An end of the lower electrode overlaps with the axial layer in a plan view. The method for manufacturing the display device according to claim 12 .

14. At the end of the etching, the edge of the bottom layer is covered by the resist. The method for manufacturing the display device according to claim 12 .

15. Upon completion of the etching, the side surface of the axial layer is covered with the resist. The method for manufacturing the display device according to claim 12 .

16. The etching is a dry etching. The method for manufacturing the display device according to claim 1 .

17. The etching is anisotropic etching. The method for manufacturing the display device according to claim 1 .

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