Low-speed half-bridge circuit and power factor correction circuit using the same

Abstract

To provide a low-speed half-bridge circuit capable of allowing deviation of timing control of switching.SOLUTION: A high-side driver 210H drives a slow-speed high-side switch Q1. A low-side driver 210L drives a slow-speed low-side switch Q2. The slow-speed high-side switch Q1 includes a first transistor M1 and a second transistor M2 that are a GaN transistor connected to face each other. The low-speed low-side switch Q2 includes a third transistor and a fourth transistor M4 that are a GaN transistor connected to face each other. The high-side driver 210H gently increases a gate-source voltage of each of the first transistor M1 and the second transistor M2 when the slow-speed high-side switch Q1 is turned on.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a power factor improvement circuit.

Background Art

[0002] An electric appliance that operates using an AC voltage as a power supply voltage is equipped with a power factor correction (PFC) circuit. The PFC circuit reduces the phase difference between the input voltage and current, suppresses the generation of harmonics, and makes the power factor approach 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

[0004] [Summary] Due to recent advancements in power semiconductors, a bridgeless totem-pole type (hereinafter referred to as the totem-pole type) PFC circuit with excellent efficiency is used. The totem-pole type PFC circuit includes a low-speed half-bridge circuit that switches in synchronization with the AC input, a high-speed half-bridge circuit that switches at high speed, and a reactor.

[0005] If the switching timing of the low-speed half-bridge circuit is misaligned, inrush current is generated. The inrush current causes input voltage distortion and malfunction of the circuit. Therefore, it is necessary to severely adjust the timing of the low-speed half-bridge circuit, and complex control is required.

[0006] The present disclosure has been made in view of such problems, and an exemplary object of one aspect thereof is to provide a low-speed half-bridge circuit that can tolerate misalignment in switching timing control.

[0007] The low-speed half-bridge circuit according to an aspect of the present disclosure is used in a totem-pole type bridgeless power factor improvement circuit. The low-speed half-bridge circuit includes a low-speed high-side switch, a low-speed low-side switch, a high-side driver that drives the low-speed high-side switch, and a low-side driver that drives the low-speed low-side switch. The low-speed high-side switch includes a first transistor and a second transistor, which are GaN transistors connected in an opposite manner. The low-speed low-side switch includes a third transistor and a fourth transistor, which are GaN transistors connected in an opposite manner. When turning on the low-speed high-side switch, the high-side driver gradually controls (soft start control) the gate-source voltage of each of the first transistor and the second transistor. When turning on the low-speed low-side switch, the low-side driver gradually controls (soft start control) the gate-source voltage of each of the third transistor and the fourth transistor.

[0008] In addition, any combination of the above components, as well as components and expressions that are mutually replaced between methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description of this item (means for solving the problems) does not explain all the essential features of the present invention. Therefore, sub-combinations of these described features can also be the present invention.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

[0010] [Detailed Description] [Overview of Embodiments] An overview of some exemplary embodiments of the present disclosure will be described. This overview simplifies and describes some concepts of one or more embodiments for the purpose of providing a basic understanding of the embodiments as a prelude to the detailed description to follow, and does not limit the scope of the invention or disclosure. This overview is not an exhaustive overview of all possible embodiments, nor is it intended to identify important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or variation) or a plurality of embodiments (examples or variations) disclosed herein.

[0011] A low-speed half-bridge circuit for a totem-pole type bridgeless power factor correction circuit according to one embodiment includes a low-speed high-side switch, a low-speed low-side switch, a high-side driver for driving the low-speed high-side switch, and a low-side driver for driving the low-speed low-side switch. The low-speed high-side switch includes a first transistor and a second transistor which are GaN transistors connected in a back-to-back manner. The low-speed low-side switch includes a third transistor and a fourth transistor which are GaN transistors connected in a back-to-back manner. When turning on the low-speed high-side switch, the high-side driver gradually controls the gate-source voltage of each of the first transistor and the second transistor (soft start control), and when turning on the low-speed low-side switch, the low-side driver gradually controls the gate-source voltage of each of the third transistor and the fourth transistor (soft start control).

[0012] By slowly increasing the voltage between the gate and source of the oppositely connected GaN-FET, a rapid rise in the drain current can be suppressed. Also, since they are opposite to each other, even if a reverse voltage is applied, only a current proportional to the respective gate-source voltage flows through each transistor. Since the drain current varies slowly, the inrush current is suppressed even if the polarity switching timing deviates from the appropriate timing.

[0013] In one embodiment, the high-side driver includes a driving transformer having a primary winding, a first secondary winding, and a second secondary winding, a control transformer having a primary winding and a secondary winding, a pulse driving circuit that supplies a driving pulse signal to the primary winding of the driving transformer, a first rectifying circuit connected to the first secondary winding of the driving transformer, a second rectifying circuit connected to the second secondary winding of the driving transformer, a first regulator with a soft start function that stabilizes the output voltage of the first rectifying circuit, a second regulator with a soft start function that stabilizes the output voltage of the second rectifying circuit, a first driver that supplies a first driving voltage corresponding to the output voltage of the first regulator between the gate and source of the first transistor in the high output state, a second driver that supplies a second driving voltage corresponding to the output voltage of the second regulator between the gate and source of the second transistor in the high output state, a transmission circuit that supplies a control pulse encoded according to the polarity of the AC voltage to the primary winding of the control transformer, and a secondary side controller that is connected to the secondary winding of the control transformer, receives the control pulse, and controls the first regulator, the second regulator, the first driver, and the second driver. The low-side driver may have the same configuration as the high-side driver.

[0014] By using an isolation transformer, the low-speed high-side can be driven without using a level shifter. The isolation transformer may be an air-core transformer.

[0015] A power factor improvement circuit according to one embodiment includes any of the above-described low-speed half-bridge circuits, a high-speed half-bridge circuit, and a reactor.

[0016] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Further, the embodiments are illustrative and not restrictive of the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0017] In this specification, the phrase "member A is in a state of being connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members without substantially affecting their electrical connection states or impairing the functions and effects achieved by their connection.

[0018] Similarly, the phrase "member C is in a state of being provided between member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members without substantially affecting their electrical connection states or impairing the functions and effects achieved by their connection.

[0019] Also, "signal A (voltage, current) is responsive to signal B (voltage, current)" means that signal A has a correlation with signal B. Specifically, it means (i) when signal A is signal B, (ii) when signal A is proportional to signal B, (iii) when signal A is obtained by level-shifting signal B, (iv) when signal A is obtained by amplifying signal B, (v) when signal A is obtained by inverting signal B, or (vi) any combination thereof, etc. It is understood by those skilled in the art that the scope of "responsive to" is determined according to the types and uses of signals A and B.

[0020] FIG. 1 is a circuit diagram of a PFC circuit 100 according to an embodiment. The PFC circuit 100 receives an AC voltage V AC generated by an AC power supply 2 on the input side and supplies an output voltage V OUT to a load 4 connected between a P-side line 102 and an N-side line 104.

[0021] The PFC circuit 100 mainly includes a low-speed half-bridge circuit 200, a high-speed half-bridge circuit 300, a reactor L1, and a controller 110.

[0022] The reactor L1 is connected in series with the AC power supply 2. The switching node of the low-speed half-bridge circuit 200 is connected to one end of the series connection circuit 4 of the AC power supply 2 and the reactor L1, and the switching node of the high-speed half-bridge circuit 300 is connected to the other end of the series connection circuit 4.

[0023] The low-speed half-bridge circuit 200 includes a low-speed high-side switch Q1, a low-speed low-side switch Q2, a high-side driver 210H, and a low-side driver 210L. The low-speed high-side switch Q1 and the low-speed low-side switch Q2 are connected in series between the P-side line 102 and the N-side line 104.

[0024] The high-side driver 210H controls the on and off of the low-speed high-side switch Q1 according to the first control signal CTRL1. The low-side driver 210L controls the on and off of the low-speed low-side switch Q2 according to the second control signal CTRL2.

[0025] The controller 110 generates the first control signal CTRL1 and the second control signal CTRL2 so that the low-speed high-side switch Q1 and the low-speed low-side switch Q2 are alternately turned on according to the polarity of the AC voltage V AC .

[0026] The high-speed half-bridge circuit 300 includes a high-speed high-side switch Q3, a high-speed low-side switch Q4, a high-side driver 310H, and a low-side driver 310L. The high-speed high-side switch Q3 and the high-speed low-side switch Q4 are connected in series between the P-side line 102 and the N-side line 104.

[0027] The high-side driver 310H controls the on and off states of the high-speed high-side switch Q3 according to the third control signal CTRL3. The low-side driver 310L controls the on and off states of the high-speed low-side switch Q4 according to the fourth control signal CTRL4.

[0028] The controller 110 switches the high-speed high-side switch Q3 and the high-speed low-side switch Q4 by PWM (pulse width modulation) control so that the power factor approaches 1, that is, the phase of the average value of the coil current I flowing through the reactor L1 approaches the phase of the AC voltage V. L of AC approaches the phase of the AC voltage V.

[0029] Figure 2 is a diagram for explaining the basic operation of the PFC circuit 100 in FIG. 1. In the section t AC ~t 0 when the AC voltage V is positive, the low-speed high-side switch Q1 is turned off and the low-speed low-side switch Q2 is turned on. In the section t 1 ~t AC when the AC voltage V is negative, the low-speed high-side switch Q1 is turned on and the low-speed low-side switch Q2 is turned off. 1 ~t 2 In the section t

[0030] The duty cycles of the high-speed high-side switch Q3 and the high-speed low-side switch Q4 are adjusted so that the phase of the average value (dashed line) of the coil current i L approaches the phase of the AC voltage V AC . Here, the continuous conduction mode (CCM) is taken as an example for explanation, but it may also operate in the boundary current mode (BCM) or the discontinuous conduction mode (DCM).

[0031] Returning to FIG. 1, the specific configuration of the low-speed half-bridge circuit 200 will be described.

[0032] The low-speed high-side switch Q1 includes a first transistor M1 and a second transistor M2, which are GaN transistors connected in a back-to-back configuration. The first transistor M1 and the second transistor M2 are N-channel and are connected with a common source.

[0033] Similarly, the low-speed low-side switch Q2 includes a third transistor M3 and a fourth transistor M4, which are GaN transistors connected in a back-to-back configuration.

[0034] The high-side driver 210H turns on the first transistor M1 and the second transistor M2 in response to a first control signal CTRL1 that instructs the turn-on of the low-speed high-side switch Q1. When turning on, the high-side driver 210H gradually raises the gate-source voltages Vgs13 and Vgs2 of the first transistor M1 and the second transistor M2 respectively by means of ramp control (soft start control).

[0035] Similarly, the low-side driver 210L turns on the third transistor M3 and the fourth transistor M4 in response to a second control signal CTRL2 that instructs the turn-on of the low-speed low-side switch Q2. When turning on, the low-side driver 210L gradually raises the gate voltages Vgs3 and Vgs4 of the third transistor M3 and the fourth transistor M4 respectively by means of ramp control (soft start control).

[0036] The above is the configuration of the PFC circuit 100. Subsequently, its operation will be described.

[0037] Figure 3 is a waveform diagram for explaining the operation of the low-speed half-bridge circuit 200 in the PFC circuit 100. At time t 0When the second control signal CTRL2 transitions to high, the low-side driver 210L soft-start controls the gate-source voltages Vgs3 and Vgs4 of the third transistor M3 and the fourth transistor M4, gradually increasing them over time. As a result, the on-resistance of the low-speed low-side switch Q2 gradually decreases over time.

[0038] That is, at a certain interval t AC immediately after the timing t 0 of the polarity switching of the alternating voltage V 0 ~t 3 the impedance of the low-speed low-side switch Q2 becomes high. Thereby, a rapid rise in the drain current Ids2 of the low-speed low-side switch Q2 can be suppressed, and thus waveform distortion and harmonics can be suppressed.

[0039] Also, since the low-speed low-side switch Q2 includes two opposing transistors M3 and M4, even if a reverse voltage is applied, only a current Ids2 proportional to each gate voltage flows through each of the transistors M3 and M4. Further, since the drain current Ids2 varies slowly, even if the timing of the polarity switching deviates from the appropriate timing, the inrush current is suppressed.

[0040] At time t 1 when the second control signal CTRL2 transitions to low, the low-side driver 210L decreases the gate-source voltages Vgs3 and Vgs4 of the third transistor M3 and the fourth transistor M4. Also, at time t 1 when the first control signal CTRL1 transitions to high, the high-side driver 210H soft-start controls the gate-source voltages Vgs1 and Vgs2 of the first transistor M1 and the second transistor M2, gradually increasing them over time. As a result, the on-resistance of the low-speed high-side switch Q1 gradually decreases over time.

[0041] That is, at a certain interval t AC immediately after the timing t 1 of the polarity switching of the alternating voltage V 1 ~t4 During this period, the impedance of the low-speed high-side switch Q1 also increases. As a result, the rapid rise of the drain current Ids1 of the low-speed high-side switch Q1 can be suppressed, and thus waveform distortion and harmonics can be suppressed.

[0042] In addition, since the low-speed high-side switch Q1 includes two opposing transistors M1 and M2, even if a reverse voltage is applied, only a current proportional to each gate voltage flows through each of the transistors M1 and M2. Also, since the drain current Ids1 varies slowly, even if the timing of the polarity switching deviates from the appropriate timing, the inrush current is suppressed.

[0043] Thus, according to the PFC circuit 100 of FIG. 1, the deviation of the switching timing control can be tolerated.

[0044] The present disclosure is understood as the block diagram or circuit diagram of FIG. 1, or extends to various devices and methods derived from the above description, and is not limited to a specific configuration. Hereinafter, in order to assist in understanding the essence and operation of the present disclosure or the present invention, and to clarify them, rather than narrowing the scope of the present disclosure, more specific configuration examples and embodiments will be described.

[0045] FIG. 4 is a block diagram of a high-side driver 210H according to an embodiment. The high-side driver 210H includes a driving transformer TRN1, a control transformer TRN2, a pulse driving circuit 212, a first rectifying circuit 214, a second rectifying circuit 216, a first regulator 218, a second regulator 220, a first driver 222, a second driver 224, a transmission circuit 226, and a secondary side controller 228.

[0046] The driving transformer TRN1 has a primary winding Wp, a first secondary winding Ws1, and a second secondary winding Ws2. The control transformer TRN2 has a primary winding Wp and a secondary winding Ws. The driving transformer TRN1 and the control transformer TRN2 may be air-core transformers.

[0047] The pulse drive circuit 212 supplies a drive pulse signal S1 to the primary winding Wp of the drive transformer TRN1.

[0048] The first rectifier circuit 214 is connected to the first secondary winding Ws1 of the drive transformer TRN1. The first rectifier circuit 214 includes a diode D1 and a capacitor C1. The pulse drive circuit 212, the drive transformer TRN1, and the first rectifier circuit 214 constitute an isolated converter, and based on the secondary-side high-side common line 202, a rectified voltage V RCT1 is generated. The high-side common line 202 is connected to the common source node of the first transistor M1 and the second transistor M2.

[0049] The second rectifier circuit 216 is connected to the second secondary winding Ws2 of the drive transformer TRN1. The second rectifier circuit 216 includes a diode D2 and a capacitor C2. The pulse drive circuit 212, the drive transformer TRN1, and the second rectifier circuit 216 constitute an isolated converter, and based on the secondary-side high-side common line 202, a rectified voltage V RCT2 is generated.

[0050] The first regulator 218 stabilizes the output voltage V RCT1 of the first rectifier circuit 214 and generates a constant voltage V LDO1 . The first regulator 218 is a linear regulator (LDO: Low Drop Output) with a soft start function. When the signal input to the soft start terminal SS is asserted (for example, high), the output voltage V LDO1 slowly rises over time towards the target level V REF .

[0051] The second regulator 220 stabilizes the output voltage V RCT2 of the second rectifier circuit 216 and generates a constant voltage V LDO2 . The second regulator 220 has the same configuration and function as the first regulator 218.

[0052] The first driver 222 is configured to be able to switch between a high output state and a low output state in response to an enable signal EN1. In the high output state, a first drive voltage V LDO1 having the same voltage level as the output voltage V DRV1 of the first regulator 218 is supplied between the gate and source of the first transistor M1.

[0053] The second driver 224 is configured to be able to switch between a high output state and a low output state in response to an enable signal EN2. In the high output state, a second drive voltage V LDO2 having the same voltage level as the output voltage V DRV2 of the second regulator 220 is supplied between the gate and source of the second transistor M2.

[0054] The transmission circuit 226 supplies a control pulse S2 encoded according to the polarity POL of the AC voltage V AC to the primary winding Wp of the control transformer TRN2. The encoding method is not particularly limited.

[0055] The secondary side controller 228 is connected to the secondary winding Ws of the control transformer TRN2 and receives the control pulse S2. The secondary side controller 228 decodes the control pulse S2 and determines the polarity POL. Based on the determined polarity POL, the secondary side controller 228 generates soft start signals SS1 and SS2 for controlling the first regulator 218 and the second regulator 220, and generates enable signals EN1 and EN2 for controlling the first driver 222 and the second driver 224.

[0056] The low side driver 210L is configured in the same manner as the high side driver 210H.

[0057] The high side driver 210H, the low side driver 210L, the low speed high side switch Q1, and the low speed low side switch Q2 are housed in one package and modularized.

[0058] Figure 5 is an operating waveform diagram of the PFC circuit 100 in Figure 4. In Figure 5, the AC voltage VAC The operation in the half cycle where is negative is shown. The secondary controller 228 receives the control pulse S2 from the transmission circuit 226 and determines the polarity POL. The pulse drive circuit 212 generates the drive pulse signal S1, and the rectified voltages V RCT1 , V RCT2 are generated at the outputs of the first rectifier circuit 214 and the second rectifier circuit 216.

[0059] When the secondary controller 228 detects a change in the polarity POL, it asserts the soft start signals SS1 and SS2 and also asserts the enable signals EN1 and EN2. As a result, the output voltages V LDO1 , V LDO2 of the first regulator 218 and the second regulator 220 gradually increase with time, and following that, the drive voltages V DRV1 , V DRV2 supplied to the gate sources of the first transistor M1 and the second transistor M2 gradually increase with time.

[0060] The above is the operation of the high-side driver 210H in FIG. 4. Note that the configurations of the high-side driver 210H and the low-side driver 210L are not limited to those shown in FIG. 4.

[0061] The embodiments merely show the principles and applications of the present invention, and in the embodiments, many modifications and arrangement changes are allowed without departing from the idea of the present invention defined in the claims.

[0062] [Appendix] The technology disclosed in this specification can be grasped as follows in one aspect.

[0063] (Item 1) A low-speed half-bridge circuit for a totem-pole type bridgeless power factor correction circuit, comprising a low-speed high-side switch, a low-speed low-side switch, a high-side driver for driving the low-speed high-side switch, A low-side driver for driving the low-speed low-side switch, comprising, The low-speed high-side switch includes a first transistor and a second transistor which are GaN transistors connected in an opposite manner, The low-speed low-side switch includes a third transistor and a fourth transistor which are GaN transistors connected in an opposite manner, When the high-side driver turns on the low-speed high-side switch, it gently raises the voltage between the gate and source of each of the first transistor and the second transistor, When the low-side driver turns on the low-speed low-side switch, it gently raises the voltage between the gate and source of each of the third transistor and the fourth transistor, a low-speed half-bridge circuit.

[0064] (Item 2) The high-side driver, A driving transformer having a primary winding, a first secondary winding and a second secondary winding, A control transformer having a primary winding and a secondary winding, A pulse drive circuit for supplying a drive pulse signal to the primary winding of the driving transformer, A first rectifier circuit connected to the first secondary winding of the driving transformer, A second rectifier circuit connected to the second secondary winding of the driving transformer, A first regulator with a soft start function for stabilizing the output voltage of the first rectifier circuit, A second regulator with a soft start function for stabilizing the output voltage of the second rectifier circuit, In a high output state, a first driver for supplying a first drive voltage corresponding to the output voltage of the first regulator between the gate and source of the first transistor, In a high output state, a second driver for supplying a second drive voltage corresponding to the output voltage of the second regulator between the gate and source of the second transistor, A transmission circuit that supplies a control pulse encoded according to the polarity of an AC voltage to the primary winding of the control transformer; A secondary-side controller that is connected to the secondary winding of the control transformer, receives the control pulse, and controls the first regulator, the second regulator, the first driver, and the second driver; comprising The low-side driver has the same configuration as the high-side driver. The low-speed half-bridge circuit according to Item 1.

[0065] (Item 3) The low-speed half-bridge circuit according to Item 1 or 2, which is housed in one package and modularized.

[0066] (Item 4) The low-speed half-bridge circuit according to Item 1 or 2, a high-speed half-bridge circuit, a reactor, and a power factor improvement circuit comprising the same.

Explanation of Signs

[0067] 100 PFC circuit 102 P-side line 104 N-side line 110 Controller L1 Reactor Q1 Low-speed high-side switch Q2 Low-speed low-side switch M1 First transistor M2 Second transistor M3 Third transistor M4 Fourth transistor 200 Low-speed half-bridge circuit 210H High-side driver 210L Low-side driver TRN1 Drive transformer TRN2 Control transformer 212 Pulse drive circuit 214 First rectifier circuit 216 Second Rectifying Circuit 218 First Regulator 220 Second Regulator 222 First Driver 224 Second Driver 226 Transmission Circuit 228 Secondary Controller 300 High-Speed Half-Bridge Circuit Q3 High-Speed High-Side Switch Q4 High-Speed Low-Side Switch 310H High-Side Driver 310L Low-Side Driver

Claims

1. A low-speed half-bridge circuit for a totem-pole type bridgeless power factor correction circuit, comprising: a low-speed high-side switch; a low-speed low-side switch; a high-side driver for driving the low-speed high-side switch; a low-side driver for driving the low-speed low-side switch; wherein the low-speed high-side switch includes a first transistor and a second transistor which are GaN transistors connected in opposite directions; the low-speed low-side switch includes a third transistor and a fourth transistor which are GaN transistors connected in opposite directions; when the high-side driver turns on the low-speed high-side switch, the gate-source voltage of each of the first transistor and the second transistor is gently increased; when the low-side driver turns on the low-speed low-side switch, the gate-source voltage of each of the third transistor and the fourth transistor is gently increased. A low-speed half-bridge circuit.

2. The high-side driver includes: a driving transformer having a primary winding, a first secondary winding, and a second secondary winding; a control transformer having a primary winding and a secondary winding; a pulse driving circuit for supplying a driving pulse signal to the primary winding of the driving transformer; a first rectifying circuit connected to the first secondary winding of the driving transformer; a second rectifying circuit connected to the second secondary winding of the driving transformer; a first regulator with a soft start function for stabilizing the output voltage of the first rectifying circuit; a second regulator with a soft start function for stabilizing the output voltage of the second rectifying circuit; a first driver for supplying a first driving voltage corresponding to the output voltage of the first regulator between the gate and source of the first transistor in a high output state; a second driver for supplying a second driving voltage corresponding to the output voltage of the second regulator between the gate and source of the second transistor in a high output state; a transmission circuit for supplying a control pulse encoded according to the polarity of an AC voltage to the primary winding of the control transformer; a secondary side controller connected to the secondary winding of the control transformer, receiving the control pulse, and controlling the first regulator, the second regulator, the first driver, and the second driver; and including The low-side driver has the same configuration as the high-side driver, the low-speed half-bridge circuit according to claim 1.

3. The low-speed half-bridge circuit according to claim 1 or 2, which is housed in one package and modularized.

4. The low-speed half-bridge circuit according to claim 1 or 2, a high-speed half-bridge circuit, a reactor, and a power factor improvement circuit comprising the same.

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