Semiconductor device

Abstract

To provide a semiconductor device capable of supporting various interface modes.SOLUTION: According to one embodiment of the present invention, a semiconductor device comprises: a data pad; at least one merger node; a first data path that is connected to between the data pad and at least the one merger node, and is for outputting a first data signal to at least the one merger node at a first mode on the basis of a data signal, a reference signal, and a mode selection signal; a second data path that is connected to between the data pad and at least the one merger node and is for outputting a second data signal to at least the one merger node at a second mode on the basis of the data signal, the reference signal, and the mode selection signal; and a synchronization path that is connected to at least the one merger node, and is for outputting the first or the second data signal as a data signal to be synchronized to at least one data strobe signal at the first mode or the second mode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to semiconductor design technology, and more particularly to a semiconductor device including an interface circuit.

Background Art

[0002] A semiconductor device can receive or output various signals by preset operations. For example, a memory device receives or outputs a data signal and a data strobe signal from a memory control device.

[0003] The semiconductor device includes an interface circuit for inputting and outputting the various signals. The interface circuit is developed variously according to modes.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a semiconductor device that supports various interface modes.

Means for Solving the Problems

[0005] According to one aspect of the present invention, a semiconductor device includes a data pad, at least one merging node, a first data path connected between the data pad and the at least one merging node for outputting a first data signal to the at least one merging node in a first mode based on a data signal, a reference signal, and a mode selection signal, a second data path connected between the data pad and the at least one merging node for outputting a second data signal to the at least one merging node in a second mode based on the data signal, the reference signal, and the mode selection signal, and a synchronization path connected to the at least one merging node for outputting the first data signal or the second data signal as a data signal synchronized with at least one data strobe signal in the first mode or the second mode.

[0006] According to another aspect of the present invention, a semiconductor device includes a data pad, at least one common node, a common path connected between the data pad and the at least one common node for outputting a common data signal to the at least one common node based on a data signal and a reference signal, at least one merging node, a first data path connected between the at least one common node and the at least one merging node for outputting a first data signal to the at least one merging node in a first mode based on the common data signal and a mode selection signal, a second data path connected between the at least one common node and the at least one merging node for outputting a second data signal to the at least one merging node in a second mode based on the common data signal and the mode selection signal, and a synchronization path connected to the at least one merging node for outputting the first data signal or the second data signal as a data signal synchronized with at least one data strobe signal in the first mode or the second mode.

[0007] According to still another aspect of the present invention, a semiconductor device includes a first data path for generating a first data signal in a first mode based on a data signal and a reference signal, a second data path for generating a second data signal in a second mode based on the data signal and the reference signal, and a synchronization path for outputting, in the first and second modes, a selected data signal among the first and second data signals as a data signal synchronized with at least one data strobe signal based on a mode selection signal, the at least one data strobe signal, and the first and second data signals.

Advantages of the Invention

[0008] An embodiment of the present invention has an effect of improving compatibility by supporting various interface modes.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to explain in detail to such an extent that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement the technical idea of the present invention.

[0011] And, throughout the specification, when a certain part is said to be "connected" to another part, this includes not only the case where it is "directly connected", but also the case where it is "electrically connected" with other elements interposed therebetween. Further, when a certain part "includes" or "comprises" a certain component, this means that, unless otherwise stated to the contrary, it does not exclude other components, but can further include or comprise other components. Also, throughout the description of the specification, even if some components are described in the singular form, it will be understood that the present invention is not limited thereto and the components can consist of a plurality.

[0012] FIG. 1 shows a configuration diagram of a semiconductor device 100 according to a first embodiment of the present invention.

[0013] As shown in FIG. 1, the semiconductor device 100 can include a data pad PD, a first data path 110, a second data path 120, and a synchronization path 130.

[0014] The data pad PD can be connected to an external device. The data pad PD can receive a data signal DQ output from the external device. The data pad PD can be connected to a supply terminal of a high voltage VTT through a termination resistor RZ.

[0015] The first data path 110 can be connected between the data pad PD and the merge node pairs TN, BN. The first data path 110 can be enabled in the first mode based on a mode selection signal EN. For example, the first mode can be a low-speed mode to which a preset internal delay time is applied. The first data path 110 can output the first differential data signals DQ1, / DQ1 as differential data signals DDQ, / DDQ to the merge node pairs TN, BN in the first mode based on the data signal DQ, a reference signal VREF, and the mode selection signal EN.

[0016] The second data path 120 can be connected between the data pad PD and the merging node pairs TN, BN. The second data path 120 can be enabled in the second mode based on the mode selection signal EN. For example, the second mode can be a high-speed mode in which the internal delay time is not applied. According to one example, in the second mode, based on the data signal DQ, the reference signal VREF, and the mode selection signal EN, the second differential data signals DQ2, / DQ2 can be output as differential data signals DDQ, / DDQ to the merging node pairs TN, BN (see FIG. 2). According to another example, in the second mode, based on the data signal DQ, the reference signal VREF, and the mode selection signal EN, the second differential data signals DQ2, / DQ2 can be output as differential data signals DDQ, / DDQ to the first merging node pairs TN, BN, and the third differential data signals DQ2’, / DQ2’ can be output as differential data signals DDQ’, / DDQ’ to the second merging node pairs TN’, BN’.

[0017] The synchronization path 130 can be connected to the merging node pairs TN, BN. In the first mode or the second mode, the synchronization path 130 can output the differential data signals DDQ, / DDQ as first to fourth data signals DQi, DQq, DQib, DQqb synchronized with the first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb. The first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb can have different phases from each other. For example, the first and second data strobe signals DQSi, DQSq can have a 90-degree phase difference, the second and third data strobe signals DQSq, DQSib can have a 90-degree phase difference, and the third and fourth data strobe signals DQSib, DQSqb can have a 90-degree phase difference.

[0018] FIG. 2 shows a block configuration diagram showing an example of the first data path 110, the second data path 120, and the synchronization path 130 shown in FIG. 1.

[0019] As shown in FIG. 2, the first data path 110 may include a first input circuit AMP1, a first replica circuit RP1, a second replica circuit RP2, and a third replica circuit RP3.

[0020] The first input circuit AMP1 can generate an input data signal based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0021] The first replica circuit RP1 can delay the input data signal by a first delay time and output the delayed data signal to the branch node VN. For example, the first replica circuit RP1 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0022] The second replica circuit RP2 can delay the delayed data signal by a second delay time and output the first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1 to the first merging node TN among the merging node pairs TN and BN. For example, the second replica circuit RP2 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series. Among the at least one repeater, the second repeater RT1 arranged at the end of the second replica circuit RP2 (i.e., closest to the first merging node TN) can be enabled according to the mode selection signal EN (see FIG. 3).

[0023] The third replica circuit RP3 can delay the delay data signal by the amount of the second delay time and output the first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1 to the second merging node BN among the merging node pairs TN and BN. For example, the third replica circuit RP3 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series. Among the at least one repeater, the third repeater RT2 disposed at the end of the third replica circuit RP3 (i.e., disposed closest to the second merging node BN) can be designed in the same manner as the second repeater RT1 and can be enabled according to the mode selection signal EN (see FIG. 3).

[0024] The first delay time and the second delay time can be determined by the internal delay time generated in the path through which the first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb are transmitted. For example, the sum of the first delay time and the second delay time can be the same as the internal delay time. Although not shown in the drawings, the internal delay time can include the time from when the data strobe signal generated by the external device is input to the pad included in the semiconductor device 100 until the first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb based on the data strobe signal are input to the synchronization path 130.

[0025] The second data path 120 can include a second input circuit AMP2.

[0026] The second input circuit AMP2 can output the second differential data signals DQ2 and / DQ2 as differential data signals DDQ and / DDQ to the first merging node TN and the second merging node BN, respectively, based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier.

[0027] The synchronization path 130 can include first to fourth comparison circuits C1 to C4 and first to fourth latch circuits LC1 to LC4.

[0028] The first comparison circuit C1 can perform a comparison operation while synchronized with the first data strobe signal DQSi for a first period of time. The first period of time may be related to the phase of the first data strobe signal DQSi. For example, the first period of time can correspond to one cycle of the first data strobe signal DQSi with reference to the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 compares the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and can generate a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 compares the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and can generate the first comparison data signal corresponding to the comparison result.

[0029] The second comparison circuit C2 can perform a comparison operation while synchronized with the second data strobe signal DQSq for a second period of time. The second period of time may be related to the phase of the second data strobe signal DQSq. For example, the second period of time can correspond to one cycle of the second data strobe signal DQSq with reference to the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 compares the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and can generate a second comparison data signal corresponding to the comparison result. The second comparison circuit C2 compares the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and can generate the second comparison data signal corresponding to the comparison result.

[0030] The third comparison circuit C3 can perform a comparison operation while being synchronized with the third data strobe signal DQSib for a third period of time. The third period of time may be related to the phase of the third data strobe signal DQSib. For example, the third period of time can correspond to one cycle of the third data strobe signal DQSib with reference to the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and generate a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and generate the third comparison data signal corresponding to the comparison result.

[0031] The fourth comparison circuit C4 can perform a comparison operation while being synchronized with the fourth data strobe signal DQSqb for a fourth period of time. The fourth period of time may be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth period of time can correspond to one cycle of the fourth data strobe signal DQSqb with reference to the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and generate a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and generate the fourth comparison data signal corresponding to the comparison result.

[0032] The first to fourth comparison circuits C1 to C4 can each receive a comparison data signal output from an adjacent comparison circuit C1, C2, C3, or C4. However, the first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This is related to decision feedback equalization (DFE) operation.

[0033] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0034] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0035] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0036] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0037] FIG. 3 shows a circuit diagram showing an example of a second repeater RT1 arranged at the end among the at least one repeater included in the second replica circuit RP2 shown in FIG. 2.

[0038] As shown in FIG. 3, the second repeater RT1 can include a first pull-up driver DD1, a first selection driver SD1, a second selection driver SD2, a first pull-down driver DD2, and a power gating element.

[0039] The first pull-up driver DD1 can be connected between the supply terminal of the first voltage and the first supply node. The first pull-up driver DD1 can pull up and drive the first supply node with the first voltage based on a first drive data signal IN corresponding to the delay data signal.

[0040] The first selection driver SD1 can be connected between the first supply node and the first output node. The first selection driver SD1 can selectively connect the first supply node and the first output node based on a mode selection signal EN. An output signal OUT corresponding to the first positive data signal DQ1 can be generated via the first output node.

[0041] The second selection driver SD2 can be connected between the first output node and the second supply node. The second selection driver SD2 can selectively connect the first output node and the second supply node based on an inverted signal / EN of the mode selection signal EN.

[0042] The first pull-down driver DD2 can be connected between the second supply node and the supply terminal of the second voltage. The first pull-down driver DD2 can pull down and drive the second supply node with the second voltage based on the first drive data signal IN.

[0043] The power gating element can enable the second repeater RT1 based on an enable signal PG_EN. For example, the enable signal PG_EN can be a write enable signal.

[0044] On the other hand, among the at least one repeater included in the third replica circuit RP3 shown in FIG. 2, the third repeater RT2 arranged at the end can be designed in the same manner as the second repeater RT1 in FIG. 3, so the description of the third repeater RT2 is omitted.

[0045] FIG. 4 shows a circuit diagram showing an example of the input circuit AMP2 included in the second data path 120 shown in FIG. 2.

[0046] As shown in FIG. 4, the second input circuit AMP2 can include a source driver SD1, a first input driver ID1, a third selection driver SD3, a second input driver ID2, a fourth selection driver SD4, a first sink driver KD1, a second sink driver KD2, and a logic circuit LOG.

[0047] The source driver SD1 can be connected between the supply terminal of the first voltage and the common node CN. The source driver SD1 can receive a bias voltage VBIAS. The source driver SD1 can supply the first voltage to the common node CN based on the bias voltage VBIAS.

[0048] The first input driver ID1 can be connected between the common node CN and the first node. The first input driver ID1 can receive a data signal DQ.

[0049] The third selection driver SD3 can be connected between the first node and the second merging node BN. The third selection driver SD3 can receive the inverted signal / EN of the mode selection signal EN.

[0050] The second input driver ID2 can be connected between the common node CN and the second node. The second input driver ID2 can receive a reference signal VREF.

[0051] The fourth selection driver SD4 can be connected between the second node and the first merging node TN. The fourth selection driver SD4 can receive the inverted signal / EN of the mode selection signal EN.

[0052] The first sink driver KD1 can be connected between the second merging node BN and the supply terminal of the second voltage. The first sink driver KD1 can receive a control signal.

[0053] The second sink driver KD2 can be connected between the first merging node TN and the supply terminal of the second voltage. The second sink driver KD2 can receive the control signal.

[0054] The logic circuit LOG can generate the control signal based on the mode selection signal EN and the enable signal PG_EN. For example, the logic circuit LOG can include a NAND gate and an inverter. The NAND gate can perform a negative logical sum operation on the mode selection signal EN and the enable signal PG_EN. The inverter can invert the output signal of the NAND gate to generate the control signal.

[0055] FIG. 5 shows a block configuration diagram showing another example of the first data path 110, the second data path 120, and the synchronization path 130 shown in FIG. 1.

[0056] As shown in FIG. 5, the first data path 110 can include a first input circuit AMP1, a first replica circuit RP1, a second replica circuit RP2, and a third replica circuit RP3.

[0057] The first input circuit AMP1 can generate an input data signal based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0058] The first replica circuit RP1 can delay the input data signal by a first delay time and output the delayed data signal to the branch node VN. For example, the first replica circuit RP1 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0059] The second replica circuit RP2 can delay the delayed data signal by a second delay time, and output the first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1 to the third merging node TN among the first merging node pairs TN, BN and the fifth merging node TN' among the second merging node pairs TN', BN'. For example, the second replica circuit RP2 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series. Among the at least one repeater, the second repeater RT1 arranged at the end of the second replica circuit RP2 (e.g., arranged closest to the third merging node TN) can be enabled according to the mode selection signal EN (see FIG. 3).

[0060] The third replica circuit RP3 delays the delay data signal by the amount of the second delay time, and outputs the first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1 to the fourth merging node BN among the first merging node pairs TN and BN, and the sixth merging node BN' among the second merging node pairs TN' and BN'. For example, the third replica circuit RP3 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series. Among the at least one repeater, the third repeater RT2 arranged at the end of the third replica circuit RP3 (e.g., arranged closest to the fourth merging node BN) can be enabled according to the mode selection signal EN (see FIG. 3).

[0061] The first delay time and the second delay time can be determined by the internal delay time generated in the path through which the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb are transmitted. For example, the sum of the first delay time and the second delay time can be the same as the internal delay time. Although not shown in the drawings, the internal delay time can include the time from when the data strobe signal generated by the external device is input to the pad included in the semiconductor device 100 to when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 130.

[0062] The second data path 120 can include second to fourth input circuits AMP2, AMP3, and AMP4.

[0063] The second input circuit AMP2 can output a differential data signal to the branch node pair TNN and BNN based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier.

[0064] The third input circuit AMP3 can output the second differential data signals DQ2 and / DQ2 as differential data signals DDQ and / DDQ to the first merging node pair TN and BN based on the differential data signal output from the second input circuit AMP2. For example, the third input circuit AMP3 can include an amplifier.

[0065] The fourth input circuit AMP4 can output the third differential data signals DQ2' and / DQ2' as differential data signals DDQ' and / DDQ' to the second merging node pair TN' and BN' based on the differential data signal output from the second input circuit AMP2. For example, the fourth input circuit AMP4 can include an amplifier.

[0066] The second to fourth input circuits AMP2, AMP3, and AMP4 can be designed to be the same as or different from the second input circuit AMP2 shown in FIG. 4, respectively.

[0067] The synchronization path 130 can include the first to fourth comparison circuits C1 to C4 and the first to fourth latch circuits LC1 to LC4.

[0068] The first comparison circuit C1 can perform a comparison operation during a first period synchronized with the first data strobe signal DQSi. The first period may be related to the phase of the first data strobe signal DQSi. For example, the first period can correspond to one cycle of the first data strobe signal DQSi based on the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and generate a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and generate the first comparison data signal corresponding to the comparison result.

[0069] The second comparison circuit C2 can perform a comparison operation during a second period synchronized with the second data strobe signal DQSq. The second period may be related to the phase of the second data strobe signal DQSq. For example, the second period can correspond to one cycle of the second data strobe signal DQSq based on the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and generate a second comparison data signal corresponding to the comparison result. The second comparison circuit C2 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and generate the second comparison data signal corresponding to the comparison result.

[0070] The third comparison circuit C3 can perform a comparison operation during a third time period, synchronized with the third data strobe signal DQSib. The third time period may be related to the phase of the third data strobe signal DQSib. For example, the third time period can correspond to one cycle of the third data strobe signal DQSib with reference to the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 compares the positive data signal DDQ' output via the third merging node TN' and the negative data signal / DDQ' output via the fourth merging node BN' during the first mode, and can generate a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 compares the positive data signal DDQ' output via the third merging node TN' and the negative data signal / DDQ' output via the fourth merging node BN' during the second mode, and can generate the third comparison data signal corresponding to the comparison result.

[0071] The fourth comparison circuit C4 can perform a comparison operation during a fourth time period, synchronized with the fourth data strobe signal DQSqb. The fourth time period may be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth time period can correspond to one cycle of the fourth data strobe signal DQSqb with reference to the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 compares the positive data signal DDQ' output via the third merging node TN' and the negative data signal / DDQ' output via the fourth merging node BN' during the first mode, and can generate a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 compares the positive data signal DDQ' output via the third merging node TN' and the negative data signal / DDQ' output via the fourth merging node BN' during the second mode, and can generate the fourth comparison data signal corresponding to the comparison result.

[0072] The first to fourth comparison circuits C1 to C4 can each receive a comparison data signal output from an adjacent comparison circuit C1 or C2 or C3 or C4. However, the first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This is related to decision feedback equalization (DFE) operation.

[0073] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0074] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0075] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0076] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0077] FIG. 6 shows a block configuration diagram of a semiconductor device 200 according to a second embodiment of the present invention.

[0078] As shown in FIG. 6, the semiconductor device 200 can include a data pad PD, a common path 210, a first data path 220, a second data path 230, and a synchronization path 240.

[0079] The data pad PD can be connected to an external device. The data pad PD can receive a data signal DQ output from the external device. The data pad PD can be connected to a supply terminal of a high voltage VTT through a termination resistor RZ.

[0080] The common path 210 can be connected between the data pad PD and the common node pairs CTN, CBN. The common path 210 can output differential common data signals CDQ, / CDQ to the common node pairs CTN, BTN based on the data signal DQ and the reference signal VREF.

[0081] The first data path 220 can be connected between the common node pairs CTN, BTN and the merged node pairs TN, BN. The first data path 220 can be enabled in the first mode based on a mode selection signal EN. For example, the first mode can be a low-speed mode to which a preset internal delay time is applied. The first data path 220 can output first differential data signals DQ1, / DQ1 as differential data signals DDQ, / DDQ to the merged node pairs TN, BN in the first mode based on the differential common data signals CDQ, / CDQ and the mode selection signal EN.

[0082] The second data path 230 can be connected between the common node pairs CTN, BTN and the merged node pairs TN, BN. The second data path 230 can be enabled in the second mode based on a mode selection signal EN. For example, the second mode can be a high-speed mode to which the internal delay time is not applied. The second data path 230 can output second differential data signals DQ2, / DQ2 as differential data signals DDQ, / DDQ to the merged node pairs TN, BN in the second mode based on the differential common data signals CDQ, / CDQ and the mode selection signal EN.

[0083] The synchronization path 240 can be connected to the merging node pair TN, BN. The synchronization path 240 can output, in the first mode or the second mode, differential data signals DDQ, / DDQ as first to fourth data signals DQi, DQq, DQib, DQqb synchronized with first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb. The first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb can have different phases from each other. For example, the first and second data strobe signals DQSi, DQSq can have a 90-degree phase difference, the second and third data strobe signals DQSq, DQSib can have a 90-degree phase difference, and the third and fourth data strobe signals DQSib, DQSqb can have a 90-degree phase difference.

[0084] FIG. 7 is a block diagram showing an example of the common path 210, the first data path 220, the second data path 230, and the synchronization path 240 shown in FIG. 6.

[0085] As shown in FIG. 7, the common path 210 can include a first input circuit AMP1.

[0086] The first input circuit AMP1 can output differential common data signals CDQ, / CDQ to the common node pair CTN, CBN based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0087] The first data path 210 can include a second input circuit AMP2, a first replica circuit RP1, a second replica circuit RP2, and a third replica circuit RP3. The second input circuit AMP2 can generate an input data signal based on the differential common data signals CDQ, / CDQ. For example, the second input circuit AMP2 can include an amplifier.

[0088] The first replica circuit RP1 can delay the input data signal by a first delay time and output the delayed data signal to the branch node VN. For example, the first replica circuit RP1 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0089] The second replica circuit RP2 can delay the delayed data signal by a second delay time and output the first positive data signal DQ1 among the first differential data signals DQ1, / DQ1 to the first merging node TN among the merging node pair TN, BN. For example, the second replica circuit RP2 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series. Among the at least one repeater, the second repeater RT1 arranged at the end of the second replica circuit RP2 (i.e., arranged closest to the first merging node TN) can be enabled according to the mode selection signal EN (see FIG. 3).

[0090] The third replica circuit RP3 can delay the delayed data signal by the second delay time and output the first negative data signal / DQ1 among the first differential data signals DQ1, / DQ1 to the second merging node BN among the merging node pair TN, BN. For example, the third replica circuit RP3 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series. Among the at least one repeater, the third repeater RT2 arranged at the end of the third replica circuit RP3 (i.e., arranged closest to the second merging node BN) can be enabled according to the mode selection signal EN (see FIG. 3).

[0091] The first delay time and the second delay time can be determined by the internal delay time generated in the paths through which the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb are transmitted. For example, the sum of the first delay time and the second delay time can be the same as the internal delay time. Although not shown in the drawings, the internal delay time includes the time from the point when the data strobe signal generated by the external device is input to the pad included in the semiconductor device 100 to the point when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 240.

[0092] The second data path 230 can include a third input circuit AMP3.

[0093] The third input circuit AMP3 can output the second differential data signals DQ2, / DQ2 as differential data signals DDQ, / DDQ to the merging node pairs TN, BN based on the differential common data signals CDQ, / CDQ. For example, the third input circuit AMP3 can include an amplifier.

[0094] The synchronization path 240 can include first to fourth comparison circuits C1 to C4 and first to fourth latch circuits LC1 to LC4.

[0095] The first comparison circuit C1 can perform a comparison operation while synchronized with the first data strobe signal DQSi for a first period of time. The first period of time may be related to the phase of the first data strobe signal DQSi. For example, the first period of time can correspond to one cycle of the first data strobe signal DQSi with reference to the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 compares the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and can generate a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 compares the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and can generate the first comparison data signal corresponding to the comparison result.

[0096] The second comparison circuit C2 can perform a comparison operation while synchronized with the second data strobe signal DQSq for a second period of time. The second period of time may be related to the phase of the second data strobe signal DQSq. For example, the second period of time can correspond to one cycle of the second data strobe signal DQSq with reference to the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 compares the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and can generate a second comparison data signal corresponding to the comparison result. The second comparison circuit C2 compares the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and can generate the second comparison data signal corresponding to the comparison result.

[0097] The third comparison circuit C3 can perform a comparison operation while being synchronized with the third data strobe signal DQSib for a third period of time. The third period of time may be related to the phase of the third data strobe signal DQSib. For example, the third period of time can correspond to one cycle of the third data strobe signal DQSib with reference to the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and generate a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and generate the third comparison data signal corresponding to the comparison result.

[0098] The fourth comparison circuit C4 can perform a comparison operation while being synchronized with the fourth data strobe signal DQSqb for a fourth period of time. The fourth period of time may be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth period of time can correspond to one cycle of the fourth data strobe signal DQSqb with reference to the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the first mode, and generate a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the positive data signal DDQ output via the first merging node TN and the negative data signal / DDQ output via the second merging node BN during the second mode, and generate the fourth comparison data signal corresponding to the comparison result.

[0099] The first to fourth comparison circuits C1 to C4 can each receive a comparison data signal output from an adjacent comparison circuit C1 or C2 or C3 or C4. However, the first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This is related to decision feedback equalization (DFE) operation.

[0100] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0101] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0102] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0103] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0104] In the embodiment of the present invention, the second data path 230 is described by way of example as including the third input circuit AMP3, but is not necessarily limited thereto, and can be designed in the same manner as the second data path 120 shown in FIG. 5. Accordingly, the connection structure between the second data path 230 and the synchronization path 240 can be designed in the same manner as the connection structure between the second data path 120 and the synchronization path 130 shown in FIG. 5.

[0105] FIG. 8 shows a block diagram of a semiconductor device 300 according to the third embodiment of the present invention.

[0106] As shown in FIG. 8, the semiconductor device 300 can include a data pad PD, a first data path 310, a second data path 320, and a synchronization path 330.

[0107] The data pad PD can be connected to an external device. The data pad PD can receive a data signal DQ output from the external device. The data pad PD can be connected to a supply terminal of a high voltage VTT via a termination resistor RZ.

[0108] The first data path 310 can be connected between the data pad PD and the synchronization path 330. The first data path 310 can generate first differential data signals DQ1 and / DQ1 in a first mode based on the data signal DQ and a reference signal VREF. For example, the first mode can be a low-speed mode to which a preset internal delay time is applied.

[0109] The second data path 320 can be connected between the data pad PD and the synchronization path 330. The second data path 320 can generate second differential data signals DQ2 and / DQ2 in a second mode based on the data signal DQ and the reference signal VREF. For example, the second mode can be a high-speed mode to which the internal delay time is not applied.

[0110] Although not well illustrated in the drawings, in the first mode, the first data path 310 can be enabled and the second data path 320 can be disabled. In the second mode, the first data path 310 can be disabled and the second data path 320 can be enabled.

[0111] The synchronization path 330 is based on the mode selection signal EN, the first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb, and the first and second differential data signals DQ1, / DQ1, DQ2, / DQ2. In the first mode and the second mode, among the first differential data signals DQ1, / DQ1 and the second differential data signals DQ2, / DQ2, the selected differential data signal can be output as the first to fourth data signals DQi, DQq, DQib, DQqb synchronized with the first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb. The first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb can have different phases from each other. For example, the first and second data strobe signals DQSi, DQSq can have a 90-degree phase difference, the second and third data strobe signals DQSq, DQSib can have a 90-degree phase difference, and the third and fourth data strobe signals DQSib, DQSqb can have a 90-degree phase difference.

[0112] FIG. 9 shows a block diagram showing an example of the first data path 310, the second data path 320, and the synchronization path 330 shown in FIG. 8.

[0113] As shown in FIG. 9, the first data path 310 can include a first input circuit AMP1, a first replica circuit RP1, a second replica circuit RP2, and a third replica circuit RP3.

[0114] The first input circuit AMP1 can generate an input data signal based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0115] The first replica circuit RP1 can delay the input data signal by a first delay time and output the delayed data signal to the branch node VN. For example, the first replica circuit RP1 can include at least one delay line (e.g., an RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0116] The second replica circuit RP2 can delay the delayed data signal by a second delay time and generate the first positive data signal DQ1 among the first differential data signals DQ1, / DQ1. For example, the second replica circuit RP2 can include at least one delay line (e.g., an RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0117] The third replica circuit RP3 can delay the delayed data signal by the second delay time and generate the first negative data signal / DQ1 among the first differential data signals DQ1, / DQ1. For example, the third replica circuit RP3 can include at least one delay line (e.g., an RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0118] The first delay time and the second delay time can be determined by the internal delay time generated in the paths through which the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb are transmitted. For example, the sum of the first delay time and the second delay time can be the same as the internal delay time. Although not shown in the drawings, the internal delay time can include the time from when the data strobe signal generated by the external device is input to the pad included in the semiconductor device 100 to when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 330.

[0119] The second data path 320 can include a second input circuit AMP2.

[0120] The second input circuit AMP2 can generate the second differential data signals DQ2 and / DQ2 based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier. Since the second input circuit AMP2 can be designed in the same manner as the second input circuit AMP2 shown in FIG. 4, a detailed description of the second input circuit AMP2 will be omitted.

[0121] The synchronization path 330 can include first and second selection circuits M1 and M2, first to fourth comparison circuits C1 to C4, and first to fourth latch circuits LC1 to LC4.

[0122] The first selection circuit M1 can generate the first differential data signals DQ1 and / DQ1 or the second differential data signals DQ2 and / DQ2 as the first differential selection data signal based on the mode selection signal EN.

[0123] The second selection circuit M2 can generate the first differential data signals DQ1 and / DQ1 or the second differential data signals DQ2 and / DQ2 as the second differential selection data signal based on the mode selection signal EN.

[0124] The first comparison circuit C1 can perform a comparison operation while synchronized with the first data strobe signal DQSi for a first period of time. The first period of time may be related to the phase of the first data strobe signal DQSi. For example, the first period of time can correspond to one cycle of the first data strobe signal DQSi based on the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 can compare the first differential selection data signal and generate a first comparison data signal corresponding to the comparison result in the first mode. The first comparison circuit C1 can compare the first differential selection data signal and generate the first comparison data signal corresponding to the comparison result in the second mode.

[0125] The second comparison circuit C2 can perform a comparison operation while synchronized with the second data strobe signal DQSq for a second period of time. The second period of time may be related to the phase of the second data strobe signal DQSq. For example, the second period of time can correspond to one cycle of the second data strobe signal DQSq based on the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 can compare the first differential selection data signal and generate a second comparison data signal corresponding to the comparison result in the first mode. The second comparison circuit C2 can compare the first differential selection data signal and generate the second comparison data signal corresponding to the comparison result in the second mode.

[0126] The third comparison circuit C3 can perform a comparison operation while being synchronized with the third data strobe signal DQSib for a third period of time. The third period of time may be related to the phase of the third data strobe signal DQSib. For example, the third period of time can correspond to one cycle of the third data strobe signal DQSib with reference to the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the second differential selection data signals during the first mode and generate a third comparison data signal corresponding to the comparison result. The third comparison circuit C3 can compare the second differential selection data signals during the second mode and generate the third comparison data signal corresponding to the comparison result.

[0127] The fourth comparison circuit C4 can perform a comparison operation while being synchronized with the fourth data strobe signal DQSqb for a fourth period of time. The fourth period of time may be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth period of time can correspond to one cycle of the fourth data strobe signal DQSqb with reference to the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the second differential selection data signals during the first mode and generate a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the second differential selection data signals during the second mode and generate the fourth comparison data signal corresponding to the comparison result.

[0128] The first to fourth comparison circuits C1 to C4 can each receive a comparison data signal output from an adjacent comparison circuit C1 or C2 or C3 or C4. However, the first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This is related to a decision feedback equalization (DFE) operation.

[0129] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0130] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0131] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0132] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0133] FIG. 10 shows a circuit diagram showing an example of the first selection circuit M1 included in the synchronization path 330 shown in FIG. 9.

[0134] As shown in FIG. 10, the first selection circuit M1 can include a source part MC1, a sink part MC2, a first selection part MC3, and a second selection part MC4.

[0135] The source part MC1 can be connected between the supply terminal of the first voltage and the output terminals + and -. For example, the source part MC1 can include a first and a second resistor. The first resistor can be connected between the supply terminal of the first voltage and the first output terminal +. The second resistor can be connected between the supply terminal of the first voltage and the second output terminal -.

[0136] The sink unit MC2 can be connected between the connection node NN and the supply terminal of the second voltage. For example, the sink unit MC2 can include a first transistor and a second transistor connected in series. The first transistor can be connected between the connection node NN and the sink node and can receive a bias voltage VBIAS at the gate terminal. The second transistor can be connected between the sink node and the supply terminal of the second voltage and can receive an enable signal PG_EN at the gate terminal.

[0137] The first selection unit MC3 can be enabled in the first mode based on the inverted signal / EN of the mode selection signal EN and can be disabled in the second mode.

[0138] The second selection unit MC4 can be enabled in the second mode based on the mode selection signal EN and can be disabled in the first mode.

[0139] On the other hand, since the second selection circuit M2 included in the synchronization path 330 shown in FIG. 9 can be designed in the same manner as the first selection circuit M1 shown in FIG. 10, a detailed description of the second selection circuit M2 will be omitted.

[0140] FIG. 11 is a block configuration diagram showing another example of the first data path 310, the second data path 320, and the synchronization path 330 shown in FIG. 8.

[0141] As shown in FIG. 11, the first data path 310 can include a first input circuit AMP1, a first replica circuit RP1, a second replica circuit RP2, and a third replica circuit RP3.

[0142] The first input circuit AMP1 can generate an input data signal based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0143] The first replica circuit RP1 can delay the input data signal by a first delay time and output the delayed data signal to the branch node VN. For example, the first replica circuit RP1 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0144] The second replica circuit RP2 can delay the delayed data signal by a second delay time and generate the first positive data signal DQ1 among the first differential data signals DQ1, / DQ1. For example, the second replica circuit RP2 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0145] The third replica circuit RP3 can delay the delayed data signal by the second delay time and generate the first negative data signal / DQ1 among the first differential data signals DQ1, / DQ1. For example, the third replica circuit RP3 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0146] The first delay time and the second delay time can be determined by the internal delay time generated in the paths through which the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb are transmitted. For example, the sum of the first delay time and the second delay time can be the same as the internal delay time. Although not shown in the drawings, the internal delay time can include the time from when the data strobe signal generated by the external device is input to the pad included in the semiconductor device 100 to when the first to fourth data strobe signals DQSi, DQSq, DQSib, and DQSqb based on the data strobe signal are input to the synchronization path 330.

[0147] The second data path 320 can include second to fourth input circuits AMP2, AMP3, and AMP4.

[0148] The second input circuit AMP2 can output differential input data signals to differential node pairs DTN and DBN based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier.

[0149] The third input circuit AMP3 can generate the second differential data signals DQ2 and / DQ2 based on the differential input data signals. For example, the third input circuit AMP3 can include an amplifier.

[0150] The fourth input circuit AMP3 can generate the third differential data signals DQ2’ and / DQ2’ based on the differential input data signals. For example, the fourth input circuit AMP4 can include an amplifier.

[0151] The second to fourth input circuits AMP2, AMP3, and AMP4 can be designed to be the same as or different from the second input circuit AMP2 shown in FIG. 4, respectively.

[0152] The synchronization path 330 can include a first and a second selection circuit M1, M2, a first to a fourth comparison circuit C1 to C4, and a first to a fourth latch circuit LC1 to LC4.

[0153] The first selection circuit M1 can generate, based on the mode selection signal EN, one of the first differential data signals DQ1, / DQ1 and the second differential data signals DQ2, / DQ2 as a first differential selection data signal. The first selection circuit M1 can be designed in the same manner as the first selection circuit M1 shown in FIG. 10.

[0154] The second selection circuit M2 can generate, based on the mode selection signal EN, one of the first differential data signals DQ1, / DQ1 and the third differential data signals DQ2’, / DQ2’ as a second differential selection data signal. The second selection circuit M2 can be designed in the same manner as the first selection circuit M1 shown in FIG. 10.

[0155] The first comparison circuit C1 can perform a comparison operation while synchronized with the first data strobe signal DQSi for a first period of time. The first period of time may be related to the phase of the first data strobe signal DQSi. For example, the first period of time can correspond to one cycle of the first data strobe signal DQSi based on the rising edge of the first data strobe signal DQSi. The first comparison circuit C1 can compare the first differential selection data signal in the first mode and generate a first comparison data signal corresponding to the comparison result. The first comparison circuit C1 can compare the first differential selection data signal in the second mode and generate the first comparison data signal corresponding to the comparison result.

[0156] The second comparison circuit C2 can perform a comparison operation while synchronized with the second data strobe signal DQSq for a second period of time. The second period of time may be related to the phase of the second data strobe signal DQSq. For example, the second period of time can correspond to one cycle of the second data strobe signal DQSq with reference to the rising edge of the second data strobe signal DQSq. The second comparison circuit C2 can compare the first differential selection data signal and generate a second comparison data signal corresponding to the comparison result in the first mode. The second comparison circuit C2 can compare the first differential selection data signal and generate the second comparison data signal corresponding to the comparison result in the second mode.

[0157] The third comparison circuit C3 can perform a comparison operation while synchronized with the third data strobe signal DQSib for a third period of time. The third period of time may be related to the phase of the third data strobe signal DQSib. For example, the third period of time can correspond to one cycle of the third data strobe signal DQSib with reference to the rising edge of the third data strobe signal DQSib. The third comparison circuit C3 can compare the second differential selection data signal and generate a third comparison data signal corresponding to the comparison result in the first mode. The third comparison circuit C3 can compare the second differential selection data signal and generate the third comparison data signal corresponding to the comparison result in the second mode.

[0158] The fourth comparison circuit C4 can perform a comparison operation while synchronized with the fourth data strobe signal DQSqb for a fourth period of time. The fourth period of time may be related to the phase of the fourth data strobe signal DQSqb. For example, the fourth period of time can correspond to one cycle of the fourth data strobe signal DQSqb with reference to the rising edge of the fourth data strobe signal DQSqb. The fourth comparison circuit C4 can compare the second differential selection data signal during the first mode and generate a fourth comparison data signal corresponding to the comparison result. The fourth comparison circuit C4 can compare the second differential selection data signal during the second mode and generate the fourth comparison data signal corresponding to the comparison result.

[0159] The first to fourth comparison circuits C1 to C4 can each receive a comparison data signal output from an adjacent comparison circuit C1 or C2 or C3 or C4. However, the first comparison circuit C1 can receive the fourth comparison data signal output from the fourth comparison circuit C4. This is related to a decision feedback equalization (DFE) operation.

[0160] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0161] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0162] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0163] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0164] FIG. 12 is a block configuration diagram showing still another example of the first data path 310, the second data path 320, and the synchronization path 330 shown in FIG. 8.

[0165] As shown in FIG. 12, the first data path 310 can include a first input circuit AMP1, a first replica circuit RP1, a second replica circuit RP2, and a third replica circuit RP3.

[0166] The first input circuit AMP1 can generate an input data signal based on the data signal DQ and the reference signal VREF. For example, the first input circuit AMP1 can include an amplifier.

[0167] The first replica circuit RP1 can delay the input data signal by a first delay time and output the delayed data signal to the branch node VN. For example, the first replica circuit RP1 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0168] The second replica circuit RP2 can delay the delayed data signal by a second delay time and generate a first positive data signal DQ1 among the first differential data signals DQ1 and / DQ1. For example, the second replica circuit RP2 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0169] The third replica circuit RP3 can delay the delay data signal by the amount of the second delay time and generate the first negative data signal / DQ1 among the first differential data signals DQ1 and / DQ1. For example, the third replica circuit RP3 can include at least one delay line (e.g., RC line) and at least one repeater. The at least one delay line and the at least one repeater can be connected in series.

[0170] The first delay time and the second delay time can be determined by the internal delay time generated in the path through which the first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb are transmitted. For example, the sum between the first delay time and the second delay time can be the same as the internal delay time. Although not shown in the drawings, the internal delay time can include the time from the point when the data strobe signal generated by the external device is input to the pad included in the semiconductor device 100 to the point when the first to fourth data strobe signals DQSi, DQSq, DQSib, DQSqb based on the data strobe signal are input to the synchronization path 330.

[0171] The second data path 320 can include a second input circuit AMP2.

[0172] The second input circuit AMP2 can generate a second differential data signal DQ2 and / DQ2 based on the data signal DQ and the reference signal VREF. For example, the second input circuit AMP2 can include an amplifier.

[0173] The synchronization path 330 can include first to fourth integrated circuits X1 to X4 and first to fourth latch circuits LC1 to LC4.

[0174] The first integrated circuit X1 can generate a first comparison data signal by selecting one of the first differential data signals DQ1 and / DQ1 and the second differential data signals DQ2 and / DQ2 during a first time based on a mode selection signal EN and a first data strobe signal DQSi, and at the same time, comparing the positive data signal and the negative data signal included in the selected differential data signal. The first time may be related to the phase of the first data strobe signal DQSi.

[0175] The second integrated circuit X2 can generate a second comparison data signal by selecting one of the first differential data signals DQ1 and / DQ1 and the second differential data signals DQ2 and / DQ2 during a second time based on a mode selection signal EN and a second data strobe signal DQSq, and at the same time, comparing the positive data signal and the negative data signal included in the selected differential data signal. The second time may be related to the phase of the second data strobe signal DQSq.

[0176] The third integrated circuit X3 can generate a third comparison data signal by selecting one of the first differential data signals DQ1 and / DQ1 and the second differential data signals DQ2 and / DQ2 during a third time based on a mode selection signal EN and a third data strobe signal DQSib, and at the same time, comparing the positive data signal and the negative data signal included in the selected differential data signal. The third time may be related to the phase of the third data strobe signal DQSib. The fourth integrated circuit X4 can generate a fourth comparison data signal by selecting one of the first differential data signals DQ1 and / DQ1 and the second differential data signals DQ2 and / DQ2 during a fourth time based on a mode selection signal EN and a fourth data strobe signal DQSqb, and at the same time, comparing the positive data signal and the negative data signal included in the selected differential data signal. The fourth time may be related to the phase of the fourth data strobe signal DQSqb.

[0177] The first latch circuit LC1 can latch the first comparison data signal as a first internal data signal DQi. For example, the first latch circuit LC1 can include an SR latch.

[0178] The second latch circuit LC2 can latch the second comparison data signal as a second internal data signal DQq. For example, the second latch circuit LC2 can include an SR latch.

[0179] The third latch circuit LC3 can latch the third comparison data signal as a third internal data signal DQib. For example, the third latch circuit LC3 can include an SR latch.

[0180] The fourth latch circuit LC4 can latch the fourth comparison data signal as a fourth internal data signal DQqb. For example, the fourth latch circuit LC4 can include an SR latch.

[0181] In the embodiment of the present invention, the second data path 320 is described by way of example as including a second input circuit AMP2, but is not necessarily limited thereto, and can be designed in the same manner as the second data path 320 shown in FIG. 9. Thereby, the connection structure between the second data path 320 and the synchronization path 330 can be designed to be similar to the connection structure between the second data path 320 and the synchronization path 330 shown in FIG. 9.

[0182] FIG. 13 shows a circuit diagram showing an example of the first integrated circuit X1 shown in FIG. 12. Since the first to fourth integrated circuits X1 to X4 can be designed in the same manner, the first integrated circuit X1 will be described representatively below.

[0183] As shown in FIG. 13, the first integrated circuit X1 can include a common source circuit SOC, a first sink circuit SK1, and a second sink circuit SK2.

[0184] The common source circuit SOC can be connected between the supply terminal of the first voltage and the output terminal pair OT1, OT2. When the first data strobe signal DQSi is at a low logic level, the common source circuit SOC can reset (reset or pre-charge) the output terminal pair OT1, OT2 to the first voltage (e.g., VDD).

[0185] The first sink circuit SK1 can be connected between the output terminal pair OT1, OT2 and the supply terminal of the second voltage. The first sink circuit SK1 can be enabled during the first mode (i.e., the low-speed mode) based on the first mode signal MD_M and can be disabled during the second mode (i.e., the high-speed mode). The first sink circuit SK1 can output differential data signals COUT, TOUT corresponding to the first differential data signals DQ1, / DQ1 to the output terminal pair OT1, OT2 based on the first data strobe signal DQSi. The differential data signals COUT, TOUT can correspond to the result of comparing the positive data signal DQ1 and the negative data signal / DQ1 included in the first differential data signals DQ1, / DQ1.

[0186] The second sink circuit SK2 can be connected between the output terminal pair OT1, OT2 and the supply terminal of the second voltage. The second sink circuit SK2 can be enabled during the second mode based on the second mode signal MD_U and can be disabled during the first mode. The second sink circuit SK2 can output differential data signals COUT, TOUT corresponding to the second differential data signals DQ2, / DQ2 to the output terminal pair OT1, OT2 based on the first data strobe signal DQSi. The differential data signals COUT, TOUT can correspond to the result of comparing the positive data signal DQ2 and the negative data signal / DQ2 included in the second differential data signals DQ2, / DQ2. When generating the differential data signals COUT, TOUT, the second sink circuit SK2 uses the equalization control signal KDFE <m:0>Based on the previous differential data signals LAT_PRE and / LAR_PRE, DFE (decision feedback equalization) operation can be performed.

[0187] The generation circuit GNR can generate differential comparison data signals LAT and / LAT based on the differential data signals COUT and TOUT. Among the positive comparison data signal LAT and the negative comparison data signal / LAT included in the differential comparison data signals LAT and / LAT, either one can be the first comparison data signal.

[0188] In an embodiment of the present invention, the common source circuit SOC, the first sink circuit SK1, the second sink circuit SK2, and the generation circuit GNR can be configured such that a comparison circuit based on a double-tail latch and a circuit for the DFE are integrated. However, the embodiments of the present invention are not necessarily limited to this, and can have a configuration in which various forms of comparison circuits (e.g., a comparison circuit based on Strong-arm, etc.) and a circuit for the DFE are integrated.

[0189] The control circuit CTR can generate a first mode signal MD_M and a second mode signal MD_U based on a mode selection signal EN and an operation enable signal EN_DIN. For example, the control circuit CTR can activate the first mode signal MD_M and deactivate the second mode signal MD_U in the first mode, deactivate the first mode signal MD_M and activate the second mode signal MD_U in the second mode, and deactivate both the first mode signal MD_M and the second mode signal MD_U in a specific mode. Here, the operation enable signal EN_DIN can be a write enable signal corresponding to a write mode, and the specific mode can be at least one mode excluding the write mode.

[0190] In the embodiments of the present invention, the control circuit CTR has been described by way of example as being included in each of the first to fourth integrated circuits X1 to X4. However, it is not necessarily limited thereto, and the first to fourth integrated circuits X1 to X4 can be designed to share one control circuit CTR.

[0191] According to such embodiments of the present invention and the like, there is an advantage that various interface modes can be supported.

[0192] The technical idea of the present invention has been specifically described by the above embodiments. However, it should be noted that the embodiments described above are for the purpose of explanation and not for limitation. Also, those of ordinary skill in the technical field of the present invention will be able to understand that various embodiments are possible through various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

Explanation of Reference Numerals

[0193] 100 Semiconductor device 110 First data path 120 Second data path 130 Synchronization path

Claims

1. A data pad and At least one merging node; a first data path connected between the data pad and the at least one merge node for outputting a first data signal to the at least one merge node in a first mode based on a data signal, a reference signal, and a mode selection signal; a second data path connected between the data pad and the at least one merged node for outputting a second data signal to the at least one merged node in a second mode based on the data signal, the reference signal, and the mode selection signal; a synchronization path coupled to the at least one merging node for outputting, in the first mode or the second mode, the first data signal or the second data signal as a data signal synchronized to at least one data strobe signal; A semiconductor device comprising:

2. The first data path includes: a first input circuit for generating an input data signal based on the data signal and the reference signal; a first replica circuit for delaying the input data signal by a first delay time and outputting the delayed data signal to a branch node; a second replica circuit for delaying the delayed data signal by a second delay time and outputting a first positive data signal corresponding to the first data signal to a first merging node; a third replica circuit for delaying the delayed data signal by the second delay time and outputting a first negative data signal corresponding to the first data signal to a second merging node; The semiconductor device according to claim 1 .

3. The second replica circuit comprises: a first pull-up driver connected between a first voltage supply end and a first supply node, the first pull-up driver receiving a first drive data signal corresponding to the delayed data signal; a first select driver connected between the first supply node and a first output node, the first select driver receiving the mode select signal; a second select driver connected between the first output node and a second supply node, the second select driver receiving an inverse of the mode select signal; a first pull-down driver connected between the second supply node and a supply end of a second voltage and receiving the first drive data signal; The semiconductor device according to claim 2 .

4. The third replica circuit comprises: a second pull-up driver connected between the first voltage supply end and a third supply node, the second pull-up driver receiving a second drive data signal corresponding to the delayed data signal; a third select driver connected between the third supply node and a second output node, the third select driver receiving the mode select signal; a fourth select driver connected between the second output node and a fourth supply node, the fourth select driver receiving an inverse of the mode select signal; a second pull-down driver connected between the fourth supply node and a supply end of a second voltage and receiving the second drive data signal; The semiconductor device according to claim 2 .

5. 3. The semiconductor device according to claim 2, wherein the first delay time and the second delay time are determined by an internal delay time occurring in a path along which the at least one data strobe signal is transmitted.

6. The second data path is 3. The semiconductor device according to claim 2, further comprising a second input circuit for outputting a second positive data signal and a second negative data signal corresponding to the second data signal to the first merged node and the second merged node, respectively, based on the data signal and the reference signal.

7. The second input circuit is a source driver connected between a supply end of the first voltage and a common node to receive a bias voltage; a first input driver connected between the common node and a first node for receiving the data signal; a fifth select driver connected between the first node and the second merging node, the fifth select driver receiving an inverse of the mode select signal; a second input driver connected between the common node and a second node for receiving the reference signal; a sixth select driver connected between the second node and the first merging node, the sixth select driver receiving the inverse of the mode select signal; a first sink driver connected between the second merging node and a supply end of a second voltage and configured to receive a control signal; a second sink driver connected between the first merging node and a supply end of the second voltage and configured to receive the control signal; a logic circuit for generating the control signal based on the mode selection signal and an enable signal; The semiconductor device according to claim 6 .

8. The synchronization path includes: at least one comparison circuit for comparing the first positive data signal or the second positive data signal output via the first merging node with the first negative data signal or the second negative data signal output via the second merging node based on the at least one data strobe signal, and generating at least one comparison data signal corresponding to the comparison result; at least one latch circuit for latching the at least one comparison data signal as the synchronized data signal; The semiconductor device according to claim 6 .

9. 9. The semiconductor device according to claim 8, wherein the at least one comparison circuit performs a decision feedback equalization (DFE) operation when generating the at least one comparison data signal.

10. The first data path includes: a first input circuit for generating an input data signal based on the data signal and the reference signal; a first replica circuit for delaying the input data signal by a first delay time and outputting the delayed data signal to a branch node; a second replica circuit for delaying the delayed data signal by a second delay time and outputting a first positive data signal corresponding to the first data signal to a first merging node and a third merging node; a third replica circuit for delaying the delayed data signal by the second delay time and outputting a first negative data signal corresponding to the first data signal to a second merging node and a fourth merging node; The semiconductor device according to claim 1 .

11. The second data path is a second input circuit for outputting a positive input data signal and a negative input data signal to a first node and a second node, respectively, based on the data signal and the reference signal; a first amplifier circuit for outputting a second positive data signal and a second negative data signal corresponding to the second data signal to the first merging node and the second merging node, respectively, based on the positive input data signal and the negative input data signal; a second amplifier circuit for outputting a third positive data signal and a third negative data signal corresponding to the second data signal to the third merging node and the fourth merging node, respectively, based on the positive input data signal and the negative input data signal; The semiconductor device according to claim 10 .

12. The synchronization path includes: at least one first comparison circuit for comparing the first positive data signal or the second positive data signal output via the first merging node with the first negative data signal or the second negative data signal output via the second merging node based on the at least one data strobe signal, and generating at least one first comparison data signal corresponding to the comparison result; at least one second comparison circuit for comparing the first positive data signal or the second positive data signal output via the third merging node with the first negative data signal or the second negative data signal output via the fourth merging node based on the at least one data strobe signal, and generating at least one second comparison data signal corresponding to the comparison result; a plurality of latch circuits for latching the at least one first comparison data signal and the at least one second comparison data signal as the synchronized data signal; The semiconductor device according to claim 11 , comprising:

13. 13. The semiconductor device according to claim 12, wherein the at least one first comparison circuit and the at least one second comparison circuit each perform a decision feedback equalization (DFE) operation when generating the at least one first comparison data signal and the at least one second comparison data signal.

14. A data pad and At least one common node; a common path connected between the data pad and the at least one common node for outputting a common data signal to the at least one common node based on a data signal and a reference signal; At least one merging node; a first data path connected between the at least one common node and the at least one merging node for outputting a first data signal to the at least one merging node in a first mode based on the common data signal and a mode selection signal; a second data path connected between the at least one common node and the at least one merging node for outputting a second data signal to the at least one merging node in a second mode based on the common data signal and the mode selection signal; a synchronization path coupled to the at least one merging node for outputting, in the first mode or the second mode, the first data signal or the second data signal as a data signal synchronized to at least one data strobe signal; A semiconductor device comprising:

15. The first data path includes: a first input circuit for generating an input data signal based on the common data signal and the mode selection signal; a first replica circuit for delaying the input data signal by a first delay time and outputting the delayed data signal to a branch node; a second replica circuit for delaying the delayed data signal by a second delay time and outputting a first positive data signal corresponding to the first data signal to a first merging node; a third replica circuit for delaying the delayed data signal by the second delay time and outputting a first negative data signal corresponding to the first data signal to a second merging node; The semiconductor device according to claim 14 , comprising:

16. the second replica circuit; a first pull-up driver connected between a first voltage supply end and a first supply node, the first pull-up driver receiving a first drive data signal corresponding to the delayed data signal; a first select driver connected between the first supply node and a first output node, the first select driver receiving the mode select signal; a second select driver connected between the first output node and a second supply node, the second select driver receiving an inverse of the mode select signal; a first pull-down driver connected between the second supply node and a supply end of a second voltage and receiving the first drive data signal; The semiconductor device according to claim 15 , comprising:

17. the third replica circuit; a second pull-up driver connected between a supply end of the first voltage and a third supply node, the second pull-up driver receiving a second drive data signal corresponding to the delayed data signal; a third select driver connected between the third supply node and a second output node, the third select driver receiving the mode select signal; a fourth select driver connected between the second output node and a fourth supply node, the fourth select driver receiving an inverse of the mode select signal; a second pull-down driver connected between the fourth supply node and a supply end of a second voltage and receiving the second drive data signal; The semiconductor device according to claim 15 , comprising:

18. 16. The semiconductor device according to claim 15, wherein the first delay time and the second delay time are determined by an internal delay time occurring in a path along which the at least one data strobe signal is transmitted.

19. The second data path is 16. The semiconductor device according to claim 15, further comprising a second input circuit for outputting a second positive data signal and a second negative data signal corresponding to the second data signal to the first merged node and the second merged node, respectively, based on the common data signal and the mode selection signal.

20. The second input circuit is a source driver connected between a supply end of the first voltage and a common node to receive a bias voltage; a first input driver connected between the common node and a first node for receiving a positive data signal of a differential data signal corresponding to the common data signal; a fifth select driver connected between the first node and the second merging node, the fifth select driver receiving an inverse of the mode select signal; a second input driver connected between the common node and a second node to receive a negative data signal of the differential data signals; a sixth select driver connected between the second node and the first merging node, the sixth select driver receiving the inverse of the mode select signal; a first sink driver connected between the second merging node and a supply end of a second voltage and configured to receive a control signal; a second sink driver connected between the first merging node and a supply end of the second voltage and configured to receive the control signal; a logic circuit for generating the control signal based on the mode selection signal and an enable signal; The semiconductor device according to claim 19 .

21. The synchronization path includes: at least one comparison circuit for comparing the first positive data signal or the second positive data signal output via the first merging node with the first negative data signal or the second negative data signal output via the second merging node based on the at least one data strobe signal, and generating at least one comparison data signal corresponding to the comparison result; at least one latch circuit for latching the at least one comparison data signal as the synchronized data signal; The semiconductor device according to claim 19 .

22. 22. The semiconductor device according to claim 21, wherein the at least one comparison circuit performs a decision feedback equalization (DFE) operation when generating the at least one comparison data signal.

23. a first data path for generating a first data signal during a first mode based on the data signal and a reference signal; a second data path for generating a second data signal during a second mode based on the data signal and the reference signal; a synchronization path for outputting a selected one of the first and second data signals as a data signal synchronized with the at least one data strobe signal in the first and second modes based on a mode selection signal, at least one data strobe signal, and the first and second data signals; A semiconductor device comprising:

24. The first data path includes: a first input circuit for generating an input data signal based on the data signal and the reference signal; a first replica circuit for delaying the input data signal by a first delay time and outputting the delayed data signal to a branch node; a second replica circuit for delaying the delayed data signal by a second delay time to generate a first positive data signal corresponding to the first data signal; a third replica circuit for delaying the delayed data signal by the second delay time to generate a first negative data signal corresponding to the first data signal; The semiconductor device according to claim 23 , comprising:

25. 25. The semiconductor device according to claim 24, wherein the first delay time and the second delay time are determined by an internal delay time occurring in a path along which the at least one data strobe signal is transmitted.

26. The second data path is a second input circuit for generating an input data signal based on the data signal and the reference signal; a first amplifier circuit for generating a third data signal corresponding to the second data signal based on the input data signal; a second amplifier circuit for generating a fourth data signal corresponding to the second data signal based on the input data signal; The semiconductor device according to claim 23 , comprising:

27. The synchronization path includes: a first selection circuit for outputting one of the first data signal and the third data signal as a first selection data signal based on the mode selection signal; at least one first comparison circuit for comparing a positive signal and a negative signal included in the first selection data signal based on the at least one data strobe signal and generating at least one first comparison data signal corresponding to the comparison result; a second selection circuit for outputting one of the first data signal and the fourth data signal as a second selection data signal based on the mode selection signal; at least one second comparison circuit for comparing a positive signal and a negative signal included in the second selection data signal based on the at least one data strobe signal and generating at least one second comparison data signal corresponding to the comparison result; a plurality of latch circuits for latching the at least one first comparison data signal and the at least one second comparison data signal as the synchronized data signal; The semiconductor device according to claim 26 , comprising:

28. 28. The semiconductor device according to claim 27, wherein the at least one first comparison circuit and the at least one second comparison circuit each perform a decision feedback equalization (DFE) operation when generating the at least one first comparison data signal and the at least one second comparison data signal.

29. The synchronization path includes: at least one integrated circuit for selecting one of the first data signal and the second data signal based on the mode selection signal and the at least one data strobe signal, and generating at least one comparison data signal by comparing a positive signal and a negative signal included in the selected data signal; at least one latch circuit for latching the at least one comparison data signal as the synchronized data signal; The semiconductor device according to claim 23 , comprising:

30. The at least one integrated circuit comprises: a common source circuit connected between a supply end of the first voltage and the pair of output nodes; a first sink circuit connected between the output node pair and a supply end of a second voltage, the first sink circuit being enabled in the first mode based on a first mode signal and disabled in the second mode, for outputting a differential data signal corresponding to the first data signal via the output node pair based on the at least one data strobe signal; a second sink circuit connected between the output node pair and a supply end of the second voltage, the second sink circuit being enabled in the second mode based on a second mode signal and disabled in the first mode, for outputting the differential data signal corresponding to the second data signal via the output node pair based on the at least one data strobe signal; a generation circuit for generating the at least one comparison signal based on the differential data signal; The semiconductor device according to claim 29 .

31. 31. The semiconductor device according to claim 30, wherein the second sink circuit performs a decision feedback equalization (DFE) operation based on at least one equalization control signal and a previous differential data signal when generating the differential data signal.

32. The at least one integrated circuit comprises:

31. The semiconductor device according to claim 30, further comprising a control circuit for generating the first mode signal and the second mode signal based on the mode selection signal and an operation enable signal.

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