Display panel and manufacturing method for the same

Abstract

To provide a display panel with improved contact reliability.SOLUTION: A display panel includes a driving element layer including a pixel driving unit, a light-emitting element including a first electrode disposed on the driving element layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a pixel defining film disposed on the driving element layer and defining a light-emitting opening part to expose at least a part of the first electrode and a group surrounding the light-emitting opening part, and a coupling electrode disposed on the pixel defining film and electrically coupled to the pixel driving unit and the second electrode.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display panel with improved contact reliability and a method for manufacturing the display panel.

Background Art

[0002] Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation devices, game consoles, etc. are equipped with a display panel for displaying images. The display panel includes a light-emitting element and a circuit for driving the light-emitting element. The light-emitting element included in the display panel emits light according to the voltage applied from the circuit to generate an image. Research on the connection between the light-emitting element and the circuit is in progress to improve the reliability of the display panel.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a display panel with improved contact reliability.

[0005] Another object of the present invention is to provide a method for manufacturing a display panel with improved contact reliability.

Means for Solving the Problems

[0006] The display panel according to an embodiment of the present invention includes a driving element layer including a pixel driving unit, a light emitting element disposed on the driving element layer and including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a pixel definition film disposed on the driving element layer and defining a light emitting opening for exposing at least a part of the first electrode and a groove surrounding the light emitting opening, and a connection electrode disposed on the pixel definition film and electrically connected to the pixel driving unit and the second electrode.

[0007] Each of the light emitting element, the pixel driving unit, and the connection electrode is provided in plurality. The plurality of connection electrodes electrically connect the plurality of light emitting elements and the plurality of pixel driving units respectively. A gap between a plurality of adjacent connection electrodes among the plurality of connection electrodes can overlap with the groove.

[0008] The connection electrode includes a first edge and a second edge surrounding the first edge, and the second edge can overlap with the groove.

[0009] The second electrode and the connection electrode can be connected in a region adjacent to the groove.

[0010] The connection electrode includes a chip portion protruding from an end of the groove, and the connection electrode can partially overlap with the groove of the pixel definition film in a plane.

[0011] The second electrode and the connection electrode can be connected at the chip portion.

[0012] A through hole is further defined in the pixel definition film, and the connection electrode can be connected to the pixel driving unit through the through hole.

[0013] The connection electrode includes a first connection electrode layer disposed on the pixel definition film and a second connection electrode layer disposed on the first connection electrode layer, and the second connection electrode layer can cover the first connection electrode layer.

[0014] The intermediate layer is disposed on the second connection electrode layer, the second electrode is disposed on the intermediate layer, and the second electrode can be connected to the second connection electrode layer at the chip portion.

[0015] A first divided pattern containing the same substance as the second connection electrode layer, a second divided pattern containing the same substance as the intermediate layer, and a third divided pattern containing the same substance as the second electrode can be disposed in the groove.

[0016] The first divided pattern and the third divided pattern can be electrically connected.

[0017] The connection electrode includes a first connection electrode layer disposed on the pixel definition film, and the intermediate layer can cover the first connection electrode layer.

[0018] A first divided pattern containing the same substance as the intermediate layer and a second divided pattern containing the same substance as the second electrode can be disposed in the groove.

[0019] The pixel definition film includes a first pixel definition film portion and a second pixel definition film portion formed on the first pixel definition film portion. The first pixel definition film portion and the second pixel definition film portion are integrally formed, and the groove can be defined in the second pixel definition film portion.

[0020] A display panel according to an embodiment of the present invention can include a driving element layer including a pixel driving portion, a light-emitting element disposed on the driving element layer and including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a pixel definition film disposed on the driving element layer and having a groove defined by removing at least a part in the thickness direction, and a connection electrode disposed on the pixel definition film and including a chip portion protruding from the end of the groove.

[0021] The pixel definition film further defines a light-emitting opening for exposing at least a part of the first electrode, and the groove can surround the light-emitting opening.

[0022] The connecting electrode is electrically connected to the pixel driving unit and the second electrode, and the second electrode and the connecting electrode can be connected at the chip portion.

[0023] A through hole is further defined in the pixel defining film, and the connecting electrode can be connected to the pixel driving unit through the through hole.

[0024] Each of the light emitting element, the pixel driving unit, and the connecting electrode is provided in plurality, and the plurality of connecting electrodes electrically connect the plurality of light emitting elements and the plurality of pixel driving units respectively, and a gap between a plurality of adjacent connecting electrodes among the plurality of connecting electrodes can overlap with the groove.

[0025] The connecting electrode includes a first edge and a second edge surrounding the first edge, and the second edge can overlap with the groove.

[0026] The connecting electrode includes a first connecting electrode layer disposed on the pixel defining film and a second connecting electrode layer disposed on the first connecting electrode layer, the second connecting electrode layer covers the first connecting electrode layer, and the second electrode can be connected to the second connecting electrode layer at the chip portion.

[0027] A first divided pattern including the same material as the second connecting electrode layer, a second divided pattern including the same material as the intermediate layer, and a third divided pattern including the same material as the second electrode are disposed in the groove, and the first divided pattern and the third divided pattern can be electrically connected.

[0028] The connecting electrode includes a first connecting electrode layer disposed on the pixel defining film, and the intermediate layer can cover the first connecting electrode layer.

[0029] A first divided pattern including the same material as the intermediate layer and a second divided pattern including the same material as the second electrode can be disposed in the groove.

[0030] The pixel definition film includes a first pixel definition film portion and a second pixel definition film portion formed on the first pixel definition film portion. The first pixel definition film portion and the second pixel definition film portion are integrally formed, and the groove can be defined in the second pixel definition film portion.

[0031] A method for manufacturing a display panel according to an embodiment of the present invention includes preparing a preliminary display panel including a base layer, a driving element layer disposed on the base layer, and a pixel definition film disposed on the driving element layer; depositing a first connection electrode layer on the preliminary display panel; etching the first connection electrode layer and a part of the pixel definition film to form a groove in the pixel definition film that overlaps with a part of the first connection electrode layer; etching the first connection electrode layer to form a connection electrode; and forming an intermediate layer and a cathode on the connection electrode and the pixel definition film.

[0032] The method for manufacturing the display panel may further include forming a chip portion defined at the end of the first connection electrode layer.

[0033] The method may further include depositing a second connection electrode layer on the first connection electrode layer and forming chip portions defined at the ends of the first connection electrode layer and the second connection electrode layer. The step of forming the connection electrode may include etching the second connection electrode layer.

[0034] The pixel definition film includes a first pixel definition film portion and a second pixel definition film portion formed on the first pixel definition film portion. The first pixel definition film portion and the second pixel definition film portion are integrally formed, and the groove can be defined in the second pixel definition film portion.

Advantages of the Invention

[0035] It is possible to provide a display panel with improved contact reliability and a method for manufacturing the same.

Brief Description of the Drawings

[0036]

Figure 1

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Mode for Carrying Out the Invention

[0037] In this specification, when a predetermined component (or region, layer, part, etc.) is described as being "on", "connected to", or "coupled to" another component, it means that it can be directly disposed / connected / coupled on the other component, or a third component can also be disposed between them.

[0038] The same reference numerals denote the same components. Also, in the drawings, the thickness, ratio, and dimensions of the components are exaggerated for the efficient explanation of the technical content. "And / or" includes all combinations of one or more that can be defined by the related components.

[0039] Terms such as first, second, etc. can be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, if it does not deviate from the scope of the rights of the present invention, the first component can be referred to as the second component, and similarly, the second component can also be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0040] Also, terms such as "below", "lower side", "above", "upper side", etc. are used to explain the association relationship of the components illustrated in the drawings. The terms are relative concepts and are explained based on the directions shown in the drawings.

[0041] Terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should not be construed as precluding the presence or possibility of addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Also, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and here, unless explicitly defined, should not be interpreted in an overly idealized or formal sense.

[0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0044] FIG. 1 is a block diagram of a display device DD according to an embodiment of the present invention.

[0045] Referring to FIG. 1, the display device DD can include a display panel DP, panel driving units SDC, EDC, DDC, a power supply unit PWS, and a timing control unit TC. In this embodiment, the display panel DP will be described as a light-emitting display panel. The light-emitting display panel can include an organic light-emitting display panel, an inorganic light-emitting display panel, a quantum dot light-emitting display panel, or the like. In the embodiments described later, the organic light-emitting display panel will be described in detail as an example. The panel driving units SDC, EDC, DDC can include a scan driving unit SDC, a light-emitting driving unit EDC, and a data driving unit DDC.

[0046] The display panel DP can include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm. The display panel DP can include a plurality of pixels connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm (where m and n are integers greater than 1).

[0047] For example, a pixel PXij located at the i-th horizontal line (or the i-th pixel row) and the j-th vertical line (or the j-th pixel column) (where i and j are integers greater than 1) can be connected to the i-th first scan line (or write scan line GWLi), the i-th second scan line (or compensation scan line GCLi), the i-th third scan line (or first initialization scan line GILi), the i-th fourth scan line (or second initialization scan line GBLi), the i-th fifth scan line (or reset scan line GRLi), the j-th data line DLj, and the i-th emission line ESLi.

[0048] The pixel PXij can include a plurality of light-emitting elements, a plurality of transistors, and a plurality of capacitors. The pixel PXij can be supplied with a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage (or reference voltage VREF), a fourth power supply voltage (or first initialization voltage VINT1), a fifth power supply voltage (or second initialization voltage VINT2), and a sixth power supply voltage (or compensation voltage VCOMP) through a power supply unit PWS.

[0049] The voltage values of the first power supply voltage VDD and the second power supply voltage VSS are set so that a current flows through the light-emitting element to emit light. For example, the first power supply voltage VDD can be set to a voltage higher than the second power supply voltage VSS.

[0050] The third power supply voltage VREF can be a voltage for initializing the gate of the driving transistor included in the pixel PXij. The third power supply voltage VREF can be used to implement a predetermined gradation by utilizing the voltage difference from the data signal. For this purpose, the third power supply voltage VREF can be set to a predetermined voltage within the voltage range of the data signal.

[0051] The fourth power supply voltage VINT1 can be a voltage for initializing the capacitor included in the pixel PXij. The fourth power supply voltage VINT1 can be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 can be set to a voltage lower than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor, that is, a voltage lower than the threshold voltage of the driving transistor with respect to the third power supply voltage VREF. However, the present invention is not limited thereto.

[0052] The fifth power supply voltage VINT2 can be a voltage for initializing the cathode of the light-emitting element included in the pixel PXij. The fifth power supply voltage VINT2 can be set to a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or can be set to a voltage similar to or the same as the third power supply voltage VREF, but is not limited thereto, and the fifth power supply voltage VINT2 may be set to a voltage similar to or the same as the first power supply voltage VDD.

[0053] The sixth power supply voltage VCOMP can supply a predetermined current to the driving transistor when compensating for the threshold voltage of the driving transistor.

[0054] On the other hand, in FIG. 1, it is illustrated that the first to sixth power supply voltages VDD, VSS, VREF, VINT1, VINT2, VCOMP are all supplied by the power supply unit PWS, but the present invention is not limited thereto. For example, the first power supply voltage VDD and the second power supply voltage VSS are all supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied corresponding to the structure of the pixel PXij.

[0055] In the embodiments of the present invention, the signal lines connected to the pixel PXij can be variously set according to the circuit structure of the pixel PXij.

[0056] The scan driver SDC receives the first control signal SCS from the timing control unit TC, and based on the first control signal SCS, can supply scan signals to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn.

[0057] The scan signal can be set to a voltage at which the transistor receiving the scan signal turns on. For example, the scan signal supplied to the P-type transistor can be set to a logic low level, and the scan signal supplied to the N-type transistor can be set to a logic high level. Hereinafter, the meaning of "a scan signal is supplied" can be understood as being supplied at a logic level that turns on the transistor controlled thereby.

[0058] In FIG. 1, for simplicity of explanation, the scan driver SDC is illustrated as having a single configuration, but the present invention is not limited thereto. Depending on the embodiment, a plurality of scan drivers can be included to supply scan signals to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn.

[0059] The light emission driver EDC can supply a light emission signal to the light emission lines ESL1 to ESLn based on the second control signal ECS. For example, the light emission signal can be sequentially supplied to the light emission lines ESL1 to ESLn.

[0060] In the example of FIG. 2A, the transistors connected to the light-emitting lines ESL1 to ESLn of the present invention can be composed of N-type transistors. At this time, the light-emitting signals supplied to the light-emitting lines ESL1 to ESLn can be set by a gate-off voltage. The transistors that receive the light-emitting signals are turned off when the light-emitting signals are supplied, and can be set to the on state in other cases.

[0061] The second control signal ECS includes a light-emitting start signal and a clock signal, and the light-emitting driving unit EDC can be implemented as a shift register that sequentially shifts the pulse-shaped light-emitting start signal using the clock signal to sequentially generate and output the pulse-shaped light-emitting signals.

[0062] The data driving unit DDC can receive a third control signal DCS and video data RGB from the timing control unit TC. The data driving unit DDC can convert the digital-form video data RGB into an analog data signal (i.e., a data signal). The data driving unit DDC can supply the data signal to the data lines DL1 to DLm corresponding to the third control signal DCS.

[0063] The third control signal DCS can include a data enable signal, a horizontal start signal, a data clock signal, etc. that indicate the output of valid data signals. For example, the data driving unit DDC includes a shift register that shifts the horizontal start signal in synchronization with the data clock signal to generate a sampling signal, a latch that latches the video data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched video data (e.g., digital-form data) into an analog-form data signal, and a buffer (or amplifier) that outputs the data signal to the data lines DL1 to DLm.

[0064] The power supply unit PWS can supply the display panel DP with a first power supply voltage VDD, a second power supply voltage VSS, and a third power supply voltage VREF for driving the pixels PXij. Further, the power supply unit PWS can supply at least one voltage among a fourth power supply voltage VINT1, a fifth power supply voltage VINT2, and a sixth power supply voltage VCOMP to the display panel DP.

[0065] As an example, the power supply unit PWS can supply each of the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP to the display panel DP via a first power supply line VDL (see FIG. 2A), which is not shown, a second power supply line VSL (see FIG. 2A), a third power supply line (or, a reference voltage line VRL, see FIG. 2A), a fourth power supply line (or, a first initialization voltage line VIL1, see FIG. 2A), a fifth power supply line (or, a second initialization voltage line VIL2, see FIG. 2A), and a sixth power supply line (or, a compensation voltage line VCL, see FIG. 2A).

[0066] The power supply unit PWS can be implemented by a power management integrated circuit, but is not limited thereto.

[0067] The timing control unit TC can generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on input video data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal, etc. The first control signal SCS is supplied to the scan drive unit SDC, the second control signal ECS is supplied to the light emission drive unit EDC, the third control signal DCS is supplied to the data drive unit DDC, and the fourth control signal PCS can be supplied to the power supply unit PWS. The timing control unit TC can re-align the input video data IRGB corresponding to the arrangement of the pixels PXij in the display panel DP to generate video data RGB (or, frame data).

[0068] On the one hand, the scan driving unit SDC, the light emitting driving unit EDC, the data driving unit DDC, the power supply unit PWS, and / or the timing control unit TC can be directly formed on the display panel DP or provided in the form of another driving chip and connected to the display panel DP. Further, at least two of the scan driving unit SDC, the light emitting driving unit EDC, the data driving unit DDC, the power supply unit PWS, and the timing control unit TC may be provided by one driving chip. For example, the data driving unit DDC and the timing control unit TC may be provided by one driving chip.

[0069] Above, the display device DD according to an embodiment has been described with reference to FIG. 1, but the display device of the present invention is not limited thereto. Depending on the configuration of the pixel, signal lines may be further added or omitted. Also, the connection relationship between one pixel and the signal lines can be changed. When any one of the signal lines is omitted, other signal lines can replace the omitted signal line.

[0070] FIGS. 2A, 2B, and 2C are equivalent circuit diagrams of pixels according to an embodiment of the present invention. FIGS. 2A, 2B, and 2C respectively exemplarily illustrate equivalent circuit diagrams of pixels PXij, PXij-1, and PXij-2 connected to the i-th first scan line GWLi (or, write scan line) and the j-th data line DLj (hereinafter, data line). Hereinafter, as an example, the pixels of pixels PXij, PXij-1, and PXij-2 are shown, and the 0th type pixel driving unit PDC, the 1st type pixel driving unit PDC-1, and the 2nd type pixel driving unit PDC-2 included in each pixel are shown. However, the configuration of the pixel and the configuration of the pixel driving unit PDC are not limited thereto and can take various forms.

[0071] As illustrated in FIG. 2A, the pixel PXij includes a light emitting element LD and a 0th type pixel driving unit PDC. The light emitting element LD is connected to the first power line VDL and the 0th type pixel driving unit PDC.

[0072] The pixel driving unit PDC of the 0th type can be connected to a plurality of scan lines GWLi, GCLi, GILi, GBLi, GRLi, data lines DLj, emission lines ESLi, and a plurality of power supply voltage lines VDL, VSL, VIL1, VIL2, VRL, VCL. The pixel driving unit PDC of the 0th type can include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8, a first capacitor C1, and a second capacitor C2. Hereinafter, a case where each of the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8 is all of the N type will be described as an example. However, the present invention is not limited thereto, and some of the first to eighth transistors T1 to T8 can be N-type transistors and the rest can be P-type transistors, and each of the first to eighth transistors T1 to T8 can be a P-type transistor, and it is not limited to any one embodiment.

[0073] The gate of the first transistor T1 can be connected to the first node N1. The first electrode of the first transistor T1 is connected to the second node N2, and the second electrode can be connected to the third node N3. The first transistor T1 can be a driving transistor. The first transistor T1 can control a driving current ILD flowing from the first power supply line VDL through the light emitting element LD to the second power supply line VSL corresponding to the voltage of the first node N1. At this time, the first power supply voltage VDD can be set to a voltage having a higher potential than the second power supply voltage VSS.

[0074] In this specification, "a transistor is connected to a signal line" means that "any one of the source, drain, and gate of the transistor has an integrated shape with the signal line or is connected through a connection electrode". Also, "a transistor is electrically connected to another transistor" means that "any one of the source, drain, and gate of the transistor has an integrated shape with any one of the source, drain, and gate of the other transistor or is connected through a connection electrode".

[0075] The second transistor T2 can include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can supply the data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. The second transistor T2 can be turned on to electrically connect the data line DLj and the first node N1 when the write scan signal GW is supplied to the write scan line GWLi.

[0076] The third transistor T3 can be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 receives the reference voltage VREF through the reference voltage line VRL, and the second electrode of the third transistor T3 can be connected to the first node N1. In this embodiment, the gate of the third transistor T3 can receive a reset scan signal GR through the i-th fifth scan line GRLi (hereinafter, the reset scan line). The third transistor T3 can be turned on to provide the reference voltage VREF to the first node N1 when the reset scan signal GR is supplied to the reset scan line GRLi.

[0077] The fourth transistor T4 can be connected between the third node N3 and the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 is connected to the third node N3, and the second electrode of the fourth transistor T4 can be connected to the first initialization voltage line VIL1 that provides the first initialization voltage VINT1. The fourth transistor T4 can be referred to as a first initialization transistor. The gate of the fourth transistor T4 can receive a first initialization scan signal GI through the i-th third scan line GILi (hereinafter, the first initialization scan line). The fourth transistor T4 can be turned on to supply the first initialization voltage VINT1 to the third node N3 when the first initialization scan signal GI is supplied to the first initialization scan line GILi.

[0078] The fifth transistor T5 can be connected between the compensation voltage line VCL and the second node N2. The first electrode of the fifth transistor T5 receives the compensation voltage VCOMP through the compensation voltage line VCL, and the second electrode of the fifth transistor T5 can be connected to the second node N2 and electrically connected to the first electrode of the first transistor T1. The gate of the fifth transistor T5 can receive the compensation scan signal GC through the i-th second scan line GCLi (hereinafter, the compensation scan line). When the compensation scan signal GC is supplied to the compensation scan line GCLi, the fifth transistor T5 can be turned on to provide the compensation voltage VCOMP to the second node N2, and the threshold voltage of the first transistor T1 can be compensated during the compensation period.

[0079] The sixth transistor T6 can be connected between the first transistor T1 and the light emitting element LD. Specifically, the gate of the sixth transistor T6 can receive the light emission signal EM through the i-th light emission line ESLi (hereinafter, the light emission line). The first electrode of the sixth transistor T6 is connected to the cathode of the light emitting element LD through the fourth node N4, and the second electrode of the sixth transistor T6 can be connected to the first electrode of the first transistor T1 through the second node N2. The sixth transistor T6 can be referred to as the first light emission control transistor. When the light emission signal EM is supplied to the light emission line ESLi, the sixth transistor T6 can be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0080] The seventh transistor T7 can be connected between the second power supply line VSL and the third node N3. The first electrode of the seventh transistor T7 is connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the seventh transistor T7 can receive the second power supply voltage VSS through the second power supply line VSL. The gate of the seventh transistor T7 can be electrically connected to the light emission line ESLi. The seventh transistor T7 can be referred to as the second light emission control transistor. When the light emission signal EM is supplied to the light emission line ESLi, the seventh transistor T7 is turned on to electrically connect the second electrode of the first transistor T1 and the second power supply line VSL.

[0081] On the other hand, in the present embodiment, although the sixth transistor T6 and the seventh transistor T7 are shown as being connected to the same light emission line ESLi and turned on through the same light emission signal EM, this is an exemplary illustration, and the sixth transistor T6 and the seventh transistor T7 may be independently turned on by other signals that distinguish them from each other. Also, in the pixel driving unit PDC of the 0th type according to an embodiment of the present invention, either one of the sixth transistor T6 and the seventh transistor T7 may be omitted.

[0082] The eighth transistor T8 can be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 can include a gate connected to the i-th fourth scan line GBLi (hereinafter, the second initialization scan line), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 can be referred to as the second initialization transistor. The eighth transistor T8 can supply the second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD can be initialized by the second initialization voltage VINT2.

[0083] On the one hand, in this embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 can be turned on simultaneously through the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be turned on simultaneously through the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 can be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 can be turned on / off simultaneously by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi may be provided by substantially a single scan line. Therefore, the cathode initialization of the light-emitting element LD and the threshold voltage compensation of the first transistor T1 can be performed at the same timing. However, this is shown by way of example and is not limited to any one embodiment.

[0084] Also, according to the present invention, the cathode initialization of the light-emitting element LD and the threshold voltage compensation of the first transistor T1 can be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be provided by substantially a single power supply voltage line. In this case, since the cathode initialization operation and the compensation operation of the driving transistor can be performed with one power supply voltage, the design of the driving unit can be simplified. However, this is shown by way of example and is not limited to any one embodiment in one embodiment of the present invention.

[0085] The first capacitor C1 can be disposed between the first node N1 and the third node N3. The first capacitor C1 can store the differential voltage between the first node N1 and the third node N3. The first capacitor C1 can be referred to as a storage capacitor.

[0086] The second capacitor C2 can be arranged between the third node N3 and the second power supply line VSL. That is, one electrode of the second capacitor C2 can be connected to the second power supply line VSL to which the second power supply voltage VSS is supplied, and the other electrode of the second capacitor C2 can be connected to the third node N3. The second capacitor C2 can store a charge corresponding to the voltage difference between the second power supply voltage VSS and the third node N3. The second capacitor C2 can be referred to as a hold capacitor. The second capacitor C2 can have a higher storage capacity compared to the first capacitor C1. Therefore, the second capacitor C2 can minimize the voltage change of the third node N3 corresponding to the voltage change of the first node N1.

[0087] In this embodiment, the light-emitting element LD can be connected to the pixel driving unit PDC of the 0th type through the fourth node N4. The light-emitting element LD can include an anode connected to the first power supply line VDL and a cathode opposed thereto. In this embodiment, the light-emitting element LD can be connected to the pixel driving unit PDC of the 0th type through the cathode. That is, in the pixel PXij according to the present invention, the connection node where the light-emitting element LD and the pixel driving unit PDC of the 0th type are connected is the fourth node N4, and the fourth node N4 can correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light-emitting element LD. Therefore, the potential of the fourth node N4 can substantially correspond to the cathode potential of the light-emitting element LD.

[0088] Specifically, the anode of the light-emitting element LD is connected to the first power supply line VDL, and the first power supply voltage VDD, which is a constant voltage, is applied thereto. The cathode can be connected to the first transistor T1 through the sixth transistor T6. That is, in the present embodiment in which the first to eighth transistors T1 to T8 are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, can be not directly affected by the characteristics of the light-emitting element LD. Therefore, even if the light-emitting element LD deteriorates, the influence on the transistors constituting the pixel driving unit PDC of the type 0, particularly the gate-source voltage Vgs of the driving transistor, can be reduced. That is, since the change amount of the driving current due to the deterioration of the light-emitting element LD can be reduced, the afterimage defect of the display panel according to the increase in the usage time can be reduced, and the lifetime can be improved.

[0089] Alternatively, as illustrated in FIG. 2B, the pixel PXij-1 may include a pixel driving unit PDC-1 of the first type including two transistors T1 and T2 and one first capacitor C1. The pixel driving unit PDC-1 of the first type can be connected to the light-emitting element LD, the write scan line GWLi, the data line DLj, and the second power supply line VSL. The pixel driving unit PDC-1 of the first type illustrated in FIG. 2B can correspond to the omission of the third to eighth transistors T3 to T8 and the second capacitor C2 in the pixel driving unit PDC illustrated in FIG. 2A. Since the area of the pixel driving unit PDC-1 of the first type illustrated in FIG. 2B is smaller than the area of the pixel driving unit PDC of the type 0 illustrated in FIG. 2A, it is possible to secure the area of the display area DA and more easily implement a high resolution.

[0090] Each of the first and second transistors T1 and T2 can be N-type or P-type. In the present embodiment, the case where each of the first and second transistors T1 and T2 is an N-type transistor will be exemplarily described.

[0091] The first transistor T1 can include a gate connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The second node N2 can be a node connected to the first power supply line VDL side, and the third node N3 can be a node connected to the second power supply line VSL side. The first transistor T1 is connected to the light-emitting element LD through the second node N2 and is connected to the second power supply line VSL through the third node N3. The first transistor T1 can be a driving transistor.

[0092] The second transistor T2 can include a gate that receives a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0093] The first capacitor C1 can include an electrode connected to the first node N1 and an electrode connected to the third node N3. The first capacitor C1 can store the data signal DATA transmitted to the first node N1.

[0094] The light-emitting element LD can include an anode and a cathode. In this embodiment, the anode of the light-emitting element LD is connected to the first power supply line VDL, and the cathode is connected to the first type of pixel driving unit PDC-1 through the second node N2. In this embodiment, the cathode of the light-emitting element LD can be connected to the first transistor T1. The light-emitting element LD can emit light corresponding to the amount of current flowing through the first transistor T1 of the first type of pixel driving unit PDC-1.

[0095] In the present embodiment where the first and second transistors T1 and T2 are N-type transistors, the second node N2 to which the cathode of the light-emitting element LD is connected to the first type of pixel driving unit PDC-1 may correspond to the drain of the first transistor T1. That is, it is possible to prevent a change in the gate-source voltage Vgs of the first transistor T1 due to the light-emitting element LD. Therefore, since the amount of change in the driving current due to the deterioration of the light-emitting element LD is reduced, the afterimage defect of the display panel according to the increase in the usage time is reduced, and the lifetime can be improved.

[0096] Alternatively, as illustrated in FIG. 2C, the pixel PXij-2 may include a second type of pixel driving unit PDC-2 including six transistors T1, T2, T3, T4a, T5a, T6a and two capacitors C1, C2.

[0097] The second type of pixel driving unit PDC-2 can be connected to the light-emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first emission line ESL1i (hereinafter, the first emission line), the i-th second emission line ESL2i (hereinafter, the second emission line), the data line DLj, the first power supply line VDL, the second power supply line VSL, the third power supply line VRL, and the initialization voltage line VIL.

[0098] The second type of pixel driving unit PDC-2 illustrated in FIG. 2C can be similar to the structure in which the fourth transistor T4 and the fifth transistor T5 are omitted from the pixel driving unit PDC illustrated in FIG. 2A. Since the area of the second type of pixel driving unit PDC-2 illustrated in FIG. 2C is smaller than the area of the type-0 pixel driving unit PDC illustrated in FIG. 2A, it is possible to secure the area of the display area DA and make it easier to implement high resolution.

[0099] Each of the first to sixth transistors T1, T2, T3, T4a, T5a, T6a can be N-type or P-type. In the present embodiment, the case where each of the first to sixth transistors T1, T2, T3, T4a, T5a, T6a is an N-type transistor will be exemplarily described.

[0100] The first transistor T1 can include a gate connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The second node N2 can be a node connected to the first power supply line VDL side, and the third node N3 can be a node connected to the second power supply line VSL side. The first transistor T1 is connected to the light emitting element LD through the second node N2 and is connected to the second power supply line VSL through the third node N3. The first transistor T1 can be a driving transistor.

[0101] The second transistor T2 can include a gate that receives a write scan signal GW through the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0102] The third transistor T3 can be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 receives a reference voltage VREF through the reference voltage line VRL, and the second electrode of the third transistor T3 can be connected to the first node N1. In this embodiment, the gate of the third transistor T3 can receive a reset scan signal GR through the reset scan line GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 is turned on and can provide the reference voltage VREF to the first node N1.

[0103] The fourth transistor T4a can be connected between the first transistor T1 and the light-emitting element LD. Specifically, the gate of the fourth transistor T4a can receive the first light-emitting signal EM1 through the first light-emitting line ESL1i. The first electrode of the fourth transistor T4a is connected to the cathode of the light-emitting element LD through the fourth node N4, and the second electrode of the fourth transistor T4a can be connected to the first electrode of the first transistor T1 through the second node N2. The fourth transistor T4a can be referred to as the first light-emitting control transistor. When the first light-emitting signal EM1 is supplied to the first light-emitting line ESL1i, the fourth transistor T4a is turned on and can electrically connect the light-emitting element LD and the first transistor T1.

[0104] The fifth transistor T5a can be connected between the second power supply line VSL and the third node N3. The first electrode of the fifth transistor T5a is connected to the second electrode of the first transistor T1 through the third node N3, and the second electrode of the fifth transistor T5a can receive the second power supply voltage VSS through the second power supply line VSL. The gate of the fifth transistor T5a can be electrically connected to the second light-emitting line ESL2i. The fifth transistor T5a can be referred to as the second light-emitting control transistor. When the second light-emitting signal EM2 is supplied to the second light-emitting line ESL2i, the fifth transistor T5a is turned on and electrically connects the second electrode of the first transistor T1 and the second power supply line VSL.

[0105] On the one hand, in this embodiment, each of the fourth transistor T4a and the fifth transistor T5a can be connected to each of the first and second emission lines ESL1i and ESL2i and turned on through the first and second emission signals EM1 and EM2 respectively. That is, the fourth transistor T4a and the fifth transistor T5a can be turned on independently of each other. However, this is only an example and is not limited thereto. For example, in one embodiment of the present invention, the fourth transistor T4a and the fifth transistor T5a can be connected to the same emission line and controlled by the same emission signal. Also, in the second type of pixel driving unit PDC-2 according to one embodiment of the present invention, either one of the fourth transistor T4a and the fifth transistor T5a may be omitted.

[0106] The sixth transistor T6a can be connected between the initialization voltage line VIL and the fourth node N4. That is, the sixth transistor T6a can include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a can be referred to as an initialization transistor. The sixth transistor T6a can supply the initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD can be initialized by the initialization voltage VINT.

[0107] The first capacitor C1 can be disposed between the first node N1 and the third node N3. The first capacitor C1 can store the differential voltage between the first node N1 and the third node N3. The first capacitor C1 can be referred to as a storage capacitor.

[0108] The second capacitor C2 can be disposed between the third node N3 and the second power supply line VSL. That is, one electrode of the second capacitor C2 can be connected to the second power supply line VSL to which the second power supply voltage VSS is supplied, and the other electrode of the second capacitor C2 can be connected to the third node N3. The second capacitor C2 can store a charge corresponding to the voltage difference between the second power supply voltage VSS and the third node N3. The second capacitor C2 can be referred to as a hold capacitor.

[0109] The light-emitting element LD can include an anode and a cathode. In the present embodiment, the anode of the light-emitting element LD is connected to the first power supply line VDL, and the cathode is connected to the second type of pixel driving unit PDC-2 through the fourth node N4. In the present embodiment, the cathode of the light-emitting element LD can be connected to the first transistor T1 through the fourth transistor T4a. The light-emitting element LD can emit light corresponding to the amount of current flowing through the first transistor T1 of the second type of pixel driving unit PDC-2.

[0110] In the present embodiment in which the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, can be not directly affected by the characteristics of the light-emitting element LD. Therefore, even when the light-emitting element LD deteriorates, the influence on the transistors constituting the second type of pixel driving unit PDC-2, particularly the gate-source voltage Vgs of the driving transistor, can be reduced. That is, since the amount of change in the driving current due to the deterioration of the light-emitting element LD is reduced, the afterimage defect of the display panel corresponding to the increase in the usage time is reduced, and the lifetime can be improved.

[0111] On the one hand, FIGS. 2A, 2B, and 2C show circuits for pixel driving units PDC, PDC-1, and PDC-2 according to an embodiment of the present invention. As long as the display panel according to an embodiment of the present invention is a circuit connected to the cathode of the light-emitting element LD, the number and arrangement relationship of transistors and the number and arrangement relationship of capacitors can be designed in various ways and are not limited to any one embodiment.

[0112] FIGS. 3A and 3B are plan views schematically showing a display panel according to an embodiment of the present invention. In each of FIGS. 3A and 3B, some components are shown with omissions. Hereinafter, the present invention will be described with reference to FIGS. 3A and 3B.

[0113] Referring to FIG. 3A, a display panel DP of an embodiment can be divided into a display area DA and a peripheral area (or non-display area) NDA. The display area DA can include a plurality of light-emitting portions EP.

[0114] The light-emitting portion EP can be an area where each pixel PXij (see FIG. 1) emits light. Specifically, each of the light-emitting portions EP can correspond to a light-emitting aperture OP-PDL (see FIG. 5) described later.

[0115] The peripheral area NDA can be arranged adjacent to the display area DA. In this embodiment, the peripheral area NDA is shown in a shape surrounding the edge of the display area DA. However, this is shown by way of example, and the peripheral area NDA can also be arranged on one side of the display area DA or omitted, and is not limited to any one embodiment.

[0116] In this embodiment, the scan driving unit SDC and the data driving unit DDC can be implemented on the display panel DP. In one embodiment, the scan driving unit SDC can be arranged in the display area DA, and the data driving unit DDC can be arranged in the peripheral area NDA. The scan driving unit SDC can be superimposed on at least a part of the plurality of light emitting units EP arranged in the display area DA in a plane. By arranging the scan driving unit SDC in the display area DA, the area of the peripheral area NDA can be reduced compared to a conventional display panel in which the scan driving unit is arranged in the peripheral area, and a display device with a thin bezel can be easily realized. That is, when the scan driving unit is arranged in the peripheral area, the area of the peripheral area increases by the area of the scan driving unit. However, by arranging the scan driving unit SDC in the display area DA, the area of the peripheral area can be reduced by at least the area of the scan driving unit SDC, and the bezel can be made smaller.

[0117] On the other hand, different from what is shown in FIG. 3A, the scan driving unit SDC may be arranged in two parts separated from each other. For example, the two scan driving units SDC can be arranged to be separated left and right via the center of the display area DA. Or, the scan driving unit SDC can be provided in two or more larger numbers and is not limited to any one embodiment.

[0118] On the other hand, FIG. 3A only shows an example of the display panel, and the data driving unit DDC may be arranged in the display area DA. At this time, a part of the light emitting units EP arranged in the display area DA may be superimposed on the data driving unit DDC in a plane.

[0119] In one embodiment, the data driving unit DDC can be provided in the form of another driving chip independent of the display panel DP and can be connected to the display panel DP. However, this is only an illustrative explanation, and the data driving unit DDC can also be formed in the same process as the scan driving unit SDC so as to constitute the display panel DP, and is not limited to any one embodiment.

[0120] As shown in FIG. 3B, the display panel DP may be in a form in which the length corresponding to the first direction DR1 is longer than the length corresponding to the second direction DR2. A state in which a plurality of pixels PX11 to PXnm arranged in n rows and m columns in the display area DA is arranged is exemplarily illustrated. In the present embodiment, the display panel DP may include a plurality of scan driving units SDC1 and SDC2. In the example of FIG. 3B, the scan driving units SDC1 and SDC2 include, for example, a first scan driving unit SDC1 and a second scan driving unit SDC2 that are arranged apart from each other in the first direction DR1.

[0121] The first scan driving unit SDC1 can be connected to a part of the scan lines GL1 to GLn, and the second scan driving unit SDC2 can be connected to another part of the scan lines GL1 to GLn. For example, the first scan driving unit SDC1 can be connected to the odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driving unit SDC2 can be connected to the even-numbered scan lines among the scan lines GL1 to GLn.

[0122] FIG. 3B shows pads PD of the data lines DL1 to DLm for ease of explanation. The pads PD can be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm can be connected to the data driving unit DDC (see FIG. 3A) through the pads PD.

[0123] According to the present invention, the pads PD can be divided and arranged at positions separated from each other through the display area DA in the peripheral area NDA. For example, a part of the pads PD can be arranged on the upper side, that is, on the side adjacent to the first scan line GL1 among the scan lines GL1 to GLn, and another part of the pads PD can be arranged on the lower side, that is, on the side adjacent to the last scan line GLn among the scan lines GL1 to GLn. In the present embodiment, the pads PD connected to the odd-numbered data lines among the data lines DL1 to DLm can be arranged on the upper side, and the pads PD connected to the even-numbered data lines among the data lines DL1 to DLm can be arranged on the lower side.

[0124] Although not shown, the display panel DP may include a plurality of upper data driving units connected to pads PD arranged on the upper side and / or a plurality of lower data driving units connected to pads PD arranged on the lower side. However, this is only an illustrative description, and the display panel DP may include one upper data driving unit connected to the pads PD arranged on the upper side and / or one lower data driving unit connected to the pads PD arranged on the lower side. The pad PD according to an embodiment of the present invention may be arranged on only one side of the display panel DP and connected to a single data driving unit, and is not limited to any one embodiment.

[0125] Also, as described above with reference to FIG. 3A, in the display panel DP in FIG. 3B as well, the scan driving unit and / or the data driving unit can be arranged in the display area DA, and thus a part of the light emitting units arranged in the display area DA can be superimposed on the scan driving unit and / or the data driving unit in a plane.

[0126] FIGS. 4A to 4D are enlarged plan views of a partial area of a display panel DP according to an embodiment of the present invention.

[0127] FIG. 4A exemplarily shows light-emitting units UT11, UT12, UT21, and UT22 arranged in two rows and two columns. Referring to FIG. 4A, the light-emitting part of the first row Rk includes the light-emitting parts that constitute the light-emitting unit UT11 in the first row and first column and the light-emitting unit UT12 in the first row and second column, and the light-emitting part of the second row Rk+1 includes the light-emitting parts that constitute the light-emitting unit UT21 in the second row and first column and the light-emitting unit UT22 in the second row and second column. In the examples of FIGS. 4A to 4D, each of the light-emitting units UT11, UT12, UT21, and UT22 is approximately the same size. Also, in the light-emitting part of the first row Rk, the light-emitting part that constitutes the light-emitting unit UT11 in the first row and first column and the light-emitting part that constitutes the light-emitting unit UT12 in the first row and second column are arranged in the same row. Similarly, in the light-emitting part of the second row Rk+1, the light-emitting part that constitutes the light-emitting unit UT21 in the second row and first column and the light-emitting part that constitutes the light-emitting unit UT22 in the second row and second column are arranged in the same row. Further, the light-emitting part that constitutes the light-emitting unit UT11 in the first row and first column and the light-emitting part that constitutes the light-emitting unit UT21 in the second row and first column are arranged in the same column. Also, the light-emitting part that constitutes the light-emitting unit UT12 in the first row and second column and the light-emitting part that constitutes the light-emitting unit UT22 in the second row and second column are arranged in the same column. Note that in the example of FIG. 4, although each of the light-emitting units UT11, UT12, UT21, and UT22 is approximately the same size, the sizes of the respective light-emitting units may be different. Also, the arrangement of each light-emitting unit in the row direction (the first direction DR1) does not have to be linear, and the light-emitting units may be arranged in the row direction in a state where they are shifted from each other in the column direction. Further, the arrangement of each light-emitting unit in the column direction (the second direction DR2) does not have to be linear, and the light-emitting units may be arranged in the column direction in a state where they are shifted from each other in the row direction.

[0128] Each of the light emitting portions EP1, EP2, and EP3 can correspond to a light emitting aperture OP-PDL (see FIG. 5) described later. That is, each of the light emitting portions EP1, EP2, and EP3 can be a region where light is emitted by the light emitting elements described above. The light emitting portions EP1, EP2, and EP3 can correspond to units that constitute an image displayed on the display panel DP (see FIG. 1). More specifically, each of the light emitting portions EP1, EP2, and EP3 can correspond to a region defined by the light emitting aperture OP-PDL described later, particularly a region defined by the lower part of the light emitting aperture OP-PDL.

[0129] The light emitting portions EP1, EP2, and EP3 can include a first light emitting portion EP1, a second light emitting portion EP2, and a third light emitting portion EP3. The first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 can emit light of different colors. For example, the first light emitting portion EP1 can emit red light, the second light emitting portion EP2 can emit green light, and the third light emitting portion EP3 can emit blue light, but the color combination is not limited to this. Also, at least two of each of the first to third light emitting portions EP1, EP2, and EP3 can emit light of the same color. For example, all of the first to third light emitting portions EP1, EP2, and EP3 can emit blue light, or all can emit white light.

[0130] The third light emitting portion EP3 that displays light emitted by the third light emitting element among the first to third light emitting portions EP1, EP2, and EP3 can include two sub-light emitting portions EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is shown by way of example, and the third light emitting portion EP3 may be provided in one pattern having an integral shape like the first and second light emitting portions EP1 and EP2, and at least one of the first and second light emitting portions EP1 and EP2 can also include spaced-apart sub-light emitting portions, and is not limited to any one embodiment.

[0131] The light-emitting part of the first row Rk includes the first to third light-emitting parts EP1, EP2, and EP3 that constitute the first-row first-column light-emitting unit UT11, and the first to third light-emitting parts EP1, EP2, and EP3a that constitute the first-row second-column light-emitting unit UT12. The light-emitting part of the second row Rk+1 can include the first to third light-emitting parts EP1, EP2, and EP3a that constitute the second-row first-column light-emitting unit UT21, and the first to third light-emitting parts EP1, EP2, and EP3 that constitute the second-row second-column light-emitting unit UT22.

[0132] In an embodiment of the present invention, the shapes of the light-emitting parts that constitute the first-row first-column light-emitting unit UT11 and the light-emitting parts that constitute the second-row second-column light-emitting unit UT22 can be substantially the same. Also, the shapes of the light-emitting parts that constitute the first-row second-column light-emitting unit UT12 and the light-emitting parts that constitute the second-row first-column light-emitting unit UT21 can be substantially the same. The shape of the light-emitting parts that constitute the first-row first-column light-emitting unit UT11 can be different from the shape of the light-emitting parts that constitute the first-row second-column light-emitting unit UT12. For example, a part of the light-emitting part of the first row Rk and a part of the light-emitting part of the second row Rk+1 can have a symmetric shape.

[0133] In one embodiment of the present invention, the third light-emitting portion EP3a of the second-row first-column light-emitting unit UT21 and the third light-emitting portion EP3 of the first-row first-column light-emitting unit UT11 can have a shape and an arrangement shape that are line-symmetric with respect to an axis parallel to the first direction DR1, and the third light-emitting portion EP3 of the second-row second-column light-emitting unit UT22 and the third light-emitting portion EP3a of the first-row second-column light-emitting unit UT12 can have a shape and an arrangement shape that are line-symmetric with respect to an axis parallel to the first direction DR1. However, this is exemplary and not limiting. In the example of FIG. 4A, it can be said that the shape and the arrangement shape of the third light-emitting portion EP3 of the first-row first-column light-emitting unit UT11 are substantially the same as the shape and the arrangement shape of the third light-emitting portion EP3 of the second-row second-column light-emitting unit UT22. Also, it can be said that the shape and the arrangement shape of the third light-emitting portion EP3a of the first-row second-column light-emitting unit UT12 are substantially the same as the shape and the arrangement shape of the third light-emitting portion EP3a of the second-row first-column light-emitting unit UT21. In addition, in each of the light-emitting units UT11, UT12, UT21, and UT22, it can be said that the shapes and the arrangement modes of the first and second light-emitting portions EP1 and EP2 are substantially the same.

[0134] FIG. 4B illustrates light-emitting portions arranged in one row. For ease of explanation, FIG. 4B shows a plurality of second electrodes EL2_1, EL2_2, EL2_3, a plurality of first to third pixel driving portions PDC1, PDC2, PDC3, first to third connection electrodes CNE1, CNE2, CNE3, and a groove GV. FIG. 4C shows the groove GV in the configuration of the display panel, a plurality of light-emitting portions EP1, EP2, EP3 arranged in the region partitioned by the groove GV, and a plurality of connection electrodes CNE1, CNE2, CNE3.

[0135] Referring to FIGS. 4B and 4C, each of the second electrodes EL2_1, EL2_2, and EL2_3 can be separated from each other by the grooves GV and electrically disconnected. In this embodiment, one light-emitting unit UT11 can include three light-emitting portions EP1, EP2, and EP3. Therefore, the light-emitting unit UT11 can include three second electrodes EL2_1, EL2_2, and EL2_3 (hereinafter, the first to third cathodes), three first to third pixel driving portions PDC1, PDC2, and PDC3, and three connection electrodes CNE1, CNE2, and CNE3. However, this is merely illustrated, and the number and arrangement of the light-emitting portions included in the light-emitting unit UT11 can be designed in various ways and are not limited to any one embodiment.

[0136] Each of the first to third pixel driving portions PDC1, PDC2, and PDC3 is electrically connected to first to third light-emitting elements LD1, LD2, and LD3 including first to third light-emitting portions EP1, EP2, and EP3, respectively. In this specification, "connected" includes not only the case of being physically directly connected but also the case of being electrically connected.

[0137] Also, as shown in FIG. 4B, each region where the first to third pixel driving portions PDC1, PDC2, and PDC3 are defined on the plane can correspond to a unit in which transistors and capacitor elements constituting a circuit PDC (see FIG. 2A, pixel driving portion PDC) for driving the light-emitting elements of the pixel are repeatedly arranged.

[0138] The first to third pixel driving portions PDC1, PDC2, and PDC3 can be sequentially arranged along the first direction DR1. On the other hand, the arrangement positions of the first to third pixel driving portions PDC1, PDC2, and PDC3 can be independently designed regardless of the positions and shapes of the first to third light-emitting portions EP1, EP2, and EP3.

[0139] For example, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged at positions different from the regions defined by the grooves GV, that is, the positions where the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged, or may be designed to have shapes and areas different from the shapes of the first to third cathodes EL2_1, EL2_2, and EL2_3. Alternatively, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged so as to overlap the positions where the first to third light emitting units EP1, EP2, and EP3 are present, and may be designed to have a shape similar to the regions defined by the grooves GV, for example, a shape similar to that of the first to third cathodes EL2_1, EL2_2, and EL2_3 and having a similar area.

[0140] In the present embodiment, each of the regions of the first to third pixel driving units PDC1, PDC2, and PDC3 is illustrated as a rectangular shape, and each of the first to third light emitting units EP1, EP2, and EP3 is arranged in a form different from the smaller area than the first to third pixel driving units PDC1, PDC2, and PDC3, and the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3 and are illustrated as an irregular shape. In the example of FIG. 4B, the long sides of the rectangular regions of the first to third pixel driving units PDC1, PDC2, and PDC3 have long sides corresponding to the length of the second direction DR2 of the light emitting unit UT11. Also, the short sides of the rectangular regions of the first to third pixel driving units PDC1, PDC2, and PDC3 are shorter than the length of the first direction DR1 of the light emitting unit UT11, and in the example of FIG. 4B, the sum of the lengths of the short sides of the first to third pixel driving units PDC1, PDC2, and PDC3 is approximately equal to the length of the first direction DR1 of the light emitting unit UT11.

[0141] Therefore, as illustrated in FIG. 4B, the first pixel driving unit PDC1 can be disposed at a position partially overlapping with the first light emitting unit EP1, the second light emitting unit EP2, and other adjacent light emitting units. More specifically, in the example of FIG. 4B, the first pixel driving unit PDC1 overlaps with a part of the first light emitting unit EP1, a part of the second light emitting unit EP2, a part of the first cathode EL2_1, a part of the second cathode EL2_2, a part of the first connection electrode CNE1, a part of the second connection electrode CNE2, a part of the first connection part CE1, etc. in the light emitting unit UT11, and can be disposed at a position overlapping with a part of other light emitting units adjacent to the light emitting unit UT11. The second pixel driving unit PDC2 can be disposed at a position overlapping with the first light emitting unit EP1, the second light emitting unit EP2, and the third cathode EL2_3. More specifically, in the example of FIG. 4B, the second pixel driving unit PDC2 overlaps with the remaining part of the first light emitting unit EP1, the remaining part of the second light emitting unit EP2, the remaining part of the first cathode EL2_1, the remaining part of the second cathode EL2_2, the remaining part of the first connection electrode CNE1, the remaining part of the second connection electrode CNE2, a part of the second connection part CE2, etc. in the light emitting unit UT11, and can be disposed at a position overlapping with a part of the third connection electrode CNE3 and a part of the third cathode EL2_3. The third pixel driving unit PDC3 can be disposed at a position overlapping with the third light emitting unit EP3. More specifically, in the example of FIG. 4B, the third pixel driving unit PDC3 overlaps with the third light emitting unit EP3 (sub-light emitting units EP31, EP32), a part of the third connection electrode CNE3 and a part of the third cathode EL2_3, a connection wiring CN3 (including the third connection part CE3 and the driving connection part CD3), etc. in the light emitting unit UT11, and can be disposed at a position overlapping therewith. On the other hand, this is an exemplary illustration, and the positions of the first to third pixel driving units PDC1, PDC2, and PDC3 can be designed in various forms and arrangements independently of the first to third light emitting units EP1, EP2, and EP3, and are not limited to any one embodiment.

[0142] The light-emitting unit UT11 can include first to third connection electrodes CNE1, CNE2, and CNE3. The first connection electrode CNE1 electrically connects the first light-emitting element LD1 that forms (or defines) the first light-emitting portion EP1 and the first pixel driving portion PDC1. The second connection electrode CNE2 electrically connects the second light-emitting element LD2 that forms the second light-emitting portion EP2 and the second pixel driving portion PDC2. The third connection electrode CNE3 can electrically connect the third light-emitting element LD3 that forms the third light-emitting portion EP3 and the third pixel driving portion PDC3.

[0143] Specifically, the first to third connection electrodes CNE1, CNE2, and CNE3 can be electrically connected in a one-to-one correspondence with the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third pixel driving portions PDC1, PDC2, and PDC3, respectively.

[0144] Each of the first to third connection electrodes CNE1, CNE2, and CNE3 can be disposed on a pixel definition film PDL (see FIG. 5) described later. As shown in FIGS. 4B, 4C, etc., the first to third connection electrodes CNE1, CNE2, and CNE3 can have an annular shape surrounding the corresponding first to third light-emitting portions EP1, EP2, and EP3. In one embodiment of the present invention, an example is illustrated in which each of the first to third connection electrodes CNE1, CNE2, and CNE3 has a closed-line annular shape, but the present invention is not limited thereto. For example, at least a part of the first to third connection electrodes CNE1, CNE2, and CNE3 may have an open-ring shape with a part cut off.

[0145] Since the first to third connection electrodes CNE1, CNE2, and CNE3 have an annular shape, the degree of freedom in the positions where the first to third connection electrodes CNE1, CNE2, and CNE3 are connected to the first to third pixel driving units PDC1, PDC2, and PDC3 can be improved. That is, by arranging the first to third connection parts CE1, CE2, and CE3 corresponding to arbitrary positions of the annular first to third connection electrodes CNE1, CNE2, and CNE3, the first to third connection electrodes CNE1, CNE2, and CNE3 and the first to third pixel driving units PDC1, PDC2, and PDC3 can be connected via the first to third connection parts CE1, CE2, and CE3. For example, the first connection electrode CNE1 is connected to the first pixel driving unit PDC1 through the first connection part CE1 at the position shown in FIG. 4B or the like, the second connection electrode CNE2 is connected to the second pixel driving unit PDC2 through the second connection part CE2 at the position shown in FIG. 4B or the like, and the third connection electrode CNE3 can be connected to the third pixel driving unit PDC3 through the connection wiring CN3 (including the third connection part CE3 and the driving connection part CD3) as shown in FIG. 4B or the like. That is, the connection wiring additionally connected to the first and second connection electrodes CNE1 and CNE2 can be omitted.

[0146] One connection wiring CN3 can electrically connect the third pixel driving unit PDC3 and the third light-emitting element LD3 constituting the third light-emitting unit EP3. Specifically, the connection wiring CN3 can correspond to a node (refer to the fourth node N4 in FIG. 2A, the second node N2 in FIG. 2B, or the fourth node N4 in FIG. 2C) where the light-emitting element LD (refer to FIG. 2A) is connected to the pixel driving unit (PDC in FIG. 2A, PDC-1 in FIG. 2B, or PDC-2 in FIG. 2C).

[0147] The connection wiring CN3 can include the third connection part CE3 and the driving connection part CD3. The third connection part CE3 can be provided on one side of the connection wiring CN3, and the driving connection part CD3 can be provided on the other side of the connection wiring CN3.

[0148] The drive connection portion CD3 can be a portion of the connection wiring CN3 that is connected to the third pixel drive portion PDC3. In the present embodiment, the drive connection portion CD3 can be connected to one electrode of the transistor that constitutes the third pixel drive portion PDC3. Specifically, the drive connection portion CD3 can be connected to the drain of the sixth transistor T6 illustrated in FIG. 2A, the drain of the first transistor T1 illustrated in FIG. 2B, or the drain of the fourth transistor T4a illustrated in FIG. 2C. Therefore, the position of the drive connection portion CD3 can correspond to the position of the transistor physically connected to the connection wiring CN3 within the pixel drive portion. The third connection portion CE3 can be a portion of the connection wiring CN3 that is connected to the third light-emitting element LD3. In the present embodiment, the third connection portion CE3 can be connected to the third connection electrode CNE3.

[0149] The first connection electrode CNE1 can include a first edge EG11 that surrounds at least a part of the first light-emitting portion EP1 and a second edge EG12 that surrounds the first edge EG11. The second connection electrode CNE2 can include a first edge EG21 that surrounds at least a part of the second light-emitting portion EP2 and a second edge EG22 that surrounds the first edge EG21. The third connection electrode CNE3 can include a first edge EG31 that surrounds at least a part of the third light-emitting portion EP3 and a second edge EG32 that surrounds the first edge EG31.

[0150] The first to third connection electrodes CNE1, CNE2, and CNE3 can be arranged to be spaced apart from each other. For example, the gaps GP1, GP2, and GP3 between a plurality of adjacent connection electrodes among the first to third connection electrodes CNE1, CNE2, and CNE3 can overlap with the groove GV. For example, the first edges EG11, EG21, and EG31 of the first to third connection electrodes CNE1, CNE2, and CNE3 do not overlap with the groove GV, but the second edges EG12, EG22, and EG32 of the first to third connection electrodes CNE1, CNE2, and CNE3 can overlap with the groove GV. The groove GV can be formed, for example, between adjacent connection electrodes CNE. Also, the groove CV can be formed, for example, between the inner edge of one connection electrode CNE and the inner edge of the other adjacent connection electrode CNE among adjacent connection electrodes CNE. Also, the groove CV can be formed, for example, between the outer edge of one connection electrode CNE and the outer edge of the other adjacent connection electrode CNE among adjacent connection electrodes CNE. Further, referring to the example of FIG. 4C, in particular, the groove CV can be formed, for example, between the portion between the inner edge and the outer edge of one connection electrode CNE and the portion between the inner edge and the outer edge of the other adjacent connection electrode CNE among adjacent connection electrodes CNE. More specifically, when referring to FIG. 4C, between the adjacent first connection electrode CNE1 and the second connection electrode CNE2, the groove GV can be formed, for example, between the adjacent first connection electrode CNE1 and the second connection electrode CNE2. Also, between the adjacent first connection electrode CNE1 and the second connection electrode CNE2, the groove GV can be formed, for example, between the first edge EG11 of the first connection electrode CNE1 and the first edge EG21 of the second connection electrode CNE2. Also, between the adjacent first connection electrode CNE1 and the second connection electrode CNE2, the groove GV can be formed, for example, between the second edge EG12 of the first connection electrode CNE1 and the second edge EG22 of the second connection electrode CNE2.Furthermore, referring to the example of FIG. 4C, particularly between the adjacent first connection electrode CNE1 and the second connection electrode CNE2, the groove GV can be formed, for example, between the portion between the first edge EG11 and the second edge EG12 of the first connection electrode CNE1 and the portion between the first edge EG21 and the second edge EG22 of the second connection electrode CNE2.

[0151] In one embodiment of the present invention, the first to third connection portions CE1, CE2, and CE3 can be arranged at non-overlapping positions (non-overlapping positions) on a plane with the first to third light emitting portions EP1, EP2, and EP3. For example, in the pixel definition film PDL, a light emitting opening OP-PDL (see FIG. 5) and a through hole OP-P (see FIG. 5) separated from the light emitting opening OP-PDL can be defined.

[0152] The through hole OP-P can include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first to third connection portions CE1, CE2, and CE3 can be arranged corresponding to each of the first to third through holes OP-P1, OP-P2, and OP-P3. The light emitting opening OP-PDL can include a first light emitting opening OP-PDL1, a second light emitting opening OP-PDL2, and a third light emitting opening OP-PDL3. The first to third light emitting portions EP1, EP2, and EP3 can be defined corresponding to each of the first to third light emitting openings OP-PDL1, OP-PDL2, and OP-PDL3. Therefore, the first to third connection portions CE1, CE2, and CE3 can be arranged at positions separated from the first to third light emitting portions EP1, EP2, and EP3.

[0153] The first to third connection electrodes CNE1, CNE2, and CNE3 can be arranged on the pixel definition film PDL (see FIG. 5). When viewed on a plane, the first connection electrode CNE1 can surround the first light emitting opening OP-PDL1, the second connection electrode CNE2 can surround the second light emitting opening OP-PDL2, and the third connection electrode CNE3 can surround the third light emitting opening OP-PDL3.

[0154] According to an embodiment of the present invention, a drive connection portion CD3, which is a position where a connection wiring CN3 is connected to a transistor TR (see FIG. 5) of a third pixel driving portion PDC3, is defined at a position non-overlapping with a third connection portion CE3 on a plane and can be disposed at a position overlapping with a third light emitting portion EP3. By connecting a third cathode EL2_3 and a pixel driving portion PDC3 through the connection wiring CN3, in the design of the pixel driving portion PDC3, restrictions according to the position and shape of the third light emitting portion EP3 can be reduced and the degree of freedom in design can be improved.

[0155] The first to third cathodes EL2_1, EL2_2, EL2_3 can be connected to the first to third connection electrodes CNE1, CNE2, CNE3. For example, the first to third cathodes EL2_1, EL2_2, EL2_3 and the first to third connection electrodes CNE1, CNE2, CNE3 can be respectively connected (or contacted) in a region adjacent to a groove GV.

[0156] Also, a connection region where the first to third cathodes EL2_1, EL2_2, EL2_3 and the first to third connection electrodes CNE1, CNE2, CNE3 are connected can surround at least a part of each of the first to third light emitting openings OP-PDL1, OP-PDL2, OP-PDL3. The first to third cathodes EL2_1, EL2_2, EL2_3 and the first to third connection electrodes CNE1, CNE2, CNE3 can be connected in a region adjacent to a groove GV, and each of the connection regions can be defined adjacent to the groove GV. That is, the first to third cathodes EL2_1, EL2_2, EL2_3 and the first to third connection electrodes CNE1, CNE2, CNE3 are not partially connected at a specific point, but can be connected over a relatively wide region, for example, a region similar to the shape of each of the first to third connection electrodes CNE1, CNE2, CNE3. That is, the area of the connection region is increased and the connection can be stably advanced.

[0157] FIG. 4D shows a groove GV, light emitting portions EP1, EP2, EP3, and a first electrode EL1.

[0158] Referring to FIG. 4D, the first electrode EL1 (hereinafter sometimes also referred to as the anode) of the light-emitting element LD (see FIG. 5) according to an embodiment of the present invention can be commonly provided to the first to third light-emitting portions EP1, EP2, and EP3. That is, the anode EL1 can be formed of a single layer that is integral throughout the display area DA. Therefore, the anode EL1 layer can be disposed to overlap with the groove GV. Alternatively, each anode EL1 of the light-emitting element LD can be formed of independent conductive patterns spaced apart from each other and can be electrically connected to each other through other conductive layers. Therefore, the anode EL1 pattern may be disposed non-overlapping with the groove GV.

[0159] As described above, the first power supply voltage VDD (see FIG. 2A) is applied to the anode EL1, and a voltage common to all the light-emitting portions can be provided. The anode EL1 is connected to the first power supply line VDL (see FIG. 2A) that provides the first power supply voltage VDD in the peripheral area NDA, or can also be connected to the first power supply line VDL (see FIG. 2A) in the display area DA, and is not limited to any one embodiment.

[0160] On the other hand, a plurality of openings can be defined in the anode EL1 according to the present embodiment, and the openings can penetrate the anode EL1 layer. The openings in the anode EL1 layer can be disposed at positions non-overlapping with the light-emitting portion EP (see FIG. 3A) and can be defined at positions generally overlapping with the groove GV. The openings can facilitate the discharge of gas generated from an organic layer disposed below the anode EL1, for example, the sixth insulating layer 60 (see FIG. 5) described later. Therefore, the gas in the organic layer disposed below the light-emitting element can be sufficiently discharged during the manufacturing process of the display panel, and the rate at which the gas discharged from the organic layer deteriorates the light-emitting element after manufacturing can be reduced.

[0161] FIG. 5 is a cross-sectional view of a display panel DP according to an embodiment of the present invention. FIG. 5 shows a cross-sectional view corresponding to the line I-I' in FIG. 4C.

[0162] Referring to FIG. 5, the display panel DP of one embodiment can include a base layer BS, a driving element layer DDL, a light-emitting element layer LDL, a sealing layer ECL, and a sensing layer ISL. However, this is only an example, and in one embodiment of the present invention, the display panel DP may not include the sensing layer ISL.

[0163] The driving element layer DDL can include a plurality of insulating layers 10, 20, 30, 40, 50, 60 disposed on the base layer BS, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, 60. The conductive patterns and semiconductor patterns can be disposed between the insulating layers 10, 20, 30, 40, 50, 60 to form a pixel driving portion PDC. FIG. 5 shows a cross-section of one of the regions in the region where one light-emitting portion is disposed for easy explanation.

[0164] The base layer BS can be a member that provides a base surface on which the pixel driving portion PDC is disposed. The base layer BS can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. The base layer BS can be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiments of the present invention are not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0165] The base layer BS can have a multilayer structure. The base layer BS can include a first polymer resin layer, a silicon oxide (SiOx) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer can be referred to as a base barrier layer.

[0166] The polymer resin layer may contain a polyimide-based resin. Further, the polymer resin layer may contain at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. On the other hand, in this specification, the “~-based” resin means containing the functional group of “~”.

[0167] Each of the insulating layer, the conductive layer, and the semiconductor layer disposed on the base layer BS can be formed by methods such as coating and vapor deposition. Thereafter, through a plurality of photolithography processes, the insulating layer, the semiconductor layer, and the conductive layer are selectively patterned to form holes in the insulating layer, or semiconductor patterns, conductive patterns, signal lines, etc. can be formed.

[0168] The driving element layer DDL may include first to sixth insulating layers 10, 20, 30, 40, 50, 60 and a pixel driving unit PDC sequentially laminated on the base layer BS. In FIG. 5, one transistor TR and two capacitors C1, C2 in the pixel driving unit PDC are illustrated.

[0169] The transistor TR corresponds to a transistor connected to the light-emitting element LD through the intermediate connection electrode CN and the connection electrode CNE, that is, a connection transistor connected to a node corresponding to the cathode of the light-emitting element LD (the fourth node N4 in FIG. 2A, the second node N2 in FIG. 2B, or the fourth node N4 in FIG. 2C). Specifically, the transistor TR in FIG. 5 can correspond to the sixth transistor T6 in FIG. 2A, the first transistor T1 in FIG. 2B, or the fourth transistor T4a in FIG. 2C. On the other hand, although not shown, other transistors constituting the pixel driving unit PDC can have the same structure as the transistor TR (hereinafter, the connection transistor) shown in FIG. 5. However, this is an exemplary explanation, and other transistors constituting the pixel driving unit PDC can also have a structure different from that of the connection transistor TR and are not limited to any one embodiment.

[0170] The first insulating layer 10 can be disposed on the base layer BS. The first insulating layer 10 is an inorganic layer and / or an organic layer and can have a single-layer or multi-layer structure. The first insulating layer 10 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 is illustrated as a single-layer silicon oxide layer. On the other hand, the insulating layers described later are inorganic layers and / or organic layers and can have a single-layer or multi-layer structure. The inorganic layer can include at least one of the substances described above, but is not limited thereto.

[0171] On one hand, the first insulating layer 10 can cover the lower conductive layer BCL. That is, the display panel DP can further include a lower conductive layer BCL disposed to overlap the connection transistor TR. The lower conductive layer BCL can block the electrical potential due to the polarization development of the base layer BS from affecting the connection transistor TR. Also, the lower conductive layer BCL can block the light incident on the connection transistor TR from below. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the lower conductive layer BCL and the base layer BS.

[0172] The lower conductive layer BCL can include a reflective metal. For example, the lower conductive layer BCL can include titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu), etc.

[0173] In one embodiment, the lower conductive layer BCL can be connected to the source of the connection transistor TR (or the transistor) through the source electrode pattern W1. In this case, the lower conductive layer BCL can be synchronized with the source of the transistor TR. However, this is shown by way of example, and the lower conductive layer BCL may be connected to the gate of the transistor TR and synchronized with the gate. Or, the lower conductive layer BCL can be connected to other electrodes and a constant voltage or a pulse signal can be applied independently. Or, the lower conductive layer BCL may be provided in an isolated form from other conductive patterns. The lower conductive layer BCL according to an embodiment of the present invention can be provided in various forms and is not limited to any one embodiment.

[0174] A connection transistor TR can be arranged on the first insulating layer 10. The connection transistor TR can include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP can be arranged on the first insulating layer 10. The semiconductor pattern SP can include an oxide semiconductor. For example, the oxide semiconductor can include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ). However, without being limited thereto, the semiconductor pattern SP may include amorphous silicon, low-temperature polycrystalline silicon, or polycrystalline silicon.

[0175] The semiconductor pattern SP can include a source region SR, a drain region DR, and a channel region CR which are classified according to the degree of conductivity. The channel region CR can be a portion that overlaps with the gate electrode GE on a plane. The source region SR and the drain region DR can be portions separated via the channel region CR. When the semiconductor pattern SP is an oxide semiconductor, each of the source region SR and the drain region DR can be a reduced region. Therefore, the source region SR and the drain region DR have a relatively high reduced metal content ratio compared to the channel region CR. Or, when the semiconductor pattern SP is polycrystalline silicon, each of the source region SR and the drain region DR can be a region doped at a high concentration.

[0176] The source region SR and the drain region DR can have relatively high conductivity compared to the channel region CR. The source region SR can be corresponded to the source electrode of the connection transistor TR, and the drain region DR can be corresponded to the drain electrode of the connection transistor TR. As shown in FIG. 5, another source electrode pattern W1 and drain electrode pattern W2 respectively connected to the source region SR and the drain region DR may be further provided. Specifically, the other source electrode pattern W1 and drain electrode pattern W2 can be integrally formed with one of the lines constituting the pixel driving unit (see PDC in FIG. 2A, PDC-1 in FIG. 2B, or PDC-2 in FIG. 2C), and is not limited to any one embodiment.

[0177] The second insulating layer 20 can commonly overlap a plurality of pixels and cover the semiconductor pattern SP. The second insulating layer 20 is an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The second insulating layer 20 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 can be a single-layer silicon oxide layer.

[0178] The gate electrode GE can be disposed on the second insulating layer 20. The gate electrode GE can be corresponded to the gate of the connection transistor TR. Also, the gate electrode GE can be disposed above the semiconductor pattern SP. However, this is shown by way of example, and the gate electrode GE can also be disposed below the semiconductor pattern SP, and is not limited to any one embodiment.

[0179] The gate electrode GE can include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or an alloy thereof, etc., but is not particularly limited thereto.

[0180] A third insulating layer 30 can be disposed on the gate electrode GE. The third insulating layer 30 is an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure.

[0181] Among the plurality of conductive patterns W1, W2, CPE1, CPE2, CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can be separated via the first insulating layer 10 and the second insulating layer 20.

[0182] In one embodiment of the present invention, the first capacitor electrode CPE1 and the lower conductive layer BCL may be integrally formed and have an integral shape. Also, the second capacitor electrode CPE2 and the gate electrode GE may be integrally formed and have an integral shape.

[0183] A third capacitor electrode CPE3 can be disposed on the third insulating layer 30. The third capacitor electrode CPE3 is separated from the second capacitor electrode CPE2 via the third insulating layer 30 and can overlap in a plane. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 can constitute a second capacitor C2.

[0184] A fourth insulating layer 40 can be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 is an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. The fourth insulating layer 40 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0185] A source electrode pattern W1 and a drain electrode pattern W2 can be arranged on the fourth insulating layer 40. The source electrode pattern W1 can be connected to the source region SR of the connection transistor TR through the first contact hole CNT1, and the source electrode pattern W1 and the source region SR of the semiconductor pattern SP can function as the source of the connection transistor TR. The drain electrode pattern W2 can be connected to the drain region DR of the connection transistor TR through the second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP can function as the drain of the connection transistor TR. A fifth insulating layer 50 can be arranged on the source electrode pattern W1 and the drain electrode pattern W2.

[0186] An intermediate connection electrode CN can be arranged on the fifth insulating layer 50. The intermediate connection electrode CN can electrically connect the pixel driving part PDC and the light emitting element LD. That is, the intermediate connection electrode CN can electrically connect the connection transistor TR and the light emitting element. The intermediate connection electrode CN can be a connection node that connects the pixel driving part PDC and the light emitting element LD. That is, the intermediate connection electrode CN can correspond to the fourth node N4 (see FIG. 2A) shown in FIG. 2A, or correspond to the second node N2 (see FIG. 2B) shown in FIG. 2B, or correspond to the fourth node N4 (see FIG. 2C) shown in FIG. 2C.

[0187] The intermediate connection electrode CN can include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along the third direction DR3. The second layer L2 can include a material different from that of the first layer L1. Also, the second layer L2 can include a material different from that of the third layer L3. The second layer L2 can have a relatively thick thickness compared to the first layer L1. Also, the second layer L2 can have a relatively thick thickness compared to the third layer L3. The second layer L2 can include a material with high conductivity. In one embodiment, the second layer L2 can include aluminum (Al).

[0188] A sixth insulating layer 60 can be disposed on the intermediate connection electrode CN. The sixth insulating layer 60 can be disposed on the fifth insulating layer 50 to cover at least a part of the intermediate connection electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 can be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 can include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), and PS (Polystyrene), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0189] The sixth insulating layer 60 can be provided with a through hole OP-60 that exposes at least a part of the intermediate connection electrode CN. The intermediate connection electrode CN can be connected to the connection electrode CNE through a part exposed from the sixth insulating layer 60 and electrically connected to the light-emitting element LD. That is, the intermediate connection electrode CN can electrically connect the connection transistor TR and the light-emitting element LD together with the connection electrode CNE. On the other hand, in the display panel DP according to an embodiment of the present invention, the sixth insulating layer 60 may be omitted or provided in plurality, but is not limited to any one embodiment. When the sixth insulating layer 60 is omitted, the intermediate connection electrode CN can also be omitted.

[0190] According to the present invention, since the lower surface of the connection electrode CNE and the upper surface of the intermediate connection electrode CN are in contact, the contact reliability can be improved. Therefore, the size of the through hole OP-P for connecting the connection electrode CNE and the intermediate connection electrode CN can be reduced or minimized. Therefore, the area and resolution of the light-emitting portion of the display panel DP can be easily increased.

[0191] The light-emitting element layer LDL can be disposed on the driving element layer DDL. The light-emitting element layer LDL can include a pixel definition film PDL and a light-emitting element LD.

[0192] The pixel definition film PDL can be an organic layer. For example, the pixel definition film PDL can include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), and PS (Polystyrene), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0193] In one embodiment, the pixel definition film PDL can have the property of absorbing light and can have, for example, a black color. The pixel definition film PDL can include a black coloring agent. The black coloring agent can include black dyes and black pigments. The black coloring agent can include carbon black, metals such as chromium, or oxides thereof. The pixel definition film PDL can correspond to a light-shielding pattern having light-shielding characteristics.

[0194] An opening OP-PDL (hereinafter, a light-emitting opening) for exposing at least a part of the first electrode EL1 described later can be defined in the pixel definition film PDL. A plurality of light-emitting openings OP-PDL can be provided and arranged corresponding to each light-emitting element. All components of the light-emitting element LD can be superposed and arranged in the light-emitting opening OP-PDL, and it can be a region where the light substantially emitted by the light-emitting element LD is displayed. Therefore, the shape of the first light-emitting portion EP1 (see FIG. 4A) can substantially correspond to the shape of the light-emitting opening OP-PDL on the plane.

[0195] A connection electrode CNE can be arranged on the pixel definition film PDL. The connection electrode CNE can electrically connect the pixel driving part PDC and the light-emitting element LD. That is, the pixel driving part PDC can be electrically connected to the light-emitting element LD via the intermediate connection electrode CN and the connection electrode CNE. The connection electrode CNE can correspond to the first connection electrode CNE1 shown in FIG. 4A. The second connection electrode CNE2 (see FIG. 4A) and the third connection electrode CNE3 (see FIG. 4A) can also have a structure similar to that of the connection electrode CNE in FIG. 5.

[0196] The connection electrode CNE can include a first edge EG1c adjacent to the light-emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The second electrode (which may also be referred to as the cathode) EL2 of the light-emitting element LD can be in contact with the connection electrode CNE in a region adjacent to the second edge EG2c. That is, the second electrode EL2 and the connection electrode CNE can be connected (or in contact) in a region adjacent to the groove GV described later.

[0197] The connection electrode CNE can include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 )). However, the material constituting the connection electrode CNE is not limited to the above examples.

[0198] According to an embodiment of the present invention, the connection electrode CNE has a shape surrounding at least a part of the light-emitting part EP1 (see FIG. 4A) defined in the light-emitting element LD. Therefore, the degrees of freedom of the positions where the connection electrode CNE and the light-emitting element LD are connected and the degrees of freedom of the positions where the connection electrode CNE and the pixel driving part PDC are connected can be improved. Since the connection electrode CNE has a shape surrounding at least a part of the light-emitting part EP1, connection with the light-emitting element LD can be ensured at any position of the connection electrode CNE, and connection with the pixel driving part PDC can be ensured at any position of the connection electrode CNE.

[0199] In addition, since the lower surface of the connection electrode CNE and the upper surface of the intermediate connection electrode CN are in contact, the contact reliability can be improved. Therefore, the sizes of the through holes OP-P and OP-60 for connecting the connection electrode CNE and the intermediate connection electrode CN can be reduced or minimized. Therefore, the area or resolution of the light-emitting portion of the display panel DP can be easily increased.

[0200] A groove GV surrounding the light-emitting opening OP-PDL can be defined in the pixel definition film PDL. The groove GV can be formed by removing a part of the pixel definition film PDL in the thickness direction of the pixel definition film PDL (for example, the third direction DR3). The groove GV can overlap with the gap between two adjacent connection electrodes CNE disposed on the pixel definition film PDL.

[0201] A part of the connection electrode CNE can protrude from the end of the groove GV toward the center of the groove GV. A part of the connection electrode CNE can be defined as a chip portion (tip, end portion) TP. In a cross-sectional view, one end or the other end between the connection electrodes CNE adjacent to each other with the groove GV interposed therebetween corresponds to both ends of the groove GV, and the chip portion TP of the connection electrode CNE is a portion where the connection electrode CNE protrudes toward the center through both ends of the groove GV. That is, the connection electrode CNE can include the chip portion TP. Since the chip portion TP protrudes toward the groove GV, the connection electrode CNE can partially overlap with the groove GV in a plane. The second electrode EL2 of the light-emitting element LD and the connection electrode CNE can be connected (or, in contact) at the chip portion TP.

[0202] In one embodiment, the second electrode EL2 and the functional layer FNL can be formed by being commonly deposited on a plurality of pixels through an open mask. Some of the functional layer FNL can include an organic layer. When the organic layer is formed commonly, lateral leakage current may be generated by the organic layer commonly provided between adjacent pixels, and as a result, color mixing and luminance defects may occur between adjacent pixels. On the other hand, in this specification, the "lateral leakage current" means a current flowing in a direction other than the third direction DR3, which is the stacking direction of the light-emitting element, that is, the direction in which an image is displayed, and intersecting the third direction DR3. The lateral leakage current can mean a current flowing in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0203] According to the present invention, in order to prevent lateral leakage current from occurring between adjacent pixels, the intermediate layer IML and the second electrode EL2 can be separated for each pixel by the chip portion TP of the connection electrode CNE. In other words, the intermediate layer IML and the second electrode EL2 are separated for each pixel via the groove GV. Therefore, it is possible to prevent the occurrence of lateral leakage current, prevent color mixing between adjacent pixel regions, and prevent luminance degradation. The chip portion TP of the connection electrode CNE can have a closed line shape with respect to each light-emitting portion, and therefore the second electrode EL2 and the functional layer FNL can have a shape divided for each light-emitting portion. That is, the second electrode EL2 and the intermediate layer IML can be electrically independent for each adjacent pixel.

[0204] The chip portion TP can have an inverse taper shape. That is, the taper angle formed by the lower surface and the side surface of the connection electrode CNE can be an obtuse angle. However, this is merely exemplary, and the taper angle can be set in various ways as long as the chip portion TP of the connection electrode CNE can electrically disconnect the second electrode EL2 for each pixel. For example, when the connection electrode CNEa (see FIG. 7) includes only the first connection electrode layer LL1 (see FIG. 7), the taper angle formed by the lower surface and the side surface of the connection electrode CNEa can be an acute angle or a right angle.

[0205] A dummy pattern DMP can be disposed in the groove GV. The dummy pattern DMP can be formed by separating a part of the connection electrode CNE (for example, the second connection electrode layer LL2 (see FIG. 6A)), the second electrode EL2, and the functional layer FNL (shown as the intermediate layer IML in FIG. 6A, and the functional layer FNL is included in the intermediate layer IML) by the chip portion TP of the connection electrode CNE. However, this is merely exemplary and not limited thereto. A detailed description will be given later with reference to FIGS. 6A to 9.

[0206] Through holes OP-P spaced apart from the light-emitting opening OP-PDL can be defined in the pixel definition film PDL. A plurality of through holes OP-P can be provided and arranged corresponding to each light-emitting element. The size of the through hole OP-P defined in the pixel definition film PDL can be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connection electrode CNE can be disposed in the through holes OP-P and OP-60 and connected to the intermediate connection electrode CN. That is, the connection electrode CNE can be connected to the pixel driving unit PDC through the through holes OP-P and OP-60. In the example of FIG. 5, the through hole OP-P is formed so as to be continuous in the third direction DR3 of the through hole OP-60. When the through holes OP-60 and OP-P are integrated and referred to as the through hole OP-P, it can be said that the connection electrode CNE is connected to the pixel driving unit PDC through the through hole OP-P.

[0207] The light-emitting element LD can include a first electrode EL1, an intermediate layer IML, and a second electrode EL2.

[0208] The first electrode EL1 can be a semi-transmissive, transmissive, or reflective electrode. According to an embodiment of the present invention, the first electrode EL1 can include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, etc., and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer can comprise at least one or more selected from the group including indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ), and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 can include a stacked structure of ITO / Ag / ITO.

[0209] In this embodiment, the first electrode EL1 can be the anode of the light-emitting element LD. That is, the first electrode EL1 can be connected to a first power supply line VDL (see FIG. 2A), and a first power supply voltage VDD (see FIG. 2A) can be applied. The first electrode EL1 can be connected to the first power supply line VDL within the display area DA (see FIG. 3A or FIG. 3B), or can be connected to the first power supply line VDL in the peripheral area NDA. In the latter case, the first power supply line VDL is disposed in the peripheral area NDA (see FIG. 3A or FIG. 3B), and the first electrode EL1 can have a shape extended to the peripheral area NDA.

[0210] In the cross-sectional view of FIG. 5, the first electrode EL1 is illustrated as overlapping the light-emitting aperture OP-PDL and not overlapping the groove GV. However, as described above with reference to FIG. 4D, the first electrode EL1 of the light-emitting element has an integral shape and can have a mesh or lattice shape in which an aperture is defined in a partial region. That is, if the same first power supply voltage VDD is applied to the first electrode EL1 of each of the plurality of light-emitting elements, the shape of the first electrode EL1 can be provided in various forms and is not limited to any one embodiment.

[0211] The intermediate layer IML can be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML can include a light-emitting layer EML and a functional layer FNL having an area larger than that of the light-emitting layer EML. The light-emitting element LD can include intermediate layers IML having various structures and is not limited to any one embodiment. For example, the functional layer FNL can be provided by a plurality of layers or by two or more layers separated via the light-emitting layer EML.

[0212] The light-emitting layer EML can include an organic light-emitting material. Further, the light-emitting layer EML can include an inorganic light-emitting material or can be provided as a mixed layer of an organic light-emitting material and an inorganic light-emitting material. The light-emitting layer EML included in each adjacent light-emitting portion EP (see FIG. 3A) in the present embodiment can include light-emitting materials that display different colors from each other. For example, the light-emitting layer EML included in each light-emitting portion EP can provide any one of blue, red, and green light. However, it is not limited thereto, and the light-emitting layer EML disposed in all the light-emitting portions EP may include a light-emitting material that displays the same color. In this case, the light-emitting layer EML can provide blue light or white light.

[0213] The functional layer FNL can be disposed between the first electrode EL1 and the second electrode EL2. Specifically, the functional layer FNL can include a first intermediate functional layer disposed between the first electrode EL1 and the light-emitting layer EML, and a second intermediate functional layer disposed between the second electrode EL2 and the light-emitting layer EML. In one embodiment of the present invention, one of the first intermediate functional layer and the second intermediate functional layer can be omitted. In this embodiment, the light-emitting layer EML is illustrated as being inserted into the functional layer FNL. That is, it can be understood that the light-emitting layer EML is disposed between the first intermediate functional layer and the second intermediate functional layer.

[0214] The functional layer FNL can control the movement of charges between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer can include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0215] The second electrode EL2 can be disposed on the intermediate layer IML. As described above, the second electrode EL2 can be connected to the connection electrode CNE and electrically connected to the pixel driving unit PDC. That is, the second electrode EL2 can be electrically connected to the connection transistor TR through the connection electrode CNE.

[0216] A sealing layer ECL can be disposed on the light-emitting element layer LDL. The sealing layer ECL can cover the light-emitting element LD and can cover the groove GV. The sealing layer ECL can include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 laminated in sequence.

[0217] However, without being limited thereto, the encapsulation layer ECL may further include a plurality of inorganic layers and organic layers in addition. For example, the encapsulation layer ECL can include a first encapsulation layer instead of the first inorganic layer. The first encapsulation layer can include a plurality of sub-encapsulation layers. At least a part of the plurality of sub-encapsulation layers can include an organic substance. For example, the first encapsulation layer can include a first sub-encapsulation layer, a second sub-encapsulation layer, and a third sub-encapsulation layer. The first and third sub-encapsulation layers can include an inorganic substance, and the second sub-encapsulation layer can include an organic substance. Even if a gap is formed in the first sub-encapsulation layer which is an inorganic layer, the gap can be filled by the second sub-encapsulation layer.

[0218] The first encapsulation layer can gently cover the chip portion TP of the groove GV and the connection electrode CNE defined in the pixel definition film PDL. Therefore, the protection function of the encapsulation layer for protecting the light-emitting element LD can be improved. However, without being limited thereto, the encapsulation layer ECL can be a glass substrate.

[0219] The first and second inorganic layers IL1, IL2 protect the light-emitting element LD from moisture and oxygen outside the display panel DP, and the organic layer OL can protect the light-emitting element LD from foreign substances such as particles remaining in the process of forming the first inorganic layer IL1. The first and second inorganic layers IL1, IL2 can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic layer OL can include an acrylic series organic layer, and the type of the substance is not limited to any one.

[0220] The sensing layer ISL can sense external inputs. In this embodiment, the sensing layer ISL can be formed on the encapsulation layer ECL through a continuous process. At this time, the sensing layer ISL can be expressed as being directly disposed on the encapsulation layer ECL. Being directly disposed can mean that no other components are disposed between the sensing layer ISL and the encapsulation layer ECL. That is, it is possible that no other adhesive member is disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is only shown by way of example. In the display panel DP according to an embodiment of the present invention, the sensing layer ISL can also be formed separately and then coupled to the display panel DP through an adhesive member, and is not limited to any one embodiment.

[0221] The sensing layer ISL can include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers can include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers can include first to third sensing insulating layers 71, 72, and 73. However, this is only shown by way of example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0222] Each of the first to third sensing insulating layers 71, 72, and 73 can have a single-layer structure or a multilayer structure laminated along the third direction DR3. The first to third sensing insulating layers 71, 72, and 73 can include an inorganic film. The inorganic film can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulating layers 71, 72, and 73 can include an organic film. The organic film can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0223] The first sensing conductive layer MTL1 is disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 can be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A part of the second sensing conductive layer MTL2 can be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can have a single-layer structure or a multilayer structure stacked along the third direction DR3.

[0224] The sensing conductive layer with a single-layer structure can include a metal layer or a transparent conductive layer. The metal layer can include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer can include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer can include conductive polymers such as PEDOT, metal nanowires, graphene, etc.

[0225] The sensing conductive layer with a multilayer structure can include a metal layer. The metal layer can have a three-layer structure of, for example, titanium (Ti) / aluminum (Al) / titanium (Ti). Alternatively, the sensing conductive layer with a multilayer structure can include at least one metal layer and at least one transparent conductive layer.

[0226] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can form a sensor for sensing an external input in the sensing layer ISL. The sensor can be driven in a capacitance mode and can be driven by either a mutual-capacitance mode or a self-capacitance mode. However, this is only an illustrative description, and the sensor can also be driven by a resistance film mode, an ultrasonic mode, or an infrared mode in addition to the capacitance mode, and is not limited to any one embodiment.

[0227] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide and may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can have various materials and various shapes as long as the visibility of the video displayed by the display panel DP is not reduced, and is not limited to any one embodiment.

[0228] FIG. 6A is a cross-sectional view showing an enlarged partial region of the display panel DP according to an embodiment of the present invention. FIG. 6A illustrates a cross-sectional view of the AA' region in FIG. 5 enlarged.

[0229] Referring to FIGS. 5 and 6A, the connection electrode CNE may include a first connection electrode layer LL1 disposed on the pixel definition film PDL and a second connection electrode layer LL2 disposed on the first connection electrode layer LL1. The second connection electrode layer LL2 can cover the first connection electrode layer LL1. For example, the second connection electrode layer LL2 can be formed to cover the upper surface and the side surface S_LL1 of the first connection electrode layer LL1. Therefore, the side surface S_LL1 of the first connection electrode layer LL1 may not be exposed to the outside. The end of the first connection electrode layer LL1 and the end of the second connection electrode layer LL2 covering the end of the first connection electrode layer LL1 can constitute the chip portion TP of the connection electrode CNE.

[0230] The second connection electrode layer LL2 can be patterned by the end of the first connection electrode layer LL1, and a part of the second connection electrode layer LL2 can be disposed within the groove GV. By disposing and patterning the second connection electrode layer LL2 on the first connection electrode layer LL1, the connection electrode CNE can have an inverse taper shape. For example, the taper angle formed by the lower surface of the first connection electrode layer LL1 and the side surface S_LL1 of the first connection electrode layer LL1 can be an acute angle or a right angle. By patterning the second connection electrode layer LL2 by the protruding end of the first connection electrode layer LL1, the second connection electrode layer LL2 can gently surround the side surface S_LL1 of the first connection electrode layer LL1, and the chip portion TP of the connection electrode CNE can have an inverse taper shape. Referring to FIG. 6A, at the end of the second connection electrode layer LL2, the taper angle formed by the lower surface of the first connection electrode layer LL1, that is, the lower surface of the connection electrode CNE, and the lower side surface that faces upward from the lower surface among the upper surface and the side surface S_LL2 can be an obtuse angle. Referring to FIG. 6A, at the end of the second connection electrode layer LL2, the taper angle formed by the lower surface of the first connection electrode layer LL1 and the upper side surface that faces upward from the lower side surface among the upper surface and the side surface S_LL2 can be an acute angle. Also, referring to FIG. 6A, the lower surface of the first connection electrode layer LL1 can be substantially parallel to the upper surface among the upper surface and the side surface S_LL2.

[0231] The first connection electrode layer LL1 and the second connection electrode layer LL2 can include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ). However, the materials constituting the first connection electrode layer LL1 and the second connection electrode layer LL2 are not limited to the above examples.

[0232] An intermediate layer IML can be disposed on the second connection electrode layer LL2. The intermediate layer IML can be formed to cover the upper surface and a part of the side surface S_LL2 of the second connection electrode layer LL2. That is, the intermediate layer IML can be formed to cover a part of the end of the second connection electrode layer LL2. The intermediate layer IML can be patterned by the chip portion TP of the connection electrode CNE, and a part of the intermediate layer IML can be disposed in the groove GV.

[0233] A second electrode EL2 can be disposed on the intermediate layer IML. The second electrode EL2 can be formed to cover the upper surface and the side surface S_IML of the intermediate layer IML. The second electrode EL2 can be patterned by the chip portion TP of the connection electrode CNE, and a part of the second electrode EL2 can be disposed in the groove GV. The second electrode EL2 can be connected (or in contact) with the second connection electrode layer LL2. For example, at the chip portion TP of the connection electrode CNE, the end of the second electrode EL2 and a part of the end of the second connection electrode layer LL2 not covered by the intermediate layer IML can be connected (or in contact) with each other.

[0234] A dummy pattern DMP can be disposed in the groove GV. The dummy pattern DMP can include a first divided pattern PP1, a second divided pattern PP2, and a third divided pattern PP3.

[0235] The first divided pattern PP1 can include the same material as the second connection electrode layer LL2. The first divided pattern PP1 can be formed simultaneously with the second connection electrode layer LL2 through one process, and can be formed separated from the second connection electrode layer LL2 by the end of the first connection electrode layer LL1.

[0236] The second divided pattern PP2 can include the same material as the intermediate layer IML. The second divided pattern PP2 can be formed simultaneously with the intermediate layer IML through one process, and can be formed separated from the intermediate layer IML by the chip portion TP of the connection electrode CNE.

[0237] The third division pattern PP3 can include the same material as the second electrode EL2. The third division pattern PP3 can be formed simultaneously with the second electrode EL2 through one process and can be formed separately from the second electrode EL2 by the chip portion TP of the connection electrode CNE. At this time, the first division pattern PP1 and the third division pattern PP3 can be electrically connected within the groove GV.

[0238] FIG. 6B is a plan view showing an enlarged partial region of the display panel DP (see FIG. 3A) according to an embodiment of the present invention, and FIG. 6C is a cross-sectional view showing an enlarged partial region of the display panel DP according to an embodiment of the present invention. FIG. 6B illustrates a plan view of an enlarged XX' region of FIG. 3A, and FIG. 6C illustrates a cross-sectional view taken along the Y-Y' cutting line of FIG. 6B. FIGS. 6B and 6C illustrate the outside of the display panel DP.

[0239] Referring to FIGS. 6A to 6C, the connection electrode CNE may not be disposed at the boundary between the display area DA (see FIG. 3A) and the non-display area NDA (also referred to as the peripheral area NDA in some cases) of the display panel DP. That is, a part of the chip portion TP of the connection electrode CNE may not be formed outside the display panel DP. For example, the chip portion N_TP (hereinafter, the outer chip portion) of the connection electrode CNE formed outside the display panel DP can be formed adjacent to the region where the light emitting portions EP1, EP2, and EP3 are disposed, and may not be formed in the region where the light emitting portions EP1, EP2, and EP3 are not disposed. An outer groove N_GV can be formed in the region where the outer chip portion N_TP is not formed. The outer groove N_GV can be formed along the boundary between the display area DA and the non-display area NDA. The outer groove N_GV can have a shape connected to the groove GV formed between the light emitting portions EP1, EP2, and EP3.

[0240] An outer dummy pattern N_DMP can be disposed in the outer groove N_GV. The outer dummy pattern N_DMP can include a first outer division pattern N_PP1, a second outer division pattern N_PP2, and a third outer division pattern N_PP3.

[0241] The first outer division pattern N_PP1 can include the same material as the second connection electrode layer LL2. The first outer division pattern N_PP1 can be formed simultaneously with the second connection electrode layer LL2 through one process and can be formed separately from the second connection electrode layer LL2 by the end of the first connection electrode layer LL1. The first outer division pattern N_PP1 can have an integrated shape connected to the first division pattern PP1.

[0242] The second outer division pattern N_PP2 can include the same material as the intermediate layer IML. The second outer division pattern N_PP2 can be formed simultaneously with the intermediate layer IML through one process and can be formed separately from the intermediate layer IML by the outer tip portion N_TP of the connection electrode CNE. The second outer division pattern N_PP2 can have an integrated shape connected to the second division pattern PP2.

[0243] The third outer division pattern N_PP3 can include the same material as the second electrode EL2. The third outer division pattern N_PP3 can be formed simultaneously with the second electrode EL2 through one process and can be formed separately from the second electrode EL2 by the outer tip portion N_TP of the connection electrode CNE. The third outer division pattern N_PP3 can have an integrated shape connected to the third division pattern PP3.

[0244] A first power supply voltage VDD, which is a constant voltage, can be applied to the third outer division pattern N_PP3. The first outer division pattern N_PP1 and the third outer division pattern N_PP3 can be electrically connected within the outer groove N_GV. Therefore, the first power supply voltage VDD can be applied to the first outer division pattern N_PP1. Since the outer groove N_GV has a shape connected to the groove GV formed between the light emitting portions EP1, EP2, and EP3, the first power supply voltage VDD can be applied to the first division pattern PP1 and the third division pattern PP3 disposed within the groove GV.

[0245] According to the present invention, by applying a first power supply voltage VDD, which is a constant voltage, to a first division pattern PP1 and a first outer division pattern N_PP1, noise coupling generated by the first division pattern PP1 and the first outer division pattern N_PP1 can be reduced or removed.

[0246] FIG. 7 is a cross-sectional view showing an enlarged partial region of a display panel DP according to an embodiment of the present invention. FIG. 7 illustrates a cross-sectional view of the AA' region in FIG. 5 enlarged. Hereinafter, when explaining FIG. 7, the same / similar reference numerals are used for the same / similar configurations as those described in FIGS. 1 to 6C, and redundant explanations are omitted.

[0247] Referring to FIGS. 5 and 7, the connection electrode CNEa can be disposed on the pixel definition film PDL. The connection electrode CNEa can electrically connect the pixel driving unit PDC and the light emitting element LD. The connection electrode CNEa can include a first connection electrode layer LL1 disposed on the pixel definition film PDL. That is, the connection electrode CNEa may be obtained by omitting the second connection electrode layer LL2 (see FIG. 6A) from the connection electrode CNE in FIG. 6A. The end of the first connection electrode layer LL1 can form the chip portion TPa of the connection electrode CNEa. In this case, the taper angle formed by the lower surface and the side surface of the connection electrode CNEa can be an acute angle or a right angle. However, it is not limited thereto, and the chip portion TPa can have an inverse taper shape. That is, the taper angle formed by the lower surface and the side surface of the connection electrode CNEa can be an obtuse angle.

[0248] An intermediate layer IML can be disposed on the first connection electrode layer LL1. The intermediate layer IML can be formed to cover the upper surface and a part of the side surface S_LL1 of the first connection electrode layer LL1. The intermediate layer IML can be patterned by the chip portion TPa of the connection electrode CNEa, and a part of the intermediate layer IML can be disposed in the groove GV.

[0249] The second electrode EL2 can be disposed on the intermediate layer IML. The second electrode EL2 can be formed to cover the upper surface and the side surface S_IML of the intermediate layer IML. The second electrode EL2 can be patterned by the chip portion TPa of the connection electrode CNEa, and a part of the second electrode EL2 can be disposed in the groove GV. The second electrode EL2 can be connected (or in contact) with the first connection electrode layer LL1. For example, at the chip portion TPa of the connection electrode CNEa, the end of the second electrode EL2 and a part of the end of the first connection electrode layer LL1 not covered by the intermediate layer IML can be connected (or in contact).

[0250] A dummy pattern DMPa can be disposed in the groove GV. The dummy pattern DMPa can include a first divided pattern PP1a and a second divided pattern PP2a.

[0251] The first divided pattern PP1a can include the same material as the intermediate layer IML. The first divided pattern PP1a can be formed simultaneously with the intermediate layer IML through one process and can be formed separately from the intermediate layer IML by the chip portion TPa of the connection electrode CNEa.

[0252] The second divided pattern PP2a can include the same material as the second electrode EL2. The second divided pattern PP2a can be formed simultaneously with the second electrode EL2 through one process and can be formed separately from the second electrode EL2 by the chip portion TPa of the connection electrode CNEa.

[0253] FIG. 8 is a cross-sectional view showing an enlarged partial region of the display panel DP according to an embodiment of the present invention. FIG. 8 illustrates a cross-sectional view of an enlarged AA' region of FIG. 5. Hereinafter, in describing FIG. 8, the same / similar reference numerals are used for the same / similar configurations as those described in FIGS. 1 to 7, and the repeated description is omitted.

[0254] Referring to FIGS. 5 and 8, the pixel definition film PDLa can include a first pixel definition film portion PDL1 and a second pixel definition film portion PDL2. The first pixel definition film portion PDL1 and the second pixel definition film portion PDL2 can be formed in one step and can have an integral shape. The first pixel definition film portion PDL1 can be disposed on the sixth insulating layer 60, and the second pixel definition film portion PDL2 can be disposed on the first pixel definition film portion PDL1. The first pixel definition film portion PDL1 can correspond to the pixel definition film PDL in FIG. 6A. The second pixel definition film portion PDL2 can have a shape that partially protrudes in the thickness direction (e.g., the third direction DR3) from the first pixel definition film portion PDL1. The groove GV can be defined in the second pixel definition film portion PDL2.

[0255] The connection electrode CNEb can be disposed on the pixel definition film PDLa. The connection electrode CNEb can electrically connect the pixel driving portion PDC and the light emitting element LD. The connection electrode CNEb can include a first connection electrode layer LL1a disposed on the pixel definition film PDLa and a second connection electrode layer LL2a disposed on the first connection electrode layer LL1a. The second connection electrode layer LL2a can cover the first connection electrode layer LL1a. For example, the second connection electrode layer LL2a can be formed to cover the upper surface and the side surface S_LL1a of the first connection electrode layer LL1a. Therefore, the side surface S_LL1a of the first connection electrode layer LL1a may not be exposed to the outside. The end portion of the second connection electrode layer LL2a that covers the end of the first connection electrode layer LL1a and the end of the first connection electrode layer LL1a can constitute the chip portion TPb of the connection electrode CNEb.

[0256] The second connection electrode layer LL2a can be patterned by the end of the first connection electrode layer LL1a, and a part of the second connection electrode layer LL2a can be disposed in the groove GV. By disposing and patterning the second connection electrode layer LL2a on the first connection electrode layer LL1a, the connection electrode CNEb can have an inverse taper shape. For example, the taper angle formed by the lower surface of the first connection electrode layer LL1a and the side surface S_LL1a of the first connection electrode layer LL1a can be an acute angle or a right angle. By patterning the second connection electrode layer LL2a by the protruding end of the first connection electrode layer LL1a, the second connection electrode layer LL2a can gently surround the side surface S_LL1a of the first connection electrode layer LL1a, and the chip portion TPb of the connection electrode CNEb can have an inverse taper shape. Further, by including the second pixel definition film portion PDL2 protruding from the first pixel definition film portion PDL1 in the pixel definition film PDLa, the chip portion TPb of the connection electrode CNEb can have an inverse taper shape due to the gradient of the second pixel definition film portion PDL2. Referring to FIG. 8, at the end of the second connection electrode layer LL2a, the taper angle formed by the lower surface of the first connection electrode layer LL1a, that is, the lower surface of the connection electrode CNEb, and the lower side surface facing upward from the lower surface among the upper surface and the side surface S_LL2a can be an obtuse angle. Referring to FIG. 8, at the end of the second connection electrode layer LL2a, the taper angle formed by the lower surface of the first connection electrode layer LL1a and the upper side surface facing upward from the lower side surface among the upper surface and the side surface S_LL2a can be an acute angle. Referring to FIG. 8, the lower surface of the first connection electrode layer LL1a can be substantially parallel to the upper surface among the upper surface and the side surface S_LL2a.

[0257] The first connection electrode layer LL1a and the second connection electrode layer LL2a can include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ). However, the materials constituting the first connection electrode layer LL1a and the second connection electrode layer LL2a are not limited to the above examples.

[0258] An intermediate layer IML can be disposed on the second connection electrode layer LL2a. The intermediate layer IML can be formed to cover the upper surface of the second connection electrode layer LL2a and a part of the side surface S_LL2a. That is, the intermediate layer IML can be formed to cover the end portion of the second connection electrode layer LL2a. The intermediate layer IML can be patterned by the chip portion TPb of the connection electrode CNEb, and a part of the intermediate layer IML can be disposed in the groove GV.

[0259] A second electrode EL2 can be disposed on the intermediate layer IML. The second electrode EL2 can be formed to cover the upper surface and the side surface S_IML of the intermediate layer IML. The second electrode EL2 can be patterned by the chip portion TPb of the connection electrode CNEb, and a part of the second electrode EL2 can be disposed in the groove GV. The second electrode EL2 can be connected (or in contact) with the second connection electrode layer LL2a. For example, at the chip portion TPb of the connection electrode CNEb, the end of the second electrode EL2 and a part of the end of the second connection electrode layer LL2a not covered by the intermediate layer IML can be connected (or in contact) with each other.

[0260] A dummy pattern DMPb can be disposed in the groove GV. The dummy pattern DMPb can include a first divided pattern PP1, a second divided pattern PP2, and a third divided pattern PP3. The first divided pattern PP1, the second divided pattern PP2, and the third divided pattern PP3 can be substantially the same as the first divided pattern PP1, the second divided pattern PP2, and the third divided pattern PP3 in FIG. 6A, respectively.

[0261] FIG. 9 is a cross-sectional view showing an enlarged partial region of a display panel DP according to an embodiment of the present invention. FIG. 9 illustrates a cross-sectional view of the AA' region in FIG. 5 enlarged. Hereinafter, in describing FIG. 9, the same / similar reference numerals are used for the same / similar configurations as those described in FIGS. 1 to 8, and the repeated descriptions are omitted.

[0262] Referring to FIGS. 5 and 9, the pixel definition film PDLa can include a first pixel definition film portion PDL1 and a second pixel definition film portion PDL2. The connection electrode CNEc can be disposed on the pixel definition film PDLa. The connection electrode CNEc can electrically connect the pixel driving portion PDC and the light-emitting element LD. The connection electrode CNEc can include a first connection electrode layer LL1a disposed on the pixel definition film PDLa. That is, the connection electrode CNEc may be obtained by omitting the second connection electrode layer LL2a (see FIG. 8) from the connection electrode CNEb in FIG. 8. The end of the first connection electrode layer LL1a can constitute the chip portion TPc of the connection electrode CNEc. In this case, the taper angle formed by the lower surface and the side surface of the connection electrode CNEc can be an acute angle or a right angle. However, it is not limited thereto, and the chip portion TPc can have an inverse taper shape. For example, by including the second pixel definition film portion PDL2 protruding from the first pixel definition film portion PDL1 in the pixel definition film PDLa, the chip portion TPc of the connection electrode CNEc can have an inverse taper shape due to the gradient of the second pixel definition film portion PDL2. That is, the taper angle formed by the lower surface and the side surface of the connection electrode CNEc can be an obtuse angle.

[0263] An intermediate layer IML can be disposed on the first connection electrode layer LL1a. The intermediate layer IML can be formed to cover the upper surface and a part of the side surface S_LL1a of the first connection electrode layer LL1a. The intermediate layer IML can be patterned by the chip portion TPc of the connection electrode CNEc, and a part of the intermediate layer IML can be disposed in the groove GV.

[0264] The second electrode EL2 can be disposed on the intermediate layer IML. The second electrode EL2 can be formed to cover the upper surface and the side surface S_IML of the intermediate layer IML. The second electrode EL2 can be patterned by the chip portion TPc of the connection electrode CNEc, and a part of the second electrode EL2 can be disposed within the groove GV. The second electrode EL2 can be connected (or in contact) with the first connection electrode layer LL1a. For example, at the chip portion TPc of the connection electrode CNEc, the end of the second electrode EL2 and a part of the end of the first connection electrode layer LL1a not covered by the intermediate layer IML can be connected (or in contact).

[0265] A dummy pattern DMPc can be disposed within the groove GV. The dummy pattern DMPc can include a first divided pattern PP1a and a second divided pattern PP2a. The first divided pattern PP1a and the second divided pattern PP2a can be substantially identical to the first divided pattern PP1a and the second divided pattern PP2a in FIG. 7, respectively.

[0266] FIGS. 10A to 10F are cross-sectional views showing a part during the steps of a display panel manufacturing method according to an embodiment of the present invention. In explaining FIGS. 10A to 10F, the same / similar reference numerals are used for the same / similar configurations with reference to FIGS. 1 to 6C, and repeated explanations are omitted. The display panel formed by the display panel manufacturing method of FIGS. 10A to 10F can correspond to FIG. 6A.

[0267] According to an embodiment of the present invention, there can be included steps of preparing a preliminary display panel including a base layer, a driving element layer disposed on the base layer, and a pixel definition film disposed on the driving element layer, depositing a first connection electrode layer on the preliminary display panel, etching (etching) a part of the first connection electrode layer and a part of the pixel definition film to form a groove of the pixel definition film that overlaps a part of the first connection electrode layer, etching the first connection electrode layer to form a connection electrode, and forming an intermediate layer and a cathode on the connection electrode and the pixel definition film.

[0268] Referring to FIG. 10A, the display panel manufacturing method of the present invention may include a step of preparing a preliminary display panel DP_I and a step of depositing a first connection electrode layer LL1. The preliminary display panel DP_I may include a base layer BS, a driving element layer DDL disposed on the base layer BS, and a pixel definition film PDL disposed on the driving element layer DDL.

[0269] The base layer BS may be a member that provides a base surface on which a pixel driving part PDC (see FIG. 5) is disposed. The driving element layer DDL may be formed by forming an insulating layer, a semiconductor layer, and a conductive layer by means such as coating and deposition, and selectively patterning the insulating layer, the semiconductor layer, and the conductive layer by photolithography and etching processes to form a semiconductor pattern, a conductive pattern, signal lines, etc. It may be formed through a normal circuit element manufacturing process. The driving element layer DDL may include first to sixth insulating layers 10, 20, 30, 40, 50, 60 (see FIG. 5) sequentially laminated on the base layer BS and a pixel driving part PDC.

[0270] The pixel definition film PDL can be formed on the driving element layer DDL. A preliminary pixel definition film can be deposited on the driving element layer DDL and selectively patterned by photolithography and etching processes to form a pixel definition film PDL in which a light emitting opening OP-PDL (see FIG. 5) and a through hole OP-P (see FIG. 5) are defined.

[0271] The first connection electrode layer LL1 can be deposited on the preliminary display panel DP_I. The step of depositing the first connection electrode layer LL1 can be carried out in a deposition process of a conductive material. The conductive material forming the first connection electrode layer LL1 can include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) and other transparent conductive oxides (TCO). However, the material constituting the first connection electrode layer LL1 is not limited to the above examples.

[0272] Thereafter, the method for manufacturing a display panel according to the present invention may include a step of forming a first photoresist layer PR1. The first photoresist layer PR1 can be formed on the first connection electrode layer LL1. The first photoresist layer PR1 can be formed by forming a preliminary photoresist layer on the first connection electrode layer LL1 and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a first photoresist layer PR1 including a first photo opening OP_PR1 can be formed.

[0273] Thereafter, referring to FIGS. 10B and 10C, the method for manufacturing a display panel according to the present invention may include a step of forming a groove GV of the pixel definition layer PDL that overlaps a part of the first connection electrode layer LL1.

[0274] Referring to FIG. 10B, the step of forming the groove GV of the pixel definition layer PDL may include a step of etching a part of the first connection electrode layer LL1. The etching step of the first connection electrode layer LL1 may be wet etching. A part of the etched first connection electrode layer LL1 can be removed to form a first opening OP_LL1 in the first connection electrode layer LL1. The first opening OP_LL1 can overlap the first photo opening OP_PR1 of the first photoresist layer PR1. The end of the first connection electrode layer LL1 that defines the first opening OP_LL1 can have a tapered shape. For example, the taper angle formed by the lower surface and the side surface of the first connection electrode layer LL1 can be an acute angle or a right angle. However, it is not limited thereto.

[0275] Thereafter, referring to FIG. 10C, the step of forming the groove GV in the pixel definition film PDL can include the step of etching a part of the pixel definition film PDL. The etching step of the pixel definition film PDL can be dry etching. A part of the etched pixel definition film PDL can be removed to form the groove GV in the pixel definition film PDL. The groove GV can overlap with the first opening OP_LL1 of the first connection electrode layer LL1 and the first photo opening OP_PR1 of the first photoresist layer PR1. The groove GV can overlap with a part of the first connection electrode layer LL1. That is, a part of the first connection electrode layer LL1 can protrude from the end (the edge of the groove GV) of the groove GV toward the center of the groove GV. For example, as shown in FIG. 10C, the first connection electrode layer LL1 extends along the pixel definition film PDL, and in the groove GV, a part of the first connection electrode layer LL1 continues to extend so as to protrude.

[0276] Referring to FIG. 10D, the method for manufacturing a display panel according to the present invention can include the steps of removing the first photoresist layer PR1 (refer to FIG. 10C), depositing the second connection electrode layer LL2, and forming the chip portion TP.

[0277] The second connection electrode layer LL2 can be deposited on the first connection electrode layer LL1. The step of depositing the second connection electrode layer LL2 can be carried out in a deposition process of a conductive material. The conductive material for forming the second connection electrode layer LL2 can include transparent conductive oxides (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) etc. However, the material constituting the second connection electrode layer LL2 is not limited to the above examples. The chip portion TP can be defined by the end of the first connection electrode layer LL1 and the end of the second connection electrode layer LL2 covering the end of the first connection electrode layer LL1.

[0278] The second connection electrode layer LL2 is patterned by the end of the first connection electrode layer LL1, and a part of the second connection electrode layer LL2 can be disposed in the groove GV. For example, in the deposition process where the second connection electrode layer LL2 is deposited on the first connection electrode layer LL1, the second connection electrode layer LL2 is deposited on the upper surface of the first connection electrode layer LL1. Since there is a portion where the first connection electrode layer LL1 does not exist in the groove GV, a part of the second connection electrode layer LL2 is deposited on the upper surface of the pixel definition film PDL in the groove GV corresponding to the end of the first connection electrode layer LL1 (corresponding to the chip portion TP of the connection electrode CNE). At this time, the second connection electrode layer LL2 is deposited so that the end of the second connection electrode layer LL2 protruding in the groove GV covers the end of the first connection electrode layer LL1. A part of the second connection electrode layer LL2 separated from the second connection electrode layer LL2 by the end of the first connection electrode layer LL1 can be defined as the first divided pattern PP1. The first divided pattern PP1 can contain the same material as the second connection electrode layer LL2, and the first divided pattern PP1 can be formed simultaneously with the second connection electrode layer LL2 through one process. A part of the second connection electrode layer LL2 can protrude from the end (edge of the groove GV) of the groove GV toward the center of the groove GV. For example, as shown in FIG. 10E, the second connection electrode layer LL2 extends along the first connection electrode layer LL1, and a part of the second connection electrode layer LL2 continues to extend so as to protrude also in the groove GV.

[0279] Thereafter, the display panel manufacturing method of the present invention can include the step of forming a second photoresist layer PR2. The second photoresist layer PR2 can be formed on the second connection electrode layer LL2. The second photoresist layer PR2 can be formed by forming a preliminary photoresist layer on the second connection electrode layer LL2 and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a second photoresist layer PR2 overlapping the groove GV can be formed.

[0280] Referring to FIG. 10E, the display panel manufacturing method of the present invention can include a step of etching the first connection electrode layer LL1 and the second connection electrode layer LL2 to form a connection electrode CNE. The etching step of the first connection electrode layer LL1 and the second connection electrode layer LL2 can be wet etching. A portion of the first connection electrode layer LL1 and the second connection electrode layer LL2 that does not overlap with the second photoresist layer PR2 (see FIG. 10D) can be etched and removed. The first connection electrode layer LL1 and the second connection electrode layer LL2 remaining after overlapping with the second photoresist layer PR2 can form a connection electrode CNE. Thereafter, the second photoresist layer PR2 can be removed.

[0281] Referring to FIG. 10F, the display panel manufacturing method of the present invention can include a step of forming an intermediate layer IML and a second electrode EL2 (or, cathode) on the connection electrode CNE and the pixel definition layer PDL. Each of the step of forming the intermediate layer IML and the step of forming the second electrode EL2 can be carried out by a vapor deposition process.

[0282] The intermediate layer IML is patterned by the chip portion TP of the connection electrode CNE, and a part of the intermediate layer IML can be disposed within the groove GV. For example, at the stage of forming the intermediate layer IML, the intermediate layer IML is deposited on the upper surfaces of the pixel definition film PDL and the second connection electrode layer LL2. Since there is a portion in the groove GV where the second connection electrode layer LL2 does not exist, a part of the intermediate layer IML is deposited on the upper surface of the first split pattern PP1 within the groove GV corresponding to the end of the second connection electrode layer LL2 (corresponding to the chip portion TP of the connection electrode CNE). At this time, the intermediate layer IML is deposited so that the end of the intermediate layer IML protruding in the groove GV covers a part of the end of the second connection electrode layer LL2. A part of the intermediate layer IML separated from the intermediate layer IML by the chip portion TP of the connection electrode CNE can be defined as the second split pattern PP2. The second split pattern PP2 can contain the same material as the intermediate layer IML, and the second split pattern PP2 can be formed simultaneously with the intermediate layer IML through one process. A part of the intermediate layer IML can protrude from the end of the groove GV (the edge of the groove GV) toward the center of the groove GV. For example, as shown in FIG. 10F, the intermediate layer IML extends along the second connection electrode layer LL2 from the pixel definition film PDL, and also continues to extend so that a part of the intermediate layer IML protrudes within the groove GV.

[0283] The second electrode EL2 is patterned by the chip portion TP of the connection electrode CNE, and a part of the second electrode EL2 can be disposed in the groove GV. For example, in the step of forming the second electrode EL2, the second electrode EL2 is deposited on the upper surface of the intermediate layer IML, and since there is a portion where the intermediate layer IML does not exist in the groove GV, a part of the second electrode EL2 is deposited on the upper surface of the second divided pattern PP2 in the groove GV corresponding to the end of the intermediate layer IML and / or the second connection electrode layer LL2 (corresponding to the chip portion TP of the connection electrode CNE). At this time, the second electrode EL2 is deposited so that the end of the second electrode EL2 protruding in the groove GV covers a part of the end of the intermediate layer IML. A part of the second electrode EL2 separated from the second electrode EL2 by the chip portion TP of the connection electrode CNE can be defined as the third divided pattern PP3. The third divided pattern PP3 can contain the same material as the second electrode EL2, and the third divided pattern PP3 can be formed simultaneously with the second electrode EL2 through one process. The first divided pattern PP1, the second divided pattern PP2, and the third divided pattern PP3 can form a dummy pattern DMP. A part of the second electrode EL2 can protrude from the end of the groove GV (the edge of the groove GV) toward the center of the groove GV. For example, as shown in FIG. 10F, the second electrode EL2 extends along the intermediate layer IML, and in the groove GV, a part of the second electrode EL2 continues to extend so as to protrude.

[0284] FIGS. 11A to 11C are cross-sectional views showing a part during the steps of a display panel manufacturing method according to an embodiment of the present invention. In explaining FIGS. 11A to 11C, the same / similar reference numerals are used for the same / similar configurations with reference to FIGS. 1 to 10F, and the repeated explanations are omitted. The display panel formed by the display panel manufacturing method of FIGS. 11A to 11C can correspond to FIG. 7.

[0285] According to an embodiment of the present invention, a method for manufacturing a display panel may include preparing a preliminary display panel DP_I (see FIG. 10A), depositing a first connection electrode layer LL1, and forming a groove GV of the pixel definition layer PDL that overlaps a part of the first connection electrode layer LL1. The steps of preparing the preliminary display panel DP_I (see FIG. 10A), depositing the first connection electrode layer LL1, and forming the groove GV of the pixel definition layer PDL that overlaps a part of the first connection electrode layer LL1 may be substantially the same as those in FIGS. 10A to 10C.

[0286] Referring to FIG. 11A, the method for manufacturing a display panel according to the present invention may include forming a chip portion TPa and forming a second photoresist layer PR2 after removing the first photoresist layer PR1 (see FIG. 10C). The chip portion TPa may be defined by the end of the first connection electrode layer LL1.

[0287] The second photoresist layer PR2 may be formed on the first connection electrode layer LL1. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the first connection electrode layer LL1 and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 that overlaps the groove GV may be formed.

[0288] Referring to FIG. 11B, the method for manufacturing a display panel according to the present invention may include etching the first connection electrode layer LL1 to form a connection electrode CNEa. The step of etching the first connection electrode layer LL1 may be wet etching. A portion of the first connection electrode layer LL1 that does not overlap the second photoresist layer PR2 (see FIG. 11A) may be etched and removed, and the remaining first connection electrode layer LL1 that overlaps the second photoresist layer PR2 may form the connection electrode CNEa. Thereafter, the second photoresist layer PR2 may be removed.

[0289] Referring to FIG. 11C, the display panel manufacturing method of the present invention can include the step of forming an intermediate layer IML and a second electrode EL2 (or, a cathode) on a connection electrode CNEa and a pixel definition layer PDL. Each of the step of forming the intermediate layer IML and the step of forming the second electrode EL2 can proceed in a vapor deposition process.

[0290] The intermediate layer IML is patterned by a chip portion TPa of the connection electrode CNEa, and a part of the intermediate layer IML can be disposed in a groove GV. For example, in the step of forming the intermediate layer IML, the intermediate layer IML is deposited on the upper surfaces of the pixel definition layer PDL and the first connection electrode layer LL1. Since there is a portion where the first connection electrode layer LL1 does not exist in the groove GV, a part of the intermediate layer IML is deposited on the upper surface of the pixel definition layer PDL in the groove GV corresponding to the end of the first connection electrode layer LL1 (corresponding to the chip portion TPa of the connection electrode CNEa). At this time, the intermediate layer IML is deposited so that the end of the intermediate layer IML protruding in the groove GV covers a part of the end of the first connection electrode layer LL1. A part of the intermediate layer IML separated from the intermediate layer IML by the chip portion TPa of the connection electrode CNEa can be defined as a first divided pattern PP1a. The first divided pattern PP1a can include the same material as the intermediate layer IML, and the first divided pattern PP1a can be formed simultaneously with the intermediate layer IML through one process. A part of the intermediate layer IML can protrude from the end (edge of the groove GV) of the groove GV toward the center of the groove GV. For example, as shown in FIG. 11C, the intermediate layer IML extends along the first connection electrode layer LL1 from the pixel definition layer PDL, and also continues to extend so that a part of the intermediate layer IML protrudes in the groove GV.

[0291] The second electrode EL2 is patterned by the chip portion TPa of the connection electrode CNEa, and a part of the second electrode EL2 can be disposed in the groove GV. For example, in the vapor deposition process in which the second electrode EL2 is vapor-deposited on the first connection electrode layer LL1, the second electrode EL2 is vapor-deposited on the upper surface of the first connection electrode layer LL1, and in the groove GV, there is a portion where the first connection electrode layer LL1 does not exist. Therefore, corresponding to the end of the first connection electrode layer LL1 (corresponding to the chip portion TPa of the connection electrode CNEa), a part of the second electrode EL2 is vapor-deposited on the upper surface of the pixel definition film PDL in the groove GV. At this time, the second electrode EL2 is vapor-deposited so that the end of the second electrode EL2 protruding in the groove GV covers the end of the intermediate layer IML. A part of the second electrode EL2 separated from the second electrode EL2 by the chip portion TPa of the connection electrode CNEa can be defined as the second divided pattern PP2a. The second divided pattern PP2a can contain the same material as the second electrode EL2, and the second divided pattern PP2a can be formed simultaneously with the second electrode EL2 through one process. The first divided pattern PP1a and the second divided pattern PP2a can form the dummy pattern DMPa. A part of the second electrode EL2 can protrude from the end (edge of the groove GV) of the groove GV toward the center of the groove GV. For example, as shown in FIG. 11C, the second electrode EL2 extends along the intermediate layer IML, and in the groove GV, a part of the second electrode EL2 continues to extend so as to protrude.

[0292] FIGS. 12A to 12F are cross-sectional views showing a part of the steps of a display panel manufacturing method according to an embodiment of the present invention. In explaining FIGS. 12A to 12F, the same / similar reference numerals are used for the same / similar configurations with reference to FIGS. 1 to 10F, and the repeated explanations are omitted. The display panel formed by the display panel manufacturing method of FIGS. 12A to 12F can correspond to FIG. 8.

[0293] Referring to FIG. 12A, the display panel manufacturing method of the present invention can include a step of preparing a preliminary display panel DPa_I and a step of depositing a first connection electrode layer LL1a. The preliminary display panel DPa_I can include a base layer BS, a driving element layer DDL disposed on the base layer BS, and a pixel definition film PDLa disposed on the driving element layer DDL.

[0294] The pixel definition film PDLa can be formed on the driving element layer DDL. A preliminary pixel definition film is deposited on the driving element layer DDL and selectively patterned by photolithography and etching processes to form a pixel definition film PDLa including a first pixel definition film portion PDL1 and a second pixel definition film portion PDL2 having a shape partially protruding from the first pixel definition film portion PDL1. The first pixel definition film portion PDL1 and the second pixel definition film portion PDL2 can be formed in one step and can have an integral shape. A halftone mask can be utilized in the above process, but the pixel definition film PDLa forming method is not limited to the above example. Also, a light-emitting opening OP-PDL (see FIG. 5) and a through hole OP-P (see FIG. 5) can be defined in the pixel definition film PDLa.

[0295] The first connection electrode layer LL1a can be deposited on the preliminary display panel DPa_I. Specifically, the first connection electrode layer LL1a can be deposited on the first pixel definition film portion PDL1 and the second pixel definition film portion PDL2 of the pixel definition film PDLa. The step of depositing the first connection electrode layer LL1a can be carried out in a deposition process of a conductive material. The conductive material for forming the first connection electrode layer LL1a can include transparent conductive oxides (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ). However, the material constituting the first connection electrode layer LL1a is not limited to the above example.

[0296] Thereafter, the display panel manufacturing method of the present invention may include a step of forming a first photoresist layer PR1. The first photoresist layer PR1 can be formed on the first connection electrode layer LL1a. The first photoresist layer PR1 can be formed by forming a preliminary photoresist layer on the first connection electrode layer LL1a and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a first photoresist layer PR1 including a first photo opening OP_PR1 can be formed.

[0297] Thereafter, referring to FIGS. 12B and 12C, the display panel manufacturing method of the present invention may include a step of forming a groove GV of the pixel definition film PDLa that overlaps a part of the first connection electrode layer LL1a.

[0298] Referring to FIG. 12B, the step of forming the groove GV of the pixel definition film PDLa may include a step of etching a part of the first connection electrode layer LL1a. The etching step of the first connection electrode layer LL1a may be wet etching. A part of the etched first connection electrode layer LL1a may be removed to form a first opening OP_LL1a in the first connection electrode layer LL1a. The first opening OP_LL1a can overlap the first photo opening OP_PR1 of the first photoresist layer PR1. The end of the first connection electrode layer LL1a that defines the first opening OP_LL1 can have a tapered shape. For example, the taper angle formed by the lower surface and the side surface of the first connection electrode layer LL1a can be an acute angle or a right angle. However, it is not limited thereto.

[0299] Thereafter, referring to FIG. 12C, the step of forming the groove GV of the pixel defining film PDLa can include the step of etching a part of the pixel defining film PDLa. The step of etching the pixel defining film PDLa can be dry etching. A part of the etched pixel defining film PDLa can be removed, and the groove GV can be formed in the pixel defining film PDLa. The groove GV can overlap with the first opening OP_LL1a of the first connection electrode layer LL1a and the first photo opening OP_PR1 of the first photoresist layer PR1. The groove GV can overlap with a part of the first connection electrode layer LL1a. That is, a part of the first connection electrode layer LL1a can protrude from the end (edge of the groove GV) of the groove GV toward the center of the groove GV. For example, as shown in FIG. 12C, the first connection electrode layer LL1a extends along the pixel defining film PDLa, and a part of the first connection electrode layer LL1a continues to extend so as to protrude even within the groove GV.

[0300] Referring to FIG. 12D, the method for manufacturing a display panel according to the present invention can include the steps of removing the first photoresist layer PR1 (see FIG. 12C), depositing the second connection electrode layer LL2a, and forming the chip portion TPb.

[0301] The second connection electrode layer LL2a can be deposited on the first connection electrode layer LL1a. The step of depositing the second connection electrode layer LL2a can be carried out by a deposition process of a conductive material. The conductive material for forming the second connection electrode layer LL2a can include transparent conductive oxides (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) etc. However, the material constituting the second connection electrode layer LL2a is not limited to the above examples. The chip portion TPb can be defined by the end of the first connection electrode layer LL1a and the end of the second connection electrode layer LL2a covering the end of the first connection electrode layer LL1a.

[0302] According to the present invention, by patterning the second connection electrode layer LL2a by the protruding end of the first connection electrode layer LL1a, the second connection electrode layer LL2a can gently surround the side surface S_LL1a of the first connection electrode layer LL1a, and the chip portion TPb of the connection electrode CNEb can have an inverse taper shape. Further, by including the second pixel definition film portion PDL2 protruding from the first pixel definition film portion PDL1 in the pixel definition film PDLa, the chip portion TPb of the connection electrode CNEb can have an inverse taper shape due to the gradient of the second pixel definition film portion PDL2.

[0303] The second connection electrode layer LL2a can be patterned by the end of the first connection electrode layer LL1a such that a part of the second connection electrode layer LL2a can be disposed within the groove GV. For example, in the deposition process of the second connection electrode layer LL2a, the second connection electrode layer LL2a is deposited on the upper surface of the first connection electrode layer LL1a, and since there is a portion where the first connection electrode layer LL1a does not exist in the groove GV, a part of the second connection electrode layer LL2a is deposited on the upper surface of the second pixel definition film portion PDL2 within the groove GV corresponding to the end of the first connection electrode layer LL1a (corresponding to the chip portion TPb of the connection electrode CNEb). At this time, the second connection electrode layer LL2a is deposited such that the end of the second connection electrode layer LL2a protruding in the groove GV covers the end of the first connection electrode layer LL1. A part of the second connection electrode layer LL2a separated from the second connection electrode layer LL2a by the end of the first connection electrode layer LL1a can be defined as the first divided pattern PP1. The first divided pattern PP1 can contain the same material as the second connection electrode layer LL2a, and the first divided pattern PP1 can be formed simultaneously through one process together with the second connection electrode layer LL2a. A part of the second connection electrode layer LL2a can protrude from the end (edge of the groove GV) of the groove GV toward the center of the groove GV. For example, as shown in FIG. 12D, the second connection electrode layer LL2a extends along the first connection electrode layer LL1a, and also continues to extend such that a part of the second connection electrode layer LL2a protrudes within the groove GV.

[0304] Thereafter, the method for manufacturing a display panel of the present invention may include a step of forming a second photoresist layer PR2. The second photoresist layer PR2 can be formed on the second connection electrode layer LL2a. The second photoresist layer PR2 can be formed by forming a preliminary photoresist layer on the second connection electrode layer LL2a and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a second photoresist layer PR2 overlapping with the groove GV can be formed.

[0305] Referring to FIG. 12E, the method for manufacturing a display panel of the present invention may include a step of etching the first connection electrode layer LL1a and the second connection electrode layer LL2a to form a connection electrode CNEb. The etching step of the first connection electrode layer LL1a and the second connection electrode layer LL2a may be wet etching. Portions of the first connection electrode layer LL1a and the second connection electrode layer LL2a that do not overlap with the second photoresist layer PR2 (see FIG. 12D) can be etched away. The first connection electrode layer LL1a and the second connection electrode layer LL2a remaining after overlapping with the second photoresist layer PR2 can form a connection electrode CNEb. Thereafter, the second photoresist layer PR2 can be removed.

[0306] Referring to FIG. 12F, the method for manufacturing a display panel of the present invention may include a step of forming an intermediate layer IML and a second electrode EL2 (or, cathode) on the connection electrode CNEb and the pixel defining film PDLa. Each of the step of forming the intermediate layer IML and the step of forming the second electrode EL2 can be carried out by a vapor deposition process.

[0307] The intermediate IML is patterned by the chip portion TPb of the connection electrode CNEb, and a part of the intermediate IML can be disposed within the groove GV. For example, at the stage of forming the intermediate IML, the intermediate IML is deposited on the upper surfaces of the pixel definition film PDLa and the second connection electrode layer LL2a. Since there is a portion where the second connection electrode layer LL2a does not exist in the groove GV, a part of the intermediate IML is deposited on the upper surface of the first divided pattern PP1 within the groove GV corresponding to the end of the second connection electrode layer LL2a (corresponding to the chip portion TPb of the connection electrode CNEb). At this time, the intermediate IML is deposited such that the end of the intermediate IML protruding in the groove GV covers a part of the end of the second connection electrode layer LL2a. A part of the intermediate IML separated from the intermediate IML by the chip portion TPb of the connection electrode CNEb can be defined as the second divided pattern PP2. The second divided pattern PP2 can contain the same material as the intermediate IML, and the second divided pattern PP2 can be formed simultaneously with the intermediate IML through one process. A part of the intermediate IML can protrude from the end of the groove GV (the edge of the groove GV) toward the center of the groove GV. For example, as shown in FIG. 12F, the intermediate IML extends along the second connection electrode layer LL2a from the pixel definition film PDLa, and also continues to extend such that a part of the intermediate IML protrudes within the groove GV.

[0308] The second electrode EL2 is patterned by the chip portion TPb of the connection electrode CNEb, and a part of the second electrode EL2 can be disposed within the groove GV. For example, at the stage of forming the second electrode EL2, the second electrode EL2 is deposited on the upper surface of the intermediate layer IML. Since there is a portion where the intermediate layer IML does not exist in the groove GV, a part of the second electrode EL2a is deposited on the upper surface of the second divided pattern PP2 within the groove GV corresponding to the end of the intermediate layer IML and / or the second connection electrode layer LL2a (corresponding to the chip portion TPb of the connection electrode CNEb). At this time, the second electrode EL2 is deposited so that the end of the second electrode EL2 protruding in the groove GV covers a part of the end of the intermediate layer IML. A part of the second electrode EL2 separated from the second electrode EL2 by the chip portion TPb of the connection electrode CNEb can be defined as the third divided pattern PP3. The third divided pattern PP3 can contain the same material as the second electrode EL2, and the third divided pattern PP3 can be formed simultaneously with the second electrode EL2 through one process. The first divided pattern PP1, the second divided pattern PP2, and the third divided pattern PP3 can form the dummy pattern DMPb. A part of the second electrode EL2 can protrude from the end (edge of the groove GV) of the groove GV toward the center of the groove GV. For example, as shown in FIG. 12F, the second electrode EL2 extends along the intermediate layer IML, and also continues to extend so that a part of the second electrode EL2 protrudes within the groove GV.

[0309] FIGS. 13A to 13C are cross-sectional views showing a part during the steps of a display panel manufacturing method according to an embodiment of the present invention. In explaining FIGS. 13A to 13C, the same / similar reference numerals are used for the same / similar configurations with reference to FIGS. 1 to 12F, and the repeated explanations are omitted. The display panel formed by the display panel manufacturing method of FIGS. 13A to 13C can correspond to FIG. 9.

[0310] According to an embodiment of the present invention, a method for manufacturing a display panel may include the steps of preparing a preliminary display panel DPa_I (see FIG. 12A), depositing a first connection electrode layer LL1a, and forming a groove GV of the pixel definition film PDLa that overlaps a part of the first connection electrode layer LL1a. The steps of preparing the preliminary display panel DPa_I (see FIG. 12A), depositing the first connection electrode layer LL1a, and forming the groove GV of the pixel definition film PDLa that overlaps a part of the first connection electrode layer LL1a may be substantially the same as those in FIGS. 12A to 12C.

[0311] Referring to FIG. 13A, the method for manufacturing a display panel according to the present invention may include the steps of forming a chip portion TPc and forming a second photoresist layer PR2 after removing the first photoresist layer PR1 (see FIG. 12C). The chip portion TPc may be defined by the end of the first connection electrode layer LL1a.

[0312] According to the present invention, since the pixel definition film PDLa includes a second pixel definition film portion PDL2 protruding from the first pixel definition film portion PDL1, the chip portion TPc of the connection electrode CNEc can have an inverse taper shape due to the gradient of the second pixel definition film portion PDL2.

[0313] The second photoresist layer PR2 can be formed on the first connection electrode layer LL1a. The second photoresist layer PR2 can be formed by forming a preliminary photoresist layer on the first connection electrode layer LL1a and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 overlapping the groove GV can be formed.

[0314] Referring to FIG. 13B, the display panel manufacturing method of the present invention can include a step of etching the first connection electrode layer LL1a to form a connection electrode CNEc. The step of etching the first connection electrode layer LL1a can be wet etching. A portion of the first connection electrode layer LL1a that does not overlap with the second photoresist layer PR2 (see FIG. 13A) can be etched and removed, and the first connection electrode layer LL1a remaining after overlapping with the second photoresist layer PR2 can form the connection electrode CNEc. Thereafter, the second photoresist layer PR2 can be removed.

[0315] Referring to FIG. 13C, the display panel manufacturing method of the present invention can include a step of forming an intermediate layer IML and a second electrode EL2 (or, cathode) on the connection electrode CNEc and the pixel defining film PDLa. Each of the step of forming the intermediate layer IML and the step of forming the second electrode EL2 can be carried out by a vapor deposition process.

[0316] The intermediate IML is patterned by the chip portion TPc of the connection electrode CNEc, and a part of the intermediate IML can be disposed within the groove GV. For example, at the stage of forming the intermediate IML, the intermediate IML is deposited on the upper surfaces of the pixel definition film PDLa and the first connection electrode layer LL1a. Since there is a portion where the first connection electrode layer LL1a does not exist in the groove GV, a part of the intermediate IML is deposited on the upper surface of the pixel definition film PDLa within the groove GV corresponding to the end of the first connection electrode layer LL1a (corresponding to the chip portion TPc of the connection electrode CNEc). At this time, the intermediate IML is deposited so that the end of the intermediate IML covers a part of the end of the first connection electrode layer LL1a. A part of the intermediate IML separated from the intermediate IML by the chip portion TPc of the connection electrode CNEc can be defined as the first divided pattern PP1a. The first divided pattern PP1a can contain the same material as the intermediate IML, and the first divided pattern PP1a can be formed simultaneously with the intermediate IML through one process. A part of the intermediate IML can protrude from the end (edge portion of the groove GV) of the groove GV toward the center of the groove GV. For example, as shown in FIG. 13C, the intermediate IML extends along the first connection electrode layer LL1a from the pixel definition film PDLa, and also continues to extend so that a part of the intermediate IML protrudes within the groove GV.

[0317] The second electrode EL2 is patterned by the chip portion TPc of the connection electrode CNEc, and a part of the second electrode EL2 can be disposed in the groove GV. For example, in the vapor deposition process in which the second electrode EL2 is vapor deposited on the first connection electrode layer LL1a, the second electrode EL2 is vapor deposited on the upper surface of the first connection electrode layer LL1a, and in the groove GV, there is a portion where the first connection electrode layer LL1a does not exist. Therefore, corresponding to the end of the first connection electrode layer LL1a (corresponding to the chip portion TPc of the connection electrode CNEc), a part of the second electrode EL2 is vapor deposited on the upper surface of the pixel defining film PDLa in the groove GV. At this time, the second electrode EL2 is vapor deposited so that the end of the second electrode EL2 protruding in the groove GV covers the end of the intermediate layer IML. A part of the second electrode EL2 separated from the second electrode EL2 by the chip portion TPc of the connection electrode CNEc can be defined as the second divided pattern PP2a. The second divided pattern PP2a can contain the same material as the second electrode EL2, and the second divided pattern PP2a can be formed simultaneously with the second electrode EL2 through one process. The first divided pattern PP1a and the second divided pattern PP2a can form the dummy pattern DMPc.

[0318] According to the above-described configuration, the light-emitting element and the pixel driving circuit can be stably contacted, and the contact reliability can be improved. For example, the connection electrode in which the cathode of the light-emitting element and the pixel driving circuit are electrically connected is connected in a relatively wide area rather than a specific point, and the contact reliability can be improved. Therefore, appearance defects caused by contact failure, for example, stain defects found when lighting, can be reduced or eliminated. As a result, the image quality and the manufacturing yield of the display panel can be improved.

[0319] In addition, since the lower surface of the connection electrode and the upper surface of the intermediate connection electrode are in contact, the contact reliability can be improved. Therefore, the size of the through hole for connecting the connection electrode and the intermediate connection electrode can be reduced or minimized. Therefore, the area and the resolution of the light-emitting portion of the display panel can be easily increased.

[0320] In addition, by including the chip portion, the connection electrodes can separate the intermediate layer and the second electrode for each pixel. Therefore, it is possible to prevent the generation of lateral leakage current between adjacent pixels, prevent color mixing between adjacent pixel regions, and prevent luminance degradation.

[0321] The preferred embodiments of the invention have been described above with reference thereto. However, those skilled in the relevant art or those with ordinary knowledge in the relevant art can understand that the invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims to be described later. Therefore, the technical scope of the invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

Description of Reference Numerals

[0322] BCL Lower Conductive Layer CN Intermediate Connection Electrode CNE Connection Electrode DDL Driving Element Layer DMP Dummy Pattern ECL Encapsulation Layer EL1, EL2 Electrodes FNL Functional Layer GV Groove IML Intermediate Layer LD Light-Emitting Element LDL Light-Emitting Element Layer OP-P Through-Hole OP-PDL Light-Emitting Aperture PDC Pixel Driving Unit PDL Pixel Definition Film PP1, PP2, PP3 Division Patterns TP Chip Portion

Claims

1. A driving element layer including a pixel driving unit; a light-emitting element disposed on the driving element layer, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a pixel defining film disposed on the driving element layer, the pixel defining film defining a light emitting opening exposing at least a portion of the first electrode and a groove surrounding the light emitting opening; a connecting electrode disposed on the pixel defining layer and electrically connected to the pixel driving part and the second electrode;

2. The light emitting device, the pixel driving part, and the connecting electrode are each provided in a plurality of parts, The plurality of connection electrodes electrically connect the plurality of light emitting elements to the plurality of pixel driving units, respectively. The display panel of claim 1 , wherein gaps between adjacent ones of the plurality of connecting electrodes overlap the grooves.

3. The display panel of claim 1 , wherein the connecting electrode includes a first edge and a second edge surrounding the first edge, the second edge overlapping the groove.

4. The display panel of claim 1 , wherein the second electrode and the connecting electrode are connected to each other in a region adjacent to the groove.

5. The display panel of claim 1 , wherein the connecting electrode includes a tip portion protruding from an end of the groove, and the connecting electrode partially overlaps the groove of the pixel defining layer in a plan view.

6. The display panel of claim 5 , wherein the second electrode and the connecting electrode are connected to each other at the tip portion.

7. The display panel of claim 5 , wherein the pixel defining layer further comprises a through hole, and the connecting electrode is connected to the pixel driving part through the through hole.

8. The connecting electrode includes a first connecting electrode layer disposed on the pixel defining layer and a second connecting electrode layer disposed on the first connecting electrode layer, The display panel of claim 5 , wherein the second connecting electrode layer covers the first connecting electrode layer.

9. the intermediate layer is disposed on the second connecting electrode layer, and the second electrode is disposed on the intermediate layer; The display panel of claim 8 , wherein the second electrode in the tip portion is connected to the second connecting electrode layer.

10. 9. The display panel of claim 8, wherein a first divided pattern including the same material as the second connecting electrode layer, a second divided pattern including the same material as the intermediate layer, and a third divided pattern including the same material as the second electrode are disposed in the groove.

11. The display panel of claim 10 , wherein the first division pattern and the third division pattern are electrically connected to each other.

12. The connecting electrode includes a first connecting electrode layer disposed on the pixel defining layer, The display panel of claim 1 , wherein the intermediate layer covers the first connecting electrode layer.

13. The display panel of claim 12, wherein a first divided pattern including a same material as the intermediate layer and a second divided pattern including a same material as the second electrode are disposed in the groove.

14. the pixel defining film includes a first pixel defining film portion and a second pixel defining film portion formed on the first pixel defining film portion, 2. The display panel of claim 1, wherein the first pixel defining film portion and the second pixel defining film portion are integrally formed, and the groove is defined in the second pixel defining film portion.

15. A driving element layer including a pixel driving unit; a light-emitting element disposed on the driving element layer, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a pixel defining layer disposed on the driving element layer, the pixel defining layer having a groove defined therein by removing at least a portion of the pixel defining layer in a thickness direction; a connecting electrode disposed on the pixel defining layer and including a tip portion protruding from an end of the groove;

16. The display panel of claim 15 , wherein the pixel defining layer further defines a light emitting opening exposing at least a portion of the first electrode, and the groove surrounds the light emitting opening.

17. the connecting electrode is electrically connected to the pixel driving part and the second electrode, The display panel of claim 15 , wherein the second electrode and the connecting electrode are connected to each other at the tip portion.

18. The display panel of claim 15, wherein a through hole is further defined in the pixel defining layer, and the connecting electrode is connected to the pixel driving part through the through hole.

19. The light emitting device, the pixel driving part, and the connecting electrode are each provided in a plurality of parts, The plurality of connection electrodes electrically connect the plurality of light emitting elements to the plurality of pixel driving units, respectively. The display panel of claim 15 , wherein gaps between adjacent ones of the plurality of connecting electrodes overlap the grooves.

20. The display panel of claim 15, wherein the connecting electrode includes a first edge and a second edge surrounding the first edge, the second edge overlapping the groove.

21. The connecting electrode includes a first connecting electrode layer disposed on the pixel defining layer and a second connecting electrode layer disposed on the first connecting electrode layer, The display panel of claim 15, wherein the second connecting electrode layer covers the first connecting electrode layer, and the second electrode is connected to the second connecting electrode layer at the tip portion.

22. a first divided pattern including a material identical to that of the second connecting electrode layer, a second divided pattern including a material identical to that of the intermediate layer, and a third divided pattern including a material identical to that of the second electrode are disposed in the groove; The display panel of claim 21, wherein the first division pattern and the third division pattern are electrically connected to each other.

23. The connecting electrode includes a first connecting electrode layer disposed on the pixel defining layer, The display panel of claim 15 , wherein the intermediate layer covers the first connecting electrode layer.

24. The display panel of claim 23, wherein a first divided pattern including a same material as the intermediate layer and a second divided pattern including a same material as the second electrode are disposed in the groove.

25. the pixel defining film includes a first pixel defining film portion and a second pixel defining film portion formed on the first pixel defining film portion, The display panel of claim 15, wherein the first pixel defining layer portion and the second pixel defining layer portion are integrally formed, and the groove is defined in the second pixel defining layer portion.

26. providing a preliminary display panel including a base layer, a driving element layer disposed on the base layer, and a pixel defining film disposed on the driving element layer; depositing a first connecting electrode layer on the preliminary display panel; forming a groove in the pixel defining layer overlapping a portion of the first connecting electrode layer by etching the first connecting electrode layer and a portion of the pixel defining layer; forming a connecting electrode by etching the first connecting electrode layer; forming an intermediate layer and a cathode on the connecting electrodes and the pixel defining layer.

27. 27. The method of claim 26, further comprising forming a tip portion defined at an end of the first connection electrode layer.

28. depositing a second connecting electrode layer on the first connecting electrode layer; forming tip portions defined at ends of the first connecting electrode layer and the second connecting electrode layer, 27. The method of claim 26, wherein forming the connecting electrode comprises etching the second connecting electrode layer.

29. the pixel defining film includes a first pixel defining film portion and a second pixel defining film portion formed on the first pixel defining film portion, 27. The method of claim 26, wherein the first pixel defining layer portion and the second pixel defining layer portion are integrally formed, and the groove is defined in the second pixel defining layer portion.

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