Photoelectric conversion device, equipment having the same, and method for manufacturing photoelectric conversion device

Abstract

To provide a photoelectric conversion device enhanced in its performance and reliability.SOLUTION: A photoelectric conversion device comprises: a semiconductor substrate having a photoelectric conversion part; a metal-containing part provided over a semiconductor substrate so as not to overlap with at least part of the photoelectric conversion part; an interlayer insulation film disposed over the semiconductor substrate so as to cover the metal-containing part; a first silicon nitride layer disposed over the photoelectric conversion part so as to have a portion located between the interlayer insulation film and the semiconductor substrate; a silicon oxide film having a portion disposed between the first silicon nitride layer and the photoelectric conversion part, and a portion disposed between the interlayer insulation film and the metal-containing part; a second silicon nitride layer disposed between the silicon oxide film and the metal-containing part; a contact plug in contact with the metal-containing part, extending through the interlayer insulation film, the silicon oxide film, and the second silicon nitride layer; and a contact plug in contact with the semiconductor substrate, extending through the interlayer insulation film and the silicon oxide film.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] In a photoelectric conversion device, a photoelectric conversion section and elements other than the photoelectric conversion section are provided on the same semiconductor substrate. An antireflection structure and a waveguide structure are provided on the photoelectric conversion section, and a contact plug or the like is connected to the elements. Therefore, it is necessary to design the photoelectric conversion device in consideration of the characteristics of both the photoelectric conversion section and other elements.

[0003] Patent Document 1 discloses forming a silicide block film (71) with a film in the same layer as a sidewall formation film (137) having a laminated structure of a silicon oxide film (134) and a silicon nitride film (135) on a photoelectric conversion section (21). Further, it is disclosed to form an etching stopper film (74) of a silicon nitride film on the entire surface of the pixel section (12) and the peripheral circuit section (13). Also, it is disclosed to form a waveguide (23) on the photoelectric conversion section (21).

[0004] Patent Document 2 discloses a control film (410) serving as an etching stopper when forming an opening (421) for a light guide member (420), and a protective film (250) serving as an etching stop for forming a contact hole in a peripheral circuit region. And it is described that the control film (410) and the protective film (250) are formed from the same silicon nitride film.

[0005] Patent Document 3 discloses forming a waveguide that penetrates an interlayer insulating film (IF1) and a contact etch stress liner film (CESL) which is a silicon nitride film and reaches a sidewall insulating film (SWI) which is a silicon nitride film.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

[0007] In the conventional technology, noise may occur due to contamination or damage to the photoelectric conversion unit, and the quality of photoelectric conversion may deteriorate. In addition, the reliability of electrical connection to elements other than the photoelectric conversion unit is important in ensuring the reliability of the photoelectric conversion device. In the conventional technology, the performance and reliability of the photoelectric conversion device are not sufficiently improved.

[0008] Therefore, an object of the present invention is to provide a photoelectric conversion device with improved performance and reliability. [Means for Solving the Problems]

[0009] A first aspect of the means for solving the problems is a photoelectric conversion device, comprising: a semiconductor substrate having a photoelectric conversion unit; a metal-containing portion provided on the semiconductor substrate so as not to overlap at least a part of the photoelectric conversion unit; an interlayer insulating film disposed on the semiconductor substrate so as to cover the metal-containing portion; a first silicon nitride layer disposed on the photoelectric conversion unit so as to have a portion located between the interlayer insulating film and the semiconductor substrate; a silicon oxide film having a portion disposed between the first silicon nitride layer and the photoelectric conversion unit and a portion disposed between the interlayer insulating film and the metal-containing portion; a second silicon nitride layer disposed between the silicon oxide film and the metal-containing portion; a contact plug penetrating through the interlayer insulating film, the silicon oxide film and the second silicon nitride layer and contacting the metal-containing portion; and a contact plug penetrating through the interlayer insulating film and the silicon oxide film and contacting the semiconductor substrate.

[0010] A second aspect of the means for solving the problems is A photoelectric conversion device, comprising: a semiconductor substrate having a photoelectric conversion portion; a metal-containing portion provided on the semiconductor substrate so as not to overlap at least a part of the photoelectric conversion portion; a first silicon nitride layer disposed on the photoelectric conversion portion, wherein a distance between the photoelectric conversion portion and the first silicon nitride layer is smaller than a distance between the wiring layer and the semiconductor substrate; a silicon oxide film having a portion disposed between the first silicon nitride layer and the photoelectric conversion portion and a portion disposed on the metal-containing portion; a second silicon nitride layer disposed between the silicon oxide film and the metal-containing portion; and a contact plug that penetrates the silicon oxide film and the second silicon nitride layer and contacts the wiring layer and the metal-containing portion.

[0011] A third aspect of the means for solving the problem is A photoelectric conversion device, comprising: a semiconductor substrate having a photoelectric conversion portion; an electrode disposed on the semiconductor substrate; a sidewall spacer covering a side surface of the electrode; an interlayer insulating film disposed on the semiconductor substrate so as to cover the electrode and the sidewall spacer; a first silicon nitride layer disposed on the photoelectric conversion portion; a silicon oxide film having a portion disposed between the first silicon nitride layer and the photoelectric conversion portion and a portion located between the interlayer insulating film and the sidewall spacer; a second silicon nitride layer having a portion disposed between the silicon oxide film and the sidewall spacer; and a contact plug that penetrates the interlayer insulating film, the silicon oxide film, and the silicon nitride layer and is connected to an element including the electrode, wherein a distance between the photoelectric conversion portion and the first silicon nitride layer is smaller than a length of the contact plug.

[0012] A fourth aspect of the means for solving the problem is a method for manufacturing a photoelectric conversion device, including a step of forming a first silicon nitride film so as to cover a metal-containing portion on a semiconductor substrate; a step of forming a silicon oxide film on the first silicon nitride film so as to cover a photoelectric conversion portion provided on the semiconductor substrate; a step of forming a second silicon nitride film so as to cover the photoelectric conversion portion; a step of forming an interlayer insulating film so as to cover a portion of the first silicon nitride film located above the metal-containing portion and a portion of the second silicon nitride film located above the photoelectric conversion portion; a step of forming a hole located above the metal-containing portion in the interlayer insulating film and the first silicon nitride film; and a step of disposing a conductor in the hole.

[0013] A fifth aspect of the means for solving the problem is a method for manufacturing a photoelectric conversion device, including a step of forming a first silicon nitride film so as to cover a metal-containing portion on a semiconductor substrate; a step of forming a second silicon nitride film so as to cover the photoelectric conversion portion and the metal-containing portion provided on the semiconductor substrate; a step of forming an interlayer insulating film so as to cover a portion of the first silicon nitride film located above the metal-containing portion and a portion of the second silicon nitride film located above the photoelectric conversion portion; a step of forming a hole located above the metal-containing portion in the interlayer insulating film and the first silicon nitride film; and a step of disposing a conductor in the hole, wherein the second silicon nitride film is thicker than the first silicon nitride film.

Advantages of the Invention

[0014] According to the present invention, a photoelectric conversion device with improved performance and reliability is provided.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0016] Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following description and drawings, common components across multiple drawings are denoted with common reference numerals. Therefore, common components will be described by referring to multiple drawings mutually, and the description of components denoted with common reference numerals will be omitted as appropriate. Also, components denoted with different reference numerals but the same name can be distinguished as the first component, the second component, the third component, and so on.

[0017] FIG. 1(a) is a schematic diagram of a device EQP including a photoelectric conversion device APR according to an embodiment of the present invention. The photoelectric conversion device APR includes a semiconductor device IC. The semiconductor device IC is a semiconductor chip provided with a semiconductor integrated circuit. In addition to the semiconductor device IC, the photoelectric conversion device APR can include a package PKG for storing these. The photoelectric conversion device APR can be used as an image sensor, an AF (Auto Focus) sensor, a photometric sensor, or a distance measurement sensor.

[0018] The device EQP may further include at least any one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a storage device MMRY, and a mechanical device MCHN. Details of the device EQP will be described later.

[0019] The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion section are two-dimensionally arranged. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Also, in the peripheral area PR, a drive circuit for driving the pixel circuit PXC, a signal processing circuit for processing signals from the pixel circuit PXC, and a control circuit for controlling the drive circuit and the signal processing circuit can be arranged. The signal processing circuit can perform signal processing such as correlated double sampling (CDS) processing, amplification processing, and analog-digital (AD) conversion processing. As another example of the semiconductor device IC, at least a part of the peripheral circuit arranged in the peripheral area PR can be arranged on a semiconductor chip different from the semiconductor chip on which the pixel area PX is arranged, and the two semiconductor chips can be stacked.

[0020] FIG. 1(b) shows an example of the pixel circuit PXC. The pixel circuit section PXC includes a photoelectric conversion element PD1, a photoelectric conversion element PD2, a transfer gate TX1, a transfer gate TX2, and a capacitive element FD. Also, the pixel circuit PXC can include an amplification transistor SF, a reset transistor RS, and a selection transistor SL. The photoelectric conversion elements PD1 and PD2 are a photodiode and a photogate, respectively. The transfer gates TX1 and TX2 are MIS (Metal-Insulator-Semiconductor) gates, and the amplification transistor SF, the reset transistor RS, and the selection transistor SL are MIS transistors. The amplification transistor SF may be a junction field effect transistor. In this example, two photoelectric conversion elements PD1 and PD2 share one amplification transistor SF. However, three or more photoelectric conversion elements may share one amplification transistor SF, or an amplification transistor SF may be provided for each of the photoelectric conversion elements PD1 and PD2. Note that the structures of the amplification transistor SF, the reset transistor RS, and the selection transistor SL may be common, and the reset transistor RS, the selection transistor SL, and the amplification transistor SF are collectively referred to as pixel transistors. The transfer gates TX1 and TX2, the pixel transistors, and the peripheral transistors are semiconductor elements including gate electrodes. In addition, the photoelectric conversion device APR can include semiconductor elements such as diodes, resistance elements, and capacitance elements.

[0021] The signal charges generated by the photoelectric conversion elements PD1 and PD2 are transferred to the floating node FN of the capacitance element FD via the transfer gates TX1 and TX2. The gate of the amplification transistor SF that forms a source follower circuit together with the current source CS is connected to the floating node FN, and a pixel signal as a voltage signal is output to the signal output line OUT. The reset transistor RS resets the charge and potential of the floating node FN, and the selection transistor SL switches the connection between the amplification transistor SF and the signal output line OUT. The reset transistor RS and the amplification transistor SF are connected to the power supply line VDD. The signal output line OUT and the power supply line VDD are provided for each column of the pixel circuit PXC. Based on the difference in signals from each of the photoelectric conversion elements PD1 and PD2, focus detection and distance measurement using the phase difference detection method become possible. In addition, imaging can be performed using the signal of one or both of the photoelectric conversion elements PD1 and PD2.

[0022] FIG. 2(a) is a schematic plan view of the vicinity of the surface in the pixel area PX of the semiconductor substrate 10 included in the photoelectric conversion device APR, and FIG. 2(b) is a schematic cross-sectional view of the photoelectric conversion device APR including a cross-section along line A-B in FIG. 2(a). Hereinafter, the structure of the photoelectric conversion device APR will be described without distinguishing between the plan view and the cross-sectional view. In the pixel column of the pixel area PX, the column direction, which is the direction in which the pixels are arranged, is defined as the X direction, the row direction, which is the direction in which the pixels of the pixel row of the pixel area PX are arranged, is defined as the Y direction, and the thickness direction indicating the thickness of the layer or film is defined as the Z direction. The X direction, Y direction, and Z direction are orthogonal to each other.

[0023] This embodiment is characterized by the positional relationship between a member (layer or film) made of silicon oxide and a member (layer or film) made of silicon nitride. The members made of silicon oxide, which will be described as separate members, are members made of different materials between them or members made of similar materials but with different compositions. The same applies to the members made of silicon nitride. The film refers to a planar continuous one, but the layer may be planar discontinuous. Silicon oxide in the following description is a compound of oxygen (O) and silicon (Si), and means a compound in which the top two of the composition ratios of the constituent elements of the compound are occupied by elements other than light elements (hydrogen (H) and helium (He)), which are oxygen (O) and silicon (Si). Silicon oxide can contain light elements such as hydrogen (H), and the amount (atomic %) thereof may be more or less than oxygen (O) and silicon (Si). Silicon oxide can contain elements other than oxygen (O) and silicon (Si) and hydrogen (H) and helium (He) at a concentration lower than that of oxygen (O) and silicon (Si). Typical elements that can be included in silicon oxide are hydrogen (H), boron (B), carbon (C), nitrogen (N), fluorine (F), phosphorus (P), chlorine (Cl), and Ar (argon). When the element other than the third most abundant light element among the constituent elements of silicon oxide is nitrogen, this silicon oxide can be referred to as silicon oxynitride or nitrogen-containing silicon oxide.

[0024] Similarly, silicon nitride is a compound of nitrogen (N) and silicon (Si), and means a compound in which the elements other than the light elements occupying the top two in the composition ratio of the constituent elements of the compound are nitrogen (N) and silicon (Si). When the element other than the light element that is the third most abundant among the constituent elements of silicon nitride is oxygen, this silicon nitride can be referred to as silicon oxynitride or oxygen-containing silicon nitride. Silicon nitride can contain elements other than nitrogen (N) and silicon (Si) at concentrations lower than those of nitrogen (N) and silicon (Si). Typical elements that can be contained in silicon nitride are boron (B), carbon (C), oxygen (O), fluorine (F), phosphorus (P), chlorine (Cl), and Ar (argon). When the element other than the light element that is the third most abundant among the constituent elements of silicon nitride is oxygen, this silicon nitride can be referred to as silicon oxynitride or oxygen-containing silicon nitride. Note that the elements contained in the constituent members of the photoelectric conversion device APR can be analyzed by energy dispersive X-ray spectrometry (EDX). Also, the hydrogen content can be analyzed by the elastic recoil detection analysis (ERDA) method.

[0025] In the pixel area PX of the semiconductor substrate 10, a photoelectric conversion unit 11, a charge detection unit 12, a drain 13 of the pixel transistor, and a source 14 of the pixel transistor are provided in the element area defined by the element isolation region 9. Also, in the peripheral area PR of the semiconductor substrate 10, a source 16 and a drain 17 of the peripheral transistor are provided in the element area defined by the element isolation region 9.

[0026] On the semiconductor substrate 10, gate electrodes 42 of transfer gates TX1 and TX2 and a gate electrode 43 of a pixel transistor are arranged. On the photoelectric conversion unit 11, a dielectric region 61 is arranged via a silicon nitride layer 31. FIG. 2(a) shows the contours of the silicon nitride layer 31 and the dielectric region 61. Further, on the semiconductor substrate 10, a gate electrode 47 of a peripheral transistor is arranged. The peripheral transistor is arranged in a peripheral area PR and is, for example, an NMOS transistor or a PMOS transistor constituting a CMOS circuit. In this example, it is a PMOS transistor.

[0027] On the semiconductor substrate 10, contact plugs 501, 502, 503, and 504 are arranged penetrating through an interlayer insulating film 40. The contact plugs 501, 502, 503, and 504 are conductive members including a barrier metal such as titanium or titanium nitride and a conductor such as tungsten. Typically, the barrier metal of the contact plugs 501, 502, 503, and 504 contacts the interlayer insulating film 40. The contact plugs 501, 502, 503, and 504 are provided in holes (contact holes) formed in the film or layer through which they penetrate. The contact plug 501 is connected to the charge detection unit 12 and the drain 13, and the contact plug 502 is connected to the gate electrodes 42 and 43. The contact plug 503 is connected to the source 16 and the drain 17, and the contact plug 504 is connected to the gate electrode 47.

[0028] On the semiconductor substrate 10, interlayer insulating films 50 and 70 are disposed. The interlayer insulating film 50 is a laminated film of an interlayer insulating layer 56 and a diffusion prevention layer 57, and wiring layers 51, 52, and 53 covered with the diffusion prevention layer 57 are provided between a plurality of interlayer insulating layers 56. The wiring layer 51 is in contact with contact plugs 501, 502, 503, and 504. The number of silicon carbide layers including the diffusion prevention layer 57 may be not less than 1 times and less than 2 times the number of copper wiring layers. In this example, the number of silicon carbide layers is 3, and the number of copper wiring layers is also 3. The interlayer insulating layer 56 is a silicon oxide layer, and it is preferable that the silicon oxide layer contains 5 to 30 atomic% of hydrogen. The diffusion prevention layer 57 is a silicon carbide layer, and the silicon carbide layer can contain 20 to 60 atomic% of hydrogen.

[0029] A dielectric member 60 is provided on the semiconductor substrate 10. The dielectric member 60 is a member in which a dielectric region 61 surrounded by the interlayer insulating films 40 and 50 and a dielectric film 62 located on the interlayer insulating film 50 are integrated. The dielectric region 61 of this example can improve the sensitivity by being arranged to straddle a plurality of photoelectric conversion units 11 as shown in FIG. 2(a), but by arranging the dielectric region 61 for each of the plurality of photoelectric conversion units 11, the light separation accuracy can also be enhanced. The material of the dielectric member 60 is silicon oxide, silicon nitride, and / or resin. The refractive index of the dielectric member 60 is preferably higher than that of the interlayer insulating layer 56, but may be equal to the refractive index of the interlayer insulating layer 56 or lower than the refractive index of the interlayer insulating layer 56. The refractive index of the dielectric member 60 may be lower than that of the diffusion prevention layer 57. The boundary between the dielectric region 61 and the dielectric film 62 is defined by a virtual plane (dotted line in FIG. 2(b)) including the upper surface of the interlayer insulating film 50. The interlayer insulating film 70 covers the dielectric member 60, and the wiring layer 55 on the interlayer insulating film 70 is connected to the wiring layer 53 via a via plug 54 penetrating the interlayer insulating film 70. The interlayer insulating film 70 is a silicon oxide film, and the silicon oxide film can contain 5 to 30 atomic% of hydrogen. An inorganic material film 80 having an in-layer lens is provided on the interlayer insulating film 70. The inorganic material film 80 can function as a passivation film or an antireflection film. The inorganic material film 80 may be a multilayer film including at least two layers of a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and a silicon oxide layer. An organic material film 90 including a planarization layer 91, a color filter layer 92, a planarization layer 93, and a microlens layer 94 is provided on the silicon nitride film. The color filter layer 92 constitutes a multicolor filter array, and the microlens layer 94 constitutes a microlens array.

[0030] FIG. 3 is a schematic cross-sectional view showing a detailed configuration between the semiconductor substrate 10, the interlayer insulating film 40, and the dielectric region 61 in the photoelectric conversion device APR described in FIG. 2.

[0031] The photoelectric conversion unit 11 constitutes photoelectric conversion elements PD1 and PD2 as photodiodes. The photoelectric conversion unit 11 includes an n-type semiconductor region 111 as a charge storage region (cathode) and a p-type semiconductor region 112 as a well region (anode) provided deeper than the semiconductor region 111 in the semiconductor substrate 10. The photoelectric conversion unit 11 includes a p-type semiconductor region 113 as a surface separation region provided between the semiconductor region 111 and the surface of the semiconductor substrate 10. The photoelectric conversion unit 11 is an embedded type photodiode by the semiconductor region 113.

[0032] The gate electrodes 42 and 43 are, for example, n-type polysilicon electrodes. The thickness T42 of the gate electrode 42 is, for example, 50 to 300 nm, typically 100 to 200 nm. The thickness of the gate electrode 43 is equivalent to the thickness T42. The gate electrode 47 has a polyside structure including a p-type polysilicon portion 471 and a metal-containing portion 473. The thickness of the gate electrode 47 may be larger than the thickness T42 or may be equivalent. Note that semiconductor elements such as resistance elements and capacitance elements arranged in the peripheral area PR can also be formed of polysilicon electrodes and can have the same configuration as the gate electrodes 42, 43, and 47. The contact plug 504 contacts (makes contact with) the metal-containing portion 473. The sidewall spacer 48 is a multilayer member including a silicon nitride layer 483 and a silicon oxide layer 482. The silicon oxide layer 482 is located between the silicon nitride layer 483 and the side surface of the gate electrode 47, and between the silicon nitride layer 483 and the semiconductor substrate 10 (semiconductor regions 151 and 161).

[0033] A gate insulating film 24 is disposed between the gate electrodes 42, 43 and the semiconductor substrate 10. A gate insulating film 26 is disposed between the gate electrode 47 and the semiconductor substrate 10. The gate insulating film 24 can be made thinner than the gate insulating film 26. For example, the thickness of the gate insulating film 24 is 5 to 10 nm, and the thickness of the gate insulating film 26 is 1 to 5 nm. The gate insulating film 24 and the gate insulating film 26 can be silicon oxide films containing nitrogen.

[0034] A sidewall spacer 48 of the gate electrode 47 is provided so as to cover the side surface of the gate electrode 47.

[0035] The charge detection unit 12 that constitutes the capacitance element FD includes a low-concentration n-type semiconductor region 121 and a high-concentration n-type semiconductor region 122. The semiconductor region 121 functions as a floating diffusion region. The semiconductor region 121 is located under the contact plug 501 and functions as a contact region with which the contact plug 501 makes contact. A metal compound (silicide) of the metal component of the contact plug 501 and the semiconductor component of the semiconductor substrate 10 may be formed between the contact plug 501 and the semiconductor substrate 10 (semiconductor regions 122, 132). Even in this case, it can be said that the contact plug 501 contacts the semiconductor substrate 10 (semiconductor regions 122, 132). The metal component of the contact plug 501 that forms the compound with the semiconductor substrate 10 may be a metal (for example, titanium) contained in the barrier metal of the contact plug 501. The drain 13 includes a low-concentration n-type semiconductor region 131 and a high-concentration n-type semiconductor region 132. The semiconductor region 131 is located under the contact plug 501 and functions as a contact region with which the contact plug 501 makes contact. The source 16 includes a low-concentration p-type semiconductor region 161 as an LDD region, a medium-concentration p-type semiconductor region 162, and a metal-containing portion 163. Similarly, the drain 17 includes a low-concentration p-type semiconductor region 171, a medium-concentration p-type semiconductor region 172, and a metal-containing portion 173. The semiconductor regions 161, 171 are located under the sidewall spacer 48, and the semiconductor regions 162, 172 are located under the metal-containing portion 173. The contact plug 503 makes contact with the metal-containing portions 163, 173. The metal-containing portions 163, 173, 473 are provided in the source 16, the drain 17, and the gate electrode 47 of the peripheral transistor, but any one of them may be provided. Also, a metal-containing portion may be provided in the pixel transistor, but since the generation of noise increases, when a metal-containing portion is provided in the pixel transistor, it is preferably arranged only under the contact plugs 501, 502 in a limited manner.

[0036] The metal-containing portions 163, 173, and 473 are regions that contain metal and are composed of metal or a metal compound. The metals contained in the metal-containing portions 163, 173, and 473 are, for example, cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), and tungsten (W). Typically, the metal-containing portions 163, 173, and 473 are portions composed of a metal compound of a semiconductor, and more typically, are portions (silicide portions) composed of a metal compound of silicon, that is, silicide. As the silicide, cobalt silicide, nickel silicide, tungsten silicide, titanium silicide, etc. are suitable. The metal-containing portions 163, 173, and 473 may be a compound of metal and germanium. The metal-containing portion 473 may be a metal nitride such as tantalum nitride, titanium nitride, aluminum nitride, etc., or may be a metal carbide. The metal-containing portions 163, 173, and 473 are provided for the purpose of reducing the resistance between the transistor and the contact plugs 503 and 504. The metal-containing portion may be provided for other purposes, for example, for making the gate electrode a metal gate, or may be provided as a light-shielding member for the semiconductor substrate 10. So that the photoelectric conversion portion 11 can receive light, the metal-containing portion is provided so as not to overlap at least the photoelectric conversion portion 11. In this example, since the metal-containing portions 163, 173, and 473 are arranged in the peripheral area PR, the metal-containing portions 163, 173, and 473 do not overlap the photoelectric conversion portion 11. Even when a metal-containing portion is provided in the pixel area PX, it is preferable that the metal-containing portion is provided so as not to overlap the photoelectric conversion portion 11.

[0037] The photoelectric conversion device APR includes a silicon nitride layer 31, a silicon oxide film 21, and a silicon nitride layer 32 disposed on a semiconductor substrate 10. The contact plugs 501 and 502 penetrate not only the interlayer insulating film 40 but also the silicon oxide film 21. The contact plugs 501 and 502 are in contact with the silicon oxide film 21 in addition to the interlayer insulating film 40. Typically, the barrier metal of the contact plugs 501 and 502 is in contact with the interlayer insulating film 40 and the silicon oxide film 21. The contact plugs 503 and 504 penetrate not only the interlayer insulating film 40 but also the silicon oxide film 21 and the silicon nitride layer 32. The contact plugs 503 and 504 are in contact with the silicon oxide film 21 and the silicon nitride layer 32. Typically, the barrier metal of the contact plugs 503 and 504 is in contact with the silicon oxide film 21 and the silicon nitride layer 32.

[0038] The silicon nitride layer 31 is disposed on the photoelectric conversion unit 11 so as to have a portion 311 located between the interlayer insulating film 40 and the semiconductor substrate 10. The silicon nitride layer 31 also has a portion 312 disposed between the dielectric region 61 and the photoelectric conversion unit 11. The thickness T312 of the portion 312 of the silicon nitride layer 31 may be smaller than the thickness T311 of the portion 311 of the silicon nitride layer 31 (T312 < T311). The thickness T312 may be 25% to 75% of the thickness T311. The thickness T311 is, for example, 30 to 120 nm, and the thickness T312 is, for example, 10 to 60 nm. When the dielectric region 61 is not provided, the entire silicon nitride layer 31 is located between the interlayer insulating film 40 and the semiconductor substrate 10, and the entire silicon nitride layer 31 may have a substantially uniform thickness (the thickness distribution is ±10% or less). The silicon nitride layer 31 on the photoelectric conversion unit 11 functions as a protective layer by itself, and can reduce damage and contamination to the photoelectric conversion unit 11 during the manufacture and use of the photoelectric conversion device APR.

[0039] In order for the silicon nitride layer 31 to improve the optical characteristics with respect to the photoelectric conversion unit 11, it is preferable that the silicon nitride layer 31 is somewhat close to the photoelectric conversion unit 11. The distance D1 between the silicon nitride layer 31 and the photoelectric conversion unit 11 is preferably smaller than the distance D5 between the semiconductor substrate 10 and the wiring layer 51 (D1 < D5). Further, the distance D1 between the silicon nitride layer 31 and the photoelectric conversion unit 11 is preferably smaller than the length L3 of the contact plug 503 (D1 < L3), and is also preferably smaller than the length of the contact plug 501. Note that the length of the contact plug 501 may be considered equal to the length L3 of the contact plug 503. Furthermore, the distance D1 between the silicon nitride layer 31 and the photoelectric conversion unit 11 is preferably smaller than the length L4 of the contact plug 504 (D1 < L4), and is also preferably smaller than the length of the contact plug 502. Note that the length of the contact plug 502 may be considered equal to the length L4 of the contact plug 504. Note that the distance D5 is approximately equal to the length L3, but the distance D5 may be smaller than the length L3 (D5 ≦ L3).

[0040] The silicon oxide film 21 is disposed between the interlayer insulating film 40 and the semiconductor substrate 10. The silicon oxide film 21 has a portion 211 provided in the pixel area PX and a portion 212 provided in the peripheral area PR. The portion 211 is disposed at least between the silicon nitride layer 31 and the photoelectric conversion unit 11. The portion 212 is disposed at least between the interlayer insulating film 40 and the peripheral transistor. The upper surface of the silicon oxide film 21, which is the surface on the side of the interlayer insulating film 40 (the surface opposite to the side of the semiconductor substrate 10), has irregularities corresponding to the shapes of the gate electrodes 42, 43, and 47. Note that the upper surface of the interlayer insulating film 40, which is the surface opposite to the side of the semiconductor substrate 10, is planarized and does not have irregularities corresponding to the shapes of the gate electrodes 42, 43, and 47. Therefore, the upper surface of the silicon oxide film 21 on the interlayer insulating film 40 has a larger height difference than the upper surface of the interlayer insulating film 40. The interlayer insulating film 40 and the silicon oxide film 21 can both be made of silicon oxide, but the interlayer insulating film 40 and the silicon oxide film 21 can be distinguished by measuring the concentrations of silicon (Si), oxygen (O), argon (Ar), boron (B), phosphorus (P), etc. The thickness T21 of the silicon oxide film 21 is, for example, 50 to 150 nm. Note that the difference in thickness between the portion 211 and the portion 212 is preferably small. The silicon oxide film 21 can have a substantially uniform thickness as a whole (the thickness distribution is ±10% or less). Note that when the silicon oxide film 21 has only the portion 211, the contact plugs 503 and 504 do not penetrate the silicon oxide film 21.

[0041] A silicon nitride layer 32 is disposed between the silicon oxide film 21 and the peripheral transistors. The silicon nitride layer 32 covers the source 16, the drain 17, the gate electrode 47, and the sidewall spacer 48. The thickness T32 of the silicon nitride layer 32 is, for example, 10 to 100 nm. The silicon nitride layer 32 may be in contact with the source 16, the drain 17, the gate electrode 47, and the sidewall spacer 48. More specifically, the silicon nitride layer 32 can be in contact with the metal-containing portions 163 and 173, the silicon nitride layer 483, and the metal-containing portion 473. Therefore, the distance between the silicon nitride layer 32 and the metal-containing portions 163, 173, and 473 can be zero.

[0042] By increasing the thickness T311 of the portion 311 of the silicon nitride layer 31, contamination through the interlayer insulating film 40 can be reduced. In particular, it is preferable that the thickness T311 is larger than the thickness T32 of the silicon nitride layer 32. The thickness T311 is preferably 110% or more of the thickness T32, and the thickness T311 may be 150% or more of the thickness T32. The thickness T311 may be 300% or less of the thickness T32, and the thickness T311 may be 150% or less of the thickness T32.

[0043] By separating the upper surface of the portion 312 from the semiconductor substrate 10 as much as possible, damage to the photoelectric conversion unit 11 can be reduced. The distance between the upper surface of the portion 312 and the semiconductor substrate 10 is represented by the sum (D1 + T312) of the thickness T312 of the portion 312 and the distance D1 between the portion 312 and the semiconductor substrate 10. Preferably, the distance between the upper surface of the portion 312 and the semiconductor substrate 10 is greater than the thickness T42 of the gate electrode 42. By providing the silicon oxide film 21, this distance D1 can be increased.

[0044] By making the thickness T312 as large as possible, contamination through the dielectric region 61 can be reduced. The thickness T312 is preferably 25% or more of the thickness T32, and more preferably 50% or more of the thickness T32. The thickness T312 may be smaller than the thickness T32, and the thickness T312 may be 75% or less of the thickness T32. When the thickness of the silicon nitride layer 31 is 150% or less of the thickness of the silicon nitride layer 32, the thickness T32 can be the thickness between the thickness T312 and the thickness T311. If the thickness T311 is sufficiently larger than the thickness T32, the thickness T312 may be larger than the thickness T32.

[0045] If the silicon oxide film 21 exists only in one of the portion 211 and the portion 212, a height difference may occur in the base of the interlayer insulating film 40 between the pixel area PX and the peripheral area PR. On the other hand, by providing both the portion 211 and the portion 212, the height difference in the base of the interlayer insulating film 40 between the pixel area PX and the peripheral area PR can be reduced as compared with the case where only one of the portion 211 and the portion 212 is provided. Therefore, the flatness of the upper surface of the interlayer insulating film 40 can be improved, and the unevenness of light interference caused by the difference in the optical path length for each pixel can be reduced. Also, the reliability of the contact plugs 501, 502, 503, 504 and the reliability of the wiring layer can be improved. The thickness T21 of the silicon oxide film 21 can be made larger than the thickness T311 of the portion 311 of the silicon nitride layer 31 and the thickness T32 of the silicon nitride layer 32 (T21>T311, T32).

[0046] The silicon nitride layer 32 can suppress the diffusion of metals from the metal-containing parts 163, 173, and 473. By disposing the silicon nitride layer 32 on the side of the metal-containing parts 163, 173, and 473 rather than the part 212 of the silicon oxide film 21, the diffusion of the metals in the metal-containing parts 163, 173, and 473 can be effectively suppressed. It is more effective when the distance between the silicon nitride layer 32 and the metal-containing parts 163, 173, and 473 is small, and it is preferable to set this distance to zero as described above.

[0047] The photoelectric conversion device APR can further include at least any one of a silicon oxide layer 22, a silicon nitride layer 33, and a silicon oxide layer 23 disposed on the semiconductor substrate 10. In this example, all three layers are provided, and among these three layers, it is particularly preferable to provide the silicon nitride layer 33. The silicon nitride layer 33 is disposed between the silicon oxide film 21 and the photoelectric conversion part 11. The silicon oxide layer 22 is disposed between the silicon oxide film 21 and the silicon nitride layer 33. The silicon oxide layer 23 is disposed between the semiconductor substrate 10 and the silicon nitride layer 33. In the pixel area PX, an insulator film 49, which is a multilayer film including the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23, covers the semiconductor substrate 10 and the gate electrodes 42 and 43. The contact plugs 501 and 502 penetrate through the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23 in addition to the interlayer insulating film 40. The contact plugs 501 and 502 can be in contact with the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23. Typically, the barrier metal of the contact plugs 501 and 502 is in contact with the silicon oxide film 21 and the silicon nitride layer 32.

[0048] The silicon nitride layer 33 may have an antireflection function for light incident on the photoelectric conversion unit 11. Further, by laminating the silicon nitride layer 33 and the silicon nitride layer 31 via the silicon oxide film 21 to cause multiple reflections, the antireflection function can be further enhanced. The portion of the silicon nitride layer 33 that covers the semiconductor region other than the photoelectric conversion unit 11 may have a function of protecting against contamination and damage of the semiconductor substrate 10. Since the silicon nitride layer 31 is not provided on the semiconductor region other than the photoelectric conversion unit 11, the silicon nitride layer 33 assumes a part of the role played by the silicon nitride layer 31 on the photoelectric conversion unit 11. The silicon oxide layer 23 may have a function as a buffer layer for preventing the silicon nitride layer 33 from contacting the semiconductor substrate 10. Since the silicon nitride layer 33 is separated from the semiconductor substrate 10, the generation of dark current can be suppressed. The distance D3 between the silicon nitride layer 33 and the semiconductor substrate 10 is preferably larger than the distance between the silicon nitride layer 32 and the metal-containing portions 163, 173. In this example, the gate insulating film 24 extends from between the semiconductor substrate 10 and the gate electrodes 42, 43 over the semiconductor region not covered by the gate electrodes 42, 43. Therefore, the distance D3 between the silicon nitride layer 33 and the semiconductor substrate 10 is equal to the sum of the thickness of the silicon oxide layer 23 and the thickness between the gate insulating film 24.

[0049] When the dielectric region 61 is made of silicon nitride, the silicon nitride layer 31 and the dielectric region 61 are made of the same material. With such a configuration, reflection at the interface between the silicon nitride layer 31 and the dielectric region 61 is less likely to occur, and the light utilization efficiency is improved.

[0050] The silicon oxide layer 23, the silicon nitride layer 33, the silicon oxide layer 22, the silicon oxide film 21, and the silicon nitride layer 31 on the photoelectric conversion unit 11 function as an antireflection layer for light to be incident on the semiconductor substrate 10. The performance of this multilayer antireflection layer depends importantly on the distance D2 between the silicon nitride layer 31 and the silicon nitride layer 33. This is because multiple reflections occur between the silicon nitride layer 33 and the silicon nitride layer 31, and the layer has the function of reducing reflection by the interference of the multiple reflected light. To control this distance D2, it is only necessary to control the total thickness of the silicon oxide layer 22 and the silicon oxide film 21. The distance D2 between the silicon nitride layer 31 and the silicon nitride layer 33 is preferably λ / 8n to 4λ / 8n (λ: wavelength of incident light (400 nm ≤ λ ≤ 800 nm), n: refractive index of silicon oxide (n ≈ 1.5)). The distance D2 is, for example, 50 to 150 nm. For improving sensitivity and preventing stray light, the distance L3 is preferably less than the maximum value of λ, that is, less than 800 nm.

[0051] The thickness of the silicon oxide layer 23 is, for example, 5 to 20 nm, the thickness T33 of the silicon nitride layer 33 is, for example, 20 to 100 nm, and the thickness of the silicon oxide layer 22 is, for example, 10 to 100 nm. The thickness of the silicon oxide film 21 is, for example, 20 to 200 nm, and the thickness of the silicon nitride layer 31 is, for example, 20 to 100 nm. The thickness of the silicon oxide film 21 can be made larger than the thickness of the silicon oxide layer 22.

[0052] To obtain the effects for improving the performance and reliability of the photoelectric conversion device APR, when arranging more suitable relationships regarding the dimensions and distances of the members such as the above-described layers and films, D3 < T312 < T32 ≤ T33 < T311 < T21 < D2 < D1 < T42 < L4 < D5 ≤ L3. Also, T21 < 100 nm, L4 > 200 nm, and L3 < 800 nm. Note that it is not necessary to satisfy this relationship for all dimensions and distances, and it may satisfy the magnitude relationship defined here in at least two combinations of dimensions and distances.

[0053] The manufacturing method of the photoelectric conversion device APR will be described with reference to FIGS. 4 to 8. FIGS. 4 to 8 show the structures of the corresponding parts of the cross-sectional view shown in FIG. 3 in the order of the processes, but the order of the processes does not necessarily have to be as shown in FIGS. 4 to 8. In FIGS. 4 to 8, the symbols are omitted for the parts that do not change and the parts that may not change compared to the parts already shown.

[0054] In process a shown in FIG. 4(a), a semiconductor substrate 10 having an element region defined by an element isolation region 9 is prepared. The element isolation region 9 can be formed by a well-known method having a LOCOS structure or a STI structure. A p-type semiconductor region 112 and an n-type semiconductor region 111 as well regions are formed in the element region of the semiconductor substrate 10.

[0055] In process b shown in FIG. 4(b), gate electrodes 42, 43, and 47 are formed on the semiconductor substrate 10. First, gate insulating films 24 and 26 are formed on the semiconductor substrate 10, and then a conductor film made of polysilicon or the like is formed on the gate insulating films 24 and 26. The gate electrodes 42, 43, and 47 are formed by patterning this conductor film. Further, semiconductor regions 113, 121, 131, 14, 131, and 171 are formed by ion implantation. The formation of the semiconductor region 111 may be performed after the formation of the gate electrode 42.

[0056] In process c shown in FIG. 4(c), an insulator film 490 is formed so as to cover the photoelectric conversion unit 11. The insulator film 490 is a multilayer film including a silicon oxide layer 220, a silicon nitride layer 330 between the silicon oxide layer 220 and the semiconductor substrate 10, and a silicon oxide layer 230 between the silicon nitride layer 330 and the semiconductor substrate 10. The insulator film 490 is formed by laminating the silicon oxide layer 230, the silicon nitride layer 330, and the silicon oxide layer 220 in this order from the semiconductor substrate 10 side. Each layer of the insulator film 490 can be formed by a thermal CVD (Chemical Vapor Deposition) method, for example, an LP (Low Pressure)-CVD method.

[0057] In step d shown in FIG. 4(d), sidewall spacer 48 is formed from insulator film 490. Sidewall spacer 48 can be formed by masking insulator film 490 with a resist pattern in pixel area PX and anisotropically etching insulator film 490 in peripheral area PR. The silicon nitride layer 483 of sidewall spacer 48 is formed from the silicon nitride layer 330 of insulator film 490, and the silicon oxide layer 482 of sidewall spacer 48 is formed from the silicon oxide layer 230 of insulator film 490. Sidewall spacer 48 may include a silicon oxide layer (not shown) formed from silicon oxide layer 220.

[0058] The portion of insulator film 490 located in pixel area PX remains as insulator film 49. The silicon oxide layer 22 of insulator film 49 is formed from the silicon oxide layer 220 of insulator film 490. The silicon nitride layer 33 of insulator film 49 is formed from the silicon nitride layer 330 of insulator film 490. The silicon oxide layer 23 of insulator film 49 is formed from the silicon oxide layer 230 of insulator film 490.

[0059] Furthermore, in step d, using sidewall spacer 48 as a mask, a medium-concentration semiconductor region 162 of source 16 and a medium-concentration semiconductor region 172 of drain 17 are formed.

[0060] In step e shown in FIG. 5(e), a portion of insulator film 49 located above photoelectric conversion unit 11 and a metal film 300 in contact with semiconductor substrate 10 are formed. Metal film 300 preferably contacts the silicon oxide layer 22 of insulator film 49. In other words, at the stage of forming metal film 300, it is preferable that silicon oxide layer 22 remains on silicon nitride layer 33 of insulator film 49. Metal film 300 can also contact gate electrode 47. Metal film 300 is, for example, a cobalt film, a nickel film, a tungsten film, or a titanium film. Metal film 300 can be formed by, for example, sputtering in peripheral area PR so as to cover semiconductor regions 162, 172 and gate electrode 47.

[0061] In the peripheral area PR, it is necessary to expose the semiconductor regions 162 and 172 of the semiconductor substrate 10 and the gate electrode 47. Therefore, when the semiconductor regions 162 and 172 and the gate electrode 47 react with oxygen in the atmosphere, a native oxide film may be formed on the surface. Alternatively, a part of the insulator film 490 or the gate insulating film 26 may remain on the surfaces of the semiconductor regions 162 and 172 and the gate electrode 47. If a native oxide film or an insulator film exists between the metal film 300 formed thereon and silicon, the reaction by heat treatment may be inhibited, and poor formation of the metal-containing portion may occur. To avoid this, immediately before forming the metal film 300, the native oxide film and the insulator film are removed by etching. For the etching, wet etching using a chemical solution containing, for example, hydrofluoric acid can be used.

[0062] With the etching of this native oxide film and insulator film, the portion of the insulator film 49 located above the photoelectric conversion unit 11 among the underlying insulator film 49 may become thinner. Specifically, the silicon oxide layer 22 of the insulator film 49 becomes thinner by etching.

[0063] In step f shown in FIG. 5(f), metal-containing portions 163, 173, and 473 are formed on the semiconductor substrate 10 using the metal film 300. After the metal film 300 is formed, a heat treatment is performed so that the metal of the metal film 300 reacts with the silicon (single-crystalline silicon) of the semiconductor substrate 10 and the silicon (polycrystalline silicon) of the gate electrode 47. As a result, metal-containing portions 163, 173, and 473 made of silicide, which is a compound of metal and silicon, are formed. The metal-containing portions 163, 173, and 473 can be cobalt silicide, nickel silicide, tungsten silicide, or titanium silicide depending on the metal species of the metal film 300. In the pixel area PX, since the silicon nitride layer 33 and the silicon oxide layer 22 cover the semiconductor substrate 10, no silicide is formed. With such a configuration, the diffusion of metals such as cobalt and nickel is reduced, and it becomes possible to reduce the leakage current in the photoelectric conversion portion 11 and the noise (so-called white defect) in the photoelectric conversion portion 11. Note that a metal-containing portion may be provided in any configuration of the pixel area PX, or a metal-containing portion may not be provided in any configuration of the peripheral area PR.

[0064] After the formation of the metal-containing portions 163, 173, and 473, the unreacted metal in the metal film 300 is removed by etching.

[0065] With the etching of the metal film 300, the portion of the insulator film 49 underlying the metal film 300 and located above the photoelectric conversion portion 11 may become thinner. Specifically, the silicon oxide layer 22 of the insulator film 49 becomes thinner by etching.

[0066] Note that the residue of the silicon oxide layer 220 remaining on the sidewall spacer 48 formed in step d can be removed by the etching of the natural oxide film or insulator film described above, or the etching of the metal film 300.

[0067] In step g shown in FIG. 5(g), a silicon nitride film 320 is formed so as to cover the metal-containing portions 163, 173, and 473 on the semiconductor substrate 10. The silicon nitride film 320 is formed across the pixel area PX and the peripheral area PR, and can be formed, for example, by plasma CVD method.

[0068] In step h shown in FIG. 5(h), the silicon nitride film 320 is removed over the photoelectric conversion unit 11. The portion of the silicon nitride film 320 located over the peripheral transistor remains as the silicon nitride layer 32.

[0069] With the etching of the silicon nitride film 320, the portion of the underlying insulator film 49 located over the photoelectric conversion unit 11 may become thinner. Specifically, the silicon oxide layer 22 of the insulator film 49 becomes thinner by etching.

[0070] In step i shown in FIG. 6(i), a silicon oxide film 21 is formed over the silicon nitride film 320 (silicon nitride layer 32) so as to cover the photoelectric conversion unit 11 provided on the semiconductor substrate 10. The silicon oxide film 21 is formed across the pixel area PX and the peripheral area PR, and can be formed, for example, by plasma CVD method.

[0071] As described above, the distance between the silicon nitride layer 31 and the semiconductor substrate 10, and further the distance between the silicon nitride layer 31 and the silicon nitride layer 33, over the photoelectric conversion unit 11 affect the reflectance. In this embodiment, the optical characteristics can be optimized by forming the silicon oxide film 21 with an appropriate thickness. Also, the thickness of the silicon oxide film 21 can be set according to the thickness of the silicon oxide layer 22 that has become thinner in some steps. The amount of reduction in the thickness of the silicon oxide layer 22 can be grasped in advance, and the thickness of the silicon oxide film 21 can be determined according to the amount of reduction. Alternatively, the thickness of the silicon oxide layer 22 may be measured during manufacturing, and the thickness of the silicon oxide film 21 may be determined according to the measurement result. For example, when the thickness of the silicon oxide film 21 needs to be larger than the thickness of the finally remaining silicon oxide layer 22, it is extremely effective to form the silicon oxide film 21. The thickness of the silicon oxide layer 22 that has become smaller is, for example, 10 to 100 nm, and the thickness of the silicon oxide film 21 is, for example, 20 to 200 nm.

[0072] In step j shown in FIG. 6(j), a silicon nitride film 310 is formed on the silicon oxide film 21 so as to cover the photoelectric conversion unit 11 provided on the semiconductor substrate 10. The silicon nitride film 310 is formed across the pixel area PX and the peripheral area PR, and can be formed by, for example, plasma CVD method. The thickness of the silicon nitride film 310 is preferably made thicker than that of the silicon nitride film 320 (silicon nitride layer 32).

[0073] In step k shown in FIG. 6(k), the silicon nitride film 310 is removed above the pixel transistor. The portion of the silicon nitride film 310 located above the photoelectric conversion unit 11 remains as the silicon nitride layer 31. The silicon nitride film 310 can be patterned into a silicon nitride layer 31 having a desired shape by lithography technology and etching technology. The silicon nitride layer 31 extends and is provided on the n-type semiconductor region 111, that is, on a part of the gate electrodes 42 of the transfer gates TX1 and TX2 from above the photoelectric conversion unit 11. The upper surface of the silicon nitride layer 31 has a shape following the height difference caused by the gate electrode 42. In the regions where the contact plugs 501 and 502 of the pixel area PX are arranged, it is preferable to remove the silicon nitride film 310 by etching.

[0074] In step l shown in FIG. 6(l), an interlayer insulating film 40 is formed. The interlayer insulating film 40 is formed so as to cover the portion of the silicon nitride film 320 located above the transistor including the electrode (silicon nitride layer 32) and the portion of the silicon nitride film 310 located above the photoelectric conversion unit 11 (silicon nitride layer 31). The interlayer insulating film 40 is flattened using a planarization method such as a reflow method, an etch-back method, or a CMP method.

[0075] In step m shown in FIG. 7(m), contact holes 401 and 402 located above the pixel transistor are formed in the interlayer insulating film 40, the silicon oxide film 21, and the insulator film 49. The contact holes 401 and 402 are holes provided at least in the interlayer insulating film 40.

[0076] To form the contact holes 401 and 402 in the pixel area PX, the interlayer insulating film 40, the silicon oxide film 21, the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23 are sequentially etched by plasma etching. At this time, the silicon nitride layer 33 can function as an etching stopper. More specifically, the etching conditions when etching the silicon oxide layer 22 are such that the etching rate with respect to the silicon nitride layer 33 is lower than the etching rate with respect to the silicon oxide layer 22. In the case where there is no silicon oxide layer 22 in the pixel area PX, the silicon oxide layer 22 may be considered to be replaced with the silicon oxide film 21.

[0077] The silicon nitride layer 33 as an etching stopper cancels the variation in the depth of the contact holes 401 and 402 when etching up to the upper layer of the silicon nitride layer 33. Then, by etching the thin silicon nitride layer 33 close to the semiconductor substrate 10 in a state where the variation in the depth of the contact holes 401 and 402 is reduced, damage to the semiconductor substrate 10 can be suppressed. Although it is preferable to bring the silicon nitride layer 33 close to the semiconductor substrate 10, since noise is likely to occur when the silicon nitride layer 33 contacts the semiconductor substrate 10, a silicon oxide layer 23 is disposed between the silicon nitride layer 33 and the semiconductor substrate 10.

[0078] When the step h is not performed, a silicon nitride film 320 is disposed on the pixel transistor. And to form the contact holes 401 and 402, etching is performed in the order of the interlayer insulating film 40, the silicon oxide film 21, the silicon nitride film 320, the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23. In this case, due to the presence of the silicon nitride film 320, the switching of the etching conditions and the etching stop conditions become complicated, and the yield may decrease. On the other hand, by removing the silicon nitride film 320 on the pixel transistor in the step h, the number of times of switching the etching conditions for etching the silicon nitride layer can be reduced (to one time). Therefore, the formation of the contact holes 401 and 402 is easy, the variation is reduced, and the yield is improved.

[0079] Similarly, when step k is not performed, the silicon nitride film 310 is disposed on the pixel transistor. To form the contact holes 401 and 402, etching is performed in the order of the interlayer insulating film 40, the silicon nitride film 310, the silicon oxide film 21, the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23. In this case, due to the presence of the silicon nitride film 310, the switching of the etching conditions and the etching stop conditions become complicated, and the yield may decrease. On the other hand, by removing the silicon nitride film 310 on the pixel transistor in step k, the number of times of switching the etching conditions for etching the silicon nitride layer 31 can be reduced (to one time). Therefore, the formation of the contact holes 401 and 402 is easy, the variation is reduced, and the yield is improved.

[0080] By ion-implanting into the semiconductor substrate 10 through the contact hole 401, semiconductor regions 122 and 132 as contact regions are formed. When forming the semiconductor regions 122 and 132, by blocking the contact hole 401 with a resist mask, it is possible to suppress the impurity from being implanted into the channel region through the gate electrodes 42 and 43.

[0081] In step n shown in FIG. 7(n), contact holes 403 and 404 located above the peripheral transistor are formed in the interlayer insulating film 40, the silicon oxide film 21, and the silicon nitride film 320 (silicon nitride layer 32). The contact holes 403 and 404 are holes provided at least in the interlayer insulating film 40.

[0082] To form the contact holes 403 and 404 for the peripheral area PR, the interlayer insulating film 40, the silicon oxide film 21, and the silicon nitride layer 32 are sequentially etched by plasma etching. At this time, the silicon nitride layer 32 can function as an etching stopper. More specifically, the etching conditions when etching the silicon oxide film 21 are such that the etching rate with respect to the silicon nitride layer 32 is lower than the etching rate with respect to the silicon oxide film 21. In addition, when there is no silicon oxide film 21 in the peripheral area PR, the silicon oxide film 21 may be considered to be replaced with the interlayer insulating film 40.

[0083] The silicon nitride layer 32 as an etching stopper cancels the variation in the depth of the contact holes 403 and 404 when etching up to the upper layer of the silicon nitride layer 32. Then, with the variation in the depth of the contact holes 403 and 404 reduced, the thin silicon nitride layer 32 close to the semiconductor substrate 10 is etched. Thereby, damage to the semiconductor substrate 10 and the scattering of metal from the metal-containing portions 163, 173, and 473 can be suppressed. For this purpose, it is better for the silicon nitride layer 32 to be as close as possible to the metal-containing portions 163, 173, and 473, and it is preferable for the silicon nitride layer 32 to be in contact with the metal-containing portions 163, 173, and 473. Also, it is better for the silicon nitride layer 32 to be as thin as possible.

[0084] When the step k is not performed, the silicon nitride film 310 is disposed on the peripheral transistor. And to form the contact holes 403 and 404, etching is performed in the order of the interlayer insulating film 40, the silicon nitride film 310, the silicon oxide film 21, and the silicon nitride layer 32. In this case, due to the presence of the silicon nitride film 310, the switching of the etching conditions and the etching stop conditions become complicated, and the yield may decrease. On the other hand, by removing the silicon nitride film 310 on the peripheral transistor in the step k, the number of times of switching the etching conditions for etching the silicon nitride layer can be reduced (to one time). Therefore, the formation of the contact holes 403 and 404 is easy, the variation is reduced, and the yield is improved.

[0085] In step o shown in FIG. 7(o), a conductor is disposed in contact holes 401, 402, 403, and 404. The conductor can be a laminate of a barrier metal and tungsten. Excess conductor on the interlayer insulating film 40 is removed by a CMP method or the like to form contact plugs 501, 502, 503, and 504.

[0086] It is preferable to separately form contact holes 401, 402 and contact holes 403, 404 as in steps m and n. Metal-containing portions 163, 173, and 473 are formed in at least a part of the peripheral area PR, and contact holes 403 and 404 expose the metal-containing portions 163, 173, and 473. In such a case, the metal of the metal-containing portions 163, 173, and 473 may scatter due to etching when forming the contact holes 403 and 404 in the peripheral area PR. Therefore, when forming the contact holes 403 and 404, it is preferable that the contact holes 401 and 402 are in any one of the states of not yet being formed, being blocked by a resist mask, or already being blocked by the contact plugs 501 and 502. In this example, the contact holes 401 and 402 are formed before the formation of the contact holes 403 and 404, and the contact holes 403 and 404 are formed with the contact holes 401 and 402 blocked by a resist mask. The resist mask can suppress the metal of the metal-containing portions 163, 173, and 473 from entering the contact holes 401 and 402.

[0087] If the influence of the scattering of the metal of the metal-containing portions 163, 173, and 473 is small, the contact holes 401, 402 and the contact holes 403, 404 may be formed simultaneously. In that case, it is preferable that the difference in thickness between the silicon nitride layer 33 and the silicon nitride layer 32 is small. For example, the thickness difference between the silicon nitride layer 33 and the silicon nitride layer 32 is preferably 10 nm or less. If they are equivalent, the contact holes 401 and 402 in the pixel area PX and the contact holes 403 and 404 in the peripheral area PR can be formed simultaneously. However, even if the thickness difference between the silicon nitride layer 33 and the silicon nitride layer 32 is 10 nm or less, it is better to perform them as separate steps like steps m and n. In particular, when the distance between the silicon nitride layer 33 and the semiconductor substrate 10 is different from the distance between the silicon nitride layer 32 and the metal-containing parts 163 and 173, it is better to perform them as separate steps like steps m and n.

[0088] The order of step m and step n may be reversed. Also, in this example, step o is performed after steps m and n. However, for example, after arranging conductors in the contact holes 401 and 402 to form the contact plugs 501 and 502, the contact holes 403 and 404 may be formed. After arranging conductors in the contact holes 403 and 404 to form the contact plugs 503 and 504, the contact holes 401 and 402 may be formed.

[0089] In the next step, as shown in FIG. 8(p1) corresponding to FIG. 2(b), an interlayer insulating film 50 and a plurality of wiring layers 51, 52, and 53 are formed on the interlayer insulating film 40. The wiring layers 51, 52, and 53 are copper layers. The wiring layer 51 can be formed by the single damascene method, and the wiring layers 52 and 53 can be formed by the dual damascene method. The interlayer insulating layer 56 is a silicon oxide layer with a thickness of 100 nm to 1000 nm, and the diffusion prevention layer 57 is a silicon carbide layer with a thickness of 10 to 100 nm. The interlayer insulating layer 56 and the diffusion prevention layer 57 can be formed by the plasma CVD method. The interlayer insulating layer 56 can be formed by the plasma CVD method using a silane-based gas as the source gas.

[0090] In step p shown in FIG. 8(p1) corresponding to FIG. 2(b) and FIG. (p2) corresponding to FIG. 3, a resist pattern having an opening corresponding to the photoelectric conversion unit 11 is formed on the interlayer insulating film 50. Then, the interlayer insulating film 50 is etched using this resist pattern as a mask. Further, the interlayer insulating film 40 is etched to form an opening 406 having a bottom formed by the silicon nitride film 310 (silicon nitride layer 31). When etching the interlayer insulating film 40, the silicon nitride layer 31 can function as an etching stopper. More specifically, the etching conditions when etching the interlayer insulating film 40 are such that the etching rate with respect to the silicon nitride layer 31 is lower than the etching rate with respect to the interlayer insulating film 40.

[0091] By the etching during the formation of the opening 406, the silicon nitride layer 31 can be etched. By etching the portion of the silicon nitride layer 31 under the opening 406, the thickness decreases from the thickness T311 to the thickness T312. Thereby, the portion 311 and the portion 312 are formed. The thickness T312 may be 25 to 75% of the thickness T311. By making the silicon nitride layer 31 thick enough, the possibility that the opening 406 penetrates the silicon nitride layer 31 during the formation of the opening 406 can be reduced. Further, the silicon nitride layer 31 can have a function of reducing plasma damage to the photoelectric conversion unit 11 during the etching for forming the opening 406. The effect of the silicon nitride layer 31 reducing plasma damage during the formation of the opening 406 also acts effectively by making the silicon nitride layer 31 thick enough.

[0092] In process q shown in FIG. 8(q1) corresponding to FIG. 2(b) and FIG. 8(q2) corresponding to FIG. 3, as shown in FIG. 3, by disposing a dielectric in the opening 406, a dielectric member 60 including a dielectric region 61 is formed. By disposing a dielectric having a refractive index higher than that of the plurality of interlayer insulating layers 56, for example, silicon nitride, in the opening 406, an optical waveguide is configured in which the dielectric region 61 serves as a core and the plurality of interlayer insulating layers 56 serve as a cladding. The dielectric disposed in the opening 406 may not have a refractive index higher than that of the plurality of interlayer insulating layers 56, and may be, for example, silicon oxide. Even if the thickness of the silicon nitride layer 31 changes due to etching when forming the opening 406 in the interlayer insulating film 40, if silicon nitride is used for the dielectric region 61, the influence on the optical characteristics of the position of the interface between the silicon nitride layer 31 and the dielectric region 61 is reduced.

[0093] A detailed example of a method for forming the dielectric member 60 will be described. First, the opening 406 is filled with silicon nitride having a refractive index higher than that of silicon oxide, which is the main material constituting the plurality of interlayer insulating layers 56. Specifically, silicon nitride is deposited on the entire surface of the semiconductor substrate 10 by the HDP (High Density Plasma)-CVD method, and the opening 406 is filled with silicon nitride. The silicon nitride layer 31 may also have a function of reducing plasma damage to the photoelectric conversion unit 11 when depositing a dielectric by the plasma CVD method. The effect of reducing plasma damage during embedding of the dielectric into the opening 406 also effectively acts by making the silicon nitride layer 31 thick enough. Then, the excess silicon nitride formed in the peripheral area PR is removed by plasma etching. Further, the silicon nitride on the interlayer insulating film 50 outside the opening 406 is planarized by the CMP (Chemical Mechanical Polishing) method. At this time, not all of the silicon nitride disposed on the interlayer insulating film 50 is removed, and a dielectric film 62 is left. The dielectric film 62 is a layer having a thickness of, for example, 100 nm to 500 nm that extends from above the dielectric region 61 to the upper surface of the interlayer insulating film 50. This is to suppress damage to the wiring layer.

[0094] Next, in the peripheral area PR, the dielectric film 62 is removed by etching. Since the dielectric film 62 made of silicon nitride has high residual stress, by reducing the area of the dielectric film 62, warping of the semiconductor substrate 10 and peeling of the dielectric film 62 and the interlayer insulating film 50 can be reduced.

[0095] In the next step r, as shown in FIG. 2(b), an interlayer insulating film 70 is formed so as to cover the dielectric film 62. The interlayer insulating film 70 is made of, for example, silicon oxide and can be formed by a plasma CVD method using silane as a source gas.

[0096] In the next step s, as shown in FIG. 2(b), via holes are formed in the interlayer insulating film 70 in the peripheral area PR. Since the dielectric film 62 has been removed from the peripheral area PR, it becomes easy to form via holes that penetrate the interlayer insulating film 70 and the interlayer insulating film 50 and reach the wiring layer 53. A via plug 54 is formed in the via hole. A wiring layer 55 is formed on the interlayer insulating film 70. The wiring layer 55 can be composed of an aluminum layer and can be patterned to include pad electrodes and light-shielding patterns.

[0097] In the next step t, as shown in FIG. 2(b), a silicon nitride film is formed by a plasma CVD method, and this silicon nitride film is processed so as to have an intra-layer lens 81 to form an inorganic material film 80.

[0098] In the next step u, as shown in FIG. 2(b), an organic material film 90 composed of a planarization layer 91, a color filter layer 92, a planarization layer 93, and a microlens layer 94 is formed on the inorganic material film 80.

[0099] In the next step v, the wafer is diced and divided into a plurality of semiconductor devices ICs.

[0100] In the next step w, the semiconductor device IC is mounted on a package PKG.

[0101] Through the above steps, the photoelectric conversion device APR can be manufactured.

[0102] It is advantageous for improving reliability that the silicon oxide film 21 has a portion 211 in the pixel area PX and a portion 212 in the peripheral area PR. This is because, by having the portion 211 and the portion 212 in the silicon oxide film 21, the difference in height between the pixel area PX and the peripheral area PR in the height of the structure formed on the semiconductor substrate 10 is reduced. The structures formed on the semiconductor substrate 10 are the gate electrodes 42, 43, the silicon nitride layers 31, 32, 33, etc. In the pixel area PX, in addition to the silicon oxide layer 22 and the silicon oxide film 21, there is a silicon nitride layer 31, and the total height becomes larger compared to the silicon nitride layer 32, etc. in the peripheral area PR. This difference in height is followed by the unevenness on the upper surface of the interlayer insulating film 40 formed on this structure. The interlayer insulating film 40 is planarized by the CMP method. At this time, if the unevenness on the upper surface of the interlayer insulating film 40 is large, it is difficult to eliminate the unevenness, and on the upper surface of the interlayer insulating film 40, portions with a large distance from the semiconductor substrate 10 and small portions are likely to occur. That is, even after the planarization of the interlayer insulating film 40, in the pixel area PX where the height of the structure is high, the interlayer insulating film 40 can be high, and in the low peripheral area PR, the interlayer insulating film 40 can be low. Also, in the pixel area PX, the closer to the peripheral area PR, the lower the interlayer insulating film 40 can be. In such a shape, in the etching when forming the contact holes 401, 402, 403, 404, there is a difference in the thickness to be etched. Therefore, there is a possibility of occurrence of opening defects or giving etching damage to the semiconductor substrate 10. In this case, concerns such as short - circuit of the contact plug and deterioration of image quality are raised. Also, in the metal material removal process when forming the contact plugs 501, 502, 503, 504 and the wiring layer 51 by the damascene method, there is a possibility that metal remains in an unintended portion. In this case, concerns such as short - circuit defects of the contact plug and wiring are raised.

[0103] In the above-described manufacturing method, step j (and step k) can also be performed after step g (and step h). And the silicon nitride layer 31 (silicon nitride film 310) can be made thicker than the silicon nitride layer 32 (silicon nitride film 320). However, it is preferable that the silicon nitride layer 31 (silicon nitride film 310) is separated from the photoelectric conversion unit 11, and the silicon nitride layer 32 (silicon nitride film 320) is brought closer to the metal-containing parts 163, 173, 473. Therefore, it is better to perform steps g and h after steps j and k.

[0104] At least one of step h, step i, and step k can be omitted. However, in terms of facilitating the formation of the contact hole as described above, it is preferable to perform steps h and k to eliminate the overlap of the silicon nitride films. Also, in order to separate the silicon nitride layer 31 (silicon nitride film 310) from the photoelectric conversion unit 11, it is preferable to perform step i to form the silicon oxide film 21. Step i is also preferable for adjusting the distance between the silicon nitride layer 31 and the silicon nitride layer 33 of the photoelectric conversion unit 11 to optimize the optical characteristics.

[0105] The silicon nitride film 320 that becomes the silicon nitride layer 32 may have a different thickness, composition, film quality, film formation method, and / or film formation conditions from the silicon nitride film 310 that becomes the silicon nitride layer 31.

[0106] As described above, it is preferable that the silicon nitride layer 31 is thicker and the silicon nitride layer 32 is thinner. In this embodiment, since the silicon nitride film 310 and the silicon nitride film 320 are formed in separate steps g and j, it is easy to optimize the thickness. The difference in thickness between the silicon nitride film 320 and the silicon nitride film 310 is preferably 5 nm or more. The thickness of both can be 10 to 100 nm, and the difference in thickness between the silicon nitride film 320 and the silicon nitride film 310 may be 50 nm or less.

[0107] The silicon nitride film 310 and the silicon nitride film 320 may have different compositions. For example, the composition ratios of silicon (Si) and nitrogen (N) may be different, or the concentrations of elements other than silicon (Si) and nitrogen (N), such as argon (Ar) and chlorine (Cl), may be different.

[0108] The silicon nitride film 310 and the silicon nitride film 320 may have different film qualities. The silicon nitride film 310 (silicon nitride layer 31) and the silicon nitride film 320 (silicon nitride layer 32) may have different residual stresses. It is preferable that the residual stress of the silicon nitride film 310 (silicon nitride layer 31) is smaller than the residual stress of the silicon nitride film 320 (silicon nitride layer 32). The effect of the residual stress will be described. The silicon nitride layer 32 can apply compressive or tensile stress to the channel region of the semiconductor substrate 10, cause distortion in the silicon crystal, and improve the mobility of carriers passing through it. By improving the mobility of the majority carriers of the transistor, the driving ability is improved. Whether it is compression or tension, and the magnitude of the stress can be arbitrarily selected according to the desired effect. The silicon nitride layer 32 can also improve the driving ability of the transistor. In the pixel area PX, in the case of a film with a large compressive or tensile residual stress in the silicon nitride film 310, there is a concern about film peeling due to the problem of adhesion to the silicon oxide layer 22. Therefore, in this embodiment, it is preferable that at least a part of the silicon nitride film 310 in the pixel area PX is removed. Also for the same reason, it is preferable that the residual stress of the silicon nitride layer 31 formed in the pixel area PX is small. That is, it is preferable that the silicon nitride layer 32 and the silicon nitride layer 31 have different residual stresses. The silicon nitride layer 32 and the silicon nitride layer 31 are formed under different conditions in separate processes. For this reason, the residual stress can be individually selected, and films with different residual stresses can be formed. Both the silicon nitride layer 32 and the silicon nitride layer 31 are insulating films made of silicon nitride and are deposited, for example, by plasma CVD method. By adjusting parameters such as the temperature and pressure of the plasma, it is possible to control the residual stress of the deposited film. Also, by adding a heat treatment process, the residual stress of the silicon nitride layer 32 can be changed. In this case, since it is necessary to heat-treat only the silicon nitride layer 32, the heat treatment may be performed before depositing the silicon nitride film 310. By having different residual stresses between the silicon nitride layer 32 and the silicon nitride layer 31, it is possible to achieve both an improvement in the driving ability of the transistor and suppression of film peeling. From this, the performance of the photoelectric conversion device APR can be improved.

[0109] The film formation methods of the silicon nitride film 310 and the silicon nitride film 320 may be different. For example, the silicon nitride film 320 may be formed by thermal CVD method, and the silicon nitride film 310 may be formed by plasma CVD method. One of the silicon nitride film 310 and the silicon nitride film 320 may be formed using DCS (dichlorosilane) as a source gas, and the other of the silicon nitride film 310 and the silicon nitride film 320 may be formed using HCD (hexachlorodisilane) as a source gas.

[0110] The film formation conditions of the silicon nitride film 310 and the silicon nitride film 320 may be different. The plasma power, gas flow rate, gas pressure, and film formation temperature of one of the silicon nitride film 310 and the silicon nitride film 320 may be different from those of the other of the silicon nitride film 310 and the silicon nitride film 320.

[0111] (Second Embodiment) FIG. 9 is a schematic cross-sectional view of the photoelectric conversion device APR according to the second embodiment. FIG. 9 is a cross-section of a portion corresponding to the schematic cross-sectional view of FIG. 3. In FIG. 9, the wiring layer 51 shown in FIG. 3 is omitted.

[0112] In the present embodiment, similar to the silicon nitride layer 31 in the pixel area PX, a silicon nitride layer 34 is disposed between the interlayer insulating film 40 and the silicon oxide film 21 in the peripheral area PR. Note that the contact plugs 503 and 504 do not penetrate the silicon nitride layer 34, and an interlayer insulating film 40 is interposed between the contact plugs 503 and 504 and the silicon nitride layer 34. By disposing the silicon nitride layer 34, the height difference of the base of the interlayer insulating film 40 caused by the thickness of the silicon nitride layer 31 can be reduced. Further, the height difference of the base of the interlayer insulating film 40 caused by the silicon nitride layer 31 being thicker than the silicon nitride layer 32 can be reduced. Further, the height difference of the base of the interlayer insulating film 40 caused by the thickness of the insulator film 49 can be reduced.

[0113] This embodiment is different in the patterning of the silicon nitride film 310 in step j of the manufacturing method of the first embodiment. In the first embodiment, after the silicon nitride film 310 is formed, the silicon nitride film 310 in the peripheral area PR is removed by etching, but in this embodiment, at least a part of the silicon nitride film 310 is left in the peripheral area PR. When patterning the silicon nitride film 310, it is patterned so that a portion at an arbitrary position in the peripheral area PR of the silicon nitride film 310 remains as the silicon nitride layer 34. That is, a part of the silicon nitride film 310 is located between the silicon nitride film 320 and the interlayer insulating film 40. The thickness of the silicon nitride layer 34 is equivalent to the thickness of the silicon nitride layer 31, and even considering errors, it is 95 to 105% of the thickness of the silicon nitride layer 31.

[0114] In this embodiment, for the same reason as in the first embodiment where the silicon oxide film 21 has a portion 211 in the pixel area PX and a portion 212 in the peripheral area PR, the reliability of the photoelectric conversion device APR can be improved. That is, under the interlayer insulating film 40, the height difference between the pixel area PX and the peripheral area PR caused by at least the thickness of the silicon nitride film 310 can be reduced, and the flatness of the upper surface of the interlayer insulating film 40 can be improved.

[0115] Here, it is preferable that the position of the silicon nitride layer 34 is a position that avoids the positions where the contact plugs 501, 502, 503, 504 are formed in later steps. In other words, the silicon nitride layer 34 is provided away from the contact plugs 501, 502, 503, 504. For this purpose, the silicon nitride film 310 can be patterned so that the silicon nitride layer 34 has openings corresponding to the contact plugs 503, 504. This is because, as described in steps n and m, when forming the contact holes 401, 402, 403, 404, if the etching of the silicon nitride film 310 is involved, it becomes difficult to switch the etching conditions and set the etching stop conditions. As described above, according to this embodiment, by leaving at least a part of the silicon nitride film 310 in the peripheral area PR, it is possible to suppress the occurrence of defects and also suppress the deterioration of the image quality.

[0116] (Third Embodiment) FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device APR according to the third embodiment. FIG. 10 is a cross-section of a portion corresponding to the schematic cross-sectional view of FIG. 3. In FIG. 9, the wiring layer 51 shown in FIG. 3 is omitted.

[0117] In this embodiment, in the pixel area PX, the semiconductor substrate 10 is provided with a charge holding portion 18 that holds the charges generated in the photoelectric conversion portion 11. The charges generated in the photoelectric conversion portion 11 are transferred to the charge holding portion 18 by a transfer gate including a gate electrode 41. The charges held in the charge holding portion 18 are transferred to the charge detection portion 12 by a transfer gate including a gate electrode 42. Since it may be considered that the thickness of the gate electrode 41 is equal to the thickness of the gate electrode 42, the thickness of the gate electrode 41 is shown as T42. The charge holding portion 18 includes an n-type semiconductor region 181 as a charge holding region, a p-type semiconductor region 182 as a well region, and a p-type semiconductor region 183 between the semiconductor region 181 and the surface of the semiconductor substrate 10.

[0118] The photoelectric conversion device APR of this embodiment further includes a light-shielding film 58 that covers the charge holding portion 18 between the silicon oxide film 21 and the charge holding portion 18. The light-shielding film 58 has an opening 580 on the photoelectric conversion portion 11, and the photoelectric conversion portion 11 receives light through the opening 580. In other words, the light-shielding film 58 does not overlap the portion below the opening 580 in the photoelectric conversion portion 11. By providing the charge holding portion 18 shielded from light by the light-shielding film 58, a global electronic shutter function can be realized. In this example, the light-shielding film 58 overlaps a part of the photoelectric conversion portion 11 in order to enhance the light-shielding property to the charge holding portion 18.

[0119] A height difference may occur between the pixel area PX and the peripheral area PR by the thickness of the light-shielding film 58. The silicon oxide film 21 has a portion 213 located between the interlayer insulating film 40 and the light-shielding film 58. By having the portion 212 of the silicon oxide film 21 located in the peripheral area PR, the height difference corresponding to the thickness of the light-shielding film 58 can be reduced. A silicon oxide film 25 is provided between the light-shielding film 58 and the silicon oxide layer 22. A portion 253 of the silicon oxide film 25 located under the light-shielding film 58 may have a function of planarizing to relieve the height difference of the base of the light-shielding film 58 by the gate electrodes 41 and 42. The silicon oxide film 25 has a portion 252 located between the silicon oxide film 21 and the silicon nitride layer 32.

[0120] Although not shown, the light-shielding film 58 is a metal-containing member, and a contact plug contacting the light-shielding film 58 can be formed in a contact hole penetrating the interlayer insulating film 40 and the silicon oxide film 21. In that case, it is preferable to provide a silicon nitride layer between the interlayer insulating film 40 and the silicon oxide film 21 as an etching stopper for the contact hole and for preventing diffusion of the metal in the light-shielding film 58.

[0121] (Regarding the device equipped with the photoelectric conversion device) The device EQP shown in Fig. 1(a) will be described in detail. The photoelectric conversion device APR may include, in addition to the semiconductor device IC having the semiconductor substrate 10, a package PKG that houses the semiconductor device IC. The package PKG may include a base on which the semiconductor device IC is fixed, a lid such as glass facing the semiconductor device IC, and connection members such as bonding wires and bumps that connect the terminals provided on the base and the terminals provided on the semiconductor device IC.

[0122] The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, and a storage device MMRY. The optical system OPT forms an image on the photoelectric conversion device APR, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes the signal output from the photoelectric conversion device APR, and is a semiconductor device such as a CPU or an ASIC for constituting an AFE (analog front end) or a DFE (digital front end). The display device DSPL is an EL display device or a liquid crystal display device that displays the information (image) obtained by the photoelectric conversion device APR. The storage device MMRY is a magnetic device or a semiconductor device that stores the information (image) obtained by the photoelectric conversion device APR. The storage device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a movable part or a propulsion part such as a motor or an engine. In the equipment EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL or transmitted externally by a communication device (not shown) provided in the equipment EQP. For this purpose, it is preferable that the equipment EQP further includes a storage device MMRY and a processing device PRCS separately from the storage circuit part and the arithmetic circuit part of the photoelectric conversion device APR.

[0123] The equipment EQP shown in FIG. 1(a) can be an electronic device such as an information terminal having a photographing function (for example, a smartphone or a wearable terminal) or a camera (for example, an interchangeable-lens camera, a compact camera, a video camera, a surveillance camera). The mechanical device MCHN in the camera can drive the components of the optical system OPT for zooming, focusing, and shutter operation. In addition, the device EQP can be a transportation device (mobile body) such as a vehicle, a ship, or an aircraft. The mechanical device MCHN in the transportation device can be used as a moving device. The device EQP as a transportation device is suitable for transporting the photoelectric conversion device APR or for assisting and / or automating driving (operation) by means of a photographing function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing for operating the mechanical device MCHN as a moving device based on the information obtained by the photoelectric conversion device APR.

[0124] By using the photoelectric conversion device APR according to this embodiment, high performance can be achieved. Therefore, when the photoelectric conversion device APR is mounted on a transportation device to perform external photographing or measurement of the external environment of the transportation device, excellent image quality and measurement accuracy can be obtained. In addition, the reliability can be enhanced to be sufficient for mounting on a device used in a harsh environment such as a transportation device. Thus, in manufacturing and selling transportation devices, determining to mount the photoelectric conversion device APR of this embodiment on the transportation device is advantageous for enhancing the performance of the transportation device.

[0125] As described above, the embodiments described can be appropriately modified without departing from the technical idea. Note that the disclosed content of the embodiments includes not only what is specifically described in this specification but also all matters that can be grasped from this specification and the drawings attached to this specification.

Description of Reference Numerals

[0126] 10 Semiconductor substrate 11 Photoelectric conversion section 40 Interlayer insulating film 163, 173 Metal-containing section 47 Gate electrode 48 Sidewall spacer 31 Silicon nitride layer 310 Silicon nitride film 32 Silicon nitride layer 320 Silicon nitride film 21 Silicon oxide film 503 Contact plug

Claims

1. a semiconductor substrate having a photoelectric conversion unit and a charge retention unit that retains charges generated by the photoelectric conversion unit; a silicide portion provided on the semiconductor substrate; an interlayer insulating film disposed on the silicide portion; a dielectric region disposed on the photoelectric conversion unit so as to be surrounded by the interlayer insulating film; a light-shielding film located between the interlayer insulating film and the semiconductor substrate; a first insulating layer made of a material other than silicon oxide and disposed between the interlayer insulating film and the photoelectric conversion unit; a first silicon oxide film having a first portion disposed between the first insulating layer and the photoelectric conversion portion and a second portion disposed between the interlayer insulating film and the silicide portion; a second silicon oxide film disposed between the first insulating layer and the photoelectric conversion portion; a second insulating layer made of a material different from silicon oxide and disposed between the first silicon oxide film and the silicide portion; Equipped with the light-shielding film is disposed so as to cover the charge retention portion, a portion of the first silicon oxide film is disposed between the first insulating layer and the light-shielding film; a gate electrode of a transfer transistor that transfers charges from the photoelectric conversion portion to the charge storage portion, and a portion of the second silicon oxide film is disposed between the light shielding film and the gate electrode of the transfer transistor.

2. An electrode is disposed on the semiconductor substrate; 2. The photoelectric conversion device according to claim 1, wherein the silicide portion is disposed on the electrode.

3. a sidewall spacer covering a side surface of the electrode; 3. The photoelectric conversion device according to claim 2, wherein the second insulating layer is disposed between the first silicon oxide film and the sidewall spacer.

4. an impurity region provided in the semiconductor substrate; 4. The photoelectric conversion device according to claim 1, wherein the silicide portion is disposed on the impurity region.

5. The photoelectric conversion device according to claim 1 , wherein the dielectric region contains silicon nitride.

6. The photoelectric conversion device according to claim 1 , wherein the first insulating layer has a portion having a thickness greater than a thickness of the second insulating layer.

7. 7. The photoelectric conversion device according to claim 1, further comprising a contact plug in contact with the interlayer insulating film and the silicide portion, the contact plug penetrating the first silicon oxide film.

8. 8. The photoelectric conversion device according to claim 1, wherein a distribution of the thickness of the first silicon oxide film from the first portion to the second portion is within ±10%.

9. 9. The photoelectric conversion device according to claim 1, wherein the first insulating layer and the second insulating layer are silicon nitride layers.

10. The photoelectric conversion device according to claim 1 , wherein the second silicon oxide film is disposed between the first silicon oxide film and the gate electrode.

11. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 10, An apparatus further comprising at least one of an optical system that forms an image on the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes a signal output from the photoelectric conversion device, a mechanical device that is controlled based on information obtained by the photoelectric conversion device, a display device that displays the information obtained by the photoelectric conversion device, and a memory device that stores the information obtained by the photoelectric conversion device.

Images