Semiconductor wafer and method for manufacturing the same

Abstract

To provide a semiconductor wafer that allows information relating to elements in the semiconductor wafer to be kept confidential before dicing to cut out semiconductor chips.SOLUTION: A semiconductor wafer 100 includes a plurality of semiconductor circuit regions 10, dicing streets DS defined between the semiconductor circuit regions 10, and a destroyed process control monitor structure PCM1 provided within the dicing streets DS.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor wafers and methods for manufacturing semiconductor wafers. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-89648 A

[0004] [overview] The present disclosure provides a semiconductor wafer that allows information relating to elements within the semiconductor wafer to be kept confidential before dicing to cut out semiconductor chips.

[0005] A semiconductor wafer of the present disclosure includes a plurality of semiconductor circuit regions, dicing streets defined between the semiconductor circuit regions, and a destroyed process control monitor structure disposed within the dicing streets. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor wafer. [Diagram 2] FIG. 2 is a plan view of one unit exposure field SN. [Diagram 3] FIG. 3 is a plan view of an example of the first process control monitor configuration PCM1. [Figure 4] FIG. 4 is a plan view of another example of the first process control monitor structure PCM1. [Diagram 5] FIG. 5 is a plan view of an example of the first process control monitor structure PCM1 destroyed by the laser beam. [Figure 6]FIG. 6 is a plan view of one unit exposure field SN for explaining blind exposure. [Figure 7] 7A and 7B are a vertical cross-sectional view of a semiconductor device having a contact electrode (FIG. 7A) and a vertical cross-sectional view of a semiconductor device having no contact electrode (FIG. 7B).

[0007] [Detailed Description] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or corresponding parts in each drawing are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0008] FIG. 1 is a plan view of a semiconductor wafer 100.

[0009] An XYZ three-dimensional orthogonal coordinate system is set. The thickness direction of the semiconductor wafer 100 is defined as the Z-axis direction, the direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The main surface of the semiconductor wafer 100 is an XY plane. Note that an orientation flat or notch formed on the outer edge of the semiconductor wafer 100 is omitted.

[0010] The semiconductor wafer 100 is divided into a plurality of unit exposure areas S N The exposure apparatus that performs division exposure of reduced projection includes a unit exposure area S N and a stepper that exposes a unit exposure area S N There is a scanner that exposes each unit exposure area S N is a unit area formed by exposure by one shot or scanning by an exposure device. N In the above, N is a natural number (1, 2, 3, etc.). Each unit exposure area S N The planar shape of each unit exposure area S is a rectangle. The dimensions of the short side and the long side of the rectangle depend on the chip size, and the unit exposure area S may be a square having the same dimensions. N are arranged in a matrix. The unit exposure area located at the left end of the first row is called the first unit exposure area S1 When moving to the column to the right of a certain unit exposure area, the number N increases by 1. Let M be a natural number (1, 2, 3, . . .) as the row number. The maximum value of M in this example is M MAX The number next to the number N at the right end of the Mth row is the number N at the left end of the M+1th row. In the figure, there are 79 (N=1 to 79) unit exposure areas S N Of course, the maximum number of shots and rows in a unit exposure area depends on the chip size, and is not limited to the numbers in this example.

[0011] Multiple unit exposure areas S N Among them, the unit exposure areas located near the edge of the semiconductor wafer 100 each include a partially incomplete exposure area. In the figure, the unit exposure areas including the incomplete exposure area are marked with an "x". More specifically, when M=1, M=M MAX The unit exposure area group (S 1 ~S 5 , S 75 ~S 79 ) each contain partially incomplete exposure areas. Also, the unit exposure areas located at the left and right ends of the rows when M is an even number (M=2, 4, 6, 8) each contain partially incomplete exposure areas. These incomplete exposure areas are the same as the left and right end unit exposure areas (S 6 , S 14 ), the left and right edge unit exposure areas (S 24 , S 34 ), the left and right edge unit exposure areas (S 46 , S 56 ), the left and right edge unit exposure areas (S 66 , S 74 ).

[0012] An exemplary substrate material of the semiconductor wafer 100 is Si (silicon). Compound semiconductors such as SiC (silicon carbide) or GaN (gallium nitride) can also be used as the substrate material of the semiconductor wafer 100. The structure of the semiconductor wafer 100 can also be a structure in which a semiconductor layer is formed on an insulating substrate or insulating layer, such as an SOI (silicon on insulator) structure.

[0013] FIG. 2 shows a single unit exposure area S N FIG.

[0014] One unit exposure area S N includes a plurality of semiconductor circuit regions 10. The plurality of semiconductor circuit regions 10 are arranged in a matrix. After dicing, each of the semiconductor circuit regions 10 becomes a semiconductor chip. A dicing street DS is set between adjacent semiconductor circuit regions 10. The dicing street width is a width that defines the space between the semiconductor circuit regions 10 along the center line (dotted line) of the dicing street DS. One unit exposure region S N In the wafer processing machine, the dicing streets DS are generally set in a grid pattern. The semiconductor wafer is diced along the dicing streets DS. The semiconductor wafer can be diced by using a blade or a laser.

[0015] A plurality of process control monitor (PCM) structures are formed in the dicing street DS.

[0016] The first process control monitor structure PCM1 includes an electrode pad and an active element. An example of an active element is a transistor. If the semiconductor circuit region 10 includes a transistor, a transistor having the same structure can be formed in the first process control monitor structure PCM1. A plurality of first process control monitor structures PCM1 are formed in a dicing street DS provided between the semiconductor circuit regions 10 in the first to fifth rows from the bottom of the figure.

[0017] The first process control monitor structure PCM1 has a plurality of electrode pads electrically connected to the terminals of the active elements. By contacting these electrode pads with probe electrodes and connecting the probe electrodes to a characteristic measuring device (e.g., a semiconductor parameter analyzer), the electrical characteristics of the active elements (e.g., current amplification factor, switching time, forward transfer admittance, etc.) can be measured. An autoprober equipped with a probe card can be used to contact the probe electrodes. In the EDS (Electrical Die Sorting) process for quality inspection, the semiconductor wafer is brought into contact with the probe card, test signals are sent to the active elements via the probe electrodes, and the electrical characteristics of the active elements are measured, thereby carrying out the quality inspection. If a semiconductor circuit region 10 or unit exposure area S does not meet the required level of quality, N These can be selected as defective products and removed in the process after dicing.

[0018] For example, if a measured characteristic value of an active element included in the first process control monitor structure PCM1 is lower than a threshold value, the active element can be determined to be defective.

[0019] The plurality of second process control monitor structures PCM2 are arranged to monitor one unit exposure area S N The second process control monitor structures PCM2 are aligned along the Y-axis direction within a dicing street DS located at the center in the X-axis direction of the semiconductor circuit regions 10 in the fourth and fifth rows from the top. The second process control monitor structures PCM2 are aligned along the X-axis direction within a dicing street DS in a gap between the semiconductor circuit regions 10 in the fourth and fifth rows from the top. The second process control monitor structures PCM2 are patterns for measuring the film thickness of specific elements, and this pattern is used for process control, and can also be used as an alignment mark when performing various processes.

[0020] One unit exposure area S NIn the dicing street DS constituting the outer frame around the wafer W, an accessory area PCM3 in which a plurality of accessory patterns are formed is set near the area constituting the four corners of the outer frame. The accessory area PCM3 is an area including a PCM structure and an alignment mark. A plurality of fourth process control monitor structures PCM4 are formed in the accessory area PCM3. The fourth process control monitor structure PCM4 is a pattern for measuring the dimensions and positional deviation of a specific element, and this pattern is used for process management, and can also be used as an alignment mark when performing various processes.

[0021] The specific elements to be measured in the second process control monitor structure PCM2 and the fourth process control monitor structure PCM4 are similar to the elements used in the semiconductor circuit region 10. These elements are wiring, electrodes, insulating films (oxide films, nitride films), etc., and the film thickness, dimensions, positional deviation, and, if necessary, electrical characteristics such as capacitance and resistance of these elements can be measured.

[0022] In the semiconductor wafers mentioned above, by measuring the characteristics of various PCM structures, it is possible to inspect whether the quality of each element (device) that constitutes them meets the required standards and to confirm whether there are any defects in the manufacturing process.

[0023] As described above, the semiconductor wafer 100 includes a plurality of semiconductor circuit regions 10, dicing streets DS set between the semiconductor circuit regions 10, and a destroyed first process control monitor structure PCM1 provided within the dicing streets DS. Since the first process control monitor structure PCM1 is destroyed, information on elements in the semiconductor wafer, i.e., information on the first process control monitor structure PCM1 and information on elements in the corresponding semiconductor chip, are kept confidential.

[0024] FIG. 3 is a plan view of an example of the first process control monitor configuration PCM1.

[0025] The first process control monitor structure PCM1 includes a transistor TR1. The transistor TR1 in this example is a field effect transistor (FET). Known types of field effect transistors include JFET (junction field effect transistor) and MISFET (metal insulator semiconductor field effect transistor). Known MISFETs include MOSFET (metal oxide semiconductor field effect transistor). Although an enhancement type N-channel MOSFET is shown in the figure as an example, the structure of the transistor TR1 is not limited to this. A DMOSFET (double diffused MOSFET) can also be used as the structure of the field effect transistor. The field effect transistor includes a source terminal connected to the source region, a gate electrode connected to the gate electrode, a drain terminal connected to the drain region, and a back gate terminal connected to the back gate electrode. A bipolar transistor can also be used as the structure of the transistor TR1. The bipolar transistor includes an emitter terminal, a base terminal, and a collector terminal.

[0026] The first process control monitor structure PCM1 includes a first electrode pad P1, a second electrode pad P2, a third electrode pad P3, and a fourth electrode pad P4 electrically connected to the respective terminals of the transistor TR1. When the transistor TR1 is a field effect transistor, the first electrode pad P1 is connected to the gate terminal, the second electrode pad P2 is connected to the source terminal, the third electrode pad P3 is connected to the drain terminal, and the fourth electrode pad P4 is connected to the back gate terminal.

[0027] The transistor TR1 is formed by the same process as the transistor formed in the semiconductor circuit region 10 (see FIG. 2). After a characteristic measuring device is connected to the first electrode pad P1 to the fourth electrode pad P4 to measure the characteristics of the transistor TR1, an overvoltage is applied to the transistor TR1 to destroy the transistor TR1. An overvoltage is a voltage that exceeds the maximum rating of a transistor and destroys the transistor. Specifically, an overvoltage can be applied between the source terminal and the gate terminal (between the first electrode pad P1 and the second electrode pad P2) to destroy the gate oxide film. Due to this destruction, information about the transistor or information reflecting the manufacturing process cannot be easily obtained. Whether the transistor has been destroyed can be determined by visual observation or by re-measuring the characteristics.

[0028] If the transistor TR1 is a bipolar transistor, for example, the transistor can be destroyed by applying a voltage exceeding the maximum rating between the emitter terminal and the base terminal (between the electrode pads connected to these).

[0029] As described above, the first process control monitor structure PCM1 in the semiconductor wafer includes the destroyed transistor TR1. Since the transistor TR1 is destroyed, it is difficult to obtain characteristic information of the transistor and the transistor in the semiconductor circuit region corresponding to the destroyed transistor.

[0030] FIG. 4 is a plan view of another example of the first process control monitor structure PCM1.

[0031] The transistor TR1 included in the first process control monitor structure PCM1 of this example is, for example, an N-channel type DMOSFET. The transistor TR1 has a source terminal connected to a source region, a gate terminal connected to a gate electrode, and a drain terminal connected to a drain region. The source terminal is connected to a first electrode pad P1, the gate terminal is connected to a second electrode pad P2, and the drain terminal is connected to a third electrode pad P3. The fourth electrode pad P4 is electrically connected to a semiconductor substrate. In the case of this structure, as in the method described in FIG. 3, after measuring the transistor characteristics, an overvoltage can be applied to destroy the transistor.

[0032] FIG. 5 is a plan view of an example of the first process control monitor structure PCM1 destroyed by the laser beam.

[0033] The structure of the first process control monitor structure PCM1 of this example is the same as that shown in FIG. 3, but the transistor TR1 is destroyed and a laser light irradiation mark SP is formed on the transistor TR1. This laser light has an intensity sufficient to destroy, for example, a gate oxide film, and can destroy the transistor TR1. A laser marker is known as a laser light irradiation device having such an intensity. The laser marker can form a dot-shaped hole having a diameter of, for example, about 14 μm at the irradiation point by irradiating the laser light once. For example, the laser light can be irradiated so that these dots are arranged in a spiral shape, and a destruction area having a diameter of 600 μm as a whole can be formed.

[0034] As described above, the transistor TR1 in the first process control monitor structure PCM1 of the semiconductor wafer is a transistor TR1 having a laser light irradiation mark SP. Since this transistor TR1 is destroyed by the laser light irradiation, it becomes difficult to obtain characteristic information of this transistor and the transistor in the semiconductor circuit region corresponding to this transistor.

[0035] Such a laser light irradiation pattern can also be used simply for marking. For example, if the measured characteristic value of a transistor is equal to or less than a threshold value, a laser marker can be used to apply a marking indicating this information within the dicing street.

[0036] FIG. 6 shows a unit exposure area S N FIG.

[0037] Most of the process control monitor structures in a semiconductor wafer can be destroyed by the application of an overvoltage or by irradiation with a laser beam as described above. On the other hand, in a unit exposure area including an incomplete exposure area shown by an "x" mark in Fig. 1, since the exposure pattern is incomplete, an overvoltage cannot be applied to the process control monitor structure, and therefore the process control monitor structure may not be destroyed.

[0038] Therefore, in the unit exposure areas including the incomplete exposure area, a process is adopted in which the process control monitor structure is not completely manufactured. As a result, the process control monitor structure is in an incomplete state, and it is not necessary to destroy the process control monitor structure in these areas. In order to create the incomplete process control monitor structure, a first process control monitor structure PCM1 (incomplete process control monitor structure PCM1) is destroyed at any exposure stage during the manufacturing of the process control monitor structure. BLD ) is shaded.

[0039] For example, in the manufacturing process of the first process control monitor structure PCM1, after forming a transistor, an insulating film is formed on a gate electrode. Then, a photoresist is applied on the insulating film, the photoresist is exposed and developed to form a pattern for forming a contact hole, and the insulating film is etched through the pattern to form a contact hole. Then, a contact electrode connected to an electrode pad is formed in the contact hole by a sputtering method, a deposition method, a chemical vapor deposition (CVD) method, a plating method, or the like. If the contact hole patterning process is prohibited here, the contact hole is not formed. The exposure device is provided with a reticle (photomask) between the exposure light source and the semiconductor substrate, and when a positive photoresist is used, the exposed area of ​​the photoresist is etched during development. If the contact hole pattern on the reticle is shielded from light, the contact hole formation pattern is not formed, and the formation of the contact hole (and the contact electrode) can be prevented. This shielding process may be performed in another exposure process. Of course, such a shielding process is not performed in a unit exposure area including a complete exposure area not marked with an "x" in FIG. 1.

[0040] An electrode layer is provided on the contact electrode. That is, after the contact electrode is formed in the contact hole, the photoresist is removed. Thereafter, photoresist is formed again on the surface of the insulating film, and the photoresist is exposed to light and developed to form an opening pattern for forming an electrode layer, and an opening is formed in the photoresist, and then an electrode layer is formed in the opening. If the above-mentioned light-shielding process is not performed, the electrode layer and the contact electrode are connected. If the above-mentioned light-shielding process is performed, no contact electrode exists below the electrode layer.

[0041] In this example, a light-shielding area SA including the semiconductor circuit area 10 of the bottom five rows is set on the reticle. BLD This incomplete process control monitor structure PCM1 is formed. BLDOn the other hand, when the light shielding process is not performed, the complete first process control monitor structure PCM1 is formed in the exposure area EA (see FIG. 2) including the bottom five rows of the semiconductor circuit area 10 in the reticle.

[0042] 7A and 7B are a vertical cross-sectional view of a semiconductor device having a contact electrode (FIG. 7A) and a vertical cross-sectional view of a semiconductor device having no contact electrode (FIG. 7B).

[0043] The process control monitor structure (transistor) not subjected to the above-mentioned light shielding treatment includes a semiconductor substrate 31 (or well). This transistor includes an impurity doped region 32 formed in the semiconductor substrate 31, a gate oxide film 33 formed on the surface of the semiconductor substrate 31, and a gate electrode 34 formed on the gate oxide film 33. An insulating film 35 is formed on the gate electrode 34, and the insulating film 35 is covered with a photoresist 36. The photoresist 36 can be removed in a later process.

[0044] As shown in FIG. 7A, the transistor formed in the exposure area EA where no light shielding treatment is performed includes a first electrode 37 and a second electrode 38. The first electrode 37 includes a contact electrode and an electrode layer located on the contact electrode. The contact electrode of the first electrode 37 is formed in a contact hole of the insulating film 35 and is connected to the gate electrode 34. The second electrode 38 includes a contact electrode and an electrode layer located on the contact electrode. The contact electrode of the second electrode 38 is formed in a contact hole of the insulating film 35 and is connected to the impurity doped region 32. When the transistor is a field effect transistor, the impurity doped region 32 indicates one of the source region and the drain region. The other region of the source region and the drain region is located on the opposite side of the gate, but this is not shown. A signal from the impurity doped region 32 can be taken out to the outside via the second electrode 38. These electrode layers correspond to the electrode pads described above. A signal capable of performing characteristic measurement can be taken out from the contact electrode of the process control monitor structure where no light shielding treatment is performed.

[0045] As shown in FIG. 7B, the transistor formed in the light-shielding region SA where the light-shielding process is performed includes a first electrode 37' and a second electrode 38' that do not have contact electrodes. The first electrode 37' includes only an electrode layer formed on the insulating film 35. The second electrode 38' also includes only an electrode layer formed on the insulating film 35. Therefore, a signal cannot be extracted from the impurity doped region 32 to the outside. That is, the process control monitor structure in the incomplete unit exposure region located in the peripheral region of the semiconductor wafer is manufactured in an incomplete intermediate state, and therefore a signal capable of performing characteristic measurement cannot be extracted.

[0046] As described above, among the multiple semiconductor circuit regions 10 in a semiconductor wafer, the dicing street adjacent to the semiconductor circuit region located on the periphery of the semiconductor wafer (the semiconductor circuit region in the unit exposure region marked with the above "x") includes an intermediate body of a process control monitor structure having a structure that cannot output a signal. Even if the transistor in the process control monitor structure cannot be destroyed by applying an overvoltage, it is not possible to extract a signal for characteristic measurement from such an intermediate body, making it difficult to extract characteristic information of the element.

[0047] Next, a method for manufacturing a semiconductor wafer will be briefly described.

[0048] As shown in Figs. 1 to 4, the method for manufacturing a semiconductor wafer includes the steps of preparing a semiconductor wafer 100 including a plurality of semiconductor circuit regions 10, dicing streets DS set between the semiconductor circuit regions 10, and a first process control monitor structure PCM1 provided in the dicing streets DS, and applying an overvoltage to the first process control monitor structure PCM1 to destroy it. The first process control monitor structure PCM1 includes a transistor, but may include a diode as an active element. When the process control monitor structure is a passive element such as a resistor, the process control monitor structure can also be destroyed by applying an overvoltage across the resistor that destroys the resistor. In the above example, it is difficult to obtain characteristic information of an element (such as a transistor) in the process control monitor structure and an element in the semiconductor circuit region corresponding to this element.

[0049] As shown in Figs. 1, 2 and 5, the method for manufacturing a semiconductor wafer includes the steps of preparing a semiconductor wafer 100 including a plurality of semiconductor circuit regions 10, dicing streets DS set between the semiconductor circuit regions 10, and a first process control monitor structure PCM1 provided in the dicing streets DS, and irradiating the first process control monitor structure PCM1 with laser light to destroy it. The first process control monitor structure PCM1 includes a transistor, but may include a diode as an active element. When the process control monitor structure is a passive element such as a resistor, it is also possible to destroy the process control monitor structure by irradiating the resistor with laser light that destroys the resistor. In the above example, it is difficult to obtain characteristic information of an element (such as a transistor) in the process control monitor structure and an element in the semiconductor circuit region corresponding to this element.

[0050] 1, 6 and 7, the method for manufacturing a semiconductor wafer includes a step of forming an intermediate of a process control monitor structure having a structure that cannot output a signal in a dicing street DS adjacent to a semiconductor circuit region located on the periphery of a semiconductor wafer 100 among a plurality of semiconductor circuit regions 10. Since the intermediate is an incomplete process control monitor structure, it is difficult to obtain characteristic information of an element (transistor, etc.) in the process control monitor structure and an element in the semiconductor circuit region corresponding to this element, even without performing a destructive process.

[0051] In the method for manufacturing a semiconductor wafer, the step of forming an intermediate of the process control monitor structure includes a step of preventing the formation of a structure for outputting a signal from the process control monitor structure. In the example shown in FIG. 7(B), a part of the reticle is shielded from light so that the structure for outputting a signal (contact electrode) is not formed, thereby preventing the formation of the structure. Other steps can be considered as the step of preventing the formation of the structure for outputting a signal. For example, a light shielding process of a mask pattern may be performed so that an opening of the mask is not formed when forming an impurity doped region. Alternatively, a process of applying an insulating material onto the region including the target process control monitor structure may be performed.

[0052] (Additional Note) As described above, according to the above-mentioned semiconductor wafer and the method for manufacturing the semiconductor wafer, it is possible to conceal information related to elements in the semiconductor wafer before dicing. Various embodiments of the present disclosure can be defined as the following additional notes.

[0053] [A1] A semiconductor wafer comprising a plurality of semiconductor circuit regions 10, dicing streets DS set between the semiconductor circuit regions, and a destroyed process control monitor structure (PCM1) provided within the dicing streets DS. Since the process control monitor structure is destroyed in the semiconductor wafer state, information about elements in the semiconductor wafer can be kept confidential. Even if the semiconductor wafer is sold, characteristic information about the elements is kept confidential.

[0054] [A2] The semiconductor wafer according to A1, wherein the process control monitor structure (PCM1) includes a destroyed transistor, the transistor being easily destroyed by application of an overvoltage.

[0055] [A3] The semiconductor wafer according to A2, wherein the transistor has a laser beam irradiation mark SP. The transistor can be destroyed by laser beam irradiation.

[0056] [A4] The semiconductor wafer according to A1, wherein, among the plurality of semiconductor circuit regions, a dicing street adjacent to a semiconductor circuit region located on the periphery of the semiconductor wafer includes an intermediate body of a process control monitor structure (PCM1) having a structure that cannot output a signal. By leaving the process control monitor structure located in a position where it is difficult to destroy it by application of an overvoltage or the like as an intermediate body rather than completing it, it is not possible to extract a signal from the process control monitor structure in the semiconductor wafer state, and information regarding elements in the semiconductor wafer can be kept confidential.

[0057] [A5] A method for manufacturing a semiconductor wafer, comprising the steps of: preparing a semiconductor wafer including a plurality of semiconductor circuit regions, dicing streets set between the semiconductor circuit regions, and a process control monitor structure provided within the dicing streets; and applying an overvoltage to the process control monitor structure (PCM1) to destroy it. In the state of the semiconductor wafer, the process control monitor structure is destroyed by applying an overvoltage, so that information relating to elements in the semiconductor wafer can be kept confidential.

[0058] [A6] A method for manufacturing a semiconductor wafer, comprising the steps of: preparing a semiconductor wafer having a plurality of semiconductor circuit regions, dicing streets set between the semiconductor circuit regions, and a process control monitor structure provided within the dicing streets; and irradiating the process control monitor structure (PCM1) with laser light to destroy it. Since the process control monitor structure is destroyed by irradiating the laser light in the semiconductor wafer state, information relating to elements in the semiconductor wafer can be kept confidential.

[0059] [A7] The method for manufacturing a semiconductor wafer according to A5 or A6, further comprising the step of forming an intermediate process control monitor structure (PCM1) having a structure that cannot output a signal in a dicing street adjacent to a semiconductor circuit region located on the periphery of the semiconductor wafer among the plurality of semiconductor circuit regions. Since the intermediate process control monitor structure cannot output a signal, information related to elements in the semiconductor wafer can be kept confidential.

[0060] [A8] The step of forming an intermediate of the process control monitor structure (PCM1) includes a step of inhibiting the formation of a structure for outputting a signal from the process control monitor structure. In the method of manufacturing a semiconductor wafer according to A7, by inhibiting the formation of the structure for outputting a signal from the process control monitor structure, it becomes impossible for the process control monitor structure to output a signal, and information relating to elements in the semiconductor wafer can be concealed.

[0061] [A9] In a semiconductor wafer, a unit exposure area S located at the center of the semiconductor wafer (FIG. 1) N A first type process control monitor structure (PCM1) formed in a dicing street DS adjacent to a semiconductor circuit region 10 (FIG. 2) in the semiconductor wafer, and a unit exposure region S located on the periphery of the semiconductor wafer. N and a second type process control monitor structure (PCM1) formed in a dicing street DS adjacent to the semiconductor circuit region 10 (FIG. 6) in the region marked with an x. The transistor of the first type process control monitor structure has a contact electrode (38) connected to the impurity doped region 32 constituting the source region or drain region of the transistor (FIG. 7(A)), and the transistor (gate oxide film 33) is destroyed (FIG. 7(A)). The transistor of the second type process control monitor structure does not have a contact electrode connected to the impurity doped region 32 constituting the source region or drain region of the transistor (FIG. 7(B)), and has a structure that cannot take out a signal to the outside. In the state of a semiconductor wafer, the first type process control monitor structure is destroyed, and the second type process control monitor structure has a structure that cannot output a signal, so that information about the elements in the semiconductor wafer can be kept secret. Even if the semiconductor wafer is sold, the characteristic information of the elements is kept secret.

[0062] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Elements in different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the claims. [Explanation of symbols]

[0063] 100...semiconductor wafer, 10...semiconductor circuit region, DS...dicing street, TR1...transistor, 31...semiconductor substrate, 32...impurity doped region, 33...gate oxide film, 34...gate electrode, 35...insulating film, 36...photoresist, 37...first electrode, 38...second electrode, EA...exposure region, P1...first electrode pad, P2...second electrode pad, P3...third electrode pad, P4...fourth electrode pad, PCM1...first process control monitor structure, PCM1 BLD …incomplete process control monitor structure, PCM2…second process control monitor structure, PCM3…accessory area, PCM4…fourth process control monitor structure, S 1 …First unit exposure area, S N ...unit exposure area, SA...light-shielded area, SP...laser light irradiation mark.

Claims

1. A plurality of semiconductor circuit regions; a dicing street set between the semiconductor circuit regions; a destroyed process control monitor structure disposed within the dicing street; A semiconductor wafer comprising:

2. the process control monitor structure includes a destroyed transistor; The semiconductor wafer of claim 1 .

3. The transistor is a transistor having a laser light irradiation mark. The semiconductor wafer of claim 2 .

4. Among the plurality of semiconductor circuit regions, a dicing street adjacent to a semiconductor circuit region located on the periphery of the semiconductor wafer includes an intermediate body of a process control monitor structure having a structure that cannot output a signal; The semiconductor wafer of claim 1 .

5. providing a semiconductor wafer including a plurality of semiconductor circuit regions, dicing streets defined between the semiconductor circuit regions, and a process control monitor structure provided within the dicing streets; applying an overvoltage to the process control monitor structure to destroy it; A method for manufacturing a semiconductor wafer comprising the steps of:

6. providing a semiconductor wafer including a plurality of semiconductor circuit regions, dicing streets defined between the semiconductor circuit regions, and a process control monitor structure provided within the dicing streets; irradiating the process control monitor structure with a laser beam to destroy it; A method for manufacturing a semiconductor wafer comprising the steps of:

7. forming an intermediate process control monitor structure having a structure that cannot output a signal within a dicing street adjacent to a semiconductor circuit region located on the periphery of the semiconductor wafer among the plurality of semiconductor circuit regions; The method for producing a semiconductor wafer according to claim 5 or 6.

8. The steps of forming an intermediate process control monitor structure include: inhibiting formation of a structure for outputting a signal from the process control monitor structure. The method for producing a semiconductor wafer according to claim 7 .

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