Photoelectric conversion device and apparatus

Abstract

To provide a technique advantageous for reducing a multiplication factor.SOLUTION: A photoelectric conversion device has a photoelectric conversion unit arranged on a semiconductor substrate comprising a first principal surface and a second principal surface on the opposite side of the first principal surface. The photoelectric conversion unit includes: a first region of a first conductivity type that forms part of the first principal surface and is connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type that is arranged apart from the first region; a third region of a second conductivity type opposite to the first conductivity type that is arranged at a position closer to the second principal surface than the first region and the second region; and a fourth region that is arranged between the first region and the second region. The second region and the third region function as an avalanche photodiode. The first region and the second region can be conductive to each other through the fourth region.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] Single Photon Avalanche Diode (SPAD) is known as a photodetector capable of detecting weak light at a single photon level by utilizing avalanche (electron avalanche) multiplication. Patent Document 1 discloses a photodetector having pixels including avalanche photodiodes (APDs) functioning as SPADs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-064086 A Summary of the Invention [Problem to be solved by the invention]

[0004] Let us consider the charge multiplication factor in APD. In SPAD, a voltage obtained by adding the breakdown voltage Vbd and excess bias Vex is generally applied between the cathode and anode of the APD, and avalanche breakdown is detected by the change (decrease) in the cathode potential when an avalanche current flows. If the cathode capacitance of the APD is Cc and the change in the cathode potential when an avalanche breakdown occurs is ΔV, the amount of charge discharged from the cathode by avalanche breakdown is expressed as Cc×ΔV. If the unit charge is qe, the number of electron-hole pairs generated in one avalanche breakdown, that is, the carrier multiplication factor, is expressed as Cc×ΔV / qe. Since the charge multiplication factor and the carrier multiplication factor are the same, hereafter, they will be simply referred to as the multiplication factor. The cathode capacitance Cc has a large capacitance component due to the wiring pattern connected to the cathode and the detection circuit for detecting the avalanche breakdown, and is, for example, about 8 fF. In addition, if the change in cathode potential ΔV at which avalanche breakdown is detected is ΔV=2.4V, which is approximately the excess bias Vex, the multiplication factor becomes 120,000. A high multiplication factor makes it possible to detect weak light at the single photon level, but on the other hand, the following problems arise.

[0005] A large number of carriers generated by avalanche breakdown flow between the anode and cathode to which the breakdown voltage Vbd is applied. Therefore, a large current flows due to the incidence of one photon, and a lot of energy is consumed. When many pixels are arranged and the number of incident photons increases, the energy consumption increases.

[0006] An object of the present invention is to provide a technique that is advantageous in suppressing the multiplication factor. [Means for solving the problem]

[0007] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device in which a photoelectric conversion unit is arranged on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the photoelectric conversion unit comprises: a first region of a first conductivity type that constitutes a part of the first main surface and is connected to a detection circuit for detecting avalanche breakdown; a second region of the first conductivity type arranged away from the first region; a third region of a second conductivity type opposite to the first conductivity type that is arranged closer to the second main surface than the first region and the second region; and a fourth region arranged between the first region and the second region, wherein the second region and the third region function as an avalanche photodiode, and the first region and the second region are configured to be conductive through the fourth region. Effect of the Invention

[0008] According to the present invention, it is possible to provide a technique that is advantageous in suppressing the multiplication factor. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Diagram 2] 2 is a block diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Diagram 3] 3 is a diagram showing an example of the operation of a pixel of the photoelectric conversion device in FIG. 2. [Figure 4] 3 is a diagram showing an example of the operation of a pixel of the photoelectric conversion device in FIG. 2. [Diagram 5] 2 is a plan view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device in FIG. 1; [Figure 6] 6 is a cross-sectional view showing an example of the configuration of the APD and PD in FIG. 5. [Figure 7] 6A and 6B are an equivalent circuit diagram and an operation example of the pixel in FIG. 5 . [Figure 8] 2 is a plan view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device in FIG. 1; [Figure 9] 6 is a cross-sectional view showing an example of the configuration of the APD and PD in FIG. 5. [Figure 10]2 is a plan view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device in FIG. 1; [Figure 11] 11 is a cross-sectional view showing an example of the configuration of the APD and PD in FIG. 10. [Figure 12] 12 is a cross-sectional view showing a modification of the APD and PD in FIG. 11. [Figure 13] 2 is a cross-sectional view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 14] 2 is a cross-sectional view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 15] 2 is a cross-sectional view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 16] 16A to 16C are diagrams showing a part of a method for manufacturing the pixel in FIG. 15. [Figure 17] 2 is a cross-sectional view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device of FIG. 1. [Figure 18] 18A to 18C are diagrams showing a part of a manufacturing method of the pixel in FIG. 17. [Figure 19] 18 is a diagram showing the distribution of impurity ions in the depth direction of a semiconductor substrate in the regions 204, 238, and 239 of the pixel in FIG. 17. [Figure 20] 2 is an equivalent circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 21] 2 is a plan view showing an example of the configuration of an APD and a PD of a pixel of the photoelectric conversion device in FIG. 1; [Figure 22] 22 is a cross-sectional view showing an example of the configuration of the APD and PD in FIG. 21. [Figure 23] 22A and 22B are an equivalent circuit diagram and an operation example of the pixel in FIG. 21. [Figure 24] 2 is an equivalent circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Diagram 25] 25 is a diagram showing an example of the operation of the pixel in FIG. 24. [Figure 26] FIG. 1 is a diagram showing an example of the configuration of a device incorporating a photoelectric conversion device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0011] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 26. The following embodiments are merely examples of the present disclosure and do not limit the invention according to the claims. In the following embodiments, a single photon avalanche diode (SPAD) is described in which the signal charge carrier is an electron and a change in cathode potential due to an avalanche current is detected. Therefore, the first conductive type semiconductor region having charges of the same polarity as the signal charge as the majority carrier is an N-type semiconductor region, and the second conductive type semiconductor region opposite to the first conductive type is a P-type semiconductor region. However, holes may be the signal charge carrier, and a configuration in which a change in anode potential is detected may also be used. In this case, the first conductive type semiconductor region having charges of the same polarity as the signal charge as the majority carrier is a P-type semiconductor region, and the second conductive type semiconductor region opposite to the first conductive type is an N-type semiconductor region.

[0012] First, a photoelectric conversion device applicable to an embodiment of the present disclosure will be described based on a general SPAD operation with reference to FIG. 1. FIG. 1 is a block diagram showing a configuration example of a photoelectric conversion device 100 according to the present embodiment. The photoelectric conversion device 100 includes a pixel array 101, a control pulse generating circuit 115, a horizontal scanning circuit 111, a readout circuit 112, a vertical scanning circuit 110, a signal line 113, and driving lines 213 and 214. The pixel array 101 includes a plurality of pixels 104 arranged in a matrix. Each pixel 104 can include a photoelectric conversion unit 102 including an avalanche photodiode (APD) and a signal processing circuit 103. The photoelectric conversion unit 102 converts light into an electrical signal. The signal processing circuit 103 outputs the converted electrical signal to the readout circuit 112.

[0013] The vertical scanning circuit 110 receives a control pulse supplied from a control pulse generating circuit 115, and supplies the control pulse to the pixels 104. The vertical scanning circuit 110 can include logic circuits such as a shift register and an address decoder.

[0014] The signal output from the photoelectric conversion unit 102 of each pixel 104 is processed by a signal processing circuit 103. The signal processing circuit 103 is provided with, for example, a counter and a memory, and a digital value is held in the memory.

[0015] The horizontal scanning circuit 111 inputs a control pulse for sequentially selecting each column to the signal processing circuit 103 in order to read out the signal from the memory in which the digital signal of the pixel 104 is held. For the selected column, a signal is output from the signal processing circuit 103 of the pixel selected by the vertical scanning circuit 110 to a signal line 113. The signal output to the signal line 113 is output via an output circuit 114 to a recording device, a signal processing device, or the like disposed outside the photoelectric conversion device 100.

[0016] 1, pixels 104 are arranged two-dimensionally in pixel array 101. However, this is not limited thereto, and pixels 104 may be arranged one-dimensionally in pixel array 101. The function of signal processing circuit 103 does not necessarily need to be provided one by one corresponding to each of all pixels 104, and for example, one signal processing circuit 103 may be shared by a plurality of pixels 104, and signal processing may be performed sequentially.

[0017] Fig. 2 is a block diagram showing an example of the configuration of one pixel 104 shown in Fig. 1. First, the basic configuration and operation of the pixel 104 including an APD will be described with reference to Fig. 2 and Figs. 3(a), 3(b), 4(a), and 4(b) described later. Next, the detailed configuration of the pixel 104 of this embodiment will be described with reference to Fig. 5 and subsequent figures.

[0018] As shown in FIG. 2, the APD 201 is disposed in the photoelectric conversion unit 102 of the pixel 104. The APD 201 generates a pair of charges according to incident light by photoelectric conversion. A potential VL is supplied to the anode of the APD 201. A potential VH higher than the potential VL supplied to the anode is supplied to the cathode of the APD 201. As a result, a reverse bias voltage is supplied between the anode and the cathode such that the APD 201 performs an avalanche multiplication operation. By supplying such a voltage, the charges generated by the incident light cause avalanche multiplication, and an avalanche current is generated. In the following description, for simplicity, VL=-Vbd and VH=Vex. Here, Vbd is the breakdown voltage of the APD 201, and Vex is the excess voltage. Usually, VL is about -20V to -30V, and VH is about 2V to 3V.

[0019] 2, the signal processing circuit 103 of the pixel 104 may include a quench element 202, a waveform shaping circuit 210, a counter circuit 211, and a selection circuit 212. However, the signal processing circuit 103 is not limited thereto, and may include other circuits related to signal processing.

[0020] The quench element 202 is connected to a supply line that supplies a potential VH and the APD 201. The quench element 202 has a function of converting a change in avalanche current occurring in the APD 201 into a voltage signal. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has a function of suppressing avalanche multiplication by suppressing the voltage supplied to the APD 201 (quench operation).

[0021] The waveform shaping circuit 210 shapes the potential change of the cathode of the APD 201 obtained when a photon is detected, and outputs a pulse signal. As a result, the waveform shaping circuit 210 functions as a detection circuit that detects an avalanche breakdown occurring in the APD 201. For example, an inverter circuit may be used as the waveform shaping circuit 210. A configuration example including one inverter as the waveform shaping circuit 210 is considered. However, this is not limited thereto, and a circuit in which a plurality of inverters are connected in series may be used as the waveform shaping circuit 210. In addition, other circuits having a waveform shaping effect may be used as the waveform shaping circuit 210.

[0022] The counter circuit 211 counts the number of pulse signals output from the waveform shaping circuit 210 and holds the counted value. When a reset control pulse is supplied from the vertical scanning circuit 110 shown in FIG. 1 via a driving line 213, the counter circuit 211 resets the value held in the counter circuit 211.

[0023] 1 via a drive line 214, the selection circuit 212 switches between electrical connection and non-connection between the counter circuit 211 and the signal line 113. The selection circuit 212 can be configured to include, for example, a buffer circuit for outputting a signal.

[0024] A switching element such as a transistor may be disposed between the quench element 202 and the APD 201 or between the photoelectric conversion unit 102 and the signal processing circuit 103 to switch the electrical connection. Similarly, the supply of the potential VH, the potential VL, etc. supplied to the photoelectric conversion unit 102 may be electrically switched using a switching element such as a transistor.

[0025] In the configuration shown in FIG. 2, a counter circuit 211 is used in the signal processing circuit 103. However, the present invention is not limited to this. Instead of the counter circuit 211, a time-to-digital conversion circuit (TDC) and a memory may be used to obtain the timing of detecting the pulse signal output from the waveform shaping circuit 210 in the photoelectric conversion device 100. In this case, the generation timing of the pulse signal output from the waveform shaping circuit 210 is converted into a digital signal by the TDC. In order to measure the timing of the output of the pulse signal, the TDC is supplied with a control pulse pREF from the vertical scanning circuit 110 via a drive line (which may be the same as the drive lines 213 and 214). The TDC obtains, as a digital signal, a signal in which the input timing of the signal output from the pixel 104 via the waveform shaping circuit 210 is set as a relative time based on the control pulse pREF.

[0026] 3(a) and 3(b) are diagrams that show the relationship between the operation of the APD 201 and the output signal. Fig. 3(a) is a diagram that shows the APD 201, the quench element 202, and the waveform shaping circuit 210 shown in Fig. 2. Here, the input side of the waveform shaping circuit 210 is nodeA, and the output side is nodeB. Fig. 3(b) shows the potential changes of nodeA and nodeB.

[0027] From time t0 to time t1, a potential difference (voltage) of potential VH-potential VL is applied to the APD 201. When a photon is incident on the APD 201 at time t1, avalanche breakdown occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the potential of nodeA drops. When the amount of potential drop becomes larger and the potential difference applied to the APD 201 becomes smaller, the avalanche breakdown in the APD 201 stops as shown at time t2, and the potential level of nodeA does not drop below a certain value. The potential at which this avalanche breakdown stops is about 0V, that is, a potential at which the voltage applied to the APD 201 is about Vbd. After that, from time t2 to time t3, a current that compensates for the potential drop from potential VL flows to nodeA, and at time t3, nodeA is stabilized to the original potential level. At this time, the portion of the output waveform at nodeA that exceeds a certain threshold value is shaped by the waveform shaping circuit 210 and is output as a signal to nodeB.

[0028] Here, the quench element 202 and the waveform shaping circuit 210 may be formed on the same semiconductor substrate as the APD 201. However, this is not limited thereto, and a chip on which the APD 201 is arranged and a chip on which the quench element 202 and the waveform shaping circuit 210 are arranged may be formed separately and stacked. For example, as indicated by the dotted line in Fig. 2, a chip (semiconductor substrate) on which the photoelectric conversion unit 102 is arranged and a chip (semiconductor substrate) on which the signal processing circuit 103 is arranged may be formed separately and stacked.

[0029] 4(a) and 4(b) are diagrams showing the relationship between the operation of an APD 201 and an output signal, which is different from the configuration shown in FIG. 3(a) and FIG. 3(b). FIG. 4(a) is an equivalent circuit diagram corresponding to FIG. 3(a), but a P-channel (P-type) MOS (MIS) transistor 203 is arranged instead of the quench element 202. FIG. 4(b) shows the potential changes of nodeA, nodeB, and nodeC in FIG. 4(a). NodeA and nodeB are the input and output nodes of the waveform shaping circuit 210, respectively, as in FIG. 3(a). NodeC is a node connected to the gate electrode of the transistor 203.

[0030] The transistor 203 is a switch for resetting the potential of nodeA to potential VH, and is controlled by the potential of nodeC. When the potential of nodeC shown in FIG. 4(b) is high, the transistor 203 is in an off state (non-conductive state, hereinafter sometimes referred to as OFF). When the potential of nodeC is low, the transistor 203 is in an on state (conductive state, hereinafter sometimes referred to as ON). A periodic pulse is input to nodeC, a part of which is shown in FIG. 4(b). The operation shown in FIG. 4(b) will be described below.

[0031] First, at time t0, the potential of node A is reset to the potential VH by the transistor 203. After that, when the transistor 203 is turned off, the potential of node A becomes a floating state at the potential VH.

[0032] Assume that a photon is incident on the APD 201 at time t1. When avalanche breakdown occurs in the APD 201 due to the incidence of the photon, the potential of nodeA decreases due to the avalanche current, and the avalanche breakdown stops at time t2. The potential of nodeA remains decreased and is in a floating state, but when a pulse to reset nodeA is input to nodeC at time t3, the potential of nodeA is reset to potential VH again. Therefore, a detection pulse of avalanche breakdown is generated at nodeB on the output side of the waveform shaping circuit 210, which is High from time t1 to time t2, from the time when the potential of nodeA reaches the determination threshold until time t3.

[0033] In the operation shown in FIG. 4(b), consider the case where a photon is incident between the time t1 and the time t3, that is, the case where the next photon is incident while the potential of nodeA remains low. In that case, the APD 201 cannot cause further avalanche breakdown for the second and subsequent photons incident between the time t1 and the time t3. Therefore, even if multiple photons are incident between the time t1 and the time t3, the number of times that the avalanche breakdown is detected in the waveform shaping circuit 210 is one. Also, for example, in the operation shown in FIG. 4(b), if no photon is incident between the time t0 and the time t3, the potential of nodeA remains at the potential VH, and the potential of nodeB remains at the low level. In other words, the number of times that the avalanche breakdown is detected is zero.

[0034] In the operation described with reference to FIG. 4(b), it is distinguished whether the number of photons incident on the APD 201 was 0 or 1 or more during one period of the reset pulse input to node C. Therefore, if multiple photons are incident during one period of the reset pulse input to node C, a signal detection loss occurs. On the other hand, in the case where photons are continuously incident one after another, in the operation described with reference to FIG. 3(b), the avalanche breakdown does not stop in the APD 201, and the avalanche current continues to flow, resulting in a so-called pile-up state. In the pile-up state, the potential of node A remains low, so that the waveform shaping circuit 210 does not generate a detection pulse, and a current (wastefully) flows in the APD 201. Therefore, the pile-up can be a major issue in terms of power consumption in the SPAD operation.

[0035] In addition to the continuous current flow caused by pile-up, the following problems may occur in SPAD operation: As described above, the following problems may occur due to the large multiplication factor in SPAD operation.

[0036] One of these is the problem of light emission crosstalk. In the APD 201, a large number of carriers are generated by the incidence of photons. It is known that some of the generated carrier pairs emit light by recombination. In a pixel array 101 having a plurality of pixels 104 (photoelectric conversion units 102), when an avalanche breakdown occurs due to a photon incident on a certain pixel 104, secondary photons emitted from that pixel 104 may be incident on surrounding pixels 104 and become spurious signals. This is called light emission crosstalk. For example, as described above, if the multiplication factor is 120,000 and it is assumed that 0.01% of the 120,000 generated carrier pairs generated by the incidence of one photon recombine, 12 secondary photons that cause light emission crosstalk will be generated.

[0037] The next problem is the change in dark current. Carriers generated by avalanche multiplication are accelerated in the high electric field area and become so-called hot carriers. Some of the hot carriers are captured in the interface near the cathode of the APD 201, changing the state of the interface. In the APD described in Patent Document 1, the area around the cathode is depleted, and many dark current carriers are generated from the interface. However, the electric field strength around the cathode is relatively low, and only a small portion of the carriers generated at the interface cause avalanche generation, but the interface-generated carriers that cause this avalanche appear as the dark current of the SPAD. If the state of the interface changes due to the capture of hot carriers, the carrier generation speed at the interface changes, and as a result, the dark current value changes. This change occurs while the SPAD is being used continuously, and problems such as the initial dark current correction becoming ineffective may occur.

[0038] Furthermore, as described above, the energy consumption increases as the number of signal photons increases. For example, if Vbd=25V, it is estimated that 120,000 carriers are generated by the incidence of one photon, and approximately 0.5 pJ of energy is consumed. If many pixels are arranged and the number of incident photons increases, the energy consumption increases. This may place a large load on the power supply system of the photoelectric conversion device 100 operating as a SPAD.

[0039] As described above, the avalanche multiplication factor is large because the capacitance components due to the wiring pattern connected to the cathode of the APD 201 and the detection circuit for detecting avalanche breakdown such as the waveform shaping circuit 210 are large. This can cause the problems of light emission crosstalk, dark current change, and power consumption as described above. If the junction capacitance of the diode at the cathode of the APD 201 becomes large, it can become a more serious problem. The junction capacitance of the diode at the cathode of the APD 201 is a capacitance component different from the capacitance due to the wiring pattern connected to the cathode of the APD 201 and the detection circuit for detecting avalanche breakdown such as the waveform shaping circuit 210.

[0040] In the pile-up state that may occur in the operation shown in FIG. 3(b), the above-mentioned problem may occur significantly. The operation shown in FIG. 4(b) has a great advantage in that such pile-up does not occur. Although signal detection loss may occur when multiple photons are incident during one period of the reset pulse input to node C, the SPAD is advantageous for photon detection in a situation where the number of incident photons is small. In a situation where the number of incident photons is small, it is difficult for multiple photons to be incident during one period of the reset pulse. Therefore, it is considered that signal detection loss hardly occurs in such a situation. However, problems of emission crosstalk, dark current change, and power consumption due to a large multiplication factor may exist even in the operation shown in FIG. 4(b).

[0041] Hereinafter, the photoelectric conversion device 100 of the present disclosure for suppressing light emission crosstalk, changes in dark current, and power consumption will be described in detail based on the operation shown in Fig. 4(b). However, each embodiment of the present disclosure is also applicable to the operation shown in Fig. 3(b).

[0042] (First embodiment) Fig. 5 is a plan view of a photoelectric conversion unit 102 arranged in a pixel 104 in the first embodiment of the present disclosure. Fig. 6 is a cross-sectional view between AB of the photoelectric conversion unit 102 shown in Fig. 5. Fig. 5 is a plan view of a main surface 251 (first main surface) of a semiconductor substrate 250 shown in Fig. 6.

[0043] The photoelectric conversion unit 102 included in the pixel 104 arranged in the photoelectric conversion device 100 is formed on a semiconductor substrate 250 having a main surface 251 and a main surface 252 (second main surface) opposite to the main surface 251. In the configuration shown in Figures 5 and 6, the photoelectric conversion unit 102 includes a region 204 (first region), a region 206 (second region), a region 208 (third region), and a region 207 (fourth region).

[0044] The region 204 is a region of high impurity concentration and N-type conductivity that constitutes a part of the main surface 251 of the semiconductor substrate 250. The region 204 is connected to a detection circuit (for example, the above-mentioned waveform shaping circuit 210) for detecting an avalanche breakdown via a connection pattern 205. The connection pattern 205 does not constitute a part of the main surface 251, but in FIG. 5, the connection pattern 205 is shown in order to easily show the connection position between the region 204 and the connection pattern 205. The region 206 is a region of high impurity concentration and N-type conductivity that is disposed away from the region 204. As shown in FIG. 6, the region 206 may constitute a part of the main surface 251 of the semiconductor substrate 250. Unlike the region 204, the region 206 is not directly connected to the connection pattern 205 that is connected to the detection circuit. The region 206 is connected to the connection pattern 205 via the region 207 and the region 204, as will be described later. Region 208 is a region of P-type conductivity, opposite to N-type, that is disposed at a position closer to main surface 252 of semiconductor substrate 250 than regions 204 and 206 .

[0045] The region 204 may be a cathode of a photodiode (PD) including a PN junction formed by the region 204 and the region 208, and the region 208 may be an anode of the PD formed by the region 204 and the region 208. Similarly, the region 206 may be a cathode of an APD including a PN junction formed by the region 206 and the region 208, and the region 208 may be an anode of the APD formed by the region 206 and the region 208. As shown in FIG. 6, the region 208 may be formed over almost the entire surface of one pixel 104 (photoelectric conversion unit 102) between the regions 204, 206 and the main surface 252 of the semiconductor substrate 250 (below the regions 204, 206 in the drawing). As shown in FIG. 6, the region 208 extends from one region 230 to the other region 230 in a cross-sectional view.

[0046] Region 207 is disposed between region 204 and region 206. Region 204 and region 206 are configured to be conductively connected through region 207. Region 207 is preferably a region having a lower impurity concentration than regions 204 and 206. In the configurations shown in FIGS. 5 and 6, region 207 is an N-type region with a low impurity concentration that functions as a resistor connecting region 204 and region 206.

[0047] As shown in FIG. 6, the photoelectric conversion unit 102 may further include regions 209, 230, 231, and 190. The region 209 is a P-type region formed to configure the main surface 252 of the semiconductor substrate 250. The region 230 is a P-type region formed at the boundary of each pixel 104 (photoelectric conversion unit 102) and isolating each pixel from the other. The region 231 (fifth region) is a photoelectric conversion region, and is a P-type or N-type region having a lower impurity concentration than the regions 204 and 206, which is disposed between the region 208 and the main surface 252 (region 209) of the semiconductor substrate 250. The region 190 is a region disposed between the regions 204, 207, and 206 and the region 208 in a region surrounded by the main surface 251, the region 208, and the region 230 of the semiconductor substrate 250. Region 190 is a P-type or N-type region that is lightly doped relative to regions 204 and 206. Regions 190 and 231 may be lightly doped relative to regions 208, 209, and 230.

[0048] 5 and 6, when light is incident on the photoelectric conversion unit 102 during operation of the photoelectric conversion device 100, the PN junction including the regions 206 and 208 functions as the above-mentioned APD 201 and causes avalanche breakdown. On the other hand, the PN junction including the regions 204 and 208 does not function as the above-mentioned APD 201 and does not basically cause avalanche breakdown. Therefore, the PN junction including the regions 204 and 208 may be referred to as a parasitic PD 232 hereinafter.

[0049] In order to make the regions 206 and 208 function as the APD 201 and to make the regions 204 and 208 not function as the APD 201, as shown in FIG. 6, the distance D1 between the regions 206 and 208 is shorter than the distance D2 between the regions 204 and 208. Therefore, in operation, a higher electric field is generated in the PN junction formed by the regions 206 and 208 than in the PN junction formed by the regions 204 and 208. Therefore, a depletion region is formed in the region of the region 208 that overlaps with the region 206 in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250. Charges generated in the region 231 by the incidence of light flow into the region 206 through this depletion region, and at that time, an avalanche breakdown is caused. The region 190 is basically depleted in operation. Therefore, electrical conduction between the regions 204 and 206 is mainly performed via the N-type region 207 that functions as a resistor. The concentration of the first conductive type impurity in the region 204 may be lower than the concentration of the first conductive type impurity in the region 206. This can also make it difficult for avalanche breakdown to occur in the regions 204 and 208.

[0050] In this embodiment, photons incident on the region 231 may be incident from the main surface 251 or from the main surface 252 of the semiconductor substrate 250. Here, it is assumed that the photons are incident from the main surface 252 of the semiconductor substrate 250. In other words, the photoelectric conversion device 100 is a so-called back-illuminated photoelectric conversion device. It is also assumed that the signal processing circuit 103 including the waveform shaping circuit 210 and the like is formed on a separate substrate that is connected via a connection pattern 205 to the semiconductor substrate 250 on which the region 231, the APD 201, and the like are disposed.

[0051] 7(a) and 7(b) are diagrams for explaining the SPAD operation of this embodiment. Fig. 7(a) is an equivalent circuit diagram of a part of the photoelectric conversion unit 102 and the signal processing circuit 103, and Fig. 7(b) shows the potential changes of nodes A to D during SPAD operation. Nodes A to C are in the same positions as those shown in Fig. 4(a). Node D is the cathode of APD 201, in other words, the potential of region 206. Moreover, node A is the potential of region 204, which is the cathode of parasitic PD 232, when the wiring resistance of connection pattern 205 can be ignored.

[0052] First, at time t0, the potential of nodeA and the potential of nodeD via region 207 are reset to potential VH by transistor 203. Transistor 203 functions as a reset circuit for resetting the potentials of regions 204 and 206 to a predetermined potential (potential VH) in accordance with a reset pulse input to node C. After that, when transistor 203 turns OFF, the potentials of nodeA and nodeD become floating at potential VH.

[0053] Next, at time t1, when a photon is incident on the photoelectric conversion unit 102 and avalanche breakdown occurs in the APD 201, the potential of nodeD decreases due to the avalanche current. At this time, the potential of nodeA also decreases due to the current flowing through region 207, but it cannot keep up with the change in the potential of nodeD and the decrease in potential is slow. When the avalanche breakdown stops at time t2, a current flows through region 207 so that nodeA and nodeD have the same potential. During this process, the potential of nodeA exceeds the threshold of the waveform shaping circuit 210, and a pulse is generated at nodeB to detect the avalanche breakdown in the APD 201.

[0054] In the above operation, an avalanche current flows from time t1 to time t2. Here, the configuration in which the APD 201 is directly connected to the waveform shaping circuit 210 as shown in FIG. 4(a) is called the configuration of the comparative example. In the potential change shown in FIG. 7(b), the potential of node D drops to the potential at which the avalanche breakdown stops, similar to the operation shown in FIG. 4(b) in the configuration of the comparative example. On the other hand, the potential of node A to which a large capacitance component due to the connection pattern 205, the waveform shaping circuit 210 (detection circuit), etc. is added cannot follow the change in the potential of node D because the region 207 functions as a resistor, and the potential change at time t2 is small. Therefore, when the capacitance component of the parasitic PD 232 added to the configuration of the comparative example is sufficiently smaller than the other capacitance components added to node A, the discharge charge amount of node A is suppressed to be smaller than that of the operation of the configuration of the comparative example. As a result, the multiplication factor of the avalanche breakdown occurring in the APD 201 is suppressed compared to the configuration of the comparative example.

[0055] Here, a quantitative explanation will be given. As a condition, the size of the pixel 104 is assumed to be several μm square, for example, 5 μm square. In that case, the diameter of the regions 204 and 206 is, for example, about 1 μm. The region 204 constituting the parasitic PD 232 may be smaller than the region 206. In the case of these conditions, the capacitance of the PN junction of the region 206 is about 0.8 fF, the additional capacitance (parasitic capacitance) from the connection pattern 205 to the input part of the waveform shaping circuit 210 is about 7.2 fF, and the capacitance of the PN junction of the region 204 is about 0.6 fF. In this embodiment, the capacitance due to the arrangement of the region 204 is increased compared to the configuration of the comparative example. However, it can be seen that the capacitance component due to the region 204 is sufficiently smaller than the capacitance components due to the connection pattern 205 and the waveform shaping circuit 210 from the connection pattern 205 to the input part of the waveform shaping circuit 210.

[0056] Next, we consider what resistance value of region 207 functioning as a resistor should have in order to suppress the carrier multiplication factor. Here, the resistance in region 207 is not necessarily an ohmic resistance. The resistance value of region 207 is a value obtained by V1 / I1, where I1 is the current flowing through region 207 when the potential difference between region 204 and region 206 is V1.

[0057] First, the potential drop of the cathode (region 206) of the APD 201 when avalanche breakdown occurs is set to 2.4V. The avalanche current in this case depends on the characteristics of the APD 201, but is approximately 50 μA under the above conditions. Therefore, in the region 206 having a capacitance of 0.8 fF, the time for the potential to drop by 2.4 V is approximately 40 ps. In this case, in order to prevent the potential of the region 204 from following the potential change of the region 206, it is necessary to set the product of the resistance value of the region 207 and the capacitance value of the region 206, that is, the so-called CR time constant, to be approximately 40 ps or more. In the case of the above conditions, since the capacitance of the region 206 is 0.8 fF, it is calculated that the resistance value of the region 207 needs to be approximately 50 kΩ or more. In reality, it is considered that the conditions will change to some extent. For example, when the avalanche current is 100 μA, it takes 20 ps for the potential of region 206 to drop by 2.4 V, and the resistance value of region 207 needs to be about 25 kΩ. In addition, when the potential of the cathode (region 206) drops by about 1.9 V when avalanche breakdown occurs, the resistance value of region 207 needs to be about 20 kΩ. Therefore, it is preferable that region 207 functions as a resistor of 20 kΩ or more. Considering the junction capacitance of region 206, the amount of avalanche current, and other configurations that can be actually formed, it is considered that the effect of suppressing the multiplication factor cannot be expected unless the resistance value of region 207 is at least about 20 kΩ.

[0058] On the other hand, the larger the resistance value of the region 207, the greater the effect of suppressing the multiplication factor. However, if the resistance value of the region 207 is too large, the response time from when the avalanche breakdown actually starts to when the avalanche breakdown is detected becomes long. For example, if the period of the pulse input to node C is 20 μs, a detection loss of the avalanche breakdown occurs unless the response occurs in a time sufficiently shorter than the period of the pulse. Therefore, if the response time is required to be 0.2 μs or less, the above-mentioned time constant is 0.2 μs or less, and the upper limit of the resistance value of the region 207 is estimated to be 250 MΩ. In general, it is difficult to form a resistor of several hundred MΩ in the pixel 104 (semiconductor substrate 250). Therefore, in the design of the actual pixel 104 (photoelectric conversion unit 102), the lower limit of the resistance value of the region 207 becomes important.

[0059] Here, as described above, when the multiplication factor at the time when the avalanche breakdown occurs becomes smaller, the width of the potential change (potential drop) of node A also becomes smaller. Therefore, the threshold value for determining the avalanche breakdown in the waveform shaping circuit 210 needs to be set to a value according to the multiplication factor changed by providing the parasitic PD 232.

[0060] The present embodiment described above with reference to FIGS. 5 to 7(a) and 7(b) will be summarized. The addition of the parasitic PD 232 to the configuration of the comparative example adds the capacitance of the PN junction of the region 204 to nodeA, which is a disadvantageous factor from the viewpoint of suppressing the multiplication factor when avalanche breakdown occurs. However, the capacitance component of the PN junction of the region 204 is sufficiently smaller than the capacitance components caused by the connection pattern 205 and the waveform shaping circuit 210. Therefore, there is no significant effect on the multiplication factor. On the other hand, the resistance value of the region 207 can be set to an appropriate value to prevent electrical conduction between nodeA and nodeD to a desired degree. This makes it possible to greatly reduce the amount of charge discharged from nodeA when avalanche breakdown occurs, compared to the SPAD operation of the configuration of the comparative example. In other words, the configuration of this embodiment suppresses the carrier multiplication factor when avalanche breakdown occurs, and is effective against three problems, namely, light emission crosstalk, changes in dark current, and power consumption when a large number of photons are incident.

[0061] Here, the configurations of the parasitic PD 232, the APD 201, and the region 207 are not limited to those shown in Fig. 5 and Fig. 6. For example, as shown in Fig. 8, the region 207 may connect the region 204 and the region 206 via a detour rather than via the shortest route. The region 207 that is laid out to make a detour has a longer distance between the region 204 and the region 206, making it easier to increase the resistance value.

[0062] 9, region 206 for forming APD 201 has a two-tiered configuration of region 206a and region 206b. Region 206a of region 206 is a shallow N-type region in contact with main surface 251 of semiconductor substrate 250, like region 204. Region 206b of region 206 is an N-type region formed at a location deeper than region 206a (closer to main surface 252 of semiconductor substrate 250) and continuing from region 206a.

[0063] The regions 204 and 206 shown in FIG. 6 are regions with different depths of the one-layer structure, and therefore can be formed by processes using different masks. On the other hand, the region 206a of the regions 204 and 206 shown in FIG. 9 can be formed using the same mask. Therefore, the planar positional relationship between the region 204 and the region 206 (region 206a) on the main surface 251 of the semiconductor substrate 250 is formed in a constant positional relationship without depending on the misalignment of the mask. This leads to the resistance value of the region 207, which is an electrical conductive path connecting the regions 204 and 206, being formed stably. The region 206b of the region 206 is formed using a mask different from the mask for forming the regions 204 and 206a. Even in this case, the position of the depletion region of the P-type region 208 is simply determined, and the mask misalignment of the region 206b with respect to the region 206a does not have a significant effect on the characteristics. The configurations shown in FIG. 8 and FIG. 9 may be used in combination. 8 and 9, the multiplication factor can be suppressed and a SPAD operation with stabilized characteristics can be realized, which can contribute to further improving the characteristics of the photoelectric conversion device 100.

[0064] 6 and 9, the region 206 is arranged to a region closer to the main surface 252 of the semiconductor substrate 250 than the region 204, so that the distance between the region 206 and the region 208 is shorter than the distance between the region 204 and the region 208. However, the present invention is not limited to this. For example, the region 204 and the region 206 may have the same shape, and a portion of the region 208 overlapping the region 206 may have a step so as to approach the region 206. For example, the region 204 and the region 206 may be formed using the same mask. On the other hand, the region 208 may include a uniform region as shown in FIG. 6 and FIG. 9, and a region that is continuous from the uniform region so as to approach the region 206 in a region that overlaps the region 206 in an orthogonal projection onto the main surface 251 of the semiconductor substrate 250. This also makes it possible to realize a SPAD operation with a suppressed multiplication factor by combining the APD 201 and the parasitic PD 232 as described above. Furthermore, since the regions 204 and 206 can be formed using one mask, the characteristics of the SPAD operation can be stabilized, similarly to the configuration shown in FIG.

[0065] Furthermore, the outer edge of each region, such as the above-mentioned regions 204, 206, 208, may be a portion where the impurity concentration is 1 / 10 of the portion where the impurity concentration is the highest in the respective region. Furthermore, for example, the outer edge of each region, such as regions 204, 206, 208, may be a portion where the impurity concentration is 1 / 100 of the portion where the impurity concentration is the highest in the respective region. Furthermore, for example, the outer edge of each region, such as regions 204, 206, 208, may be a portion where the impurity concentration is 1 / 100 of the portion where the impurity concentration is the highest in the respective region. 16 Furthermore, when adjacent regions have different conductivity types, the outer edge of each region may be a portion where the conductivity type changes.

[0066] Second embodiment Next, a photoelectric conversion device 100 according to a second embodiment of the present disclosure will be described. Fig. 10 is a plan view of a photoelectric conversion unit 102 arranged in a pixel 104 in this embodiment. Fig. 11 is a cross-sectional view between AB of the photoelectric conversion unit 102 shown in Fig. 10. Fig. 10 is a plan view of a main surface 251 of a semiconductor substrate 250 shown in Fig. 11. An equivalent circuit of this embodiment shown in Figs. 10 and 11 may be similar to the circuit of the first embodiment described above using Figs. 5 to 9 and shown in Fig. 7(a), and the operation may also be similar.

[0067] 11, in this embodiment, the regions 204 and 206 have a structure in which they are stacked in the depth direction. More specifically, the region 206 is disposed between the region 204 and the region 208. Hereinafter, the depth direction is the direction from the main surface 251 toward the main surface 252 of the semiconductor substrate 250. Hereinafter, it may be expressed as "getting deeper" as it approaches the main surface 252 from the main surface 251.

[0068] The APD 201 is composed of a region 206 and a region 208. A low concentration of P-type impurities or a low concentration of N-type impurities is introduced into the region 207. An electron layer having a low density of N-type conductivity is formed in the region 207 during operation, regardless of the conductivity type of the impurities, and serves as a resistor connecting the region 204 and the region 206. When the region 207 is effectively an N-type region, the operation of the region 207 is the same as that of the first embodiment described above. Here, the "effective" conductivity type means the conductivity type with the higher impurity concentration when P-type impurities and N-type impurities are mixed, and the difference between the concentrations is the effective concentration. In the above-mentioned embodiment and the following embodiment, the conductivity type of each region may be the effective conductivity type.

[0069] Hereinafter, a case will be described in which the region 207 is effectively a P-type region, but the majority carriers are electrons. If the region 207, which is effectively a P-type impurity region, is a neutral region or completely depleted during operation, electrical continuity between the region 204 and the region 206 is cut off, and the region 206 of the APD 201 is always in a floating state. Therefore, information on the occurrence of avalanche breakdown in the APD 201 is not transmitted, and the region 206 does not function as a SPAD. On the other hand, if the thickness in the depth direction and the impurity concentration of the P-type region 207 are appropriate, the majority carriers in the region 207 can be electrons with a low density, and the region 207 can function as a resistor between the region 204 and the region 206. Specifically, the Debye length of the P-type region 207 is set to be approximately the thickness in the depth direction of the region 207. As a result, the majority carriers in the region 207 can be electrons with a low density.

[0070] The regions 204 and 206 are high-concentration N-type regions, and have high-density electrons as majority carriers. The quasi-Fermi levels of the regions 204 and 206 do not change so that the majority carriers become holes in the P-type region 207. This is because the limit of the change in the quasi-Fermi level is determined by the Debye length. Therefore, in the P-type region 207, electrons become majority carriers, although the density is low, and the region 207 can act as a resistor. It is easier to realize a lower-density electron layer when the region 207 is a P-type region with a moderate concentration than when the region 207 is an N-type region. Therefore, the region 207 is more likely to function as a high-resistance region. Compared to the configurations described using Figures 5 to 9, the configuration shown in Figure 11 can have a shorter distance between the region 204 and the region 206. Therefore, it may be necessary to increase the resistance per unit length of the region 207 more than in the above-mentioned configuration.

[0071] As described above, when the region 207 acts as a resistor and exhibits a desired resistance value, the multiplication factor when an avalanche breakdown occurs can be suppressed more than that of the SPAD of the comparative example by the same operating principle as in the first embodiment described using Figures 5 to 9. As a result, even in the configurations shown in Figures 10 and 11, problems such as light emission crosstalk, changes in dark current, and power consumption caused by a large multiplication factor can be improved.

[0072] 10 and 11, in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250, the regions 204 and 206 are arranged to overlap each other. Therefore, compared to the plan view of FIG. 5, the areas occupied by the regions 204 and 206 are smaller. Therefore, it may be easily applied when reducing the size of the pixel 104 (photoelectric conversion unit 102). Furthermore, the three layers of the regions 204, 206, and 207 can be formed using the same mask. As a result, characteristic variations due to mask misalignment of the regions 204, 206, and 207 are less likely to occur, and further, manufacturing costs can be reduced.

[0073] FIG. 12 is a modified example of the configuration shown in FIG. 11. In the configuration shown in FIG. 12, the region 233 (sixth region) is a P-type region, and an effective P-type impurity concentration is introduced therein such that the region is basically depleted during operation. The region 207 is an N-type or P-type impurity introduction region having approximately the same depth as the region 233, and is formed locally in the central portion of the region 204 and the region 206 in the orthogonal projection onto the main surface 251 of the semiconductor substrate 250. As described above, the region 207 is a region in which electrons become majority carriers at a low density during operation. Therefore, when the region 207 is P-type, its effective impurity concentration is lower than the effective impurity concentration of the region 233.

[0074] In the configurations shown in FIG. 11 and FIG. 12, the region 207 becomes an electrical conductive path between the region 204 and the region 206. In the configuration shown in FIG. 12, the region 207 has a smaller cross-sectional area perpendicular to the direction of current flow, so that a large resistance value can be easily obtained compared to the configuration shown in FIG. 11. The region 204, the region 206, and the region 233 can be formed using the same mask. In the configuration shown in FIG. 12, the region 207 may further be doped with N-type impurities with a mask different from the mask used to form the region 204, the region 206, and the region 233. Thereby, the region 207 can be effectively an N-type region, or a P-type region having an effective impurity concentration lower than that of the region 233. In addition, the mask used to form the region 207 and to form the connection pattern 205 may be used. The N-type impurities when forming the region 206 are substantially distributed such that the center portion spreads in the depth direction. Therefore, depending on the design of the distribution of the impurity concentrations, when the regions 204, 206, and 233 are formed using the same mask, the region 207 may be formed locally at the same time.

[0075] In the configuration of this embodiment, the region 204 and the region 206 are arranged so as to overlap each other in an orthogonal projection onto the main surface 251 of the semiconductor substrate 250. In this case, the region 206 may be arranged so as to be included in the region 204. Also, the region 204 may be arranged so as to be included in the region 206.

[0076] In the configuration of this embodiment, as in the configuration shown in the first embodiment described above, the carrier multiplication factor when an avalanche breakdown occurs can be suppressed. This provides an improvement effect on the above-mentioned problems of light emission crosstalk, dark current change, and power consumption. Furthermore, even when the size of the pixel 104 is reduced, the configuration of this embodiment in which the regions 204, 207, and 206 overlap can be effectively applied. Furthermore, the configuration in which the regions 204, 207, and 206 overlap can further reduce characteristic variations while suppressing an increase in the manufacturing process.

[0077] Third embodiment Next, a photoelectric conversion device 100 according to a third embodiment of the present disclosure will be described with reference to FIG. 13. FIG. 13 is a cross-sectional view of a photoelectric conversion unit 102 arranged in a pixel 104 in this embodiment. The photoelectric conversion device 100 in this embodiment differs from the modified example of the second embodiment shown in FIG. 12 in that the photoelectric conversion unit 102 has a region 232. Other than this point and the points described below, the photoelectric conversion device 100 is substantially similar to the second embodiment, and therefore may not be described. The circuit diagram and SPAD operation in this embodiment are also similar to the operations described in FIG. 5, FIG. 7(a), FIG. 7(b), etc.

[0078] In this embodiment, the region 232 is connected to a detection circuit for detecting an avalanche breakdown via the connection pattern 205. The region 232 is a high impurity concentration N-type conductivity region that constitutes a part of the main surface 251 of the semiconductor substrate 250. The region 232 makes an ohmic connection between the region 204 and the connection pattern 205. The N-type impurity concentration of the region 232 is higher than the N-type impurity concentration of the region 204. In a plan view, the region 204 is disposed so as to surround the region 232.

[0079] In plan view, region 207 is disposed at a position overlapping connection pattern 205. In this case, after the step of forming a through hole for providing connection pattern 205, region 207 can be formed by utilizing the through hole, and N-type impurities may be introduced to a depth approximately equal to that of region 233. On the other hand, in this case, the resistance value of region 207 may be affected by region 232. In order to reduce the effect on the resistance value, region 207 and connection pattern 205 may be disposed so as not to overlap each other in plan view, as shown in FIG.

[0080] The suitable impurity concentration of each region is described below. Note that the impurity concentration here refers to the effective impurity concentration, and refers to the difference in impurity concentration when P-type and N-type impurities are mixed. Also, the impurity concentrations shown below are examples, and each region described in each embodiment is not limited to the range of impurity concentrations shown below.

[0081] For example, the impurity concentration of the region 204 is 1×10 15 ~1×10 20 cm -3 The impurity concentration of the region 206 is preferably in the range of 5×10 16 ~2×10 18 cm -3 By setting the impurity concentration of the region 206 to a predetermined value or more, it becomes easier for the region 206 to function as a part of the APD 201, and by setting the impurity concentration of the region 206 to a predetermined value or less, it becomes easier to electrically separate the region 206 from the region 204. The impurity concentration of the region 208 is preferably within a range of 2×10 16 ~2×10 17 cm -3 It is preferable that the impurity concentration of region 208 is within the range of 2×10. By setting the impurity concentration of region 208 at a predetermined value or more, it becomes easier to make it function as part of APD 201, and by setting the impurity concentration of region 208 at a predetermined value or less, it becomes easier to vertically penetrate and deplete a part of region 208 during operation. The impurity concentration of region 233 is determined by the distance between region 204 and region 206 and the impurity distribution of these two regions. Therefore, it varies depending on the conditions, but it is preferably, for example, 2×10 16 ~2×10 18 cm -3 It is preferable that the area 209 and the area 230 are within a range of, for example, 5×10 16 ~2×10 18 cm -3 The area 232 is preferably in the range of, for example, 1×10 19 ~1×10 20 cm -3 As described above, the region 207 may be either P-type or N-type. For example, the region 207 is formed by doping an N-type impurity into a part of the region 233 to have an impurity concentration of, for example, 5×10 16 cm -3A conductive path is formed as the following P-type or N-type region. During operation, region 233 is depleted, and the region 207 in the depleted region 233 has a low potential for electrons and serves as a conductive path for electrons. If the semiconductor substrate before ion implantation is P-type, a part of the semiconductor substrate located between region 204 and region 206 may become P-type region 233 even if P-type impurity ions are not introduced to form region 233.

[0082] 13, the impurity concentrations of the regions 204 and 232 are different, but the region 204 may be formed with a high impurity concentration similar to that of the region 232, and no impurity may be introduced into the region corresponding to the region 232. Furthermore, when the region 232 is formed, the region 207 may be formed naturally by tailing the N-type impurity distribution in the depth direction.

[0083] In the configuration of this embodiment, as in the configurations shown in the first and second embodiments described above, the carrier multiplication factor when avalanche breakdown occurs can be suppressed. This provides an improvement effect on the above-mentioned problems of light emission crosstalk, dark current change, and power consumption. Furthermore, even when the size of the pixel 104 is further reduced due to the presence of the region 232, the configuration of this embodiment in which the regions 204, 207, and 206 overlap can be effectively applied. Furthermore, the configuration in which the regions 204, 207, and 206 overlap can further reduce characteristic variations while suppressing an increase in the manufacturing process.

[0084] (Fourth embodiment) Next, a photoelectric conversion device 100 according to a fourth embodiment of the present disclosure will be described with reference to FIG. 15. FIG. 15 is a cross-sectional view of a photoelectric conversion unit 102 arranged in a pixel 104 in this embodiment. The photoelectric conversion device 100 in this embodiment differs from the third embodiment shown in FIG. 13 in that the region 233 has a doughnut shape with a hollow center in a plan view. Other than this point and the points described below, the photoelectric conversion device 100 is substantially similar to the third embodiment, and therefore may not be described. The circuit diagram and SPAD operation in this embodiment are also similar to the operations described in FIG. 5, FIG. 7(a), FIG. 7(b), etc.

[0085] 16 is a diagram showing a method for forming the region 233 of the photoelectric conversion unit 102 arranged in the pixel 104 in this embodiment. In the figure, a resist 240 is arranged on a semiconductor substrate. The resist 240 is used when forming the region 204, the region 206, and the region 233. P-type impurity ions 241 are ions used to form the region 233.

[0086] According to a normal semiconductor manufacturing process, after applying resist to the entire surface of the semiconductor substrate, the resist in the region overlapping the region 204 and the region 206 in a plan view is partially etched away. Next, the region 204 corresponding to the first cathode is formed by shallowly implanting N-type impurity ions, and the region 206 corresponding to the second cathode is formed by implanting N-type impurity ions to a predetermined depth. Also, as shown in FIG. 16, the donut-shaped region 233 is formed by implanting P-type impurity ions 241 obliquely with respect to the interface of the semiconductor substrate while rotating the semiconductor substrate. The hollowed-out portion is a P-type semiconductor with a low impurity concentration or an N-type semiconductor. The desired region 207 can be formed by controlling the impurity concentration of the region 190, the impurity concentration of the region 233, the diameter of the hollowed-out portion, and the like.

[0087] When an N-type impurity is introduced into the region 233 to form a P-type or N-type region 207 with a low impurity concentration, the amount of N-type impurity introduced per unit area must be approximately equal to the amount of P-type impurity in the region 233. For example, if the P-type impurity concentration in the region 233 is 1×10 17 / cm 3 The N-type impurity introduced to form the region 207 is 1.1×10 17 / cm 3 So, 1×10 16 / cm 3 An N-type region 207 is formed having a concentration of 1×10 16 / cm 3 In the N-type region 207, the total number of P-type and N-type is 2.1 × 10 17 / cm 3 If the region 207 is a cube with a side length of 0.3 μm, the region 207 has 1.1×10 17 ×(0.3×10 -4 ), or 2970 N-type impurity ions. Similarly, there are 2700 P-type impurity ions. The effective number of N-type impurity ions is (2970 - 2700), or 270. These numbers are average numbers, and in reality the numbers vary. Statistics teaches us that the standard deviation of variation is the root of the average number. In this case, the variation in the number of P-type and N-type impurity ions combined is the root of (2970 + 2700), or about 75. In other words, for an effective number of N-type impurity ions that is an average of 270, the standard deviation of the variation is 75. Therefore, for a concentration of 1×10 16 / cm 3 The standard deviation of the N-type carrier conduction path is 1±0.28×10 16 / cm 3This results in a very large variation. The cause of this large variation is that many P-type impurity ions and many N-type impurity ions are mixed in the region 207 as described above. If a large variation occurs in the region 207 among many pixels, that is, if the resistance value of the region 207 varies greatly from pixel to pixel, the effect of the present invention will be reduced in actual operation. However, according to this embodiment, only a small number of impurities are present in the central hollow portion of the region 233 that becomes the region 207. If the numerical values ​​of the above example are applied, there are only 270 N-type impurity ions on average in the region 207. The standard deviation of the variation is about 16 times the root of 270, which is significantly reduced from the standard deviation of 75 in the above example. Therefore, according to this embodiment, the characteristic variation in many pixels is small, and similarly to the first to third embodiments, the effect of improving each of the three problems of light emission crosstalk, changes in dark current, and power consumption when a large number of photons are incident is exhibited.

[0088] Fifth embodiment Next, a photoelectric conversion device 100 according to a fifth embodiment of the present disclosure will be described with reference to FIG. 17. FIG. 17 is a cross-sectional view of a photoelectric conversion unit 102 arranged in a pixel 104 in this embodiment. The photoelectric conversion device 100 in this embodiment differs from the third embodiment shown in FIG. 13 in that it includes a region 238 and a region 239. Other than this point and the points described below, the photoelectric conversion device 100 is substantially similar to the third embodiment, and therefore may not be described. The circuit diagram and SPAD operation in this embodiment are also similar to the operations described in FIG. 5, FIG. 7(a), FIG. 7(b), etc.

[0089] Region 238 is a P-type region formed over a wider range at a depth similar to that of region 233 in a cross-sectional view, so as to surround region 233 in a planar view. Region 239 is an N-type region formed over a wider range at a depth similar to that of region 206 in a cross-sectional view, so as to surround region 206 in a planar view. Region 233 and region 206 are shaped to overlap region 204 in a planar view, and region 238 and region 239 are shaped to overlap both in a planar view. The following description is based on the assumption that the shape is as described above, but is not limited to this shape.

[0090] Region 207 can be formed by introducing N-type impurities into a part of region 233. However, in this case, as described in the fourth embodiment, if the impurity concentration of region 233 is high, a problem may occur in that the characteristics of region 207 vary greatly. In order to reduce the large variation in characteristics, it is necessary to reduce the concentration of P-type impurities in region 233. However, it may be difficult to reduce the concentration of P-type impurities in region 233 without variation.

[0091] FIG. 16 shows how P-type impurity ions are obliquely implanted into the semiconductor substrate to form the doughnut-shaped region 233 after the regions 204 and 206 are formed in the openings of the resist 240. However, it is not easy to form the doughnut shape with high accuracy, and basically, P-type impurity ions are implanted almost vertically into the semiconductor substrate to form the uniform region 233. When the regions 204 and 206 are formed, a considerable concentration of N-type impurity layer is deposited between these two regions, that is, in the region where the region 233 is to be formed. Therefore, a situation may arise in which a larger amount of P-type impurity must be introduced to form the region 233 that exceeds this N-type impurity and electrically separates the regions 204 and 206. The cause of this problem occurs when the region 206 is formed. In general, when impurity ions are implanted, a certain distribution occurs in the depth direction of the semiconductor substrate, so when the region 206 is formed, a certain N-type impurity distribution occurs shallower than the peak, but this problem occurs due to a different mechanism.

[0092] In general, in the formation of semiconductor elements, a process of forming desired openings in a resist and then implanting impurity ions into a semiconductor substrate is repeated. Basically, only the impurity ions that enter the resist openings are selectively introduced into the semiconductor substrate. However, when the opening area is small and the energy of the impurity ion implantation is increased to form elements in deep portions, the phenomenon that some of the impurity ions implanted into the resist enter the openings becomes prominent. That is, the relatively high-energy ions implanted into the resist move in the depth direction while gradually losing kinetic energy in the resist. Since these impurity ions move randomly in the planar direction, impurity ions implanted in positions particularly close to the resist openings may appear in the resist openings and enter the semiconductor substrate at the openings. Such impurity ions have lost some kinetic energy by the time they appear in the resist openings, and are generally deposited on the shallower side than the desired depth. Such unnecessary impurity ions are generated in large numbers near the boundaries of the resist openings. When the resist opening area is large, such unnecessary impurity ions are limited to the influence of only the vicinity of the resist opening boundaries, but when the opening area is small, such unnecessary impurity ions actually enter the entire resist opening.

[0093] When N-type impurity ions are implanted to form the region 206, the above-mentioned situation occurs, and unnecessary N-type impurity ions that pass through the resist are deposited on the shallower side than the depth at which the region 206 is to be formed, i.e., in the region where the region 233 is to be formed. Therefore, more P-type impurity ions are required to form the region 233. A large number of P-type and N-type impurity ions are mixed in the region 207 formation portion, which may cause large characteristic variations in the region 207 as described in the fourth embodiment. A method for easily reducing such large characteristic variations in the region 207 will be described below.

[0094] In this embodiment, the impurity concentration of the region 206 is reduced to reduce the amount of N-type ion implantation itself when forming the region 206. The amount of unnecessary N-type impurity ions entering the region where the region 233 is formed is also reduced in proportion to the amount of implantation. On the other hand, the region 206 corresponding to the second cathode plays a role in forming the APD together with the region 208, so a certain minimum impurity concentration is required. Therefore, the region 239, which has a planar area larger than the region 206, is made to play a part of the role of forming the region 206. The region 239 is formed by implanting N-type impurity ions under almost the same energy conditions as those for the N-type impurity ion implantation for forming the region 206. This makes it possible to reduce the amount of N-type impurity ions required when forming the region 206.

[0095] For example, the amount of N-type impurity ions required per unit area in region 206 is 1×10 13 / cm 2 The implantation amount of N-type impurity ions when forming the region 206 is set to 6×10 12 / cm 2 The amount of N-type impurities implanted during the formation of the region 239 is 4×10 12 / cm 2 In total, the amount of N-type impurity ions to be introduced into the region 206 is 1×10 13 / cm 2 When the region 239 is formed, the influence of unnecessary N-type impurity ions via the resist remains near the boundary of the region 239 and hardly enters the region 233. Therefore, by forming the region 206 together with the region 239, the amount of unnecessary N-type impurity ions entering the region 233 can be reduced. This allows the amount of P-type impurity ions introduced to form the region 233, in other words, the amount of N-type impurity ions introduced to form the region 207 to be reduced. Therefore, the characteristic variation of the region 207 can be reduced. During operation, it is preferable that the region 239 other than the region 206 is depleted. Otherwise, the PN junction capacitance of the region 206 increases, and the original purpose of the present invention, which is to reduce the carrier multiplication factor when an avalanche occurs, is at least partially impaired.

[0096] 18 is a pixel cross-sectional view of the process of forming the region 238 and the region 239 shown in FIG. 17. After the ion implantation of the region 204, the region 206, and the region 233, the process shown in FIG. 18 is carried out without a thermal process. In the figure, a resist 242 having an opening corresponding to the region where the region 238 is to be formed is arranged on the semiconductor substrate. Also shown is the implantation direction of P-type impurity ions 243 for forming the region 238. After the region 238 is formed, the same resist 242 is used to subsequently perform N-type impurity ion implantation for forming the region 239.

[0097] It is generally known that implanting impurity ions parallel to the crystal axis of a semiconductor substrate causes channeling of the ions, resulting in the ions penetrating deeper than the desired depth of the semiconductor substrate. Since the direction perpendicular to the surface of a semiconductor substrate is usually also the direction of the crystal axis, implanting impurity ions perpendicular to the surface of the semiconductor substrate causes channeling. On the other hand, a semiconductor region into which impurity ions are introduced at a high concentration partially loses its crystal structure and becomes partially amorphous. Therefore, even if impurity ions are implanted into an amorphous region, channeling is suppressed because the crystal axis is broken.

[0098] In the step of FIG. 18, ion implantation has already been performed in the region 204, the region 206, and the region 233. In particular, the region 204 is implanted with approximately 1×10 18 cm -3The high concentration impurity ions described above are introduced, and this portion is assumed to be amorphous. When P-type impurity ions are implanted to form the region 238 in this state, channeling is suppressed in the region 204 in plan view, and channeling occurs in the other portions. The P-type impurity ions penetrate deeply in the portion where channeling occurs, and some of them reach the region 239. Therefore, the effective N-type impurity concentration of the region 239 in this portion decreases, and the region 239 becomes more likely to be depleted. On the other hand, in the regions 204 and 206 in plan view, the proportion of the P-type impurity ions reaching the depth of the region 206 is smaller, and the effective N-type impurity concentration of the region 206 does not decrease much. Therefore, by the method of forming the region 238 shown in FIG. 18, the N-type impurity concentration of the region 239 other than the regions 204 and 206 in plan view can be selectively decreased, and this portion can be depleted during operation.

[0099] 19 shows the depth direction distribution of impurity ions in regions 204, 238, and 239. Of the two impurity ion distributions in region 238, the solid line shows the distribution in regions 204 and 206 on the planar layout. The dotted line shows the distribution in other portions, and it is shown that the distribution extends significantly to region 239.

[0100] The concentration of the P-type impurity in the region 233 is determined by the sum of the P-type impurity implantation in the process shown in Fig. 16 and the P-type impurity implantation in the process shown in Fig. 18, but the P-type impurity implantation in the process shown in Fig. 16 may not be performed. In addition, the N-type impurity ions in the region 206 and the region 239 may be implanted in an oblique direction slightly shifted from the vertical axis direction of the surface of the semiconductor substrate in order to suppress channeling. In this way, the APD characteristics formed by the region 206 and the region 208 are improved, and the overlap of the impurity distribution with the region 238 in the region 239 other than the region 206 becomes large, so that depletion is likely to occur during actual operation.

[0101] After the steps of forming region 238 and region 239 shown in FIG. 18 are completed, region 207 is formed. Region 207 may be formed in the same step as region 232, or may be formed in a separate step. In the case of separate steps, region 207 and region 232 may be disposed in positions that do not overlap in plan view, as shown in FIG. 14. Region 232 may not be formed by making the N-type impurity concentration of region 204 very high. Region 207 may also be formed at the same time by forming region 232 slightly deeper.

[0102] In the configuration of this embodiment, the carrier multiplication factor when an avalanche breakdown occurs can be suppressed, similarly to the configurations shown in the above-mentioned first to fifth embodiments. Moreover, according to this embodiment, while suppressing the characteristic variations, it is effective in addressing three problems, namely, light emission crosstalk, changes in dark current, and power consumption when a large number of photons are incident.

[0103] Sixth embodiment Next, the SPAD operation of the sixth embodiment of the present disclosure will be described with reference to FIG. 20. FIG. 20 is an equivalent circuit diagram of a part of the photoelectric conversion unit 102 and the signal processing circuit 103. Compared with the equivalent circuit shown in FIG. 7(a), the configuration shown in FIG. 20 includes an additional transistor 234. The transistor 234 is an N-type MOS transistor. The gate electrode of the transistor 234 is connected to nodeB. When nodeB becomes High, the transistor 234 turns ON and sets the potentials of nodeA and nodeD to a potential level at which the APD 201 does not cause avalanche breakdown. In other words, when the waveform shaping circuit 210 (detection circuit) detects an avalanche breakdown, the transistor 234 functions as a setting circuit that sets the potentials of the regions 204 and 206 to a potential at which avalanche breakdown does not occur in the photoelectric conversion unit 102. In the configuration shown in FIG. 20, when the transistor 234 turns ON, the potentials of the regions 204 and 206 become 0V, which is the ground level.

[0104] In the above-mentioned first to fifth embodiments, as shown in FIG. 7(b), the multiplication factor when the avalanche breakdown occurs is suppressed, and as a result, the potentials of nodeA and nodeD remain high even after the avalanche breakdown occurs. Therefore, if further photons are incident in this state, further avalanche breakdown may occur, and the potentials of nodeA and nodeD may become even lower due to discharge caused by the avalanche current. In that case, nodeB has already become high level due to the incidence of the first photon, and the state of nodeB does not change with the incidence of the second or subsequent photons. In other words, the avalanche breakdown caused by the incidence of the second or subsequent photons is not detected as a signal, and wasteful electron-hole pairs are generated.

[0105] Therefore, in the circuit shown in Fig. 20, a transistor 234 is provided. When an avalanche breakdown occurs due to the incidence of one photon during one period of the periodic reset pulse input to nodeC, the signal at nodeB generated by the waveform shaping circuit 210 becomes a high level indicating that an avalanche breakdown has been detected. This turns on the transistor 234, and nodeA and nodeD become the ground level. As a result, even if a subsequent photon is incident before the next reset pulse is input to nodeC, avalanche breakdown does not occur in the APD 201. In other words, the occurrence of avalanche breakdown is suppressed to a necessary minimum.

[0106] Here, this embodiment is effective when the transistor 203 operates as a reset circuit for resetting the potentials of the region 204 (node ​​A) and the region 206 (node ​​D) to a predetermined potential. When the transistor 234 resets the node A and the node D (when the transistor 234 is ON), no electron-hole pairs are generated in the APD 201. The reset by the transistor 234 is a discharge across a potential difference of about 2 V to the ground level. Therefore, the required electrical energy is much smaller than the discharge across a potential difference of about 20 to 30 V to a large negative potential VL when an avalanche breakdown occurs.

[0107] As described above, according to this embodiment, in addition to suppressing the carrier multiplication factor when an avalanche breakdown occurs, it is possible to prevent the occurrence of unnecessary avalanche breakdown within one period of a reset pulse periodically input to node C. Therefore, this embodiment has an improved effect on the problems of light emission crosstalk, changes in dark current, and power consumption, more than the above-mentioned first to fifth embodiments.

[0108] Seventh embodiment Next, a photoelectric conversion device 100 according to a seventh embodiment of the present disclosure will be described with reference to Figs. 21 to 23(a) and 23(b). Fig. 21 is a plan view of a photoelectric conversion unit 102 disposed in a pixel 104 in this embodiment. Fig. 22 is a cross-sectional view of the photoelectric conversion unit 102 between AB shown in Fig. 21. Fig. 21 is a plan view of a main surface 251 of a semiconductor substrate 250 shown in Fig. 22. Fig. 23(a) is an equivalent circuit diagram of a part of the photoelectric conversion unit 102 and the signal processing circuit 103, and Fig. 23(b) shows the potential changes of nodes A to E during SPAD operation. Nodes A to D are located in the same positions as those shown in Fig. 7(a). Node E is a node connected to a gate electrode 235 of a transistor 237 described later.

[0109] In the configurations shown in FIG. 21 and FIG. 22, the region 206 may constitute a part of the main surface 251 of the semiconductor substrate 250. Furthermore, the photoelectric conversion unit 102 further includes a transistor 237 that causes the region 204 and the region 206 to function as a source region or a drain region, respectively, and the region 207 to function as a channel region. The transistor 237 is an N-type MOS transistor. The transistor 237 includes a gate electrode 235 and a gate insulating film 236 disposed between the gate electrode 235 and the main surface 251 of the semiconductor substrate 250. Since the region 190 is basically depleted during operation, the non-formation or formation of a channel region (region 207) directly below the gate electrode 235 is determined by controlling the potential of the gate electrode 235. As a result, the transistor 237 controls the conduction between the region 204 and the region 206. As shown in the equivalent circuit diagram of FIG. 23( a ), the transistor 237 is disposed between node D connected to the cathode of the APD 201 and node A connected to the cathode of the parasitic PD 232 .

[0110] Next, the SPAD operation of this embodiment will be described with reference to Fig. 23(b). A pulse that periodically turns on the transistor 237 is input to nodeE connected to the gate electrode 235 of the transistor 237. This causes the transistor 237 to conduct at a predetermined cycle. Also, a reset pulse is input to nodeC at the same cycle as that of nodeE. This causes the transistor 203, which functions as a reset circuit for resetting the potentials of the regions 204 and 206 to a predetermined potential (potential VH), to reset the potentials of the regions 204 and 206 at the same cycle as that of the transistor 237.

[0111] At time t0, the reset of nodeA and nodeD ends. While the transistor 237 is conducting due to the input of a pulse to nodeE, a reset pulse is input to nodeC and transistor 203 turns ON. This starts the reset, and the potential of not only region 204 (nodeA) but also region 206 (nodeD) is reset. Next, transistor 237 turns OFF, and thereafter, transistor 203 turns OFF. As a result, nodeA and nodeD become floating at potential VH.

[0112] When a photon is incident at time t1, avalanche breakdown occurs in the APD 201, and the potential of the region 206 (node ​​D) drops to near the ground level, stopping avalanche multiplication. At this time, the discharge capacity of node D, which has only a small capacitance, is small, so the carrier multiplication factor is small. At time t2, node D becomes floating, maintaining the potential at which avalanche multiplication stopped.

[0113] Next, at time t3, nodeE goes High and transistor 237 turns ON. As a result, nodeA and nodeD become conductive, and a potential change occurs so that nodeA and nodeD have the same potential. The potential of nodeA drops and the potential of nodeD rises, but the capacitance added to nodeA is large and the capacitance added to nodeD is small, so the potential change of nodeA is small. Waveform shaping circuit 210 (detection circuit) detects avalanche breakdown according to the potential of nodeA (region 204) when transistor 237 becomes conductive. Therefore, avalanche breakdown in APD 201 can be detected by setting the decision threshold of waveform shaping circuit 210 to an appropriate value so that small potential changes of nodeA can be detected.

[0114] At time t4, the potential of nodeC goes low, turning on the transistor 203, and again resetting the nodes A and D. Next, at time t5, the potential of nodeC goes high, and again returning to the state at time t0.

[0115] In this embodiment, the carrier multiplication factor when an avalanche breakdown occurs may be further suppressed to a smaller value than in the first to fifth embodiments. In the configurations shown in the first to fifth embodiments, nodeA and nodeD are always electrically connected to each other through the region 207 functioning as a resistor. Therefore, when an avalanche breakdown occurs in the APD 201, a certain amount of discharge occurs in nodeA, which has a large capacitance. On the other hand, in this embodiment, the electrical connection between nodeA and nodeD can be almost completely cut off while the transistor 237 is OFF and a channel region is not generated. Therefore, when an avalanche breakdown occurs in the APD 201, only discharge occurs in nodeD, which has a small loaded capacitance.

[0116] Also, consider the case where multiple photons are incident during one reset cycle by the transistor 203 (reset circuit). Even in that case, in this embodiment, the potential of node D is sufficiently lowered to about the ground level due to the avalanche breakdown caused by the first incident photon. Therefore, avalanche breakdown due to the incidence of the second or subsequent photons does not occur. Therefore, in this embodiment, it is not necessary to provide the transistor 234 shown in the third embodiment.

[0117] As described above, according to this embodiment, the carrier multiplication factor when an avalanche breakdown occurs can be further suppressed compared to the above-mentioned embodiments. Therefore, this embodiment exerts a further improvement effect on each of the above-mentioned three problems, namely, light emission crosstalk, dark current change, and power consumption.

[0118] Eighth embodiment Next, a photoelectric conversion device 100 according to an eighth embodiment of the present disclosure will be described. This embodiment can be considered as a modification of the seventh embodiment described above, and similarly to the configurations shown in Figs. 21 and 22 described above, the APD 201 and the parasitic PD 232 are connected by a transistor 237. Meanwhile, in this embodiment, as shown in Fig. 24, a comparator 220 is used as a detection circuit for detecting an avalanche breakdown, instead of the waveform shaping circuit 210. NodeA is connected to the - input terminal of the comparator 220, and nodeF is connected to the + input terminal.

[0119] Next, the SPAD operation in this embodiment will be described with reference to Fig. 25. This embodiment corresponds to the incidence of a plurality of photons in one signal detection operation (operation between two consecutive reset pulses input to node C), operates to count the number of incident photons, and performs signal processing.

[0120] As shown in FIG. 25, in this embodiment, as in the seventh embodiment described above, a pulse is periodically input to nodeE, and the transistor 237 conducts at a predetermined period. On the other hand, unlike the seventh embodiment, a reset pulse is not input to nodeC at the same period as nodeE, and a reset pulse for resetting the potentials of the regions 204 and 206 is input each time the transistor conducts a predetermined number of times. In the example shown in FIG. 25, one reset pulse is input to nodeC for every four pulses input to nodeE. The relationship between the reset pulse input to nodeC and the pulse input to nodeE when a reset pulse is input to nodeC may be the same as the relationship shown in FIG. 23(b).

[0121] During one cycle in which a reset pulse is input to nodeC, a pulse that turns on the transistor 237 multiple times is periodically input to nodeE. In the example shown in FIG. 25, photons are incident at times t1, t2, and t3. This is the incidence at the first, third, and fourth cycles of four cycles in which a pulse is input to nodeE during one cycle in which a reset pulse is input to nodeC. Even if a photon is incident and an avalanche breakdown occurs in the APD 201, the transistor 237 becomes conductive due to the input of a pulse to nodeE, and the potential of nodeD (region 206) rises. Therefore, three avalanche breakdowns occur in the APD 201 in response to each of the three incident photons, and each time the transistor 237 turns on, the potential of nodeA drops by an amount equivalent to the total amount of discharge in the three avalanche breakdowns. The potential of nodeA from time t4 to time t5 is a potential that has dropped by an amount equivalent to the total amount of discharge in the three avalanche breakdowns. The capacitance added to the APD 201 (region 206) is small, and the amount of discharge per avalanche breakdown is small. Therefore, this embodiment utilizes the fact that avalanche breakdown can occur multiple times in the APD 201 even when nodeA (and nodeD) are not reset to the potential VH.

[0122] 25, nodeF and nodeB are shown in an enlarged scale from time t4 to time t5. Step-like potentials V0, V1, V2, V3, and V4 are input to nodeF, which is connected to the positive input terminal of comparator 220. Vn (n=0, 1, 2, 3, 4) are potentials corresponding to the number of avalanche breakdowns that occur during one period of the reset pulse input to nodeC. Each value is set so that when Vn, which satisfies n≧k for k occurrences of avalanche breakdown, is input to nodeF, nodeB, which corresponds to the output of comparator 220, is inverted from High to Low.

[0123] Generally, the comparator 220 may operate only during the period from time t4 to time t5 since a current always flows during operation. Also, during the current-off period other than the period from time t4 to time t5, the potential of nodeB may be set to High. Since the circuit configuration of such a comparator is very common, details are omitted.

[0124] In the example shown in FIG. 25, nodeB inverts at time t6 when nodeF becomes V3. Therefore, the number of occurrences of avalanche breakdown is determined to be three. In this manner, the comparator 220 (detection circuit) generates a multi-value signal according to the potential of nodeA before the transistor 237 is turned on a predetermined number of times and the transistor 203 (reset circuit) resets the potentials of nodeA and nodeD. This makes it possible to count the number of occurrences of avalanche breakdown due to the incidence of multiple photons in one signal detection operation (operation between two consecutive reset pulses input to nodeC).

[0125] This embodiment is not limited to the configuration shown in FIG. 24. There may be a circuit configuration in which the steady-state current does not flow when the comparator 220 is operating. There may also be a case where the connection between the parasitic PD 232 and the APD 201 is the region 207 that functions as a resistor as in the first and second embodiments. When the region 207 functions as a resistor, a configuration is conceivable in which an N-type transistor is arranged between the negative input terminal and nodeA of the comparator 220, with the source region connected to nodeA and the drain region connected to the negative input terminal, and the gate electrode is set to a constant potential. Using the saturation region operation of this transistor, discharge is performed by avalanche breakdown occurring in the APD 201 from the drain region. As long as the saturation region operation is maintained, a potential change equivalent to the total discharge charge amount due to multiple avalanche currents occurs in the drain region. The comparator 220 detects the potential change in the drain region and can count the number of avalanche breakdowns that have occurred.

[0126] Here, the count number of the comparator 220 and the number of avalanche breakdowns that have actually occurred do not necessarily have to match. All that is required is a circuit that converts an analog quantity, that is, the total discharge charge amount generated by multiple avalanche breakdowns, into a digital quantity. For example, a digital signal "1" may correspond to "2.5" avalanche breakdowns in the APD 201. In other words, the conversion gain, which is the digital signal / the number of actual avalanche breakdowns, may take a value other than 1. When the conversion gain is set small, a small digital signal can represent many avalanche breakdowns.

[0127] Furthermore, for example, a circuit equivalent to a source follower may be connected to node A instead of the comparator 220. In that case, the circuit connected to node A may have a configuration used in a so-called readout circuit of a CMOS sensor, which performs AD conversion of the source follower output.

[0128] As described with reference to FIG. 2, in general, in a SPAD, the number of occurrences of avalanche breakdown is added up in each pixel 104 using a counter circuit 211, and the maximum count number is determined by the number of bits of the counter circuit 211. Since the size of the pixel 104 is limited, the number of bits of the counter that can be formed is also limited. Therefore, if the conversion gain of the above-mentioned digital signal / actual number of avalanche breakdowns is reduced, it is possible to handle a larger number of incident photons. In other words, the saturation signal of the pixel 104 can be increased. In particular, when the number of incident photons is large, it may be effective to reduce such a conversion gain.

[0129] As described above, according to this embodiment, like the seventh embodiment, the carrier multiplication factor when an avalanche breakdown occurs can be suppressed. That is, this embodiment has an improvement effect on the above-mentioned three problems of light emission crosstalk, dark current change, and power consumption. Furthermore, compared to the seventh embodiment, the period of the reset pulse input to node C can be made shorter. Therefore, it is possible to reduce the power consumption required for the drive pulse (reset pulse). Furthermore, as described above, it is also possible to increase the saturation signal of the pixel.

[0130] Here, an application example of the photoelectric conversion device 100 according to the above-mentioned embodiment will be described below. FIG. 26 is a schematic diagram of an equipment EQP equipped with the photoelectric conversion device 100. As shown in FIG. 26, the photoelectric conversion device 100 is accommodated in a semiconductor package PKG. The package PKG may include a base body to which the photoelectric conversion device 100 is fixed, a cover body such as glass facing the photoelectric conversion device 100, and a conductive connection member such as a bonding wire or bump that connects a terminal provided on the base body to a terminal provided on the photoelectric conversion device 100. The equipment EQP may further include at least one of a control device CTRL, a processing device PRCS, a display device DSPL, and a memory device MMRY.

[0131] The optical system OPT forms an image on the pixel array 101, and may be, for example, a lens, a shutter, or a mirror. The control device CTRL controls the operation of the photoelectric conversion device 100, and may be, for example, a semiconductor device such as an ASIC. The processing device PRCS processes a signal output from the photoelectric conversion device 100, and may be, for example, a semiconductor device such as a CPU or an ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays data obtained by the photoelectric conversion device 100. The memory device MMRY is a magnetic device or a semiconductor device that stores data obtained by the photoelectric conversion device 100. The memory device MMRY may be a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN may have a moving part or a propulsion part such as a motor or an engine. The mechanical device MCHN also drives parts of the optical system OPT for, for example, zooming, focusing, and shutter operation. In the device EQP, the data output from the photoelectric conversion device 100 is displayed on the display device DSPL, or transmitted to the outside by a communication device (not shown) included in the device EQP. For this reason, the device EQP may include a memory device MMRY and a processing device PRCS.

[0132] The equipment EQP incorporating the photoelectric conversion device 100 can be applied to surveillance cameras, and on-board cameras mounted on transport equipment such as automobiles, railroad cars, ships, aircraft, and industrial robots. In addition, the equipment EQP incorporating the photoelectric conversion device 100 can be applied not only to transport equipment but also to a wide range of equipment that uses object recognition, such as an intelligent transport system (ITS).

[0133] The device EQP is suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras) having a photographing function. In the camera. The device EQP may also be transportation equipment such as vehicles, ships, and aircraft. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device 100 and for assisting and / or automating driving (piloting) by using a photographing function. The processing device for assisting and / or automating driving (piloting) can perform processing for operating a mechanical device as a moving device based on information obtained by the photoelectric conversion device 100. Alternatively, the device EQP may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0134] According to the above-described embodiment, it is possible to provide a technique that is advantageous for suppressing the multiplication factor. Therefore, if the photoelectric conversion device according to the embodiment is used for equipment EQP, the value of the equipment can also be improved.

[0135] The disclosure of this specification includes the following photoelectric conversion devices and instruments.

[0136] (Item 1) A photoelectric conversion device including a photoelectric conversion unit disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type constituting a portion of the first main surface and connected to a detection circuit for detecting an avalanche breakdown; a second region of the first conductivity type spaced apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being disposed closer to the second main surface than the first region and the second region; a fourth region disposed between the first region and the second region, the second region and the third region function as an avalanche photodiode; A photoelectric conversion device, characterized in that the first region and the second region are configured to be electrically conductive through the fourth region.

[0137] (Item 2) 2. The photoelectric conversion device according to item 1, wherein the first region and the third region do not function as an avalanche photodiode.

[0138] (Item 3) 3. The photoelectric conversion device according to item 1 or 2, wherein a distance between the second region and the third region is shorter than a distance between the first region and the third region.

[0139] (Item 4) A photoelectric conversion device including a photoelectric conversion unit disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type constituting a part of the first main surface and connected to a detection circuit for detecting an avalanche breakdown; a second region of the first conductivity type spaced apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being disposed closer to the second main surface than the first region and the second region; a fourth region arranged to connect the first region and the second region, A photoelectric conversion device, wherein the distance between the second region and the third region is shorter than the distance between the first region and the third region.

[0140] (Item 5) 5. The photoelectric conversion device according to any one of items 1 to 4, wherein the fourth region has a lower impurity concentration than the first region and the second region.

[0141] (Item 6) the photoelectric conversion unit further includes a fifth region between the third region and the second main surface, the fifth region having an impurity concentration lower than those of the first region and the second region; A photoelectric conversion device described in any one of items 1 to 5, characterized in that charges generated in the fifth region by the incidence of light flow into the second region through a depletion region formed in a region of the third region that overlaps with the second region in an orthogonal projection onto the first principal surface.

[0142] (Item 7) 7. The photoelectric conversion device according to any one of items 1 to 6, wherein the fourth region includes a region of the first conductivity type.

[0143] (Item 8) 8. The photoelectric conversion device according to item 7, wherein the fourth region functions as a resistor connecting the first region and the second region.

[0144] (Item 9) 9. The photoelectric conversion device according to item 8, wherein the fourth region functions as a resistor of 20 kΩ or more.

[0145] (Item 10) 10. The photoelectric conversion device according to any one of items 1 to 9, wherein the second region constitutes a part of the first main surface.

[0146] (Item 11) 10. The photoelectric conversion device according to any one of items 1 to 9, wherein the second region is disposed between the first region and the third region.

[0147] (Item 12) The photoelectric conversion device described in any one of items 1 to 11, further comprising a setting circuit that sets the potentials of the first region and the second region to potentials at which avalanche breakdown does not occur in the photoelectric conversion unit when the detection circuit detects an avalanche breakdown.

[0148] (Item 13) 13. The photoelectric conversion device according to any one of items 1 to 12, further comprising a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential.

[0149] (Item 14) the second region constitutes a part of the first main surface, the photoelectric conversion unit further includes a transistor that causes the first region and the second region to function as a source region or a drain region, respectively, and the fourth region to function as a channel region; 7. The photoelectric conversion device according to any one of items 1 to 6, wherein the transistor controls conduction between the first region and the second region.

[0150] (Item 15) further comprising a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential; The transistor is turned on at a predetermined period, 15. The photoelectric conversion device according to item 14, wherein the reset circuit resets the potentials of the first region and the second region in the same cycle as the transistor.

[0151] (Item 16) Item 16. The photoelectric conversion device according to item 15, wherein the detection circuit detects an avalanche breakdown in response to the potential of the first region when the transistor is conductive.

[0152] (Item 17) further comprising a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential; The transistor is turned on at a predetermined period, 15. The photoelectric conversion device according to item 14, wherein the reset circuit resets the potentials of the first region and the second region every time the transistor is turned on a predetermined number of times.

[0153] (Item 18) Item 18. The photoelectric conversion device of item 17, wherein the detection circuit generates a digital signal corresponding to the potential of the first region before the transistor is conductive for the predetermined number of times and the reset circuit resets the potentials of the first region and the second region.

[0154] (Item 19) 19. The photoelectric conversion device according to any one of items 15 to 18, wherein the reset circuit starts a reset while the transistor is conductive.

[0155] (Item 20) Item 12. The photoelectric conversion device according to item 11, characterized in that it includes at least a region where the first region and the second region overlap in a planar view, and has a sixth region of the second conductivity type arranged at a depth between the first region and the second region.

[0156] (Item 21) The photoelectric conversion device according to item 20, characterized in that the fourth region is surrounded by the sixth region in a plan view, has approximately the same depth as the sixth region, and is a region having an impurity concentration of the second conductivity type lower than an impurity concentration of the sixth region or a region of the first conductivity type. (Item 22) A photoelectric conversion device according to any one of items 1 to 21, A processing device that processes a signal output from the photoelectric conversion device; An apparatus comprising:

[0157] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0158] 100 Photoelectric conversion device 102 Photoelectric conversion unit 204,206,207,208 area 201 APD 250 Semiconductor Substrates 251,252 Main surface

Claims

1. A photoelectric conversion device including a photoelectric conversion unit disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type constituting a portion of the first major surface and connected to a detection circuit for detecting an avalanche breakdown; a second region of the first conductivity type spaced apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being disposed closer to the second main surface than the first region and the second region; a fourth region disposed between the first region and the second region, the second region and the third region function as an avalanche photodiode; A photoelectric conversion device, characterized in that the first region and the second region are configured to be electrically conductive through the fourth region.

2. 2 . The photoelectric conversion device according to claim 1 , wherein the fourth region has an impurity concentration lower than those of the first region and the second region.

3. 2. The photoelectric conversion device according to claim 1, wherein the first region and the third region do not function as an avalanche photodiode.

4. 2 . The photoelectric conversion device according to claim 1 , wherein the distance between the second region and the third region is shorter than the distance between the first region and the third region.

5. A photoelectric conversion device including a photoelectric conversion unit disposed on a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The photoelectric conversion unit is a first region of a first conductivity type constituting a portion of the first major surface and connected to a detection circuit for detecting an avalanche breakdown; a second region of the first conductivity type spaced apart from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being disposed closer to the second main surface than the first region and the second region; a fourth region arranged to connect the first region and the second region, A photoelectric conversion device, wherein a distance between the second region and the third region is shorter than a distance between the first region and the third region.

6. 6. The photoelectric conversion device according to claim 5, wherein the fourth region has an impurity concentration lower than those of the first region and the second region.

7. the photoelectric conversion unit further includes a fifth region between the third region and the second main surface, the fifth region having an impurity concentration lower than those of the first region and the second region; The photoelectric conversion device according to claim 1, characterized in that charges generated in the fifth region by the incidence of light flow into the second region through a depletion region formed in a region of the third region that overlaps with the second region in an orthogonal projection onto the first principal surface.

8. The photoelectric conversion device according to claim 1 , wherein the fourth region includes a region of the first conductivity type.

9. The photoelectric conversion device according to claim 8 , wherein the fourth region functions as a resistor connecting the first region and the second region.

10. The photoelectric conversion device according to claim 9 , wherein the fourth region functions as a resistor of 20 kΩ or more.

11. The photoelectric conversion device according to claim 1 , wherein the second region constitutes a part of the first main surface.

12. The photoelectric conversion device according to claim 1 , wherein the second region is disposed between the first region and the third region.

13. The photoelectric conversion device according to claim 1, further comprising a setting circuit that sets the potentials of the first region and the second region to a potential at which avalanche breakdown does not occur in the photoelectric conversion unit when the detection circuit detects an avalanche breakdown.

14. 2. The photoelectric conversion device according to claim 1, further comprising a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential.

15. The second region constitutes a part of the first main surface, the photoelectric conversion unit further includes a transistor that causes the first region and the second region to function as a source region or a drain region, respectively, and the fourth region to function as a channel region; 2 . The photoelectric conversion device according to claim 1 , wherein the transistor controls conduction between the first region and the second region.

16. a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential; The transistor is turned on at a predetermined period, 16. The photoelectric conversion device according to claim 15, wherein the reset circuit resets the potentials of the first region and the second region in the same cycle as that of the transistor.

17. 17. The photoelectric conversion device according to claim 16, wherein the detection circuit detects an avalanche breakdown in response to a potential of the first region when the transistor is turned on.

18. a reset circuit for resetting the potentials of the first region and the second region to a predetermined potential; The transistor is turned on at a predetermined period, 16. The photoelectric conversion device according to claim 15, wherein the reset circuit resets the potentials of the first region and the second region every time the transistor is turned on a predetermined number of times.

19. The photoelectric conversion device of claim 18, wherein the detection circuit generates a digital signal corresponding to the potential of the first region when the transistor is conductive for the predetermined number of times and before the reset circuit resets the potentials of the first region and the second region.

20. 17. The photoelectric conversion device according to claim 16, wherein the reset circuit initiates a reset while the transistor is conductive.

21. The photoelectric conversion device according to claim 12, characterized in that it includes at least a region where the first region and the second region overlap in a planar view, and has a sixth region of the second conductivity type arranged at a depth between the first region and the second region.

22. The photoelectric conversion device according to claim 21, characterized in that the fourth region is surrounded by the sixth region in a planar view, has approximately the same depth as the sixth region, and is a region having an impurity concentration of the second conductivity type lower than the impurity concentration of the sixth region or a region of the first conductivity type.

23. A photoelectric conversion device according to any one of claims 1 to 22, A processing device that processes a signal output from the photoelectric conversion device; An apparatus comprising:

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