Design support system and coordination device

Abstract

To provide a design support system capable of reducing a time period from designing to production of a semiconductor by providing design support information on the basis of information obtained through manufacturing of the semiconductor.SOLUTION: A design support system 10 includes: a designing unit 2; a wafer process unit 3; a packaging unit 4; and a coordination device 1 which acquires, from the wafer process unit 3, wafer process information measured in a wafer process, acquires, from the packaging unit 4, packaging process information measured in the packaging process, and provides design support information obtained on the basis of the wafer process information and the packaging process information to the designing unit 2.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a design support system and a control device. [Background technology]

[0002] Conventionally, general-purpose semiconductors that can be installed in various products have been mass-produced. For example, general-purpose semiconductors include CPUs (Central Processing Units) installed in personal computers. Conventional general-purpose semiconductors based on the basic concept of von Neumann architecture were designed to have high performance in sequential processing.

[0003] According to Moore's Law, it is believed that production costs can be reduced by increasing the integration density of semiconductors, and traditionally the main goal was to increase the production volume of general-purpose semiconductors and reduce production costs. However, increasing the production volume of semiconductors requires a large investment in equipment. For this reason, the fabless production method, in which a company that mainly designs semiconductors outsources the production of semiconductors to an external company, became mainstream.

[0004] Patent Document 1 discloses a technique relating to lithography-based pattern optimization. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Pat. No. 1,144,9659 Summary of the Invention [Problem to be solved by the invention]

[0006] With recent advances in AI (Artificial Intelligence) technology, semiconductors are being used for AI processing. Because AI processing involves parallel processing, it is not appropriate to use general-purpose semiconductors. For this reason, there has been a demand for the manufacture of dedicated semiconductors optimized for each AI used. However, dedicated semiconductors are semiconductors that can only be used in specific products, and will not function if installed in products other than the specific product. For this reason, mass-producing dedicated semiconductors is not realistic, and even if it were possible to mass-produce dedicated semiconductors, there is a problem in that it would be extremely costly.

[0007] As semiconductors become more miniaturized, not only has the TAT for semiconductor manufacturing increased, but the rules and constraints for semiconductor design have also become more complex, lengthening the time required for design. For this reason, if a problem was found in the semiconductor design during development, it took a huge amount of time and money to redo the design and manufacturing (prototype). Therefore, a method to reduce the number of redesigns of semiconductors was needed.

[0008] In the current semiconductor manufacturing method, there are separate companies that design semiconductors and companies that manufacture semiconductors. Therefore, the optimal manufacturing conditions or the causes of failures that can only be known by the companies that manufacture semiconductors based on design information from the companies that design semiconductors are not shared with the companies that design semiconductors. Even if the optimal manufacturing conditions and the causes of failures are shared between companies, the companies that design semiconductors do not know how to optimally design semiconductors and simply repeat trial and error, which takes a long time to design. Even if the technology disclosed in Patent Document 1 is used, the time required for design remains the same.

[0009] The present invention has been made in view of the above circumstances, and has an object to significantly shorten the time it takes from semiconductor design to production. [Means for solving the problem]

[0010] The design support system of the present invention includes a design unit that designs a wafer process for manufacturing wafers and a packaging process for manufacturing packages from the wafers, a wafer process unit that manages the wafer process, a packaging unit that manages the packaging process for wafers manufactured by the wafer process unit, and a control device that acquires wafer process information measured in the wafer process from the wafer process unit, acquires packaging process information measured in the packaging process from the packaging unit, and provides design support information calculated based on the wafer process information and the packaging process information to the design unit. Effect of the Invention

[0011] According to the present invention, by providing design support information based on information obtained by manufacturing semiconductors, it is possible to significantly reduce the time it takes from designing to producing semiconductors. Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0012] [Figure 1] 1 is an overall configuration diagram showing an example of a semiconductor manufacturing process according to an embodiment of the present invention; [Diagram 2] FIG. 11 is a diagram showing an example of a post-process in a packaging process according to an embodiment of the present invention. [Diagram 3] 1 is a block diagram showing an example of the overall configuration of a design support system according to an embodiment of the present invention; [Figure 4] 2 is a block diagram showing an example of the internal configuration of a command device according to an embodiment of the present invention; FIG. [Diagram 5] 1 is a flowchart illustrating an example of an AI-assisted design solution provided by a design unit according to an embodiment of the present invention. [Figure 6] FIG. 13 is a diagram showing an experiment of a difference between data obtained by a batch type and a single-wafer type according to an embodiment of the present invention. [Figure 7] FIG. 11 is a diagram showing the contents of data obtained by a batch type and a single wafer type according to an embodiment of the present invention. [Figure 8]FIG. 1 is a diagram showing the difference in turnaround time between a conventional manufacturing method and a manufacturing method according to the present embodiment. [Figure 9] FIG. 1 is a diagram illustrating a manufacturing method using a full-sheet device according to an embodiment of the present invention. [Figure 10] FIG. 11 is a diagram illustrating an example of the operation of a guidance and management unit according to an embodiment of the present invention. [Figure 11] FIG. 2 illustrates an example of a heterogeneous integration (hetero) design with chiplets according to an embodiment of the present invention. [Figure 12] FIG. 1 illustrates three example processes that can reduce packaging turnaround time according to an embodiment of the present invention. [Figure 13] FIG. 11 is a diagram showing an example of change in turnaround time in a packaging process according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functions or configurations are designated by the same reference numerals, and redundant description will be omitted.

[0014] [One embodiment] <An example of the semiconductor manufacturing process> FIG. 1 is a diagram showing an overall configuration of an example of a semiconductor manufacturing process according to an embodiment.

[0015] The semiconductor manufacturing process is roughly divided into a design process, a wafer process for manufacturing wafers, and a packaging process for manufacturing packages from wafers. In this embodiment, the manufacturing technology for design is called MFD (Manufacturing for Design) to distinguish it from DFM (Design for Manufacturing), which is a conventional design technology for manufacturing. MFD is a methodology that supports design based on data obtained in the wafer process and packaging process. In the design support system 10 according to this embodiment (see FIG. 3 described later), by repeating MFD and DFM, it becomes possible to realize Design-Manufacturing Co-Optimization (DMCO), which represents the cooperation and optimization of semiconductor design and manufacturing. As a result, the design support system 10 according to this embodiment aims to halve the total cycle time from semiconductor design to packaging.

[0016] In the design process, semiconductors and circuit layouts are designed. In this embodiment, a new design methodology supported by an AI (Artificial Intelligence) model is provided to the applicant's customer. For example, the AI ​​model learns silicon big data measured by various measuring devices in the wafer process and packaging process, and each AI model shown in FIG. 4 described later is trained, improving the performance of the PDK (Process Design Kit). In this embodiment, the trained AI model is used in the design process to assist the design by the customer's designer, thereby automating semiconductor design.

[0017] The PDK contains technology information necessary for semiconductor design, such as what device models are available, what design rules should be used for design, and what regulatory components should be extracted. Designers import this information into the PDK tool to design semiconductors. The MFD in which the AI ​​model learns from silicon big data, as shown in Figure 1, and the MFD in which the AI ​​model assists the designer in design by navigating the designer, are configured in a hierarchical structure.

[0018] (General wafer and packaging processes) The wafer and packaging processes are divided into front-end and back-end processes. The front-end process includes the front-end line (FEOL: Front End of Line) where elements are formed, the back-end line (BEOL: Back End of Line) where wiring is formed, and wafer characteristic inspection.

[0019] FEOL includes, for example, a cleaning process, a film deposition process, a photolithography process, an etching process, an ion implantation process, and a wafer inspection process, and these processes are repeated. BEOL includes, for example, a cleaning process, a film deposition process, a photolithography process, an etching process, a planarization process, and a wafer inspection process, which are performed repeatedly on wafers manufactured through FEOL. In the wafer inspection process, electrical characteristics of the wafer are inspected after it has been manufactured through the BEOL stage. When the wafer characteristic inspection is completed, the wafer is completed.

[0020] The back-end process includes the assembly process and the inspection process. The assembly process includes the dicing process, die bonding process, wire bonding process, and molding process for wafers that are determined to be non-defective as a result of the wafer characteristic inspection. The inspection process includes the final inspection process for the semiconductors produced in the molding process. These back-end processes consisting of the assembly process and inspection process are carried out in simple packaging processes using wire bonding of a single chip and complex packaging processes in which multiple chips are stacked. Once the final inspection process is completed, the packaged semiconductor (also called a chip) is completed.

[0021] (Wafer process and packaging process according to this embodiment) In general, in wafer processes, there are batch processes in which the processes of wafers in a lot are the same, and single-wafer processes in which wafers in a lot are processed one by one and the processes of each wafer can be changed, and usually both are mixed. In the wafer process according to this embodiment, all processes are processed by single-wafer processes. This allows the time required to complete one lot to be reduced to less than the normal time required to complete. Furthermore, by changing the conditions for each wafer and prototyping them, a larger amount of data is accumulated in the same time compared to processes including batch processes, and silicon big data is formed. Silicon big data contributes to improving the yield of wafers in the wafer process. In addition, silicon big data is used to learn an AI model (design AI model 72 in FIG. 4 described later) in the design process (MFD). In addition, in the wafer process, the single-wafer process allows the processing time (x) for one wafer to be reduced to less than half of the conventional time.

[0022] Currently, with the advances being made in chiplet technology, the packaging process has evolved to include multiple highly bonded wafers to wafers, wafers to chips, and chips to chips, each of which is then mounted onto a substrate to form a multi-chip, with the combinations becoming extremely diverse and complex. The post-processing described below conceptually involves chipping the wafer completed in the pre-processing, mounting the chips on a substrate (such as a silicon substrate) with another rewiring, and then mounting the substrate on the final packaging substrate. Since a substrate with another rewiring is mounted on the packaging substrate, multiple chips with each function are integrated and connected. Therefore, even if not all functions are integrated on one chip, the same functions can be realized by a packaging substrate product in which multiple chips with each function are integrated.

[0023] FIG. 2 is a diagram showing an example of a post-process in a packaging process compatible with multi-chip configuration. For example, the wafer manufactured in the above-mentioned pre-processing is subjected to a bump formation process and a dicing process. In addition, a TSV process, a rewiring layer formation process, and a bump formation process are performed on the rewiring substrate. Then, a chip mounting process is performed in which the chips separated by the dicing process are combined with the rewiring substrate, and after the sealing process and bump formation process, a substrate mounting process is performed on the packaging substrate. After the sealing process, a final inspection process is performed.

[0024] In the design process, heterogeneous (heterogeneous integration) design is possible using chiplet technology based on design support information received from a chiplet technology platform that includes multiple IPs. In the semiconductor field, the functional blocks that make up LSIs, such as CPUs, image processing circuits, and memories, are considered design assets and are called IP (Intellectual Property) cores or simply IP. In this specification, IP is described as a circuit element in semiconductor design. Various circuit elements are assumed, such as simple standard cells, interface functional blocks, and CPU cores. Details of chiplets will be described later from Figure 11 onwards.

[0025] <Example of design support system configuration> 3 is a block diagram showing an example of the overall configuration of a design support system 10 according to this embodiment. The design support system 10 includes a control device 1, a design section 2, a wafer process section 3, and a packaging section 4.

[0026] The control device 1 provides a platform that can be arbitrarily accessed by the design section 2, the wafer process section 3, and the packaging section 4. To this end, the control device 1 acquires wafer process information measured in the wafer process for manufacturing wafers from the wafer process section 3, acquires packaging process information measured in the packaging process from the packaging section 4, and provides design support information calculated based on the wafer process information and the packaging process information to the design section 2.

[0027] The supervision device 1 uses the wafer process information as silicon big data and the packaging process information as packaging big data to perform an analysis using a design AI model 72 shown in FIG. 4 described below to create design support information. In the analysis using the design AI model 72, correlations between various types of parameters are obtained based on the silicon big data and the packaging big data. The design AI model 72 provides design support information including optimal parameter combinations, values, etc. to the design unit 2.

[0028] The design unit 2 designs the wafer process and the wafer packaging process. The design support information provided by the control device 1 and the design support function of the AI ​​model enable optimal design of semiconductors, so the design unit 2 can increase the convergence speed of the design. Note that the design unit 2 may import information on the semiconductor designed by a designer using the design support function of the AI ​​model, or may import information on the semiconductor designed by the AI ​​model itself.

[0029] The wafer process section 3 has a function of managing the wafer process, and manufactures wafers based on the design information designed by the design section 2. The wafer process section 3 transmits data measured by various measuring devices in the wafer process to the control device 1 as wafer process information.

[0030] The packaging unit 4 has a function of managing the packaging process for the wafers manufactured by the wafer process unit 3. The packaging unit 4 performs a packaging process for the wafers manufactured by the wafer process unit 3, in which various chips are arranged on a substrate and wiring is performed between the multiple chips, based on the arrangement information designed by the design unit 2. The packaging unit 4 also transmits data measured by various measuring devices in the packaging process to the control device 1 as packaging process information.

[0031] 4 is a block diagram showing an example of the internal configuration of the supervising device 1 according to this embodiment. The supervising device 1 operates as a platform that provides the functions of each part of the design section 2. The supervising device 1 includes a wafer process information collecting section 50, a packaging process information collecting section 60, a design process learning section 70, and an isolating section 75. Conventionally, correlation data was obtained from data obtained in the wafer process using the knowledge of engineers. In contrast, in this system, the design AI model 72 can extract new correlation data with high accuracy from large amounts of data that engineers cannot handle.

[0032] The wafer process information collecting unit 50 accumulates wafer process information acquired for each wafer manufactured in the wafer process, and outputs the wafer process information to the design process learning unit 70. The wafer process information collecting unit 50 includes a data acquiring unit 51, a feedback unit 52, and a wafer process DB (Data Base) 55.

[0033] The data acquisition unit 51 acquires a large amount of data for each wafer in the wafer process as wafer process information. The data acquired by the data acquisition unit 51 is stored in the wafer process DB 55.

[0034] The feedback unit 52 outputs the data (wafer process information) read from the wafer process DB 55 to the design process learning unit .

[0035] The packaging process information collecting unit 60 accumulates packaging process information acquired each time a chip cut out from a wafer manufactured in the packaging process is packaged, and outputs the packaging process information to the design process learning unit 70. This packaging process information collecting unit 60 includes a data acquiring unit 61, a feedback unit 62, and a packaging process DB 65.

[0036] The data acquisition unit 61 acquires a large amount of data measured for each packaged product in the packaging process as packaging process information. The data acquired by the data acquisition unit 61 is stored in the packaging process DB 65.

[0037] The feedback unit 62 outputs the data (packaging process information) read from the packaging process DB 65 to the design process learning unit .

[0038] The design process learning unit 70 has a design AI model 72 that obtains first design support information for supporting the design of the wafer process based on the wafer process information, and obtains second design support information for supporting the design of the packaging process based on the packaging process information. The design process learning unit 70 includes a design DB 71 and a design learning unit 73.

[0039] The design DB 71 accumulates wafer process information provided from the wafer process information collection unit 50, and accumulates packaging process information provided from the packaging process information collection unit 60. The design DB 71 also stores a design AI model 72 used in the design process. The design AI model 72 has a function of supporting various designs in the design process. For this reason, the design AI model 72 provides the functions of the generation unit 21, optimization unit 22, and guidance and management unit 23 to the design unit 2.

[0040] Depending on the application of DMCO, unsupervised, supervised, or reinforcement learning is used as the machine learning in the design AI model 72. For example, the optimization unit 22 and the guidance and management unit 23 described below use reward-based machine learning to determine which wiring and design policy is more preferable, so reinforcement learning is likely to be used. For example, when the optimization unit 22 obtains a correlation between manufacturing data and electrical characteristics, supervised learning is used, in which the electrical characteristics are used as the correct answer for the output result. When the optimization unit 22 automatically classifies defect data, unsupervised learning is used. The machine learning selection is not limited to these.

[0041] The design learning unit 73 performs machine learning or the like based on the wafer process information and packaging process information stored in the design DB 25 to update the design AI model 72. The updated design AI model 72 is stored in the design DB 71.

[0042] The isolating unit 75 sets the separation range of the process between the designer who is the customer and the person who manufactures the wafer based on the design (for example, the manufacturer who is the applicant). The isolating unit 75 can arbitrarily set the separation range between the designer and the applicant and separate them. In this embodiment, a plurality of processes included in the design process are separated, and the design unit 2 assists the customer's designer in designing according to the separation range. The separation range is shown in FIG. 5, which will be described later.

[0043] The design unit 2 has a generation unit 21 (Generator), an optimization unit 22 (Optimizer), and a guidance and management unit 23 (Navigator / Manager) as functions provided by the design AI model 72.

[0044] The generation unit 21 has a function of generating code required for design based on specifications written in a natural language. The optimization unit 22 performs a process of searching for an optimal solution of a combination of design parameters under various predetermined constraints. For example, the optimization unit 22 searches for an optimal solution of a combination by reducing a leakage current while maintaining a clock frequency. When the optimization unit 22 obtains an optimal solution, it outputs the information about the optimal solution to the guidance and management unit 23.

[0045] The guidance and management unit 23 provides at least one of the first design support information and the second design support information based on the combination optimum solution to guide the designer in the design and manages the design by the designer. For example, the guidance and management unit 23 has a function of navigating the designer to speed up the PPA convergence of the current design based on past design experience. PPA will be described later with reference to FIG. 7.

[0046] Among the functions of the guidance and management unit 23, guidance is a function related to the entire design flow. In order to proceed with the various steps included in the design process, the designer is guided in light of past experience to avoid repetitive steps. Among the functions of the guidance and management unit 23, management is a function that plans and manages the design itself. For example, when designing a chip with certain specifications, the guidance and management unit 23 plans what blocks the SOC should be divided into so that the design can proceed without bottlenecks.

[0047] 5 is a flow chart showing an example of an AI-aided design solution. The AI-aided design solution is provided to a customer by a design AI model 72 running on the design unit 2.

[0048] In semiconductor design, the semiconductor requirements are first formulated (Requirement specification formulation). Then, development planning is formulated and the system-level design is carried out (System-level design). After the system-level design is completed, front-end design (F / E Design) and back-end design (B / E Design) are carried out.

[0049] Front-end design includes everything from algorithm design to logic verification. In front-end design, after the designer designs an algorithm, the algorithm is rewritten as a program in C language, for example. Then, high-level synthesis is performed to automatically generate a hardware description language using the behavioral description in C language as input. In addition, after the designer designs the system level, RTL (Resister Transfer Level) design is performed to realize logic circuits, etc., using a hardware description language. After RTL design or high-level synthesis, function verification is performed, logic synthesis is performed, and then logic verification is performed. After logic verification, the process returns to system-level design or proceeds to the next back-end design.

[0050] In the back-end design, floor planning is performed based on the results of logic verification in the front-end design and the results of test circuit insertion. After floor planning, floor layout is designed. After placement and wiring, physical verification and lithography verification are performed.

[0051] After the placement and wiring, static timing analysis and power rail analysis are performed. Power rail analysis also includes signal integrity. After the placement and wiring, power consumption analysis is performed. After the above-mentioned test circuit insertion, test pattern generation is performed, and after the placement and wiring, gate simulation is performed. These are the contents of each design included in the back-end design.

[0052] Back-end design includes placement and routing, timing, and physical verification including power analysis. After back-end design, the wafer process and packaging process shown in Figure 1 are carried out. That is, after power supply analysis, samples produced in the wafer process and packaging process are shipped (sample shipment), and the operation of the samples is verified. If the sample operation is satisfactory, mass-production products produced in the wafer process and packaging process are shipped (mass-production shipment).

[0053] The AI-aided design solution shown in FIG. 5 is composed of three elements (the generation unit 21, the optimization unit 22, and the guidance and management unit 23) that the design AI model 72 shown in FIG.

[0054] The generation unit 21 includes, for example, system level design, algorithm design, program description, and RTL design in the front-end design, as shown in the area surrounded by the dashed line in the upper part of Fig. 5. The generation unit 21 automatically generates code by a program, etc.

[0055] 5, the optimization unit 22 includes, for example, floor planning, placement and wiring, physical verification, lithography verification, static timing analysis, power supply analysis, power consumption analysis, test circuit insertion, test pattern generation, and gate simulation in back-end design. The optimization unit 22 determines optimal conditions for various processes, and encourages the designer to design under optimal conditions.

[0056] The guidance and management unit 23 can optimize the hierarchical design to achieve a short TAT (Turn Around Time) design according to this embodiment. TAT means the time it takes from the start to the completion of a process. In some cases, the TAT is a long period from the start of semiconductor design to the completion of manufacturing, and in other cases, the TAT is the period from the start of design to the completion of design in the design process as in this embodiment.

[0057] As shown as (1) to (3) on the right side of Fig. 5 and as already explained, the applicant and the customer can arbitrarily divide the scope of responsibility. The division of the scope of responsibility is determined by the design capability and business model of the customer, and the division unit 75 shown in Fig. 4 manages the divided scope of responsibility. For example, in the division shown in Figure 5 (1), the customer, who wants to fully utilize the applicant's manufacturing technology, is responsible for the entire design, including development planning, front-end design, and back-end design, and the applicant is responsible for manufacturing and shipping sample products or shipping mass-produced products.

[0058] In the division shown in Figure 5 (2), the customer is responsible for everything from development planning to front-end design, and the applicant performs back-end design and manufactures and ships sample products or mass-produced products. In such a case, the customer wants to entrust the applicant with design corresponding to manufacturing technology, that is, back-end design, which is a heavy burden. In the division shown in FIG. 5(3), a customer who has little design experience but wants to create a product using semiconductors is responsible for up to system level design, and the applicant is responsible for all subsequent processes.

[0059] Traditionally, various vendors have provided various design tools for each block shown in Figure 5. In recent years, the complexity of design rules and constraints has increased with miniaturization, making designs more advanced, and it has become increasingly difficult for designers to master the design tools required for design. In addition, in front-end design, there has been a tendency to pack circuits capable of implementing various functions into a single semiconductor device so that designers can obtain as many functions as possible. On the other hand, back-end design involves physical design. For this reason, back-end designers pack as many cells as possible into a small area of ​​the wafer and design how to wire them together. As a result, back-end designers often end up spending more time on designing to realize the functions designed in the front-end.

[0060] On the other hand, the system level design, algorithm design, and rewriting in C language shown in Fig. 5 may be an automatic generation process in which the design AI model 72 automatically generates machine code by analyzing specifications written in natural language. Also, the design AI model 72 can encompass each process in the back-end design, take into account various constraints, and automatically perform optimization processing to find the optimal combination of parameters.

[0061] Furthermore, the design AI model 72 can judge the quality of a design by learning various designs or patterns performed in the past. For this reason, the design AI model 72 has a support function of, for example, proposing to the designer an optimal combination of design tools so that the designer can create an optimal design.

[0062] According to the AI-aided design solution shown in Fig. 5, the cycle time can be halved compared to conventional design methods. Furthermore, in the AI-aided design solution according to this embodiment, the navigator can replicate the capabilities of an expert designer. This allows even an unskilled designer to design semiconductors in the same way as an expert designer. In conventional design methods, there were many reworks (ECO: Engineering Change Order) at the final stage of the design, which prolonged the design process. On the other hand, by using the AI-assisted design solution according to the present embodiment, the number of reworks can be significantly reduced, and the TAT can be further shortened.

[0063] <Differences in data obtained between batch and single-wafer systems> Next, the differences between the data obtained by the conventional manufacturing process and the manufacturing process according to the present embodiment, and the results derived from the data, will be described with reference to FIGS.

[0064] Figure 6 is a diagram showing the difference in data obtained between the batch method and the single-wafer method through experiments. The horizontal axis of Figure 6 represents the number of parameters that can be obtained during semiconductor production, and the vertical axis represents the experimental time. The parameters shown on the horizontal axis are values ​​obtained by varying certain process conditions (e.g., temperature, pressure, flow rate, plasma power, etc.) (for example, 850°C, 900°C, 950°C, etc. for temperature). The experimental time on the vertical axis is the time it takes to obtain a semiconductor manufactured under certain process conditions.

[0065] In a batch process, the same process is performed on a large number of wafers at the same time. The black dots in Figure 6 represent the data acquired for each process. A linear graph was created by connecting the four black dots, shown as "Batch" in Figure 6.

[0066] On the other hand, in the single-wafer method (shown as "single" in Figure 6), the data obtained during the manufacturing process for each wafer is represented by a large number of white dots. The difference between the data obtained by the single-wafer processing and the data obtained by the batch processing can be seen from Figure 6. That is, in the batch processing in Figure 6, because the processing time is long, the data obtained in the same experimental time as the single-wafer processing is, for example, only four pieces of data (black dots), which are arranged in an approximately linear fashion, whereas in the single-wafer processing (single), multiple pieces of data can be obtained in the same experimental time, resulting in a nonlinear change.

[0067] FIG. 7 is a diagram showing the contents of data obtained by the batch type and the single-wafer type. The upper diagram (1) in Figure 7 shows a graph of PPA (performance power area). The PPA graph shows the density distribution function of a certain characteristic parameter. The horizontal axis of the graph shows characteristic variation. For example, the threshold voltage of a transistor has characteristic variation due to manufacturing variations. If the characteristic variation is high, the response will be slow, and if the characteristic variation is low, the response will be fast.

[0068] The PPA is designed using various parameters of the PDK. The PPA is expressed as a function with multiple types of σ as variables, as shown in the following equation (1). PPA = f(···, σ,···) …(1)

[0069] Here, σ represents the variance of the most important design parameter. Design parameters are parameters that designers set when designing a semiconductor. For example, σ is formed from values ​​that are directly linked to physical manufacturing, such as the alignment accuracy of the equipment, gas flow rate, and furnace temperature. Ultimately, the PPA of a chip is a function of the manufacturing parameters. Manufacturing parameters are parameters that are set in the manufacturing equipment when semiconductors are manufactured. This σ is expressed as a function with multiple manufacturing parameters m as variables, as shown in the following equation (2). σ = g(m 1 , m 2 , ) …(2)

[0070] Typically, designers select the manufacturing parameters m 1 , m 2 Since various designs are based on data called σ that incorporates , ..., designers do not need to worry about physical information. Also, since the complex process of semiconductor manufacturing is expressed by σ, designers do not need to know how semiconductors are manufactured.

[0071] The graphs shown in Figure 6 are reproduced at the bottom of Figure 7. Graph (2) in Figure 7 shows data obtained with the batch system, and graph (3) in Figure 7 shows data obtained with the single, or sheet-fed system.

[0072] As mentioned above, σ is a value determined by the correlation of manufacturing parameters. Designers want to minimize the variation of design parameters, and the sooner the variation is reduced, the better. The smaller the value of σ, the better. However, in the data obtained by the batch method, there are only a few m values, as shown by the black dots in Figure 7. i A linear graph is drawn due to the correlation of the parameters. Therefore, even if a designer fits with the smallest σ, it is unclear whether this σ is the minimum value. Also, if the minimum value of σ swings left or right, the amount of change in σ becomes large, which makes semiconductor manufacturing unstable.

[0073] On the other hand, in the single-fed system, many m i A nonlinear graph is drawn based on the correlation of the parameters. In this graph, the minimum value of σ becomes clear, so that the optimal solution can be easily found. Therefore, the optimization unit 22 shown in FIG. 4 can find the minimum value of a function with multiple manufacturing parameters as variables as the optimal solution for each of the wafer process information and packaging process information, and the guidance and management unit 23 can guide the designer to the optimal solution.

[0074] The error shown in graph (3) is the value that was determined to be the minimum value of σ in graph (2) which shows the data obtained by the batch method. In reality, it is not the minimum value of σ, but the slope of the graph is large. Therefore, a slight m i The change in σ tends to be large due to the fluctuation of m. On the other hand, the point shown as the optimal solution in graph (3) has a small slope, so if this point is the minimum value of m i Even if changes, σ is less likely to change.

[0075] As mentioned above, if a designer fits at an incorrect position without being aware of the optimal value of σ, the quality of the manufactured semiconductors will vary, and many semiconductors will be produced that do not pass inspection in the later process. In semiconductor design, it is important for the design how early the minimum value of σ can be found in advance, so it can be said that there is a much greater advantage to finding the minimum value of σ by adopting the single-wafer method rather than the batch method.

[0076] In addition, designers can accelerate the verification of PDK by combining silicon big data with TCAD (Technology CAD) models. For example, first, designers predict the correlation between manufacturing parameters and design parameters using TCAD. Next, the designers can verify the correlation between manufacturing parameters and design parameters using silicon big data through MFD, where silicon big data obtained in the full-wafer process is analyzed by the design AI model 72.

[0077] FIG. 8 is a diagram showing the difference between the TAT in the conventional manufacturing method and the TAT in the manufacturing method according to the present embodiment. In the conventional manufacturing method shown in the upper part of Fig. 8, the front-end line is executed first, then the back-end line is executed, and the manufacturing of the semiconductor is completed. In this way, the time from the start to the completion of the manufacturing of the semiconductor is called the conventional TAT.

[0078] In the manufacturing method according to this embodiment shown in the lower part of Fig. 8, the front-end line and the back-end line are started at the same time, and semiconductors are manufactured in parallel. That is, after both the front-end line and the back-end line are completed, the wafers produced in the front-end line and the wafers produced in the back-end line are bonded together, and the manufacturing of the semiconductor is completed.

[0079] This manufacturing method for bonding wafers together is called wafer bonding. In this way, the manufacturing method according to the present embodiment can shorten the TAT significantly compared to conventional manufacturing methods. Reducing the TAT in the manufacturing method according to the present embodiment is called "reducing TAT."

[0080] 9 is a diagram for explaining a manufacturing method using an all-single-wafer apparatus (not shown) according to this embodiment. The all-single-wafer apparatus is an apparatus used in the wafer process and the packaging process.

[0081] The lower left of Fig. 9 shows a graph showing the difference in data obtained by the batch type and the single-wafer type shown in Fig. 6. In the all-single-wafer processing apparatus according to this embodiment, integrated production is performed for each wafer. In this integrated production, the amount of silicon data obtained from the all-single-wafer processing apparatus is, for example, approximately 100 times the amount of conventional data. For this reason, the silicon data obtained from the all-single-wafer processing apparatus is called silicon big data.

[0082] Silicon big data is data acquired by advanced measuring devices and sensors mounted on each device. After useful data is extracted from the silicon big data, it is analyzed by the design AI model 72. In addition, packaging big data is data acquired by advanced measuring devices and sensors installed in each device installed in the packaging process.

[0083] The design AI model 72 evaluates highly accurate correlation and characteristics by combining various types of data contained in silicon big data, enabling highly accurate correlation and characterization. In this embodiment, the series of processes in which data is passed from the manufacturing domain to the design domain and trends, optimal values, etc. obtained from the data acquired in the manufacturing domain are utilized in the design domain is called MFD.

[0084] Silicon big data includes, for example, TEG (Test Element Group) data, sample data, and MP (Mass Production) data. The TEG data, sample data, and MP data each include design data, electrical property test data, and manufacturing data (measurement length, film thickness, defect information, etc.).

[0085] TEG data is data obtained using a foundry's process verification mask that includes a TEG. TEG data is data obtained from device and process technology, such as SPICE models and design rules. TEG data is used for device and process technology in the design domain.

[0086] The sample data is data obtained by using a mask for operation verification based on a customer's design. The sample data is data obtained in a design environment, such as data on a PDK and standard cells. The MP data is data obtained using a mask for mass production products, and is used in the design process for rapid design convergence.

[0087] SPICE models and design rules in device and process technologies, PDKs and standard cells in the design environment, and high-level design convergence in the design process are all related to each other and affect each other.

[0088] A comparison example of a PDK without MFD and a PDK with MFD is shown on the right side of Figure 9. The PDK without MFD is for designing using conventional silicon data, and the processing window for the PDK without MFD is shown. Conventional silicon data has a small processing window size, making it difficult to analyze data accurately, whereas a PDK with an MFD can obtain abundant silicon data (silicon big data), increasing the processing window size. Therefore, the PDK according to this embodiment improves the accuracy of data analysis.

[0089] Furthermore, with regard to the variation (margin) considered in the design, in a PDK without an MFD, the variation is small and the design is limited, so redesign occurs many times and the design convergence is slow. On the other hand, in the PDK with an MFD according to this embodiment, the variation is large and the degree of freedom in the design is improved. Therefore, with a PDK with an MFD, redesign is not required and the design convergence is extremely fast.

[0090] Fig. 10 is a diagram showing an example of the operation of the guidance and management unit 23 described in Fig. 5. Here, an example of the operation of the guidance and management unit 23 in the chip design process will be described. The guidance and management unit 23 detects a bottleneck design block from multiple design blocks into which the entire design is divided. The guidance and management unit 23 then changes the bottleneck design block to equalize the time required to complete multiple design blocks designed in parallel, and guides the designer to the changed multiple design blocks. An example of the operation of the guidance and management unit 23 will be described with reference to operations (1) to (4) shown in Fig. 10.

[0091] In operation (1), the guidance and management unit 23 performs optimal design division for fast design convergence. For example, the guidance and management unit 23 divides the whole design into a number of individual design blocks HLB1 to HLBn.

[0092] In operation (2), the guidance and management unit 23 detects a bottleneck in each divided design block early and finds a solution to eliminate the bottleneck. For example, as shown by the dashed-dotted circle in Fig. 10, the guidance and management unit 23 detects the design block HLB3 as a bottleneck. In this case, the guidance and management unit 23 redesigns the design block so that the bottleneck can be eliminated. At this time, the shape of each design block is changed, the netlist is updated, and so on.

[0093] In operation (3), the guide and management unit 23 applies the design change. At this time, the guide and management unit 23 makes a best plan for the design change. For example, the guide and management unit 23 changes the size and shape of the design block. In addition, the guide and management unit 23 performs rework (ECO) on the design block HLB2 that does not have a large impact on the manufacturing schedule. Furthermore, the guidance and management unit 23 performs rearrangement and wiring (re-PnR) of the design block HLB4. As a result, the manufacturing time of the block HLB3 detected as the bottleneck is shortened, and the manufacturing time of each of the design blocks HLB1 to HLBn is no longer affected by the bottleneck, so that the design time for the entire design blocks HLB1 to HLBn is shortened.

[0094] In operation (4), the guide and management unit 23 verifies the full chip. The full chip refers to a combination of the design blocks HLB1 to HLBn whose bottlenecks have been eliminated in operation (3). If the verification result in operation (4) is good, the design information is taped out and shared with the front-end and back-end processes.

[0095] FIG. 11 is a diagram showing an example of heterogeneous integration (hetero) design using chiplets. FIG. 11 shows a chiplet library 80 and a configuration example of a chiplet. The chiplet library 80 is constructed in, for example, the design DB 71 shown in FIG. 4. For this reason, the design process learning unit 70 has the chiplet library 80 that accumulates information on the chiplets. In the packaging process according to this embodiment, a chiplet platform consisting of a plurality of circuit elements (IPs) is used.

[0096] The left side of Fig. 11 shows IP groups including specialized IPs and AI accelerators that provide features of the customer's product. The IPs that the customer selects for their own design are called domain-specific IP groups 81. The individual IPs included in the domain-specific IP group 81 are shown in Fig. 11 as "IP Core1", "IP Core2", etc.

[0097] The IPs included in the domain-specific IP group 81 do not function as products by themselves, so they require a CPU for a controller, a memory interface, etc. The CPU for a controller, the memory interface, etc. are general-purpose IPs that are common and can be shared, so they are called platform IPs 82 as a platform-like IP group. The platform IPs 82 are used as the platform for chiplets.

[0098] The chiplet library 80 is a library that accumulates existing chiplets that can be combined according to the customer's application. The chiplet library 80 accumulates various IPs included in a domain-specific IP group 81, a foundation IP group 82, etc. A customer can select any chiplet from the chiplet library 80.

[0099] A customer can design his / her own chiplet, even if the chiplet is not stored in the chiplet library 80, to differentiate his / her chiplet from other companies' chiplets. By using a chiplet selected from the chiplet library 80, the customer can determine the system on chip (SoC) configuration specific to the customer at an early stage. This allows the customer to mount the custom chiplet he / she designed on a semiconductor substrate.

[0100] For example, the board 85 shown on the right side of Fig. 11 is an example in which domain-specific IPs 81a and 81b obtained from the chiplet library 80 and a board IP 82a are mounted. Also, the board 86 is an example in which a domain-specific IP 81b obtained from the chiplet library 80, a domain-specific IP 81c newly created by a customer, and a board IP 82a are mounted. In this way, the boards 85 and 86 are mounted with a common board IP 82a, while the board 85 is mounted with a combination of existing chiplets. Also, the board 86 is mounted with a combination of existing chiplets and new chiplets.

[0101] Information on the chiplets mounted on the substrates 85 and 86 is stored in the chiplet library 80, and is also fed back to the packaging design process as shown by the arrow at the bottom of FIG. 11 (MFD). Therefore, the design unit 2 can inform the designer of the optimal combination of chiplets and support the design of the chiplets. For example, the guidance and management unit 23 guides the combination of a board-type circuit element (board IP group 82) and a specialized circuit element (domain-specific IP group 81) based on the combination information of the chiplets stored in the chiplet library 80. Therefore, whereas it took a long time to determine the circuit elements by trial and error in the past, in this embodiment, the combination of the circuit elements guided by the guidance and management unit 23 is determined quickly.

[0102] Figure 12 shows three examples of processes that can shorten the TAT of the packaging process. In Figure 12, the interposer is an inorganic material such as silicon that has been wired using semiconductor front-end process technology. Multiple chips are connected by mounting them on the interposer.

[0103] In the packaging process according to the present embodiment, technologies such as LDI (Laser Direct Imager) exposure (maskless exposure technology), chip size standardization, and parallel integration are used, as shown in Fig. 12. As the maskless exposure technology, for example, there is a maskless direct drawing technology that directly draws a circuit by irradiating a laser. In addition, for example, a unique two-dimensional or three-dimensional packaging technology is used for the chip size standardization and parallel integration.

[0104] The two-dimensional packaging technology is a technology for arranging multiple chips on a plane, while the three-dimensional packaging technology is a technology for arranging multiple chips not only on a plane but also in the height direction. In addition, useful information is extracted from various information obtained from the packaging process, sent to the design process, and used for learning (MFD). The optimization unit 22 optimizes the maskless direct writing of the interposer in the packaging process, the standardization of the chip size of the interposer, and the mounting of at least one chip on the interposer and the manufacture of the package substrate. The guidance and management unit 23 provides design support by guiding the optimized information to the designer. This makes it easier for the designer to design a semiconductor based on the optimized information.

[0105] The explanatory diagram (1) in Figure 12 shows an example of a maskless exposure technology for forming a circuit pattern on a substrate. The left side of the explanatory diagram (1) shows an example of conventional stepper exposure. In stepper exposure, a wiring pattern 92 is formed on the upper surface of an interposer 91 using a photomask 93. The wiring pattern 92 formed by the photomask 93 is the same everywhere.

[0106] An example of LDI exposure according to this embodiment is shown on the right side of the explanatory diagram (1). LDI exposure is one of the maskless exposure techniques in which a laser beam 95 is irradiated onto the upper surface of an interposer 91, and a wiring pattern is drawn by direct drawing. The laser beam 95 is irradiated onto the interposer 91 based on three-dimensional CAD data designed by the design department 2 (see FIG. 3). The laser beam 95 can change the wiring pattern 94 for each section of the interposer 91.

[0107] 12(2) shows an example of standardizing the chip size of the interposer 91. The chip size of the interposer 91 is standardized to a size of, for example, a mm×b mm. In this embodiment, by standardizing the chip size, it is not necessary to create interposers 91 of various sizes, and therefore the settings of the transport mechanism for the interposer 91 can be unified.

[0108] Diagram (3) in FIG. 12 shows an example of parallel integration of packaging devices. In wafer manufacturing in diagram (3), for example, the manner in which three wafers are manufactured is shown. In interposer manufacturing in diagram (3), defective points 96, where defects have occurred in part of the wiring pattern formed on interposer 91, are indicated by crosses. In conventional interposer manufacturing shown on the left side of interposer manufacturing, defective points 96 are left as they are. On the other hand, in interposer manufacturing according to the present embodiment, multiple chips determined to be non-defective in wafer manufacturing are mounted in good points 97 that avoid defective points 96.

[0109] In package substrate manufacturing in the explanatory diagram (3), a package substrate 98 is manufactured. The package substrate 98 is usually a substrate made of an organic material, on which wiring is performed using semiconductor post-processing technology. At least one chip integrated in the interposer 91 is mounted on the package substrate 98 and packaged. In the conventional package substrate manufacturing shown on the left side of the explanatory diagram (3) in Fig. 12, no association is found between the interposer manufactured in the interposer manufacturing process and the defective portion. On the other hand, in the package substrate manufacturing process according to the present embodiment, a good portion 97 in an interposer 91 manufactured in the interposer manufacturing process is mounted directly on a package substrate 98.

[0110] FIG. 13 is a diagram showing an example of change in TAT in the packaging process. An example of homogeneous integration is shown in the upper part of Figure 13. In homogeneous integration, all the functions are integrated on one silicon chip, so the TAT is longer. An example of heterogeneous integration is shown in the bottom of Figure 13. In heterogeneous integration, chiplets with separate functions are fabricated in parallel and then integrated in an assembly step.

[0111] As shown in FIG. 13, for example, a CPU (x nm), memory (y nm), and I / O (z nm) are manufactured in parallel. The processing performed according to the CPU (x nm), which has the longest manufacturing time, is called the wafer MFG step. The manufacturing of the interposer also starts at the same time that the various parts to be integrated are manufactured. The manufacturing process of the interposer is called the interposer MFG step. (1) Exposure processing and (2) Standardization of chip size, which are performed in the interposer MFG step and are explained in FIG. 12, contribute to shortening the processing time of the interposer MFG step. The processing time of the interposer MFG step is shorter than that of the wafer MFG step.

[0112] After the wafer MFG step, the integration step is performed. In the integration step, each chip is integrated in parallel on the interposer. As a result, in the packaging process, the parallel integration (3) explained in FIG. 12 contributes to shortening the processing time of the integration step. Therefore, the TAT for heterogeneous integration is shorter than that for homogeneous integration.

[0113] In the design support system 10 according to the embodiment described above, the supervisory device 1 acquires wafer process information from the wafer process section 3, and acquires packaging process information from the packaging section 4. The design AI model 72 of the supervisory device 1 analyzes the wafer process information and packaging process information, and provides the information obtained by determining the optimal conditions of parameters in each process, etc., to the design section 2 as design support information. The design section 2 provides the designer with design support information suitable for semiconductor design, and supports the design of each process in semiconductor manufacturing. The designer can spend less time on trial and error in the design process, thereby shortening the time required for design.

[0114] The generation unit 21 of the design unit 2 shown in Fig. 4 has a function to generate the code required for design from specifications written in natural language, so the designer can concentrate on writing the specifications in natural language. Therefore, compared to the conventional case where the designer analyzes the specifications and generates the code by himself, it is possible to automatically obtain code that appropriately reflects the specifications.

[0115] The optimization unit 22 of the design unit 2 optimizes each process included in the wafer process and the packaging process based on the design support information received from the supervisory device 1. The design AI model 72 according to this embodiment calculates the correlation and tendency of various manufacturing parameters based on the huge amount of silicon big data obtained in the single-wafer process, thereby finding an optimal solution. By optimizing the wafer process and packaging process designed by the design department 2, unnecessary processes and duplicated processes during the actual manufacturing of semiconductors are eliminated. This eliminates the need for designers to redesign semiconductors and processes, and shortens the TAT until design completion.

[0116] In addition, the guidance and management unit 23 of the design unit 2 navigates the designer to speed up the PPA convergence of the current design based on past design experience. This allows the designer to seek an optimal solution that minimizes the variation in design parameters, and speed up the design of a good semiconductor.

[0117] In addition, in the chip design process shown in Fig. 10, divided design blocks that can become bottlenecks are detected at an early stage. The bottlenecks are then eliminated by changing the shape of the design blocks, etc. This equalizes the manufacturing time of the divided design blocks, and the time until they are manufactured as a full chip is significantly shorter than the conventional manufacturing time.

[0118] 11 stores a domain-specific IP group 81 and a base IP group 82. A designer can select any chip from the chiplet library 80 and combine at least one chip on a board to create a design. This increases the design freedom of the chiplet.

[0119] 12 and 13, in the packaging process, the interposer is irradiated with a laser beam to directly draw a wiring pattern, the chip size of the interposer is standardized, and parallel integration is performed. Therefore, in the packaging process, the TAT for the heterogeneous integration according to the present embodiment can be shortened compared to the TAT for the conventional homogeneous integration.

[0120] In addition, various manufacturing equipment in the wafer process section 3 and the packaging section 4 may be arranged in a virtual space, and a simulation of the manufacturing equipment in the virtual space may be performed based on the above-mentioned silicon big data. In this simulation, the supervisory device 1 may again acquire information obtained from the manufacturing equipment in the virtual space that operates based on various information designed by the design AI model 72 of the supervisory device 1, and information on virtual wafers, etc. By repeating the simulation, it becomes possible to identify areas where defects are predicted and extract bottleneck processes before the actual wafer manufacturing, and the design accuracy by the design section 2 can be further improved.

[0121] The present invention is not limited to the above-described embodiment, and it goes without saying that various other applications and modifications are possible without departing from the gist of the present invention as set forth in the claims. For example, the above-mentioned embodiment describes the system configuration in detail and specifically in order to explain the present invention in an easily understandable manner, and is not necessarily limited to a system having all of the described configurations. In addition, it is also possible to add, delete, or replace part of the configuration of the present embodiment with other configurations. In addition, the control lines and information lines shown are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are connected to each other. [Explanation of symbols]

[0122] 1...control device, 2...design department, 3...wafer process department, 4...packaging department, 10...design support system, 21...generation department, 22...optimization department, 23...guidance and management department, 50...wafer process information collection department, 60...packaging process information collection department, 71...isolating department, 80...chiplet library, 81...domain-specific IP group, 82...base IP group, 91...interposer

Claims

1. a design department that designs a wafer process for manufacturing a wafer and a packaging process for manufacturing a package from the wafer; A wafer process section that manages the wafer process; a packaging unit that manages the packaging process for the wafers manufactured by the wafer process unit; a control device that acquires wafer process information measured in the wafer process from the wafer process section, acquires packaging process information measured in the packaging process from the packaging section, and provides design support information obtained based on the wafer process information and the packaging process information to the design section. Design support system.

2. The control device includes: a wafer process information collecting unit that accumulates the wafer process information acquired for each of the wafers manufactured in the wafer process; a packaging process information collecting unit that accumulates the packaging process information acquired each time a chip cut from the wafer manufactured in the packaging process is packaged; and a design process learning unit having a design AI model that obtains first design support information for supporting the design of the wafer process based on the wafer process information output from the wafer process information collection unit, and obtains second design support information for supporting the design of the packaging process based on the packaging process information output from the packaging process information collection unit. The design support system according to claim 1 .

3. The design AI model is a generator that generates code required for design based on specifications written in natural language; an optimization unit that searches for an optimal combination of design parameters under predetermined constraints; a guidance and management unit that provides at least one of the first design support information and the second design support information based on the combination optimum solution to guide a design and manages the design, The design department is provided with the functions of the design AI model The design support system according to claim 2 .

4. the optimization unit determines, for each of the wafer process information and the packaging process information, a local minimum value of a function having a plurality of manufacturing parameters as variables as the optimal solution; The guidance and management unit guides the optimal solution. The design support system according to claim 3.

5. The guidance and management unit detects a design block that is a bottleneck from among a plurality of design blocks into which an entire design is divided, changes the design block that is the bottleneck, equalizes the time required for the completion of the plurality of design blocks that are designed in parallel, and guides the changed plurality of design blocks. The design support system according to claim 4.

6. The design process learning unit has a chiplet library that accumulates information about chiplets, The guidance and management unit provides guidance on combinations of platform-type circuit elements and specialized-type circuit elements based on combination information of the chiplets stored in the chiplet library. The design support system according to claim 4.

7. The optimization unit optimizes a maskless direct drawing of an interposer in the packaging process, a standardization of a chip size of the interposer, and a mounting of a chip on the interposer and a manufacturing of a package substrate; The guidance and management unit guides the user to optimized information. The design support system according to claim 6.

8. Obtaining wafer process information measured in a wafer process from a wafer process section that manages a wafer process for manufacturing wafers, and obtaining packaging process information measured in a packaging process from a packaging section that manages the packaging process for the wafers manufactured by the wafer process section, and providing design support information obtained based on the wafer process information and the packaging process information to a design section that designs the wafer process and the packaging process. Control device.

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