Semiconductor integrated circuit

Abstract

To suppress an output transistor from being turned on unintentionally.SOLUTION: A first resistor R1 is connected between a gate and a source of an output transistor 110 which is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A control circuit 120 has an output stage 122 including a second N-type region N2, and controls a gate voltage of the output transistor 110. A forced-off circuit 130 includes a third N-type region N3 forming a second parasitic transistor Qp2 together with a first N-type region N1 and is configured so that a first transistor M1 is turned on when a parasitic current flows through the second parasitic transistor Qp2.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to semiconductor integrated circuits.

Background Art

[0002] In various electronic circuits and electronic devices, a linear regulator is used to generate a voltage that maintains a constant voltage level regardless of the power supply voltage (input voltage). The linear regulator receives a DC input voltage at the input node and generates a stabilized output voltage at the output node at a predetermined target level.

[0003] The linear regulator includes an output transistor connected between the input node and the output node, and a feedback circuit that supplies a signal corresponding to the error between the output voltage and the reference voltage to the gate of the output transistor.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] As a result of studying the linear regulator, the present inventor recognized the following problems.

[0006] When the feedback circuit is in the disabled state, it is necessary to surely turn off the output transistor. For this purpose, a configuration in which a resistor is inserted between the gate and source of the output transistor, that is, between the gate of the output transistor and the input node, was considered. In this configuration, when the output of the feedback circuit becomes high impedance, the gate of the output transistor is pulled up by the resistor, and the output transistor is turned off.

[0007] However, when the substrate potential becomes a negative voltage due to noise generated inside or outside the semiconductor substrate on which the linear regulator is integrated, the bipolar transistor existing in the output stage of the feedback circuit conducts and sinks the parasitic current. When this parasitic current flows through the resistor added between the gate and source of the output transistor, a voltage drop occurs and the output transistor turns on.

[0008] A similar problem can occur not only in linear regulators but also in load switches, electronic fuses, and the like.

[0009] This disclosure has been made in such a situation, and an exemplary purpose of one of its aspects is to provide a semiconductor integrated circuit capable of suppressing unintentional turning on of an output transistor.

[0010] A semiconductor integrated circuit according to an aspect of the present disclosure includes an output transistor that is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a first N-type region where a negative potential is generated, a first resistor connected between the gate and source of the output transistor, a control circuit that controls the gate voltage of the output transistor, the control circuit being connected to the first resistor and including a second N-type region that forms a first parasitic transistor together with the first N-type region, a first transistor that is a P-channel MOSFET connected between the gate and source of the output transistor, and a third N-type region that forms a second parasitic transistor together with the first N-type region, and includes a forced-off circuit configured such that the first transistor turns on when a parasitic current flows through the second parasitic transistor.

[0011] Another aspect of the semiconductor integrated circuit of the present disclosure includes an output transistor that is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a first N-type region where a negative potential is generated, a first resistor connected between the gate and source of the output transistor, and a control circuit that controls the gate voltage of the output transistor. The control circuit is connected to the first resistor and includes a second N-type region that forms a first parasitic transistor together with the first N-type region. The control circuit further includes a third N-type region that forms a second parasitic transistor together with the first N-type region. The forced-off circuit is configured to supply a cancellation current to the gate of the output transistor when a parasitic current flows through the second parasitic transistor.

[0012] In addition, any combination of the above components, as well as components and expressions that are mutually substituted between methods, devices, systems, etc., are also effective as aspects of the present invention. Furthermore, the description of this item (means for solving the problem) does not explain all the essential features of the present invention. Therefore, sub-combinations of these described features can also be the present invention.

Brief Description of the Drawings

[0013]

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[0014] [Detailed Description] (Overview of the Embodiment) An overview of some exemplary embodiments of the present disclosure will be described. This overview is provided as a prelude to the detailed description that follows and is intended to provide a basic understanding of the embodiments by simplifying and explaining some concepts of one or more embodiments. It is not intended to limit the scope of the invention or the disclosure. This overview is not an exhaustive overview of all possible embodiments, nor is it intended to identify all important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, "an embodiment" may be used herein to refer to one embodiment (example or variation) or multiple embodiments (examples or variations) disclosed in this specification.

[0015] A semiconductor integrated circuit according to an embodiment includes an output transistor that is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a first N-type region where a negative potential is generated, a first resistor connected between the gate and source of the output transistor, a control circuit that controls the gate voltage of the output transistor, the control circuit being connected to the first resistor and including a second N-type region that forms a first parasitic transistor together with the first N-type region, a first transistor that is a P-channel MOSFET connected between the gate and source of the output transistor, and a third N-type region that forms a second parasitic transistor together with the first N-type region, and includes a forced-off circuit configured such that the first transistor turns on when a parasitic current flows through the second parasitic transistor.

[0016] When a negative voltage is generated in the first N-type region, a parasitic current flows through the first parasitic transistor. In this situation, a parasitic current also flows through the second parasitic transistor. When a parasitic current flows through the second parasitic transistor, the first transistor turns on, and the gate-source voltage of the output transistor decreases. This can prevent the output transistor from turning on.

[0017] In one embodiment, the third N-type region may be closer to the first N-type region than the second N-type region. In this case, the current amplification factor (hfe) of the second parasitic transistor including the third N-type region becomes larger than that of the first parasitic transistor including the second N-type region, and the driving ability of the forced-off circuit can be enhanced.

[0018] In one embodiment, the forced-off circuit may further include a second resistor connected between the gate and source of the first transistor, and the gate of the first transistor may be connected to the third N-type region.

[0019] The forced-off circuit includes a second transistor that is an N-channel MOSFET, and the third N-type region may be the drain of the second transistor. The forced-off circuit includes a second transistor that is an NPN bipolar transistor, and the third N-type region may be the collector of the second transistor. The forced-off circuit includes a PN junction diode, and the third N-type region may be the cathode of the PN junction diode.

[0020] In one embodiment, the forced-off circuit may further include a third transistor whose gates and sources are commonly connected to the first transistor, and whose gate-drain is connected and provided on the path of the parasitic current.

[0021] In one embodiment, the forced-off circuit includes a third resistor whose first end is connected to the source of the output transistor and whose second end is connected to the third N-type region, and an amplifier that controls the gate voltage of the first transistor according to the voltage drop of the third resistor.

[0022] A semiconductor integrated circuit according to an embodiment includes an output transistor that is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a first N-type region where a negative potential is generated, a first resistor connected between the gate and source of the output transistor, a control circuit that controls the gate voltage of the output transistor, the control circuit being connected to the first resistor and including a second N-type region that forms a first parasitic transistor together with the first N-type region, and a third N-type region that forms a second parasitic transistor together with the first N-type region, the forced-off circuit being configured to supply a canceling current to the gate of the output transistor when a parasitic current flows through the second parasitic transistor.

[0023] When a negative voltage is generated in the first N-type region, a parasitic current flows through the first parasitic transistor. In this situation, a parasitic current also flows through the second parasitic transistor. When a parasitic current flows through the second parasitic transistor, a canceling current is supplied to the gate of the output transistor. Since the parasitic current sunk by the control circuit is canceled by the canceling current generated by the forced-off circuit, the current flowing through the first resistor becomes smaller. Thereby, the voltage drop across the first resistor is reduced, and the output transistor can be prevented from turning on.

[0024] In one embodiment, the forced-off circuit further includes a first transistor that is a P-channel MOSFET connected between the gate and source of the output transistor, and a second resistor connected between the gate and source of the first transistor, and the gate of the first transistor may be connected to the third N-type region.

[0025] In one embodiment, the forced-off circuit may further include a first transistor that is a P-channel MOSFET connected between the gate and source of the output transistor, and a third transistor whose gates and sources are commonly connected to those of the first transistor, and whose gate-drain is connected and is provided on the path of the parasitic current.

[0026] In one embodiment, the forced-off circuit may include a first transistor which is a P-channel MOSFET connected between the gate and source of the output transistor, a third resistor having a first end connected to the source of the output transistor and a second end connected to the third N-type region, and an amplifier that controls the gate voltage of the first transistor according to the voltage drop across the third resistor.

[0027] In one embodiment, the control circuit may include an error amplifier that receives a feedback signal corresponding to the drain voltage of the output transistor at a first input node, receives a reference voltage at a second input node, and has an output connected to the gate of the output transistor.

[0028] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and repeated explanations are omitted as appropriate. Also, the embodiments are illustrative and not restrictive of the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0029] In this specification, the phrase "member A is in a state of being connected to member B" includes cases where member A and member B are physically directly connected, and cases where member A and member B are indirectly connected via other members that do not affect the electrical connection state or inhibit the function. Similarly, the phrase "member C is provided between member A and member B" includes cases where member A and member C, or member B and member C are directly connected, as well as cases where they are indirectly connected via other members that do not affect the electrical connection state or inhibit the function.

[0030] Also, "signal A (voltage, current) is responsive to signal B (voltage, current)" means that signal A has a correlation with signal B. Specifically, (i) when signal A is signal B, (ii) when signal A is proportional to signal B, (iii) when signal A is obtained by level-shifting signal B, (iv) when signal A is obtained by amplifying signal B, (v) when signal A is obtained by inverting signal B, (vi) or any combination thereof, etc. It is understood by those skilled in the art that the scope of "responsive to" is determined according to the types and uses of signals A and B.

[0031] The vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification are appropriately enlarged or reduced for ease of understanding, and each waveform shown is also simplified, exaggerated, or emphasized for ease of understanding.

[0032] FIG. 1 is a circuit diagram of a semiconductor integrated circuit 100 according to an embodiment. The semiconductor integrated circuit 100 receives an input voltage V IN at an input terminal (input pin) VIN and generates an output voltage V OUT at an output terminal (output pin) VOUT. The semiconductor integrated circuit 100 includes an input line 102, an output line 104, an output transistor 110, a first resistor R1, a control circuit 120, a forced-off circuit 130, and a first N-type region N1, and is integrally formed on a single semiconductor substrate. In this embodiment, the semiconductor integrated circuit 100 is integrated on a P-type semiconductor substrate.

[0033] The input line 102 is connected to the input terminal VIN, and the output line 104 is connected to the output terminal VOUT.

[0034] The output transistor 110 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), with its source connected to the input line 102 and its drain connected to the output line 104.

[0035] The first N-type region N1 is a node where a negative potential can be generated. For example, when the semiconductor integrated circuit 100 is a controller or a motor driver of a DC / DC converter, a negative potential is generated at the switching node connected to the inductor. A high-side transistor and a low-side transistor are connected to this switching node. In this case, the drain or collector of the low-side transistor becomes the first N-type region N1.

[0036] The control circuit 120 controls the output voltage V generated at the output terminal VOUT by controlling the gate voltage Vg of the output transistor 110. OUT to control.

[0037] The control circuit 120 includes a second N-type region N2 connected to the first resistor R1. This second N-type region N2 can be, for example, the drain (or collector) of an N-channel MOSFET (or NPN bipolar transistor) M11 that constitutes the output stage 122 of the control circuit 120. The form of the output stage 122 is not particularly limited, and an open-drain form or a push-pull form can be adopted.

[0038] The second N-type region N2 forms an NPN-type first parasitic transistor Qp1 together with the first N-type region N1 and the P-type substrate.

[0039] When the control circuit 120 is in a disabled state, that is, when the output of the output stage 122 is in a high-impedance state, a first resistor R1 is connected between the gate and source of the output transistor 110 to prevent the gate voltage Vg of the output transistor 110 from becoming indeterminate.

[0040] The forced-off circuit 130 includes a first transistor M1, a second transistor M2, and an intermediate circuit 132.

[0041] The first transistor M1 is a P-channel MOSFET and is connected between the gate and source of the output transistor 110. The second transistor M2 is an N-channel MOSFET including a third N-type region N3 in the drain, and the source is grounded. The second transistor M2 may be a bipolar transistor including a third N-type region N3 in the collector.

[0042] The third N-type region N3, together with the first N-type region N1 and the P-type substrate, forms an NPN-type second parasitic transistor Qp2.

[0043] The forced-off circuit 130 is configured such that the first transistor M1 turns on when a parasitic current I PARAS2 flows through the second parasitic transistor Qp2.

[0044] For example, the intermediate circuit 132 applies a voltage exceeding the threshold voltage V PARAS2 of the P-channel MOSFET between the gate and source of the first transistor M1 when a parasitic current I gs(th) flows through the second parasitic transistor Qp2.

[0045] The above is the configuration of the semiconductor integrated circuit 100. Before explaining the operation of the semiconductor integrated circuit 100, the comparative technology studied by the inventor and the problems arising therefrom will be explained.

[0046] FIG. 2 is a circuit diagram of a semiconductor integrated circuit 100R according to the comparative technology. The semiconductor integrated circuit 100R is obtained by omitting the forced-off circuit 130 from the semiconductor integrated circuit 100 of FIG. 1.

[0047] FIG. 3 is a simplified cross-sectional view of the semiconductor integrated circuit 100R of FIG. 2. The semiconductor integrated circuit 100R is formed on a P-type semiconductor substrate 300. As described above, the second N-type region N2, the P-type semiconductor substrate 300, and the first N-type region N1 of the control circuit 120 form an NPN-type parasitic transistor Qp1.

[0048] Now, assume that during the operation of the semiconductor integrated circuit 100R, a voltage lower than the substrate potential (0 V), that is, a negative voltage -V, is generated in the first N-type region N1. Then, the parasitic transistor Qp1 turns on, and a parasitic current I paras1 flows. This parasitic current I PARAS1 flows through the first resistor R1 in the circuit diagram of FIG. 2.

[0049] When the parasitic current I PARAS1 flows, a voltage drop R1×I PARAS1 is generated across the first resistor R1. This voltage drop is applied between the gate and source of the output transistor 110. When the voltage drop exceeds the threshold voltage V gs(th) of the output transistor 110, the output transistor 110 enters the conducting state, and an unintended output voltage V OUT is generated on the output line 104.

[0050] Next, the operation of the semiconductor integrated circuit 100 in FIG. 1 will be described.

[0051] FIG. 4 is a simplified cross-sectional view of the semiconductor integrated circuit 100 in FIG. 1. The semiconductor integrated circuit 100 is formed on a P-type semiconductor substrate 300, and N-type regions N1 to N3 are formed.

[0052] The second N-type region N2, the P-type semiconductor substrate 300, and the first N-type region N1 of the control circuit 120 form an NPN-type first parasitic transistor Qp1. Also, the third N-type region N3, the P-type semiconductor substrate 300, and the first N-type region N1 of the forced-off circuit 130 form an NPN-type second parasitic transistor Qp2.

[0053] When a voltage lower than the substrate potential, that is, a negative voltage -V, is generated in the first N-type region N1 during the operation of the semiconductor integrated circuit 100, the first parasitic transistor Qp1 turns on, and a parasitic current I paras1 flows. At this time, the second parasitic transistor Qp2 also turns on, and a parasitic current I paras2 flows.

[0054] FIG. 5 is a circuit diagram for explaining the operation of the semiconductor integrated circuit 100. When a negative potential is generated in the first N-type region N1 as described above, a current I PARAS1 flows through the first parasitic transistor Qp1, and a current I PARAS2 flows through the second parasitic transistor Qp2. When the current I PARAS2 flows, the forced-off circuit 130 applies a voltage V ON greater than the threshold voltage Vgs(th) between the gate and source of the first transistor M1 to turn on the first transistor M1. When the first transistor M1 is turned on, the combined impedance Z gs of the parallel connection circuit of the first transistor M1 and the first resistor R1 becomes low. The voltage V gs between the gate and source of the output transistor 110 is V gs =Z gs ×I PARAS1 . If Z gs is low, then Z gs ×I PARAS1 <V gs(th) , and the turning on of the output transistor 110 can be prevented.

[0055] Viewed from another perspective, the forced-off circuit 130 is configured to supply a cancellation current I PARAS2 having an amount of current depending on the current I PARAS2 to the gate of the output transistor 110 when the current I CANCEL flows. The current I R flowing through the resistor R1 is I PARAS1 -I CANCEL . When I PARAS1 ≒I CANCEL , the current I R becomes very small, and the voltage drop R×I R across the first resistor R1 also becomes very small. Thereby, it is possible to prevent the voltage between the gate and source of the output transistor 110 from exceeding the threshold voltage V gs(th) .

[0056] The above is the operation of the semiconductor integrated circuit 100. According to this semiconductor integrated circuit 100, the parasitic current I PARAS1 sunk by the control circuit 120This can prevent the output transistor 110 from turning on and suppress the occurrence of an unintended output voltage V OUT at the output terminal VOUT.

[0057] Here, in order to surely turn off the output transistor 110, the parasitic current I PARAS2 should preferably be of the same order as or greater than the parasitic current I PARAS1 . For this purpose, the current amplification factors h fe1 , h fe2 of the two parasitic transistors Qp1 and Qp2 shown in FIGS. 4 and 5 h fe1 <h fe2 should preferably satisfy the relationship.

[0058] FIG. 6 is a diagram showing a preferable arrangement of a plurality of N-type regions. On the P-type semiconductor substrate 300, the third N-type region N3 is preferably closer to the first N-type region N1 than the second N-type region N2. For example, the second N-type region N2, the third N-type region N3, and the first N-type region N1 may be arranged adjacent to each other in this order in a certain direction. With such an arrangement, h fe1 <h fe2 the relationship can be satisfied.

[0059] Next, a specific configuration example of the forced-off circuit 130 will be described.

[0060] FIG. 7 is a circuit diagram of a semiconductor integrated circuit 100A including a forced-off circuit 130A according to an embodiment. The forced-off circuit 130A includes a first transistor M1, a second transistor M2, and a second resistor R2. The second resistor R2 is connected between the gate and source of the first transistor M1 and corresponds to the intermediate circuit 132 in FIG. 1.

[0061] When a parasitic current I PARAS2 flows through the second parasitic transistor Qp2, a voltage drop V ON = R2 × I PARAS2 occurs across the second resistor R2. This voltage drop V ONWhen applied between the gate and source of the first transistor M1, the impedance of the first transistor M1 becomes low, and the turning-on of the output transistor 110 can be prevented.

[0062] Viewed from another perspective, the voltage drop V of the resistor R2 ON When applied between the gate and source of the first transistor M1, a cancellation current I flows through the first transistor M1 CANCEL flows, and the current flowing through the resistor R1 becomes small, so that the voltage drop of the first resistor R1 can be reduced, and the turning-on of the output transistor 110 can be prevented.

[0063] FIG. 8 is a circuit diagram of a semiconductor integrated circuit 100B including a forced-off circuit 130B according to an embodiment. The forced-off circuit 130B includes a first transistor M1, a second transistor M2, and a third transistor M3. The third transistor M3 corresponds to the intermediate circuit 132 in FIG. 1.

[0064] The gates and sources of the third transistor M3 and the first transistor M1 are commonly connected. The gate-drain terminals of the third transistor M3 are connected, and it is arranged on the path of the parasitic current I PARAS2 The first transistor M1 and the third transistor M3 form a current mirror circuit, and the current I flowing through the third transistor M3 PARAS2 is folded back to generate a cancellation current I CANCEL .

[0065] Viewed from another perspective, when the parasitic current I PARAS2 flows through the third transistor M3, the voltage V between the gate and source of the first transistor M1 ON increases, and it can also be interpreted that the impedance of the first transistor M1 becomes small.

[0066] FIG. 9 is a circuit diagram of a semiconductor integrated circuit 100C including a forced-off circuit 130C according to an embodiment. The forced-off circuit 130C includes a second transistor M2, a first transistor M1, a third resistor R3, and an amplifier AMP1. The third resistor R3 and the amplifier AMP1 correspond to the intermediate circuit 132 in FIG. 1.

[0067] A first end of the third resistor R3 is connected to the source of the output transistor 110, and a second end thereof is connected to the drain of the second transistor M2.

[0068] The amplifier AMP1 amplifies the voltage drop across the third resistor R3 and controls the gate-source voltage V of the first transistor R2. The amplifier AMP1 may be an operational amplifier or a comparator. ON

[0069] When a parasitic current I flows through the second transistor M2, a voltage drop R3×I occurs across the third resistor R3. This voltage drop is amplified by the amplifier AMP1 and applied between the gate and source of the first transistor M1. PARAS2 PARAS2

[0070] The above is a configuration example of the forced-off circuit 130. The configuration of the forced-off circuit 130 is not limited to that illustrated here. For example, the forced-off circuit 130 may be configured with a current source that supplies a canceling current I corresponding to the parasitic current I to the gate of the output transistor 110. PARAS2 CANCEL

[0071] Finally, the application of the semiconductor integrated circuit 100 will be described.

[0072] The semiconductor integrated circuit 100 may be a power management IC (PMIC: Power Management Integrated Circuit).

[0073] FIG. 10 is a circuit diagram of the power management IC 200 according to the embodiment. The power management IC 200 includes a plurality of DC / DC converters 210_1 and 210_2, and a linear regulator 230. The number of DC / DC converters 210 (number of channels) is not limited to two. Also, in this embodiment, the DC / DC converter 210 is a buck converter, but it may be a boost converter or a buck-boost converter. The DC / DC converter 210 includes a switching circuit 212, an inductor L1, an output capacitor C1, and a controller 214.

[0074] The linear regulator 230 corresponds to the semiconductor integrated circuit 100 described so far. The linear regulator 230 includes an output transistor 110, a first resistor R1, a control circuit 120, and a forced-off circuit 130. The output voltage V OUT is divided by resistors R11 and R12. The divided feedback voltage V FB is input to the feedback pin FB. The control circuit 120 includes an error amplifier (operational amplifier) 232, amplifies the error between the feedback voltage V OUT obtained by dividing the output voltage V FB and the reference voltage V REF , and supplies it to the gate of the output transistor 110. A forced-off circuit 130 is connected to the gate of the output transistor 110.

[0075] In such a power management IC 200, during the operation of the DC / DC converter 210, a negative voltage is generated at the output node of the switching circuit 212, that is, the connection node SW of the high-side transistor MH and the low-side transistor ML. Therefore, the drain of the low-side transistor ML corresponds to the first N-type region N1 in FIG. 1.

[0076] In the power management IC 200, the enabling and disabling of the DC / DC converter 210 and the linear regulator 230 are controlled independently. By providing the forced-off circuit 130 in the linear regulator 230, when the linear regulator 230 is in the disabled state and the DC / DC converter 210 switches, it is possible to prevent the output transistor 110 from turning on.

[0077] Note that the application of the semiconductor integrated circuit 100 is not limited to the linear regulator, and it may be a voltage follower circuit. Alternatively, the output transistor 110 may be a semiconductor switch such as a load switch or an electronic fuse.

[0078] It should be understood by those skilled in the art that the embodiments are illustrative, and there are various modifications to the combination of each component and each processing process, and such modifications are also included in the scope of the present disclosure or the present invention.

[0079] (Modification 1) The forced-off circuit 130 may include a PN junction diode instead of or in addition to the second transistor M2. The cathode of the PN junction diode may function as the third N-type region N3.

[0080] (Modification 2) In the embodiment, the case where the semiconductor integrated circuit 100 is formed on a P-type semiconductor substrate has been described, but the present disclosure is not limited thereto. The present disclosure is also applicable when a P-type well is formed on an N-type semiconductor substrate and an N-channel MOSFET is configured within the P-type well.

[0081] (Supplementary Note) The following techniques are disclosed in this specification.

[0082] (Item 1) An output transistor that is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and A first N-type region where a negative potential is generated, A first resistor connected between the gate and source of the output transistor, A control circuit for controlling the gate voltage of the output transistor, the control circuit being connected to the first resistor and including a second N-type region that forms a first parasitic transistor together with the first N-type region, A first transistor that is a P-channel MOSFET connected between the gate and source of the output transistor, and a third N-type region that forms a second parasitic transistor together with the first N-type region, the forced turn-off circuit being configured such that when a parasitic current flows through the second parasitic transistor, the first transistor turns on, A semiconductor integrated circuit comprising the above.

[0083] (Item 2) An output transistor that is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), A first N-type region where a negative potential is generated, A first resistor connected between the gate and source of the output transistor, A control circuit for controlling the gate voltage of the output transistor, the control circuit being connected to the first resistor and including a second N-type region that forms a first parasitic transistor together with the first N-type region, Including a third N-type region that forms a second parasitic transistor together with the first N-type region, the forced turn-off circuit being configured to supply a cancellation current to the gate of the output transistor when a parasitic current flows through the second parasitic transistor, A semiconductor integrated circuit comprising the above.

[0084] (Item 3) On a semiconductor substrate, the semiconductor integrated circuit according to item 1 or 2, wherein the third N-type region is closer to the first N-type region than the second N-type region.

[0085] (Item 4) The forced-off circuit includes a second transistor that is an N-channel MOSFET, and the third N-type region is the drain of the second transistor. The semiconductor integrated circuit according to any one of items 1 to 3.

[0086] (Item 5) The forced-off circuit includes a second transistor that is an NPN bipolar transistor. The third N-type region is the collector of the second transistor. The semiconductor integrated circuit according to any one of items 1 to 3.

[0087] (Item 6) The forced-off circuit includes a PN junction diode, and the third N-type region is the cathode of the PN junction diode. The semiconductor integrated circuit according to any one of items 1 to 3.

[0088] (Item 7) The forced-off circuit further includes a second resistor connected between the gate and source of the first transistor, and the gate of the first transistor is connected to the third N-type region. The semiconductor integrated circuit according to item 1.

[0089] (Item 8) The forced-off circuit further includes a third transistor whose gates and sources are commonly connected to the first transistor, and whose gate-drain is connected, and is provided on the path of the parasitic current. The semiconductor integrated circuit according to item 1.

[0090] (Item 9) The forced-off circuit a third resistor whose first end is connected to the source of the output transistor and whose second end is connected to the third N-type region, an amplifier that controls the gate voltage of the first transistor according to the voltage drop of the third resistor. The semiconductor integrated circuit according to item 1, further including

[0091] (Item 10) The forced-off circuit A first transistor, which is a P-channel MOSFET connected between the gate and the source of the output transistor; A second resistor connected between the gate and the source of the first transistor; The semiconductor integrated circuit according to item 2, further comprising the gate of the first transistor being connected to the third N-type region.

[0092] (Item 11) The forced-off circuit includes: A first transistor, which is a P-channel MOSFET connected between the gate and the source of the output transistor; A third transistor, in which the gates and the sources of the third transistor are commonly connected to those of the first transistor, the gates and the drains are connected, and the third transistor is provided on the path of the parasitic current; The semiconductor integrated circuit according to item 2, further comprising the above.

[0093] (Item 12) The forced-off circuit includes: A first transistor, which is a P-channel MOSFET connected between the gate and the source of the output transistor; A third resistor, with the first end connected to the source of the output transistor and the second end connected to the third N-type region; An amplifier that controls the gate voltage of the first transistor according to the voltage drop of the third resistor; The semiconductor integrated circuit according to item 2, further comprising the above.

[0094] (Item 13) The control circuit includes an error amplifier that receives a feedback signal corresponding to the drain voltage of the output transistor at a first input node, receives a reference voltage at a second input node, and has an output connected to the gate of the output transistor, according to any one of items 1 to 12.

[0095] (Item 14) Further comprising a DC / DC converter; The semiconductor integrated circuit according to any one of items 1 to 13, wherein the first N-type region is the drain of the low-side transistor of the switching circuit of the DC / DC converter.

Explanation of Signs

[0096] 100 Semiconductor integrated circuit IN Input terminal OUT Output terminal 102 Input line 104 Output line 110 Output transistor 120 Control circuit 122 Output stage 122 Error amplifier R11,R12 Feedback resistors 130 Forced-off circuit 132 Intermediate circuit R1 First resistor R2 Second resistor Qp1 First parasitic transistor Qp2 Second parasitic transistor M1 First transistor M2 Second transistor M3 Third transistor N1 First N-type region N2 Second N-type region N3 Third N-type region 200 Power management IC 210 DC / DC converter 230 Linear regulator 300 P-type semiconductor substrate

Claims

1. An output transistor which is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), A first N-type region where a negative potential is generated, A first resistor connected between the gate and source of the output transistor, A control circuit for controlling the gate voltage of the output transistor, the control circuit being connected to the first resistor and including a second N-type region that forms a first parasitic transistor together with the first N-type region, A first transistor which is a P-channel MOSFET connected between the gate and source of the output transistor, and a third N-type region that forms a second parasitic transistor together with the first N-type region, the forced turn-off circuit being configured such that the first transistor turns on when a parasitic current flows through the second parasitic transistor, A semiconductor integrated circuit comprising the above.

2. An output transistor which is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), A first N-type region where a negative potential is generated, A first resistor connected between the gate and source of the output transistor, A control circuit for controlling the gate voltage of the output transistor, the control circuit being connected to the first resistor and including a second N-type region that forms a first parasitic transistor together with the first N-type region, A forced turn-off circuit including a third N-type region that forms a second parasitic transistor together with the first N-type region, the forced turn-off circuit being configured to supply a canceling current to the gate of the output transistor when a parasitic current flows through the second parasitic transistor, A semiconductor integrated circuit comprising the above.

3. On a semiconductor substrate, the semiconductor integrated circuit according to claim 1 or 2, wherein the third N-type region is closer to the first N-type region than the second N-type region.

4. The semiconductor integrated circuit according to claim 1 or 2, wherein the forced turn-off circuit includes a second transistor which is an N-channel MOSFET, and the third N-type region is the drain of the second transistor.

5. The forced turn-off circuit includes a second transistor which is an NPN bipolar transistor, The semiconductor integrated circuit according to claim 1 or 2, wherein the third N-type region is the collector of the second transistor.

6. The forced-off circuit includes a PN junction diode, and the third N-type region is the cathode of the PN junction diode. The semiconductor integrated circuit according to claim 1 or 2.

7. The forced-off circuit further includes a second resistor connected between the gate and the source of the first transistor, and the gate of the first transistor is connected to the third N-type region. The semiconductor integrated circuit according to claim 1.

8. The forced-off circuit further includes a third transistor whose gates and sources are commonly connected to the first transistor, and whose gate-drain is connected, and which is provided on the path of the parasitic current. The semiconductor integrated circuit according to claim 1.

9. The forced-off circuit a third resistor having a first end connected to the source of the output transistor and a second end connected to the third N-type region; an amplifier that controls the gate voltage of the first transistor according to the voltage drop of the third resistor; The semiconductor integrated circuit according to claim 1, further comprising.

10. The forced-off circuit a first transistor which is a P-channel MOSFET connected between the gate and the source of the output transistor; a second resistor connected between the gate and the source of the first transistor; The semiconductor integrated circuit according to claim 2, further comprising, wherein the gate of the first transistor is connected to the third N-type region.

11. The forced-off circuit a first transistor which is a P-channel MOSFET connected between the gate and the source of the output transistor; a third transistor whose gates and sources are commonly connected to the first transistor, and whose gate-drain is connected, and which is provided on the path of the parasitic current; The semiconductor integrated circuit according to claim 2, further comprising.

12. The forced-off circuit a first transistor which is a P-channel MOSFET connected between the gate and the source of the output transistor; a third resistor having a first end connected to the source of the output transistor and a second end connected to the third N-type region; an amplifier that controls the gate voltage of the first transistor according to the voltage drop of the third resistor; The semiconductor integrated circuit according to claim 2, further comprising.

13. The control circuit receives a feedback signal corresponding to the drain voltage of the output transistor at a first input node, receives a reference voltage at a second input node, and includes an error amplifier whose output is connected to the gate of the output transistor, the semiconductor integrated circuit according to claim 1 or 2.

14. Further comprising a DC / DC converter, The semiconductor integrated circuit according to claim 1 or 2, wherein the first N-type region is the drain of a low-side transistor of a switching circuit of the DC / DC converter.

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