Silicon photonics device for lidar sensor and method for fabrication

Abstract

To provide a silicon photonics device for LIDAR.SOLUTION: A structure of a silicon photonics device for LIDAR includes a first insulating structure and a second insulating structure that are disposed above one or more etched silicon structures overlying a substrate member. A metal layer is disposed above the first insulating structure without a prior deposition of a diffusion barrier and an adhesion layer. A thin insulating structure is disposed above the second insulating structure. A first configuration of the metal layer, the first insulating structure and the one or more etched silicon structures forms a free-space coupler. A second configuration of the thin insulating structure above the second insulating structure forms an edge coupler.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure generally relates to silicon photonics devices, and more specifically, to silicon photonics devices for light detection and ranging (LIDAR) applications and methods of manufacturing the same.

Background Art

[0002] LIDAR, also known as radio detection and ranging (RADAR), is used in various applications including imaging and collision avoidance. Various components used in LIDAR systems, such as modulators, optical filters, optical switches, optical waveguides, photodiodes, phase shifters, wavelength converters, etc., are implemented on complementary metal oxide semiconductor (CMOS) compatible silicon photonics chips such as silicon-on-insulator (SOI) platforms. One of the main challenges faced in the development of LIDAR systems is the inadequacies related to the coupling efficiency, wavelength sensitivity, reliability, and link budget performance of the various components.

Summary of the Invention

[0003] According to one embodiment, the present disclosure describes the structure of a silicon photonics device for LIDAR. The silicon photonics device includes a substrate member, an antenna formed on the substrate member, and a photodiode formed on the substrate member and coupled to the antenna. The antenna is a one-dimensional grating coupler. The antenna includes a primary formation of a first grating structure in the upper part of the substrate member, a secondary formation of a first metal layer on the upper part of the first grating structure, and a tertiary formation of a diffusion barrier and an adhesive layer on the upper part of the first metal layer. The diffusion barrier, the adhesive layer, and the first metal layer form a reflective mirror structure. For example, the first metal layer is an MT0 (Metal0) layer. For example, the first metal layer is any one of the group consisting of aluminum, gold, silver, and copper. The antenna includes a first dielectric structure coupled to the first grating structure. For example, the first dielectric structure is any one of the group consisting of silicon nitride and silicon. The antenna includes a second grating structure coupled to the substrate member and a first metal layer coupled to the second grating structure. The antenna includes an intermediate formation of an oxide layer between the substrate member and the first formation of the first grating structure and between the first formation of the first grating structure and the second formation of the first metal layer. The silicon photonics device further includes a second dielectric structure coupled to a third dielectric structure, and the second dielectric structure and the third dielectric structure form an edge coupler. For example, the first dielectric structure and the third dielectric structure are present on the same plane. For example, the diffusion barrier and the adhesive layer are any one of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. For example, the first distance between the lower end of the first dielectric structure and the upper end of the first grating structure is in the range between 100 nanometers and 500 nanometers, the second distance between the lower end of the first metal layer and the upper end of the first grating structure is in the range from 800 nanometers to 1200 nanometers, and the third distance between the upper end of the first dielectric structure and the lower end of the first metal layer is in the range from 500 nanometers to 1600 nanometers. For example, the fourth distance between the lower end of the second dielectric structure and the upper end of the third dielectric structure is about 450 nanometers. For example, the first dielectric structure and the third dielectric structure have the same height. For example, the height of the second dielectric structure is about three times or less the height of the third dielectric structure. For example, the height of the first metal layer is twice the height of the diffusion barrier and the adhesive layer.The present disclosure describes a LIDAR sensor including a silicon photonics device as described herein. The present disclosure describes an autonomous vehicle control system including the silicon photonics device as described herein.

[0004] According to one embodiment, the present disclosure describes the structure of a silicon photonics device. The silicon photonics device includes a substrate member and a first antenna formed on the substrate member. The first antenna includes a first lattice structure coupled to the substrate member, a first dielectric structure coupled to the first lattice structure, and a first metal layer coupled to the first dielectric structure. The silicon photonics device further includes a second antenna formed on the substrate member. The second antenna includes a second lattice structure coupled to the substrate member, and the first metal layer is coupled to the second lattice structure. The silicon photonics device further includes a photodiode formed on the substrate member and coupled to the second antenna. The first antenna further includes a diffusion barrier and an adhesive layer on top of the first metal layer, and the diffusion barrier, the adhesive layer, and the first metal layer form a reflective mirror structure. The first antenna further includes intermediate oxide layers between the first lattice structure and the first dielectric structure, and between the first dielectric structure and the first metal layer. For example, the first antenna is a one-dimensional lattice coupler. For example, the first metal layer is an MT0 (Metal0) layer. For example, the first metal layer is any one of the group consisting of aluminum, gold, silver, and copper. For example, the first dielectric structure and the second dielectric structure are present on the same plane. For example, the first dielectric structure, the second dielectric structure, and the third dielectric structure are formed using either silicon nitride or silicon. For example, the diffusion barrier and the adhesive layer are any one of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. For example, the first distance between the lower end of the first dielectric structure and the upper end of the first lattice structure is in the range between 100 nanometers and 500 nanometers, the second distance between the lower end of the first metal layer and the upper end of the first lattice structure is in the range from 800 nanometers to 1200 nanometers, and the third distance between the upper end of the first dielectric structure and the lower end of the first metal layer is in the range from 500 nanometers to 1600 nanometers. For example, the fourth distance between the upper end of the second dielectric structure and the lower end of the third dielectric structure is about 450 nanometers. For example, the first dielectric structure and the second dielectric structure have the same height. For example, the height of the third dielectric structure is about three times or less the height of the second dielectric structure. For example, the height of the first metal layer is twice the height of the diffusion barrier and the adhesive layer.The present disclosure describes a LIDAR sensor including a silicon photonics device as described herein. The present disclosure describes an autonomous vehicle control system including the silicon photonics device as described herein.

[0005] According to one embodiment, the present disclosure describes a method of manufacturing a silicon photonics device for LIDAR. The method includes obtaining a substrate member and forming a silicon structure on the substrate member, forming a first dielectric structure and a second dielectric structure on the silicon structure, disposing a first oxide layer on the first dielectric structure and the second dielectric structure, forming a third dielectric structure on the first oxide layer and the second dielectric structure, forming a metal layer on the first oxide layer and the first dielectric structure, and forming a diffusion barrier and an adhesion layer on the metal layer. For example, the silicon structure is a grating. For example, the diffusion barrier and the adhesion layer on the metal layer form a reflective mirror structure. For example, the diffusion barrier and the adhesion layer are any one of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. For example, the metal layer is any one of the group consisting of aluminum, gold, silver, and copper. For example, the first dielectric structure and the second dielectric structure are present in the same plane as each other. The method further includes forming the first dielectric structure by disposing a first layer of an insulator compound on the silicon structure and etching the first layer of the insulator compound to form the first dielectric structure. The method further includes disposing a second layer of the insulator compound on the lower surface of the substrate member before etching the first layer of the insulator compound, and removing the second layer of the insulator compound disposed on the lower surface of the substrate member after forming the first dielectric structure. For example, the first layer and the second layer of the insulator compound are silicon nitride (Si 3 N 4)It is any one of the group consisting of and silicon. For example, the method of disposing the first layer of the insulator compound on the silicon structure and disposing the second layer of the insulator compound on the lower surface of the substrate member is performed by any one of the group consisting of a low-pressure chemical vapor deposition (LPCVD) process and a plasma-enhanced chemical vapor deposition (PECVD) process. The method further includes the step of disposing a film of a resistive metal alloy heater on the silicon structure. The method further includes the step of forming a third dielectric structure by disposing a second oxide layer on the metal layer, etching an opening in the second oxide layer on the second dielectric structure, and forming the third dielectric structure on the second dielectric structure within the opening. The method further includes the step of forming a second silicon structure on the substrate member, the step of doping a part of the second silicon structure to form a photodiode, and the step of forming a metal contact for the photodiode on the doped part of the second silicon structure. The method further includes the step of forming a second silicon structure on the substrate member, the step of forming a second diffusion barrier and an adhesion layer on the second silicon structure, the step of forming a second metal layer on the second diffusion barrier, the adhesion layer, and the second silicon structure, and the step of forming a third diffusion barrier and an adhesion layer on the second metal layer. The present disclosure describes a silicon photonics device manufactured by the method described herein. The present disclosure also describes a LIDAR sensor system including the silicon photonics device manufactured by the method described herein.

[0006] According to one embodiment, the present disclosure describes a method of manufacturing a silicon photonics device for a vehicle. The method includes obtaining a substrate member and forming a first silicon structure coupled to the substrate member, forming a first oxide layer on the first silicon structure, forming a metal layer on the first oxide layer and the first silicon structure, and forming an adhesive layer on the metal layer that acts as a diffusion barrier and is configured to adhere to the metal layer. The method further includes forming a first dielectric structure on the first oxide layer and the first silicon structure, and forming a second oxide layer on the first dielectric structure, where the second oxide layer is formed between the first oxide layer and the metal layer. The method further includes performing chemical mechanical polishing of the first oxide layer, and forming a spacer between the first silicon structure and the first dielectric structure. The method further includes forming a second silicon structure on the first oxide layer, where the second oxide layer is formed on the second silicon structure, and forming a third silicon structure on the second silicon structure and the second oxide layer. For example, the first dielectric structure and the second silicon structure are present in the same plane as each other. The method further includes forming a first layer of an insulator compound on the first oxide layer and etching the first layer of the insulator compound to the first oxide layer to form the first dielectric structure on the first oxide layer and the first silicon structure. The method further includes forming a second layer of the insulator compound on the lower surface of the substrate member before etching the first layer of the insulator compound, and removing the second layer of the insulator compound formed on the lower surface of the substrate member after forming the first dielectric structure. The method further includes forming a third silicon structure on the second silicon structure and the second oxide layer by etching an opening in the second oxide layer formed on the second silicon structure and forming the third silicon structure in the opening. The method further includes forming a fourth silicon structure on the substrate member, doping one or more specific portions of the fourth silicon structure to form a photodiode, and forming one or more metal contacts for the photodiode on a portion of the fourth silicon structure.For example, the first layer and the second layer of the insulator compound include any one of the group consisting of silicon nitride (Si. 3 N 4 ) and silicon. For example, the method of forming the first layer of the insulator compound on the first oxide layer and the second layer of the insulator compound on the lower surface of the substrate member is performed by any one of the group consisting of low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). For example, the first silicon structure is a lattice structure. For example, the metal layer includes any one of the group consisting of aluminum, gold, silver, and copper. For example, the adhesive layer includes any one of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. The present disclosure describes a silicon photonics device manufactured by the method described herein. The present disclosure also describes a LIDAR sensor system including a silicon photonics device manufactured by the method described herein.

[0007] Those skilled in the art will understand that the summary is for illustrative purposes only and is not intended to limit in any way. Any of the features described herein can be used with any other feature, and any subset of such features can be used in combination depending on various embodiments. Other aspects, inventive features, and advantages of the devices and / or processes described herein, which are defined only by the claims, will become apparent from the detailed description presented herein together with the accompanying drawings. Further, the language used in the present disclosure is selected in principle for readability and for the purpose of explanation, and does not limit the scope of the subject matter disclosed in the present disclosure.

Brief Description of the Drawings

[0008] Embodiments are shown by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals refer to like elements, where

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[0013] It should be understood that alternative embodiments of the structures and methods described herein can be employed without departing from the principles described herein.

DETAILED DESCRIPTION

[0014] In the following description, numerous specific details are presented for the purpose of providing a thorough understanding of various aspects of various exemplary embodiments. It should be noted that any particular exemplary embodiment can be implemented without all of the specific details and / or with variations, substitutions, and combinations of the various features and elements described herein. Hereinafter, embodiments of the present disclosure will be referred to in detail, and examples thereof are shown in the accompanying drawings. Wherever possible, the same reference numbers used in the drawings and the description refer to the same or similar components.

[0015] Also, relative terms such as "lower" or "bottom" or "rear" or "down" and "upper" or "top" or "front" or "up" can be used to describe the relationship of one element to another element as shown in the drawings. It will be understood that relative terms are intended to include various directions of the device in addition to the directions shown in the drawings. For example, if the device is inverted in one of the drawings, an element described as being on the "lower" side of another element will face the "upper" side of the other element. Thus, the exemplary term "lower" can include both "lower" and "upper" directions depending on the particular direction of the drawing. Similarly, if the device is inverted in one of the drawings, an element described as being "down" or "at the bottom" of another element will face the "up" of the other element. Thus, the exemplary terms "down" or "bottom" can include both up and down directions.

[0016] Referring to the drawings, like numbers indicate like parts throughout the several views, and FIG. 1a shows an exemplary hardware and software environment for an autonomous vehicle 100 in which various techniques disclosed herein can be implemented. For example, vehicle 100 can include a powertrain 102 that includes a prime mover 104 driven by an energy source 106 and capable of powering a drive train 108, as well as a control system 110 that includes a direction control 112, a powertrain control 114, and a brake control 116. Vehicle 100 can be any number of various types of vehicles including vehicles that can transport people and / or cargo and move on land, and it should be understood that the foregoing components 102-116 can vary greatly depending on the type of vehicle in which these components are utilized.

[0017] For simplicity, the embodiments discussed below focus on wheeled land vehicles such as passenger cars, vans, trucks, buses, etc. In such embodiments, the prime mover 104 may include one or more electric motors and / or internal combustion engines (among other things). The energy source 106 may include, for example, a fuel system (e.g., providing gasoline, diesel, hydrogen, etc.), a battery system, a solar panel or other renewable energy source, and / or a fuel cell system. The drive train 108 includes a transmission suitable for converting the output of the prime mover 104 into vehicle motion and / or any other mechanical drive components, as well as one or more brakes configured to stop or decelerate the vehicle 100 so that it can be controlled, and a direction or steering component suitable for controlling the trajectory of the vehicle 100 (e.g., a rack and pinion steering linkage that generally allows one or more wheels of the vehicle 100 to pivot about a vertical axis to change the angle of the plane of rotation of the wheel relative to the longitudinal axis of the vehicle). In one embodiment, a combination of a power train and an energy source can be used (e.g., in the case of an electric / gas hybrid vehicle), and in other embodiments, multiple electric motors (e.g., dedicated to individual wheels or axles) can be used as the prime mover 104. In the case of a hydrogen fuel cell implementation, the prime mover 104 may include one or more electric motors, and the energy source 106 may include a fuel cell system driven by hydrogen fuel.

[0018] The direction control 112 may include one or more actuators and / or sensors for controlling and receiving feedback from the direction or steering components so that the vehicle 100 can follow the desired trajectory. The power train control 114 is configured to control the output of the power train 102, for example, by controlling the output power of the prime mover 104 and controlling the gears of the transmission of the drive train 108, to control the speed and / or direction of the vehicle 100. The brake control device 116 may be configured to control one or more brakes that decelerate or stop the vehicle 100, such as disc or drum brakes coupled to the wheels of the vehicle.

[0019] Other vehicle types, including but not limited to all-terrain vehicles, rail vehicles, and construction machinery, may utilize various power trains, drive trains, energy sources, direction controls, power train controls, and brake controls. Also, in one embodiment, some of the components may be coupled, for example, the direction control of the vehicle may be primarily processed by changing the output of one or more prime movers. Thus, the embodiments disclosed herein are not limited to the specific use of the technology described herein in autonomous land vehicles.

[0020] In the illustrated embodiment, full or semi-autonomous control of the vehicle 100 is implemented by the vehicle control system 120, which may include one or more processors 122 and one or more memories 124, and each processor 122 is configured to execute program code instructions 126 stored in the memory 124. The plurality of processors may include, for example, a plurality of graphics processing units (「GPUs」) and / or a plurality of central processing units (「CPUs」).

[0021] Sensor 130 may include various sensors suitable for collecting information from the vehicle's surrounding environment for use in controlling the operation of vehicle 100. For example, sensor 130 may include one or more detection and distance measurement sensors (e.g., RADAR sensor 134, LIDAR sensor 136, or both), a 3D positioning sensor 138, such as a satellite navigation system like GPS (Global Positioning System), GLONASS (Globalnaya Navigazionnaya Sputnikovaya Sistema, or Global Navigation Satellite System), BeiDou Navigation Satellite System (BDS), Galileo, Compass, etc. The 3D positioning sensor 138 can be used to determine the vehicle's position on the earth using satellite signals. Sensor 130 may optionally include camera 140 and / or IMU (Inertial Measurement Unit) 142. Camera 140 can be a monographic or stereographic camera and can record still and / or video images. IMU 142 may include multi-gyroscopes and accelerometers that can detect the linear and rotational motion of vehicle 100 from three directions. One or more encoders 144, such as wheel encoders, can be used to monitor the rotation of one or more wheels of vehicle 100. In one embodiment, LIDAR sensor 136 may include the structure of a silicon photonics device for a coherent LIDAR system, as described in detail below.

[0022] The output of sensor 130 can be provided to a series of control subsystems 150 including a position estimation subsystem 152, a perception subsystem 154, a planning subsystem 156, and a control subsystem 158. The position estimation subsystem 152 is mainly responsible for accurately determining the position and orientation of vehicle 100 (sometimes also referred to as "pose" or "pose estimation") within the surrounding environment and generally within a certain reference frame. The perception subsystem 154 is mainly responsible for detecting, tracking, and / or identifying objects within the surrounding environment of vehicle 100. A machine learning model according to one embodiment can be utilized to track objects. The planning subsystem 156 is mainly responsible for planning the trajectory or movement path of vehicle 100 over a certain time frame given a desired destination, as well as static and moving objects within the environment. A machine learning model according to one embodiment can be utilized to plan the vehicle trajectory. The control subsystem 158 is mainly responsible for generating appropriate control signals for controlling various controls of the vehicle control system 120 in order to implement the planned trajectory of vehicle 100. Similarly, a machine learning model can be utilized to generate one or more signals for controlling the autonomous vehicle 100 in order to implement the planned trajectory.

[0023] The set of components for the vehicle control system 12 shown in FIG. 1a should be understood to be merely one example. In one embodiment, individual sensors may be omitted. Additionally or alternatively, in one embodiment, multiple sensors of the same type shown in FIG. 1a can be used redundantly and / or to cover various regions around the vehicle. Also, there may be other types of additional sensors other than those described above to provide actual sensor data related to the operation and environment of a wheeled land vehicle. Similarly, various types and / or combinations of control subsystems can be used in other embodiments. Also, although subsystems 152-158 are illustrated as being separate from processor 122 and memory 124, in one embodiment, some or all of the functions of subsystems 152-158 can reside in one or more memories 124 and be implemented as program code instructions 126 executed by one or more processors 122, and these subsystems 152-158 can, in some cases, be implemented using the same processor and / or memory. Subsystems can be implemented using at least in part various dedicated circuit logics, various processors, various field programmable gate arrays ("FPGAs"), various application specific integrated circuits ("ASICs"), various real-time controllers, etc., and as described above, multiple subsystems can use circuits, processors, sensors, and / or other components. Also, the various components of vehicle control system 120 can be networked in various ways.

[0024] In one embodiment, vehicle 100 may also include a secondary vehicle control system (not shown) that can be used as a redundant or backup control system for vehicle 100. In one embodiment, the secondary vehicle control system can fully operate autonomous vehicle 100 if an adverse event occurs in vehicle control system 120, but in other embodiments, the secondary vehicle control system may have only limited functions such as performing a controlled stop of vehicle 100 in response to an adverse event detected by the primary vehicle control system 120. In yet other embodiments, the secondary vehicle control system may be omitted.

[0025] Generally, various architectures including various combinations of software, hardware, circuit logic, sensors, networks, etc. can be used to implement the various components shown in FIG. 1a. Each processor can be implemented, for example, as a microprocessor, and each memory can include not only a random access memory (“RAM”) device including main storage, but also any supplementary level of memory such as cache memory, non-volatile or backup memory (e.g., programmable or flash memory), read-only memory, etc. Also, each memory can be considered to include not only any cache memory within the processor, which is physically located elsewhere in vehicle 100, but also any storage capacity used as virtual memory, e.g., stored in a mass storage device or other computer controller. One or more of the processors 122 shown in FIG. 1a, or a completely different processor, can be used to perform additional functions within vehicle 100 other than for autonomous control purposes, such as operating an entertainment system control, doors, lighting, convenience functions, etc.

[0026] In addition, for additional storage, vehicle 100 may include one or more high-capacity storage devices, such as removable disk drives, hard disk drives, direct access storage devices ("DASD"), optical drives (e.g., CD drives, DVD drives, etc.), solid state storage drives ("SSD"), network-attached storage, storage area networks, and / or tape drives, etc.

[0027] Furthermore, vehicle 100 may include a user interface 118 that enables vehicle 100 to receive multiple inputs from a user or operator and generate outputs therefor, such as one or more displays, touchscreens, voice and / or gesture interfaces, buttons, and tactile controls, etc. Otherwise, user input may be received via other computers or electronic devices, such as mobile device apps or web interfaces.

[0028] Also, vehicle 100 may include one or more network interfaces (e.g., network interface 162) suitable for communicating with one or more networks 176 to enable communication of information with other computers or electronic devices, including central services such as cloud services, etc., thereby receiving information including machine learning models and other data learned for use in autonomous control. The one or more networks 176 may be, for example, communication networks and may include one or more wide area networks ("WAN") such as the Internet, one or more local area networks ("LAN") such as Wi-Fi LAN, mesh networks, and one or more bus subsystems. The one or more networks 176 may optionally utilize one or more standard communication technologies, protocols, and / or inter-process communication technologies. In one embodiment, data collected by the one or more sensors 130 can be uploaded via network 176 to computing system 172 for additional processing.

[0029] In the illustrated embodiment, vehicle 100 can communicate with computing system 172 via network 176 and signal line 178. In one embodiment, computing system 172 is a cloud-based computing device. Machine learning engine 166, which is operable on computing system 172, generates a machine learning model based on simulation scenarios and simulated sensor data for use in the autonomous control of vehicle 100. The machine learning model is transmitted from computing system 172 to vehicle 100 and can be used in control subsystems 152-158 suitable for performing the function.

[0030] Not only each processor shown in FIG. 1a, but also the various additional controllers and subsystems disclosed herein generally operate under the control of an operating system and execute, or depend on, various computer software applications, components, programs, objects, modules, data structures, etc., as will be described in detail below. Also, the various applications, components, programs, objects, modules, etc. can be performed in one or more processors of other computers (e.g., computing system 172) connected to vehicle 100 via network 176, for example, in a distributed, cloud-based, or client-server computing environment, in which case the processing required to implement the functions of the computer program is allocated to multiple computers and / or services via the network.

[0031] Generally, the routines executed to implement the various embodiments described herein are referred to herein as "program code," whether implemented as part of an operating system, a specific application, component, program, object, module, or sequence of instructions, or a subset thereof. Program code generally consists of one or more instructions that reside at various times in various memories and storage devices and, when read and executed by one or more processors, perform the steps necessary to execute the steps or elements for implementing the various aspects of the present disclosure. Also, although the embodiments are described in the context of fully functional computers and systems, it should be understood that the various embodiments described herein can be distributed as a variety of forms of program products and that such embodiments can be implemented regardless of the particular type of computer-readable medium used to actually effect the distribution.

[0032] Examples of computer-readable media include types of non-transitory media such as volatile and non-volatile memory devices, floppy and other removable disks, solid state drives, hard disk drives, magnetic tape, and optical disks (e.g., CD-ROM, DVD, etc.).

[0033] Also, the various program codes described below can be identified based on the applications implemented in specific embodiments. However, the subsequent specific program nomenclature is used merely for convenience, and thus, it should be understood that the present disclosure should not be limited to use only in any specific application identified and / or implied by such nomenclature. Further, the ways in which a computer program can be composed of routines, procedures, methods, modules, objects, etc. are generally infinite, and when considering the various ways in which program functions are allocated to the various software layers resident within a normal computer (e.g., operating system, library, API, application, applet, etc.), it should be understood that the present disclosure is not limited to the specific structure and allocation of the program functions described herein.

[0034] The exemplary environment shown in FIG. 1a is not intended to limit the embodiments disclosed herein. In fact, other alternative hardware and / or software environments can be used without departing from the scope of the embodiments disclosed herein.

[0035] Figure 1b is an exemplary high-level block diagram of a silicon photonics device 105 for a coherent LIDAR system according to one embodiment. The silicon photonics device 105 includes a configuration of a photodiode (PD) 125, a grating coupler 145, an edge coupler 165, and a 2×2 mixer 180. In one embodiment, the PD 125 can be a germanium (Ge) PD. In other embodiments, the PD 125 can be a silicon PD, an indium gallium arsenide PD, a cadmium mercury telluride PD, a lead (II) sulfide PD, a molybdenum disulfide PD, a graphene PD, and / or combinations thereof. The grating coupler 145 can be used to couple light into and out of the silicon photonics device 105. The operation of the grating coupler 145 is related to the refractive index change caused by etching or deposition on a silicon-on-insulator (SOI) wafer during the manufacturing process. In one embodiment, the grating coupler 145 can be a one-dimensional grating coupler. For example, if the refractive index of the grating coupler 145 changes only in one direction, this is a one-dimensional grating coupler, and light is coupled in the direction of the refractive index change. In other embodiments, the grating coupler 145 can be a two-dimensional grating coupler. The grating couplers 145a, 145b, 145c can be free-space couplers. The grating couplers 145a, 145b are associated with the receiver antenna, and the grating coupler 145c is associated with the transmitter antenna. Each 2×2 mixer 180 is a frequency mixer that receives, as an input, a signal received through one of the local oscillator (LO) signals (e.g., LOS and LOP) and one of the grating couplers (e.g., 145a and 145b) associated with the receiver antenna. Thereafter, the output signal from the mixer 180 is directed to the photodiode 125 for detection and sensing. The edge coupler 165 is coupled to an amplifier 170. The amplifier 170 is a light source for the silicon photonics device 105. For example, the amplifier 170 generates light that is coupled to the silicon photonics device 105 through the edge coupler 165.The transmit (TX) port connected to the lattice coupler 145c associated with the transmitter antenna is connected directly or indirectly to the edge coupler 165.

[0036] FIG. 2 shows a schematic cross-sectional view showing the structure of a silicon photonics device 200 for a coherent LIDAR system according to an embodiment. The structure of the silicon photonics device 200 is fabricated using a silicon-on-insulator (SOI) wafer. As shown in FIG. 3, the SOI wafer 300 may include an SOI layer 202, a buried oxide (BOX) layer 206, and a bulk silicon substrate member 204 that provides support for the SOI wafer. The BOX layer 206 is present between the SOI layer 202 and the bulk silicon substrate member 204. The SOI layer 202 can be etched and patterned with one or more silicon structures 402, 404, 406, 408 coupled to the bulk silicon substrate member 204. For example, the SOI layer 202 can be a crystalline silicon (c-Si) layer. A portion of the c-Si layer disposed on the BOX layer 206 can be selectively and partially etched to pattern one or more silicon structures 402, 404, 406, and 408. The silicon structures 402, 404, 406, and 408 can include one or more of an island structure, a rib structure, a grat structure, and a slab structure. The silicon structure can include one or more non-uniform grating structures that form optical waveguides used for optical input / output. In addition to the optical waveguides, other optical device structures such as lasers, optical modulators, optical detectors, and optical switches can also be fabricated in the SOI layer 202. The depth of the edge of the silicon structure partially etched in the SOI layer 202 can range between about 50 nm and about 300 nm. The thickness of the BOX layer 206 is, for example, about 3000 nm, but can have a range between about 1500 nm and about 3500 nm. As will be described in detail below, a dielectric material or an insulator compound layer can be disposed and etched on the silicon structure to pattern one or more insulating or dielectric structures. For example, a first insulating structure 702 is patterned and etched in an insulator compound layer to couple to a separated silicon structure 404. In this embodiment, the first insulating structure 702 is present on the same plane as the second insulating structure 704. The thickness or height of the insulating structures 702 and 704 is, in FIG. 2, about 400 nm, but can have a range between about 300 nm and about 600 nm.In some embodiments, the insulator composite layer can be a dielectric material having a higher optical refractive index than the contacting cladding material. For example, the insulator compound layer can be a silicon nitride (Si. 3 N 4 ) layer. One advantage of using an Si 3 N 4 layer in a coherent LIDAR system silicon photonics chip is the ability to handle higher optical output. In other examples, the insulator compound layer can be an amorphous silicon (a-Si) layer, a crystalline silicon (c-Si) layer, etc. The distance between the bottom surface of the first insulating structure 702 and the top of the silicon structure can be, for example, about 240 nm, but can have a range of about 100 nm to about 500 nm. The germanium (Ge) photodiode 125 can be fabricated on the silicon structure through doping.

[0037] The structure of the silicon photonics device 200 may include a metal 1 (MT1) layer 1002, a metal 2 (MT2) layer 1402, and a metal 3 (MT3) layer 1404, which are a plurality of metal routing layers for forming interconnections. After the formation of the MT1 layer 1002, the metal 0 (MT0) layer 1108 may be coupled to the first insulating structure 702. In one embodiment, the diffusion barrier and adhesion layer 1106 may be coupled to the metal layer 1104. The diffusion barrier and adhesion layer 1106 may be disposed on top of or above the metal layer 1104. The MT0 layer 1108 composed of the metal layer 1104 and the diffusion barrier and adhesion layer 1106 may form a reflective mirror structure coupled to the first layer insulating structure 702. In other embodiments, the diffusion barrier and adhesion layer 1106 with excellent optical properties such as reflectivity may be disposed on the upper and lower portions of the metal layer 1104. The diffusion barrier and adhesion layer 1106 may be tantalum nitride, indium oxide, copper silicide, tungsten nitride, titanium nitride, and / or combinations thereof. There is an oxide layer or cladding 1408 that fills the space between different structures formed on the silicon photonics device 200. The distance separating the upper end of the first insulating structure 702 and the lower end of the MT0 layer 1108 is, for example, about 900 nm, but may have a range between about 500 nm and about 1600 nm. The distance separating the lower end of the MT0 layer 1108 and the upper end of the silicon structure 404 is about 1140 nm, but may have a range between about 800 nm and about 1200 nm. In one embodiment, the thickness of the metal layer 1104 may be twice the thickness of the diffusion barrier and adhesion layer 1106. For example, the thickness of the metal layer 1104 may be about 100 nm, and the thickness of the diffusion barrier and adhesion layer 1106 may be about 50 nm. Also, a thin insulating structure 1302 made of the same insulating material as the first insulating structure 702 and the second insulating structure 704 may be coupled to the second insulating structure 704. For example, the thin insulating structure 1302 may be disposed on the second insulating structure 704. In one embodiment, the thickness of the thin insulating structure 1302 may be less than or equal to about 3.6 times the thickness of the second insulating structure 704. For example, when the thickness of the second insulating structure 704 is about 400 nm, the thickness of the thin insulating structure 1302 is about 110 nm. The distance between the lower end of the thin insulating structure 1302 and the upper end of the second insulating structure 704 may be about 450 nm.

[0038] In FIG. 2, one or more of the MT0 layer 1108, the first insulating structure 702, and the partially etched silicon structures 402, 404 form a grating coupler 145 for coupling to free space. For example, the MT0 layer 1108 and the silicon structure 402 form a grating coupler 145 associated with the receiver antenna of the silicon photonics device 200 for a coherent LIDAR system. In other examples, the MT0 layer 1108, the first insulating structure 702, and the silicon structure 404 form a grating coupler 145 associated with the transmitter antenna of the silicon photonics device 200 for a coherent LIDAR system. The MT0 layer 1108 functions as a silicon photonics chip-free space interface. The BOX layer 206 functions as a low optical refractive index cladding material. The oxide layer cladding 1408 also functions as a low optical refractive index cladding material. The cladding can be one or more layers of a lower optical refractive index material in contact with a higher optical refractive index core material such as the silicon structures 402, 404 and the insulating structures 702, 704. A thin insulating structure 1302 disposed on top of and overlapping the second insulating structure 704 forms an edge coupler 165 for coupling to other semiconductor devices such as amplifier 170 or a silicon photonics device. The coupling between the thin insulating structure 1302 and the second insulating structure 704 functions as an amplifier-silicon photonics chip interface. FIG. 2 shows the thin insulating structure 1302 and the second insulating structure 704 overlapping from edge to edge, but it should be understood that there may be an offset in this overlap. In one embodiment, the edge coupler 165 can be fabricated from a single insulating structure. The edge coupler 165 made of the configuration of the dual insulating structures 704 and 1302 provides a higher coupling efficiency (CE) than the configuration of a single insulating structure and better matches the optical mode of a coherent LIDAR system. In other embodiments, the structure of the edge coupler 165 can be patterned on the crystalline silicon (c-Si) layer itself without the need to use insulator compounds such as 3 N 4 etc.

[0039] In one embodiment, the structure of the grating coupler 145 can be configured using another upper insulating structure (not shown in FIG. 2) on the first insulating structure 702. This upper insulating structure can be made of the same insulating material as the insulating material of the first insulating structure 702. The upper insulating structure or the first insulating structure 702 thereunder can be etched and patterned to form a plurality of isolated bars of the insulating structure, and combined with the MT0 layer 1108 to form the grating coupler 145. For example, if a plurality of isolated bars of the insulating structure are patterned in the upper insulating structure, these isolated bars can form a grating coupler associated with the receiver antenna together with the MT0 layer 1108. In another example, if a plurality of isolated bars of the insulating structure are patterned in the first insulating structure 702, these isolated bars can form a grating coupler associated with the transmitter antenna together with the upper insulating structure and the MT0 layer 1108. In other embodiments, the silicon structures 402, 404 and the isolated bars of the insulating structure patterned on the upper insulating structure or the first insulating structure 702 can be mixed and matched with the MT0 layer 1108 to form the grating coupler 145.

[0040] The advantage of the grating coupler 145 structure etched and patterned in the silicon photonics device 200 of FIG. 2 is that it helps to meet the link budget requirements for use in automotive grade LIDAR systems. For example, the structure of the grating coupler 145 can reduce the insertion loss at the interface between the silicon photonics device 200 for coherent LIDAR and the free space of both the transmission and reception paths, resulting in an improvement of about 2 dB to 6 dB in the overall link budget. The optical loss of the transmitter or output type grating coupler is calculated twice in the link budget because the light exits such a coupler, reflects from the target, and returns to the grating coupler. The structure of the grating coupler 145 can easily achieve a coupling loss of about 0.25 dB without lithography constraints. Due to lithography constraints, the structure of the grating coupler 145 can facilitate the achievement of a coupling loss of about 0.5 dB to about 1.0 dB.

[0041] Figures 3 to 17 show schematic cross-sectional views illustrating a method of manufacturing a silicon photonics device according to an embodiment.

[0042] As shown in FIG. 3, an SOI wafer 300 is provided. In one embodiment, the SOI wafer 300 includes a bulk silicon substrate member 204 that is a first layer or base layer, and a buried oxide (BOX) layer 206 of an electrical insulating material such as silicon dioxide (SiO 2 ) having a thickness of about 3000 nm as a second layer or intermediate layer, and an active crystalline silicon (c-Si) SOI layer 202 having a thickness of about 220 nm as a third layer or top layer. It can be a three-layer wafer.

[0043] As shown in FIG. 4, the c-Si layer or SOI layer 202 shown in FIG. 3 can be precisely patterned and etched to form non-uniform silicon structures such as gratings 402, ribs 404, islands 406, and slabs 408 disposed on the BOX layer 206. The remaining portion of the SOI layer 202 shown in FIG. 3 can be etched down to the BOX layer 206. The grating 402 silicon structure is etched to a depth of about 70 nm, and the slab 408 silicon structure is etched to a depth of about 130 nm from the top. The rib 404 structure is patterned and etched into an isolated full-thickness (e.g., 220 nm) bar of the silicon structure.

[0044] As shown in FIG. 5, an oxide layer or cladding 502 is deposited on the silicon structures 402, 404, 406, 408 up to a height of about 240 nm from the upper ends of the silicon structures 402, 404, 406, 408. After oxide deposition, the upper portion of the SOI wafer 300 undergoes a CMP (Chemical Mechanical Polishing) or planarization process. Such oxide layer deposition and planarization processes are performed to form a spacer between the silicon structures 402, 404, 406, 408 and an insulator compound or material to be subsequently deposited on the upper portion of the SOI wafer 300.

[0045] As shown in FIG. 6, the first layer 602 and the second layer 604 of an insulator compound or material such as silicon nitride (Si 3 N 4 ) are deposited on top of the oxide layer 502 and below the substrate member 204. Such deposition can be achieved using chemical vapor deposition. The thickness of the first layer 602 deposited on top of the SOI wafer 300 is about 400 nm. In one embodiment, the chemical vapor deposition method used can be a low-pressure chemical vapor deposition (LPCVD) method. In the LPCVD method, Si 3 N 4 is deposited on both sides (top and bottom) of the SOI wafer 300. The LPCVD method can apply a strong tensile stress to the SOI wafer 300 and deform it. Such double-sided deposition of Si 3 N 4 is performed to eliminate the influence of the tensile stress and prevent warping of the SOI wafer 300 structure. In one embodiment, plasma-enhanced chemical vapor deposition (PECVD) can be used as a method for depositing an insulator compound layer on top of the SOI wafer 300. In the PECVD method, double-sided deposition of the insulator compound may not be necessary. In one embodiment, amorphous silicon (a-Si) can be used as the insulator compound.

[0046] As shown in FIG. 7, the layer 602 deposited on top of the oxide layer 502 in FIG. 6 is patterned and etched to form two coplanar insulating structures or dielectric elements 702 and 704 disposed on top of the oxide layer 502. The insulating structure 702 can overlap and be coupled with the silicon structure 404. The remaining portion of the layer 602 deposited on top of the oxide layer 502 is etched down to the oxide layer 502. The thickness of the two coplanar insulating structures 702 and 704 is, for example, about 400 nm. After the layer 602 deposited on top of the SOI wafer 300 is patterned and etched, the SOI wafer 300 can be cleaned to remove all photoresist.

[0047] As shown in FIG. 8, the layer 604 deposited on the lower part of the substrate member 204 in FIG. 7 is removed after forming two coplanar insulation structures 702 and 704. By patterning and etching the deposited layer 604 on the upper part of the SOI wafer 300 in FIG. 6, the tensile stress applied to the upper part of the SOI wafer 300 is released. In order to balance the tensile stress applied to the lower part of the SOI wafer 300, the layer 604 deposited on the lower part of the SOI wafer 300 in FIG. 7 is removed. After the layer 604 deposited on the lower part of the SOI wafer 300 is removed, the upper end of the SOI wafer 300 can be deeply cleaned to remove contaminants that may have been transferred to the upper part of the SOI wafer 300.

[0048] As shown in FIG. 9, the etched silicon structure 406 disposed on the BOX layer 206 is doped to form the photodiode 125. For example, germanium can be used as a material for forming the photodiode 125 in FIG. 9. It should be understood that other materials such as silicon, indium gallium arsenide, lead (II) sulfide, cadmium mercury telluride, or combinations thereof can also be used to form their respective photodiodes. Following the formation of the photodiode 125, another oxide layer 902 is deposited on the upper part of the SOI wafer 300.

[0049] As shown in FIG. 10, three conductive vias are formed on the terminals of the MT1 layer 1002 and the photodiode 125. The MT1 layer 1002 and the conductive vias are formed by first depositing and patterning the first diffusion barrier and the adhesion layer 1004a. Thereafter, metal 1001 is deposited and patterned in the center. Finally, the second diffusion barrier and the adhesion layer 1004b are deposited and patterned. That is, the metal 1001 is sandwiched between two thin diffusion barriers and the adhesion layers 1004a and 1004b. In one embodiment, the metal 1001 can be deposited using one or more of aluminum, copper, gold, silver, or combinations thereof. In one embodiment, the diffusion barriers and the adhesion layers 1004a, 1004b can be deposited using tantalum nitride (TaN). The thickness of the diffusion barriers and the adhesion layers 1004a, 1004b is about 50 nm. The thickness of the metal 1001 deposited to form the MT1 layer 1002 is about 750 nm. The distance between the MT1 layer 1002 and the upper part of the silicon structure 402 is about 740 nm.

[0050] As shown in FIG. 11, the MT0 layer 1108 is formed. The purpose of this new MT0 layer 1108 is to form a high-reflectivity mirror structure in the silicon photonics device 105. After the formation of the MT1 layer 1102 shown in FIG. 10, an oxide layer 1102 with a thickness of about 300 nm is deposited on top of the SOI wafer 300 as shown in FIG. 11. The metal layer 1104 is deposited and patterned on the first insulating structure 702. The thickness of this deposited metal layer 1104 is about 100 nm. The diffusion barrier and adhesion layer 1106 can be deposited and patterned on top of the metal layer 1104 to improve the adhesion. The thickness of this upper diffusion barrier and adhesion layer 1106 is about 50 nm. Thus, the deposited metal layer 1104 and the diffusion barrier and adhesion layer 1106 form the MT0 layer 1108 as shown in FIG. 11. The formation of the MT0 layer 1108 is different in that the base diffusion barrier and adhesion layer are not deposited before the metal layer 1104 is deposited. That is, the metal layer 1104 is deposited first without having a diffusion barrier and adhesion layer underneath. For example, a diffusion barrier and adhesion layer of tantalum nitride (TaN) material has a low reflectivity. If the TaN diffusion barrier and adhesion layer are deposited before the metal layer 1104, this may adversely affect the reflectivity of the MT0 layer 1108 for forming a high-reflectivity mirror structure. In other embodiments, a material having excellent optical properties in terms of reflectivity can be used as the diffusion barrier and adhesion layer under the metal layer 1106. During the subsequent formation of the MT1 layer 1002 and the MT0 layer 1108, there is an intentional omission of the CMP (Chemical Mechanical Polishing) process for planarizing the SOI wafer 300. The CMP process may introduce uncertainties in the oxide spacing between two different layers. Such an intentional omission of the CMP process is performed to minimize the change in the oxide spacing. In one embodiment, the SOI wafer 300 may undergo a CMP process during the subsequent formation of the MT1 layer 1002 and the MT0 layer 1108. The openings can be etched within the oxide spacing to the desired depth at which the MT0 layer 1108 can be patterned. The configuration of the MT0 layer 1108, the insulating structure 702, and the silicon structures 402, 404 forms one or more grating couplers 145 as described herein.The distance between the lower part of the MT0 layer 1108 and the upper part of the silicon structure 404 is about 1140 nm. The distance between the lower part of the MT0 layer 1108 and the upper part of the insulating structure 702 is about 900 nm. The distance between the lower part of the first insulating structure 702 and the upper part of the silicon structure 404 is about 240 nm.

[0051] As shown in FIG. 12, another oxide layer 1202 is deposited on the MT1 layer 1002, the MT0 layer 1108, the oxide layer 1102, and other upper structures. After the oxide deposition, the upper part of the SOI wafer 300 undergoes a CMP (Chemical Mechanical Polishing) or planarization process.

[0052] As shown in FIG. 13, an opening can be etched in the oxide layer 1202 on the second insulating structure 704. Si 3 N 4 A thin layer of an insulator compound such as is deposited in the opening and patterned to form a thin insulating structure 1302 on the upper part of the second insulating structure 704. The thickness of the thin insulating structure 1302 is about 110 nm. The distance between the lower part of the thin insulating structure 1302 and the upper part of the second insulating structure 704 is about 450 nm. The configuration of the thin insulating structure 1302 on the upper part of the second insulating structure 704 forms the edge coupler 165 as described herein.

[0053] As shown in FIG. 14, the backend of the line manufacturing step is performed. This includes the formation of the MT2 layer 1402 and the MT3 layer 1404, the addition of conductive vias connecting different metal layers, the deposition of more oxide layers 1408, the deposition of the heater HTR 1406, and the execution of the CMP processing step. The thickness of the metal deposited on the MT3 layer 1404 is about twice that of the MT2 layer 1402. For example, the thickness of the metal deposited on the MT2 layer 1402 is about 1000 nm, and the thickness of the metal deposited on the MT3 layer 1404 is about 2000 nm. Thin coatings of diffusion barriers and adhesion layers are deposited on the top and bottom of the deposited metals of the MT2 layer 1402 and the MT3 layer 1404. A thin film of resistive metal alloy is deposited as the heater HTR 1406 on the silicon structure etched from the SOI layer. An example of a resistive metal alloy is titanium nitride (TiN). The HTR 1406 can be used to heat the silicon photonics device chip. The heater HTR 1406 can also be used to change the refractive index of the waveguide structure useful for the operation of phase shifters and optical switches. The distance between the top of the MT2 layer 1402 and the bottom of the MT3 layer 1404 is about 800 nm. To form contacts to the silicon photonics device chip, an opening can be etched to a depth of about 200 nm in the oxide layer 1408 directly above the MT3 layer 1404.

[0054] As shown in FIG. 15, shallow trenches DT_OX 1502 are formed in the BOX layer 206 and deep trenches DT_SI 1504 are formed in the substrate member 204. The formation of the shallow trenches DT_OX 1502 removes the oxide layer 1408 and the BOX layer 206 down to the substrate member 204. The depth of the DT_SI 1504 is about 150 μm.

[0055] As shown in FIG. 16, undercut etching is performed to release the suspension structure.

[0056] As shown in FIG. 17, the backside of the SOI wafer 300 is polished to an optical quality. The thickness of the substrate member or handle 204 is about 600 μm after the backside polishing of the SOI wafer 300.

[0057] The foregoing schematic diagram is part of an integrated circuit chip design. The chip design is generated in a graphical computer programming language and stored on a computer-readable storage medium (e.g., a virtual hard drive such as a disk, tape, physical hard drive, or storage access network). If the designer does not manufacture the chip or produce the photolithography mask used in chip manufacturing, the designer transmits the resulting design directly or indirectly to such an entity by physical means (e.g., providing a copy of the computer-readable storage medium storing the design) or electronically (e.g., via the Internet). The stored design is generally converted into an appropriate format (e.g., GDSII) for photolithography mask fabrication, which includes several copies of the chip design to be formed on the wafer. The photolithography mask is used to define the areas of the wafer (and / or the layers thereon) to be etched or processed.

[0058] The foregoing detailed description of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the exact form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to best utilize the disclosure in various embodiments and with various modifications suited to the particular use contemplated. It is intended that the scope of the disclosure be defined by the claims appended hereto. Although one embodiment of the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein can be changed within the scope of the disclosure. Further, the scope of the disclosure is not intended to be limited to the particular implementations of the processes, machines, manufactures, compositions of matter, means, methods, and steps described herein. Those skilled in the art will readily appreciate that presently existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform substantially the same function as described herein can be utilized. Also, achieving substantially the same results as described herein can be accomplished by the disclosure. Accordingly, the appended claims are intended to cover such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. 1. A method for manufacturing a silicon photonics device, comprising: obtaining a substrate member and forming a silicon structure on the substrate member; forming a first dielectric structure and a second dielectric structure on the silicon structure; disposing a first oxide layer over the first dielectric structure and the second dielectric structure; forming a third dielectric structure on the first oxide layer and the second dielectric structure; forming a metal layer over the first oxide layer and the first dielectric structure; forming a diffusion barrier and adhesion layer over the metal layer.

2. The method of claim 1 , wherein the silicon structure is a lattice.

3. The step of forming a first dielectric structure includes: disposing a first layer of an insulating compound over the silicon structure; 2. The method of claim 1, further comprising: etching the first layer of insulating compound to form a first dielectric structure.

4. disposing a second layer of insulating compound on a bottom surface of the substrate member prior to etching the first layer of insulating compound; 4. The method of claim 3, further comprising the step of removing the second layer of insulator compound disposed on a bottom surface of the substrate member after forming the first dielectric structure.

5. The first and second layers of the insulating compound are made of silicon nitride (Si ３ N ４ 5. The method according to claim 4, wherein the metal is any one of the group consisting of silicon.

6. 5. The method of claim 4, wherein the steps of disposing a first layer of the insulating compound on a silicon structure and disposing a second layer of the insulating compound on a bottom surface of the substrate member are performed by one of the group consisting of low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD).

7. The method of claim 1 , wherein the diffusion barrier and adhesion layer on the metal layer form a reflective mirror structure.

8. The method of claim 7 , wherein the first dielectric structure and the second dielectric structure are coplanar with each other.

9. The step of forming the third dielectric structure includes: disposing a second oxide layer over the metal layer; Etching an opening in the second oxide layer over the second dielectric structure layer; and forming the third dielectric structure on the second dielectric structure in the opening.

10. The method of claim 1 , wherein the metal layer is one of the group consisting of aluminum, gold, silver and copper.

11. 2. The method of claim 1, wherein the diffusion barrier and adhesion layer is one of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride.

12. forming a second silicon structure on the substrate member; doping portions of the second silicon structure to form a photodiode; 2. The method of claim 1, further comprising forming a metal contact for a photodiode on the doped portion of the second silicon structure.

13. forming a second silicon structure on the substrate member; forming a second diffusion barrier and adhesion layer on the second silicon structure; forming a second metal layer on the second diffusion barrier and adhesion layer and on the second silicon structure; 2. The method of claim 1, further comprising forming a third diffusion barrier and adhesion layer over the second metal layer.

14. The method of claim 1 further comprising the step of disposing a film of a resistive metal alloy heater on the silicon structure.

15. 15. A silicon photonics device manufactured by a process according to the method of any one of claims 1 to 14.

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