Storage device

Abstract

To provide writing means that does not take long time to perform writing in a storage device having a non-volatile memory including an anti-fuse element.SOLUTION: A storage device includes: a memory part that is formed by an anti-fuse element and includes a writing condition storage region where writing condition is stored and a writing region where information is written; and a control part that performs writing operation and reading operation on the memory part by controlling a voltage applied to the anti-fuse element and that applies, to the anti-fuse element, a writing voltage in a pulse form having a fixed cycle upon the writing operation. The control part controls the writing condition with reference to the writing condition storage region upon the writing operation.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a memory device.

Background Art

[0002] A memory device equipped with a non-volatile memory using anti-fuses of OTP (One Time Programmable) unit cells is used. There are two types of OTP non-volatile memories: those using fuse elements and those using anti-fuses. Anti-fuses can be highly integrated in terms of structure and enable writing of a larger number of data compared to fuse elements. Also, due to the manufacturing variation in the resistance values connected in parallel to the anti-fuse elements and the temperature change due to the environment, there are differences in the number of pulses and voltage required to cause a state change in the anti-fuse. To absorb this variation, it is common to apply the number of pulses according to the worst case to the anti-fuse. In order to absorb the differences in the number of pulses and voltage required for the anti-fuse to cause a state change, there is the one described in Patent Document 1, which is characterized by controlling the write time and write voltage.

[0003] In Patent Document 1, when writing to the anti-fuse of the OTP unit cell, the write operation and the read operation are performed in one cycle. The data detected in the read operation is compared with a reference value, and when the detected data and the reference value are different, the write operation time and the amplitude of the write voltage are increased.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the above-mentioned literature, the characteristics of the anti-fuse of the OTP unit cell cannot be determined at the stage before application, and the write time and the control of the write voltage are impossible unless the write operation and the read operation are performed at least once, leaving a problem in the extension of the write time. Compared with the conventional fuse, the anti-fuse can be highly integrated in terms of structure, and a large number of data can be written even with the same area as the conventional one. On the other hand, the extension of the write time leads to a decrease in usability, which is a problem that will become apparent in the future.

[0006] The present invention has been made in view of the above problems, and an object thereof is to provide a writing means that does not prolong the writing time in a storage device having a non-volatile memory including an anti-fuse.

Means for Solving the Problems

[0007] The present invention adopts the following configuration. That is, A memory unit composed of anti-fuse elements, the memory unit including a write condition storage area for storing write conditions and a write area where information is written; A control unit that performs a write operation and a read operation on the memory unit by controlling the voltage applied to the anti-fuse element, and applies a pulse-shaped write voltage having a constant period to the anti-fuse element during the write operation; A storage device comprising: The control unit controls the write conditions by referring to the write condition storage area during the write operation. The storage device is characterized in that.

Effects of the Invention

[0008] According to the present invention, in a storage device having a non-volatile memory including an anti-fuse, it is possible to provide a writing means that does not prolong the writing time.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

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Figure 11

Figure 12

Figure 13

Mode for Carrying Out the Invention

[0010] Hereinafter, with reference to the drawings, preferred embodiments of the present invention will be described in detail by way of example. However, the dimensions, materials, shapes, relative arrangements, etc. of the components described in this embodiment are not intended to limit the scope of the present invention only to these, unless otherwise specified. Also, regarding the materials, shapes, etc. of the members once described in the following explanation, unless otherwise described again, they are the same as the initial explanation in the subsequent explanations. For configurations and processes not particularly illustrated or described, well-known techniques or publicly known techniques in the relevant technical field can be applied. Also, duplicate explanations may be omitted.

[0011] <Example 1> (OTP Memory) FIG. 1 is an example of an equivalent circuit showing the state before writing of a general non-volatile OTP memory 11 using anti-fuses 10 included in the memory device of the present invention. The non-volatile OTP memory 11 of this embodiment has a transistor 12, an anti-fuse 10, a writing circuit 13, a selector circuit 15, and a reading circuit 14.

[0012] The anti-fuse 10 includes an anti-fuse element Ca and a resistance element Ra. The writing circuit 13 supplies power during writing. The selector circuit 15 inputs a control signal to the gate terminals of the writing circuit 13 and the transistor 12. The reading circuit 14 reads the state of the anti-fuse element Ca. A first terminal and a second terminal are connected to the input A of the anti-fuse element Ca, and the source of the transistor 12 is connected to the output B. Note that the drain terminal of the transistor 12 is connected to GND.

[0013] The anti-fuse element Ca is an element that has a first resistance value before information is written and a second resistance value after information is written. The first resistance value is greater than the second resistance value, and the greater the difference between the first resistance value and the second resistance value, the more ideal it is. For example, the anti-fuse element Ca functions as a capacitor and has a high resistance value before information is written, but shows a low resistance value after being written. FIG. 1 shows writing to the anti-fuse element. Since it shows the state before programming, the anti-fuse element Ca is described as a capacitor.

[0014] Next, the programming operation for the anti-fuse element Ca will be described. During programming, the writing circuit 13 connected to the first terminal is switched so that a high voltage is applied to the anti-fuse element Ca. Further, by applying a LOW-level signal to the gate of the transistor 12 corresponding to the anti-fuse element Ca to be programmed, the transistor 12 is turned on. As a result, a high voltage is applied to the target anti-fuse element Ca from the first terminal.

[0015] However, when the state change of the anti-fuse element Ca is performed by a static stress that continuously applies a constant voltage, electrons are trapped in the insulating film of the anti-fuse element Ca, and the state does not change normally. To address this, generally, a LOW-level signal and a HI-level signal are alternately repeated for the gate of the transistor 12, and a pulse-shaped writing voltage having a certain period is applied. This reduces the trapping of electrons in the insulating film of the anti-fuse element Ca and enables the state of the anti-fuse element Ca to change normally.

[0016] Next, the operation during reading will be described. During reading, the transistor 12 is turned on by applying a LOW-level signal to the gate of the transistor 12 corresponding to the anti-fuse 10 to be read. In this state, a weak current is supplied from the reading circuit 14. Since the resistance value of the anti-fuse element Ca differs depending on whether information is written or not, the combined resistance value of the anti-fuse element Ca and the resistance element Ra also differs similarly. The determination of whether it is written or not is made by utilizing the difference in resistance values caused by this state change, that is, the difference in the potential difference applied across both terminals of the anti-fuse 10.

[0017] (Constituent Blocks) Figure 2 is a block diagram for determining the number of write pulses in Example 1. Here, write conditions such as write time, write voltage, and number of write times are set in the non-volatile OTP memory 11. The non-volatile OTP memory 11 in Example 1 has a write pulse number storage area 20 that stores the number of write times, which is one of these write conditions, an applied pulse number inspection area 21, and a write area 22. The non-volatile OTP memory 11 is connected to a write circuit 13 and a read circuit 14 via the input A shown in FIG. 1.

[0018] The write circuit 13 is connected to the CPU 23 and a write power supply 24. The read circuit 14 is connected to the CPU 23 and a read power supply 25. The circuit switching during writing and reading is controlled by the CPU 23. When writing, a high voltage is applied from the write power supply 24, and when reading, a weak current is supplied from the read power supply 25. Also, the anti-fuse 10 to be written / read is selected by switching the connection to the gate terminal of the corresponding transistor 12 by a selector circuit 27. The selector circuit 27 is connected to a pulse generation unit 26, and a pulse signal is applied to the gate terminal of the transistor 12 via the selector circuit 27.

[0019] Note that the selector circuit 27 is connected to the CPU 23 and can be switched by the CPU 23. For example, during the inspection of the number of applied pulses, the gate terminal of the transistor 12 corresponding to the anti-fuse 10 in the applied pulse number inspection area 21 is connected to the pulse generation unit 26. Also, the pulse generation unit 26 is connected to a pulse generation power supply 28 and the CPU 23, and by being controlled by the CPU 23, it is possible to generate a pulse signal a desired number of times. Further, the CPU 23 is connected to a memory 29 having a non-volatile memory (e.g., ROM) and a volatile memory (e.g., RAM). In the memory 29, a correlation table of write pulses and write bits as shown in FIG. 4 is stored.

[0020] (Processing Flow of Pulse Determination) Figure 3 is a flowchart for determining write pulses in Example 1. Unless otherwise specified, the control of each step is implemented with a control unit such as CPU 23 as the main operating body. Typically, the determination of the number of write pulses is carried out using anti-fuse elements for inspection in the pre-shipment inspection at the factory. The results of the inspection are stored in the anti-fuse elements for storage, and writing is performed using the information stored in the anti-fuse elements for storage at the user's site.

[0021] In step S101, the pulse number inspection is started. Next, in step S102, the selector circuit 27 is switched so that the anti-fuse 10 in the applied pulse number inspection area 21 is selected. Next, in step S103, the state of the anti-fuse 10 is read out. Next, in step S104, a check is made on the state of the read anti-fuse 10 (whether it is written or not).

[0022] If it is determined in the check of step S104 that the read value is at a level assumed to be the state after writing, the process proceeds to step S105. In step S105, it is determined that it is an initial defect, and error processing is performed. On the other hand, if the state of the anti-fuse 10 read in step S104 is at a level assumed to be before writing, the process proceeds to step S106. In step S106, 10k pulses are applied. Next, in step S107, the state of the anti-fuse 10 is read out again. Next, in step S108, a check is made for the presence or absence of a change in the state of the read anti-fuse 10.

[0023] If it is determined in the check of step S108 that there is no state change (not written), the process proceeds to step S109. In step S109, the process moves to a determination of whether the total number of applied pulses exceeds 100k pulses. If the total number of applied pulses does not exceed 100k pulses (S109 = Yes), the application of 10k pulses (S106), the reading of the state change (S107), and the determination of the presence or absence of the state change (S108) are repeated again. On the other hand, the total number of applied pulses If it is determined that the number exceeds 100k pulses (S109 = No), the process proceeds to step S105 to perform error processing.

[0024] In this way, pulses are applied in increments of 10k. If it is determined that there has been a state change in the anti-fuse 10 (the write operation has been completed normally) (S108 = Yes), the process proceeds to step S110. In step S110, the selector circuit 27 is switched to the write count storage area so that the anti-fuse 10 in the write pulse count storage area 20 is selected. Next, in step S111, the total number of pulses that the anti-fuse 10 had until it reached the state change is referred to, as well as the write pulse count and the set value in the write count storage area as shown in FIG. 4, and the total applied pulse count is written. Finally, in step S112, the process ends.

[0025] The write operation in Example 1, which is performed according to the write pulse count determined in this way, will be described. As described with reference to FIG. 2, the non-volatile OTP memory 11 has a write pulse count storage area 20, an applied pulse count inspection area 21, and a write area 22, and is connected to a write circuit 13 and a read circuit 14 via the input A shown in FIG. 1. And the switching of the write / read circuit is controlled by the CPU 23. Here, at the time of writing, a high voltage is applied from the write power supply 24. Also, the anti-fuse 10 to be written / read is selected by switching the connection between the gate terminal of the transistor 12 connected to the output B and the pulse generation unit 26 by the selector circuit 27. The selector circuit 27 is connected to the pulse generation unit 26 and the CPU 23 and is controlled by the CPU 23. Also, the pulse generation unit 26 is connected to the pulse generation power supply 28 and the CPU 23 and can generate a pulse signal a desired number of times by being controlled by the CPU 23. Also, the CPU 23 is connected to a memory area having a correlation table of write pulses and write bits as shown in FIG. 4, and can set the pulse count based on the result of reading the information in the write count storage area.

[0026] (Processing Flow of Writing Operation) FIG. 5 is a flowchart during the writing operation in the first embodiment. At step S201, the writing operation is started. Next, at step S202, the selector circuit 27 is switched so that the anti-fuse 10 in the write pulse number storage area 20 is selected. Next, at step S203, the state of the anti-fuse 10 into which the set value of the pulse number has been written is read out. After reading the write pulse number information, at step S204, the write pulse number is set.

[0027] When performing the writing operation, first at step S205, the selector circuit 27 selects the target anti-fuse 10. Next, at step S208, the writing operation to the anti-fuse 10 is executed with the set write pulse number. Next, at step S207, a read operation is performed on the anti-fuse 10 on which the writing has been executed. Next, at step S208, based on the content read from the anti-fuse 10, it is determined whether there is a state change (whether writing has been performed).

[0028] Here, if it is determined that there is no state change (writing has not been executed) in the anti-fuse element Ca (S208 = No), the process proceeds to step S209. In step S209, the number of retry times is checked. If the number of retry times is less than 3 (S209 = Yes), the application of the set pulse number (S206), the read operation (S207), and the determination of whether there is a state change (S208) are performed again. On the other hand, if it is determined that the number of retry times is 3 or more (S209 = Yes), the process proceeds to step S210 to perform error processing, and then the process ends at step S211. Note that if it is determined that a state change has occurred (writing has been performed) in step S208 (Yes), the process directly proceeds to step S211 and ends the process.

[0029] As described above, according to this embodiment, before applying a pulse to the anti-fuse element Ca, the number of write pulses to the anti-fuse element Ca is determined according to the flow of FIG. 3. Therefore, since it is possible to supply an optimal number of pulses to the anti-fuse element Ca to be written, the write time is not prolonged, leading to a reduction in processing time.

[0030] <Example 2> Next, Example 2 will be described. Regarding the same configuration and operation as in Example 1, the same reference numerals may be used and the description may be simplified.

[0031] (Constituent block) FIG. 6 is a block diagram of a configuration for determining a write voltage in Example 2. In the non-volatile OTP memory 11 of Example 2, write conditions such as a write time, a write voltage, and a write count are also set. The non-volatile OTP memory 11 of Example 2 includes a write voltage storage area 30 that stores a write voltage, which is one of these write conditions, an applied voltage inspection area 31, and a write area 22. The applied voltage inspection area 31 has a plurality of anti-fuse elements Ca, and the target anti-fuse element Ca can be changed for each inspection voltage.

[0032] The write circuit 13 is connected to the CPU 23 and a write power supply 24. The read circuit 14 is connected to the CPU 23 and a read power supply 25. The circuit switching during writing / reading is controlled by the CPU 23. During writing, a high voltage is applied from the write power supply 24, and during reading, a weak current is supplied from the read power supply 25. When writing / reading, the circuit switching is controlled by the CPU 23. During writing, a high voltage is applied from the write power supply 24, and during reading, a weak current is supplied from the read power supply 25.

[0033] And the writing power supply 32 of the second embodiment has a voltage level conversion unit 33, and the voltage value can be changed by the CPU 23. Further, the anti-fuse 10 to be written / read is selected by switching the connection to the gate terminal of the corresponding transistor 12 by the selector circuit 27. The selector circuit 27 is connected to the pulse generation unit 26, and the pulse signal is applied to the gate terminal of the transistor 12 via the selector circuit 27.

[0034] Note that the selector circuit is connected to the CPU 23, and can be switched to the corresponding transistor 12 by the CPU 23. Further, the pulse generation unit 26 is connected to the pulse generation power supply 28 and the CPU 23, and can generate a pulse signal by being controlled by the CPU 23. Further, the CPU 23 is connected to a memory 29 including a non-volatile memory (e.g., ROM) and a volatile memory (e.g., RAM). A correlation table between the write voltage and the write bit is stored in the memory 29 of the second embodiment.

[0035] (Determination Flow of Write Voltage) FIG. 7 is a flowchart of the write voltage determination in the second embodiment. In step S301, the write voltage inspection is started. Next, in step S302, the selector circuit 27 is switched so that the anti-fuse 10 for 10V inspection in the write voltage storage area 30 is selected. Next, in step S303, the write voltage is set to 10V. Next, in step S304, the state of the anti-fuse 10 is read. Next, in step S305, the state check (whether it is written or not) of the read anti-fuse 10 is performed.

[0036] If it is determined by the check in step S305 that the read value is at the level assumed to be the state after writing, the process proceeds to step S306. In step S306, it is determined that there is an initial defect, and error processing is performed. On the other hand, if the state of the anti-fuse 10 read in step S305 is at the level assumed to be before writing, the process proceeds to step S307. In step S307, a predetermined pulse is applied at 10V. Next, in step S308, the state of the anti-fuse 10 is read again. Next, in step S309, a check is made for the presence or absence of a change in the state of the read anti-fuse 10.

[0037] If it is determined by the check in step S309 that there is no state change (not written), the process proceeds to step S310. In step S310, it is determined whether the current set value of the write voltage is less than a certain voltage (here 40V). If the set value is less than the predetermined voltage (S310 = Yes), the process proceeds to step S311, and the anti-fuse 10 in the applied voltage inspection area 31 is changed. Then the process proceeds to step S312, and the write voltage is increased (here +5V). After that, the flow from step S304 to S309 is repeated again.

[0038] The above process is repeated until the write voltage reaches a predetermined value (here 40V). And if there is no change in the anti-fuse 10 even when the write voltage is equal to or greater than the predetermined value (when S309 = No), the process proceeds to step S306, and it is determined that there is an initial defect and error processing is performed.

[0039] On the other hand, if it is determined as a result of increasing the write voltage by 5V each time and applying it that there is a change in the state of the anti-fuse 10 (the write operation has been completed normally) (when S309 = Yes), the process proceeds to step S313. In step S313, the selector circuit 27 is switched to the write voltage storage area 30. Next, in step S314, the voltage at which the state change occurred in the anti-fuse 10 is written. Next, in step S315, the process ends.

[0040] ​The write / read operation in Example 2, which is performed according to the applied voltage determined in this way, will be described. As described with reference to FIG. 6, the non-volatile OTP memory 11 has a write voltage storage area 30 that stores a write voltage, which is one of the write conditions, an applied voltage inspection area 31, and a write area 22, and is connected to a write circuit 13 and a read circuit 14 via the input A described in FIG. 1. The write circuit 13 is connected to the CPU 23 and a write power supply 32, and the read circuit 14 is connected to the CPU 23 and a read power supply 25. The switching of the write / read circuit is controlled by the CPU 23. Here, at the time of writing, a high voltage is applied from the write power supply 32, and at the time of reading, a weak current is supplied from the read power supply 25.

[0041] Here, the write power supply 32 can change the voltage value by a voltage level conversion unit 33 according to the signal of the CPU 23. Also, the anti-fuse 10 to be written / read is selected by switching the connection with the gate terminal of the corresponding transistor 12 by a selector circuit 27. The selector circuit 27 is connected to a pulse generation unit 26, and a pulse signal is applied to the gate terminal of the transistor 12 via the selector circuit 27. Also, the selector circuit 27 is connected to the CPU 23, and the CPU 23 can switch to the corresponding transistor 12. Also, the pulse generation unit 26 is connected to a pulse generation power supply 28 and the CPU 23, and can generate a pulse signal by being controlled by the CPU 23. Also, the CPU 23 is connected to a memory 29 including a non-volatile memory (for example, ROM) and a volatile memory (for example, RAM). A correlation table of the write voltage and the write bit is stored in the memory.

[0042] (Processing Flow of Write Operation) FIG. 8 is a flowchart during the writing operation in Example 2. In step S401, the writing operation is started. Next, in step S402, the selector circuit 27 is switched so that the anti-fuse 10 in the write voltage storage area 30 is selected. Next, in step S403, the state of the anti-fuse 10 written with the set value of the applied voltage is read. After reading the write voltage information, in step S404, the write voltage is set.

[0043] When performing the writing operation, first in step S405, the selector circuit 27 selects the target anti-fuse 10. Next, in step S406, the writing operation to the anti-fuse 10 is performed at the set write voltage. Next, in step S407, a read operation is performed on the anti-fuse 10 for which the writing has been executed. Next, in step S408, based on the content read from the anti-fuse 10, the presence or absence of a state change (the presence or absence of writing) is determined.

[0044] Here, if it is determined that there is no state change (writing has not been executed) in the anti-fuse element Ca (S408 = No), the process proceeds to step S409. In step S409, the number of retry times is checked. If the number of retry times is less than 3 (S409 = Yes), voltage application is performed again with the set value (S406), the read operation (S407), and the determination of the presence or absence of a state change (S408) are performed. On the other hand, if it is determined that the number of retry times is 3 or more (S409 = No), the process proceeds to step S410 to perform error processing, and then the process ends in step S411. Incidentally, if it is determined in step S408 that a state change has occurred (writing has been performed) (Yes), the process directly proceeds to step S411 to end the process.

[0045] As described above, according to this embodiment, since the write voltage is appropriately set before applying voltage to the anti-fuse element Ca, the write time is not prolonged, leading to a reduction in the processing time. <Example 3>

[0046] <Example 3> Next, Example 3 will be described. Regarding the configuration and operation similar to those of Examples 1 and 2, the same reference numerals may be used, and the description may be simplified.

[0047] (Configuration Blocks) FIG. 9 is a configuration block diagram during the write operation in Example 3. For the non-volatile OTP memory 11 of Example 3, write conditions such as write time, write voltage, and write count are also set. The non-volatile OTP memory 11 of Example 3 has a write pulse count storage area 20 that stores the write count, which is one of these write conditions, an applied pulse count inspection area 21, and a write area 22. The non-volatile OTP memory 11 is connected to a write circuit 13 and a read circuit 14 via the input A shown in FIG. 1.

[0048] The write circuit 13 is connected to the CPU 23 and a write power supply 24. The read circuit 14 is connected to the CPU 23 and a read power supply 25. The circuit switching during writing and reading is controlled by the CPU 23. During writing, a high voltage is applied from the write power supply 24, and during reading, a weak current is supplied from the read power supply 25. Also, the anti-fuse 10 to be written / read is selected by switching the connection between the gate terminal of the transistor 12 connected to the output B shown in FIG. 1 and the pulse generation unit 26 by a selector circuit 27. The selector circuit 27 is connected to the pulse generation unit 26 and the CPU 23, and is controlled by the CPU 23. Also, the pulse generation unit 26 is connected to a pulse generation power supply 28 and the CPU 23, and by being controlled by the CPU 23, it is possible to generate a pulse signal a desired number of times.

[0049] Also, in Embodiment 3, a temperature detection unit 34 connected to the CPU 23 is provided near the non-volatile OTP memory 11. The temperature detection unit 34 can be of any type as long as it can detect temperature. For example, a temperature sensor made of a diode can be used. The placement location of the temperature detection unit 34 is preferably near the non-volatile OTP memory. Specifically, it is preferably close enough so that temperature changes can be detected with the required accuracy. Also, the CPU 23 is connected to the memory 29. The memory 29 stores a correlation table of write pulses and write bits as shown in FIG. 4, in addition to a correlation table of temperature and the number of write pulses as shown in FIG. 11. Thereby, the CPU 23 can generate the number of pulses based on the information in the write pulse number storage area 20 and the temperature information detected by the temperature detection unit 34.

[0050] (Processing Flow of Write Operation) FIG. 10 is a flowchart during the write operation in an embodiment of the present invention. At step S501, the write operation is started. Next, at step S502, the selector circuit 27 is switched so that the anti-fuse 10 in the write pulse number storage area 20 is selected. Next, at step S503, the state of the anti-fuse 10 with the set value of the number of pulses written is read. After reading the write pulse number information, at step S504, the number of write pulses is set.

[0051] Here, it is known that due to the characteristics of the anti-fuse, the higher the temperature, the less likely the state change occurs, and when the temperature exceeds a certain threshold, it cannot be blown regardless of the number of pulses. Therefore, in Embodiment 3, at step S505, the temperature of the anti-fuse 10 is detected by the temperature detection unit 34 arranged around the anti-fuse element Ca, and the temperature information is acquired. Next, at step S506, it is determined whether the temperature exceeds a predetermined threshold (here, 100°C) or is below the threshold.

[0052] If the temperature exceeds the threshold value (S506 = No), the process proceeds to step S507, and in order to lower the temperature, a wait control for a certain period of time (here, 1 second) is inserted. After the end of the wait control, the temperature information is acquired again (S505), and a determination is made (S506). On the other hand, if the temperature information is below the threshold value (S506 = Yes), the process proceeds to step S508. In step S508, referring to the table of temperature and additional applied pulse number as shown in FIG. 11, the additional pulse number is determined.

[0053] When performing the writing operation, first, in step S509, the selector circuit 27 selects the target anti-fuse 10. Next, in step S510, the writing operation to the anti-fuse 10 is executed with the set number of writing pulses. Next, in step S511, a reading operation is performed on the anti-fuse 10 for which the writing has been executed. Next, in step S512, based on the content read from the anti-fuse 10, the presence or absence of a state change (the presence or absence of writing) is determined.

[0054] Here, if it is determined that there is no state change (writing has not been executed) in the anti-fuse element Ca, the process proceeds to step S513. In step S513, the number of retry times is checked. If the number of retry times is less than 3 (S513 = Yes), the writing execution (S510), the reading operation (S511), and the determination of the presence or absence of a state change (S512) are performed again. On the other hand, if it is determined that the number of retry times is 3 or more (S513 = Yes), the process proceeds to step S514 to perform error processing, and then the process ends in step S515. In addition, if it is determined in step S512 that a state change has occurred (writing has been performed) (Yes), the process directly proceeds to step S515 and the process ends.

[0055] As described above, according to this embodiment, before applying a pulse to the anti-fuse element Ca, the temperature of the environment is measured, and the number of write pulses to the anti-fuse element Ca is determined with reference to the detected temperature information. Therefore, since the optimal number of pulses can be supplied to the anti-fuse element Ca to be written, the writing time is not prolonged, leading to a reduction in processing time. Note that in this embodiment, the temperature information is combined with the determination of the number of pulses, but the temperature information may be combined with the control of the voltage magnitude.

[0056] <Example 4> Subsequently, Example 4 will be described. Regarding the configuration and operation similar to those of Examples 1 to 3, the same reference numerals will be used, and the description may be simplified. Example 4 will describe a liquid ejection device to which the storage device of each of the above examples is applied.

[0057] FIG. 12 is a schematic configuration diagram showing an example of the overall configuration of an inkjet type liquid ejection device 100 (recording device) according to Example 4. The liquid ejection device 100 includes a liquid ejection head 110 (recording head), a carriage 120, and a controller 130 which is a control unit for performing drive control thereof.

[0058] The liquid ejection head 110 is provided with a plurality of nozzles (discharge ports) for discharging a liquid such as ink. The liquid ejection head 110 also includes a semiconductor substrate (recording element substrate) provided with a plurality of liquid ejection elements corresponding to the plurality of nozzles. The liquid ejection head 110 drives each liquid ejection element based on a control signal from the controller 130. Thereby, ink is ejected from the corresponding nozzle, and desired recording is performed on the recording medium P. The recording medium P is typically a sheet-like paper material, but is not limited thereto.

[0059] The carriage 120 that supports the liquid ejection head 110 is reciprocally moved in the direction of arrow d1 along the guide 140 based on a control signal from the controller 130. The recording medium P is It is conveyed in the direction d2 by the conveyance mechanism of the liquid ejection device 100. The controller 130 can record a desired image on the recording medium P by performing drive control of the liquid ejection head 110 while reciprocating the carriage 120.

[0060] FIG. 13 is a schematic diagram showing an example of the configuration of the liquid ejection head 110. The liquid ejection head 110 includes a functional unit 200 for realizing a recording function which is the main function, and a storage device 300 capable of storing predetermined information. The functional unit 200 and the storage device 300 may be provided on the same semiconductor substrate or on different semiconductor substrates.

[0061] The functional unit 200 includes a plurality of liquid ejection elements 210 (recording elements) and an element drive unit 220 capable of individually driving these plurality of liquid ejection elements 210. As the drive source of the liquid ejection element 210, a heater element, an electrothermal conversion element, a piezoelectric element, etc. are suitable, but not limited thereto. The storage device 300 can store the unique information of the liquid ejection head 110. Examples of the unique information include an identifier, a serial number, a unique parameter, etc. The storage device 300 includes a non-volatile OTP memory 11. Further, in addition to that, the storage device 300 may include at least a part of the circuit related to the control and read / write of the non-volatile OTP memory 11 as described in the above embodiment.

[0062] In the liquid ejection device 100 according to the present embodiment, since the writing time for the non-volatile OTP memory 11 having the anti-fuse element Ca does not become longer, it is possible to shorten the time required for image recording.

[0063] [Configuration 1] A memory unit composed of an anti-fuse element, the memory unit including a write condition storage area for storing write conditions and a write area where information is written. A control unit that performs a write operation and a read operation on the memory unit by controlling the voltage applied to the anti-fuse element, wherein a pulse-shaped write voltage having a constant period is applied to the anti-fuse element during the write operation. A storage device comprising: The control unit controls the write conditions by referring to the write condition storage area during the write operation. A storage device characterized by the above. [Configuration 2] The memory unit further includes an inspection area used for an inspection to determine the write conditions. The control unit determines the write conditions based on the result of applying the write voltage to the anti-fuse elements in the inspection area, and stores the determined write conditions in the write condition storage area. The storage device according to Configuration 1, characterized by the above. [Configuration 3] The control unit applies the write voltage to the anti-fuse elements in the inspection area while changing the write conditions, and stores the write conditions when the write operation to the anti-fuse elements is normally completed in the write condition storage area. The storage device according to Configuration 2, characterized by the above. [Configuration 4] The write condition is the number of pulses of the write voltage applied to the anti-fuse element. The storage device according to any one of Configurations 1 to 3, characterized by the above. [Configuration 5] The write condition is the magnitude of the write voltage applied to the anti-fuse element. The storage device according to any one of Configurations 1 to 3, characterized by the above. [Configuration 6] The storage device further includes a temperature detection unit that detects temperature information of the memory unit. The control unit determines the write conditions based on the temperature information. The memory device according to Configuration 2 or 3, characterized in that... [Configuration 7] When the temperature information exceeds a predetermined threshold during the writing operation, the control unit performs wait control to lower the temperature. The memory device according to Configuration 6, characterized in that...

Explanation of Signs

[0064] 10: Anti-fuse, 11: Non-volatile OTP memory, 20: Write count storage area, 21: Applied pulse number inspection area, 22: Write area, 23: CPU

Claims

1. A memory unit composed of anti-fuse elements, the memory unit including a write condition storage area for storing write conditions and a write area where information is written, A control unit that performs a write operation and a read operation on the memory unit by controlling a voltage applied to the anti-fuse elements, and applies a pulse-shaped write voltage having a constant period to the anti-fuse elements during the write operation, the control unit, A storage device comprising: The control unit controls the write conditions by referring to the write condition storage area during the write operation A storage device characterized by the above.

2. The memory unit further includes an inspection area used for an inspection to determine the write conditions, The control unit determines the write conditions based on the result of applying the write voltage to the anti-fuse elements in the inspection area, and stores the determined write conditions in the write condition storage area The storage device according to claim 1, characterized by the above.

3. The control unit applies the write voltage to the anti-fuse elements in the inspection area while changing the write conditions, and stores the write conditions when the write operation on the anti-fuse elements is normally completed in the write condition storage area The storage device according to claim 2, characterized by the above.

4. The write condition is the number of pulses of the write voltage applied to the anti-fuse elements The storage device according to any one of claims 1 to 3, characterized by the above.

5. The write condition is the magnitude of the write voltage applied to the anti-fuse elements The storage device according to any one of claims 1 to 3, characterized by the above.

6. The storage device further includes a temperature detection unit that detects temperature information of the memory unit, The control unit determines the write conditions based on the temperature information The storage device according to claim 2 or 3, characterized by the above.

7. When the temperature information exceeds a predetermined threshold during the write operation, the control unit performs wait control to lower the temperature The storage device according to claim 6, characterized by the above.

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