Silicon-on-insulator substrate including trap-rich layer and method for manufacturing the same

Abstract

To provide a silicon-on-insulator (SOI) substrate having a trap rich layer and a method for manufacturing the SOI substrate.SOLUTION: An SOI substrate includes a high resistivity base layer including a trap rich region including silicon and arsenic diffused into a first side, a silicon dioxide layer located on the first side and having a thickness in the range of 1000-5000 angstroms, and a transfer layer located on the silicon dioxide layer. The trap rich region has a thickness in the range of 1 to 10 microns and a trap density in the range of 0.8×1010 cm2 eV-1 to 1.2×1010 cm2 eV-1, the high resistivity base layer has a resistivity in the range of 50 to 100 ohm-meters and a thickness in the range of 500 to 700 microns, and the transfer layer includes a silicon wafer and has a thickness in the range of 500 to 5000 angstroms.SELECTED DRAWING: None

Description

Technical Field

[0001] Cross - reference to related applications This application is related to and claims the benefit of U.S. Provisional Patent Application No. 62 / 911,827, filed on October 7, 2019, entitled "Silicon-on-Insulator Substrate Containing a Trap Rich Layer and Method of Making the Same", U.S. Provisional Patent Application No. 62 / 911,835, filed on October 7, 2019, entitled "Silicon-on-Insulator Substrate Containing a Trap Rich Layer and Method of Making the Same", and U.S. Provisional Patent Application No. 62 / 911,843, filed on October 7, 2019, entitled "Silicon-on-Insulator Substrate Containing a Trap Rich Layer and Method of Making the Same", and is an international (PCT) patent application, the entire contents of these provisional patent applications being incorporated herein by reference in their entirety.

[0002] The field of the present invention relates to silicon-on-insulator substrates and methods of making such substrates. In particular, the field of the present invention relates to silicon-on-insulator substrates having a trap rich layer and methods of making such substrates.

Background Art

[0003] Integrated chips are formed on a substrate containing a semiconductor material. Conventionally, integrated chips have been formed on a bulk substrate containing a solid layer of semiconductor material. More recently, silicon-on-insulator substrates have emerged as an alternative. A silicon-on-insulator (SOI) substrate is a substrate having a thin layer of active silicon separated from a lower handle wafer. A layer of insulating material electrically insulates the thin layer of active silicon from the handle wafer, thereby reducing current leakage in the devices formed within the thin layer of active silicon. The thin layer of active silicon provides fast switching times and low operating voltages, thereby enabling the production of SOI substrates that are widely used for the manufacture of high-capacity radio frequency (RF) systems such as RF switches.

[0004] SOI substrates typically use handle wafers with high resistivity. By using handle wafers with high resistivity, SOI substrates can meet application requirements such as insulation between devices and the Q factor of passive components. However, if the doping of such high-resistivity handle wafers is low, depending on the type of charge present in the buried oxide layer on the handle wafer, carriers from the surface and subsurface regions of the handle wafer can increase along the surface of the high-resistivity handle wafer and form an accumulation layer or an inversion layer. The voltage applied to the devices within the upper thin layer of active silicon can interact with such an accumulation layer, resulting in parasitic surface conduction that can lead to unwanted crosstalk and / or non-linear distortion of the RF signal in the device.

Brief Description of the Drawings

[0005] With reference to the accompanying drawings, some embodiments of the present invention are described herein by way of example only. Referring specifically to the drawings in detail, it is emphasized that specific matters are shown for the purpose of exemplarily explaining embodiments of the present invention by way of example. In this regard, the description in conjunction with the drawings will clarify to those skilled in the art how embodiments of the present invention can be implemented.

[0006]

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[0007] In some embodiments, the substrate includes a high-resistivity base layer having a first side and a second side, a silicon nitride layer disposed on the first side of the high-resistivity base layer, a silicon dioxide layer disposed on the silicon nitride layer opposite to the high-resistivity base layer, and a silicon layer disposed on the silicon dioxide layer opposite to the silicon nitride layer.

[0008] In some embodiments, a method for fabricating a substrate includes providing a first silicon wafer having a first side and a second side, depositing a silicon nitride layer on the first side of the first silicon wafer, depositing a silicon dioxide layer on the opposite side of the first silicon wafer from the first side of the silicon nitride layer, providing a second silicon wafer, introducing a hydrogen implant into the second silicon wafer to define a cleavage plane, activating the silicon dioxide layer, bonding the second silicon wafer to the activated silicon dioxide layer to thereby produce an integrated wafer, annealing the integrated wafer, applying tension to the integrated wafer in one direction to separate the first silicon wafer and the second silicon wafer from each other, and cleaving the second silicon wafer at the cleavage plane to thereby fabricate a silicon-on-insulator substrate.

[0009] In some embodiments, the step of depositing the silicon nitride layer is performed using a high-density plasma chemical vapor deposition process. In some embodiments, the step of depositing the silicon dioxide layer is performed using a high-density plasma chemical vapor deposition process.

[0010] In some embodiments, the substrate includes a high-resistivity base layer having a first side and a second side, an arsenic layer diffused on the first side of the high-resistivity base layer, a silicon dioxide layer disposed on the first side of the high-resistivity base layer covering the arsenic layer, and a silicon layer disposed on the silicon dioxide layer on the side opposite to the arsenic layer.

[0011] In some embodiments, the method for fabricating a substrate includes providing a first silicon wafer having a first side and a second side, diffusing an arsenic layer on the first side of the first silicon wafer, depositing a silicon dioxide layer on the first side of the high-resistivity base layer covering the arsenic layer, providing a second silicon wafer, introducing a hydrogen implant into the second silicon wafer to define a cleavage plane, activating the silicon dioxide layer, bonding the second silicon wafer to the activated silicon dioxide layer to thereby fabricate an integrated wafer, annealing the integrated wafer, applying a tension to the integrated wafer in one direction to separate the first silicon wafer and the second silicon wafer from each other, and cleaving the second silicon wafer at the cleavage plane by an edge of the second silicon wafer, thereby fabricating a silicon-on-insulator substrate.

[0012] In some embodiments, the step of diffusing the arsenic layer is performed by rotating (or spinning) a solution containing arsenic and diffusing arsenic for a controlled time under a controlled temperature. In some embodiments, the step of depositing the silicon dioxide layer is performed using a high-density plasma chemical vapor deposition process.

[0013] In some embodiments, a silicon-on-insulator substrate includes a layer structure including, in order, (1) a high-resistivity base layer having a first side and a second side opposite the first side, (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer, and (3) a transfer layer positioned on the silicon dioxide layer, the high-resistivity base layer including (a) silicon, and (b) a trap-rich region including arsenic diffused within the first side of the high-resistivity base layer, the trap-rich region having (i) a thickness in the range of 1 to 10 microns, and (ii) a trap density in the range of 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 , the high-resistivity base layer having (a) a low efficiency in the range of 50 to 100 ohm-meters, and (b) a thickness in the range of 500 to 700 microns, the silicon dioxide layer having a thickness in the range of 1000 to 5000 angstroms, the transfer layer including a silicon wafer, and having a thickness in the range of 500 to 5000 angstroms.

[0014] In some embodiments, the trap-rich region has a trap density in the range of 10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 . In some embodiments, the trap-rich region includes arsenic interspersed within the crystal structure of the silicon of the high-resistivity base layer. In some embodiments, the trap-rich region has a thickness in the range of 4 to 7 microns. In some embodiments, the high-resistivity base layer has a thickness in the range of 550 to 650 microns. In some embodiments, the silicon dioxide layer has a thickness in the range of 2000 to 4000 angstroms. In some embodiments, the transfer layer has a thickness in the range of 2000 to 3500 angstroms.

[0015] A method includes providing a first silicon wafer having a first side and a second side; applying an arsenic solution, which is a liquid colloidal solution, to the first side of the first silicon wafer; holding the first silicon wafer having the arsenic solution on the first side at a controlled temperature for a controlled time to bring about arsenic diffused on the first side of the first silicon wafer and generate a trap-rich region; depositing a silicon dioxide layer on the first side of the first silicon wafer using a high density plasma chemical vapor deposition (HDPCVD) process; providing a second silicon wafer having a first side and a second side opposite to the first side; introducing a hydrogen implant into the second silicon wafer to define a cleavage plane; activating the silicon dioxide layer; contacting the first side of the second silicon wafer with the activated silicon dioxide layer to generate an integrated wafer; annealing the integrated wafer; applying tension to the integrated wafer in one direction to separate the first silicon wafer and the second silicon wafer from each other; and cleaving the second silicon wafer at the cleavage plane at an edge of the second silicon wafer to thereby fabricate a silicon-on-insulator substrate. In the step of holding the first silicon wafer, the controlled time is in the range of 5 hours to 20 hours, the controlled temperature is in the range of 700 to 1200 degrees Celsius, the thickness of the trap-rich region is in the range of 1 to 10 microns, and the trap-rich region is 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1having a trap density within the range, in the step of depositing the silicon dioxide layer, the HDPCVD process uses an inductively coupled plasma source, the inductively coupled plasma source is driven at an output within the range of 65 watts to 225 watts, the HDPCVD process uses an oxygen gas flow, a silane gas flow, and an argon gas flow, the flow rate of the oxygen gas flow is within the range of 20 to 35 sccm, the flow rate of the silane gas flow is within the range of 20 to 35 sccm, the flow rate of the argon gas flow is within the range of 20 to 35 sccm, the HDPCVD process is carried out at a pressure within the range of 5 millitorr to 20 millitorr, the HDPCVD process is carried out using a bias power within the range of 0 to 100 watts, the HDPCVD process is carried out on the first silicon wafer maintained at a temperature within the range of 100 to 250 degrees Celsius, the deposition rate of the silicon dioxide layer is within the range of 900 to 1100 angstroms per minute, the thickness of the silicon dioxide layer is within the range of 1500 to 5000 angstroms, in the step of introducing a hydrogen implant into the second silicon wafer, a part of the thickness of the second silicon wafer between the first side of the second silicon wafer and the cleavage plane is within the range of 500 to 5000 angstroms, the step of activating the silicon dioxide layer includes low-pressure plasma activation bonding at a pressure within the range of 0.1 to 100 Pa, in the step of annealing the integrated wafer, the annealing is carried out at a temperature within the range of 200 to 400 degrees Celsius for a time within the range of 1 hour to 8 hours.

[0016] In some embodiments, the step of applying an arsenic solution to the first side of the first silicon wafer includes spin-coating the arsenic solution on the first side of the first silicon wafer. In some embodiments, the liquid colloidal solution includes glass infused with arsenic. In some embodiments, the flow rates of the oxygen gas flow, the silane gas flow, and the argon gas flow are identical to each other. In some embodiments, the flow rates of the oxygen gas flow, the silane gas flow, and the argon gas flow are selected to control the refractive index of the silicon dioxide layer. In some embodiments, the controlled time is selected to control the charge dissipation of the trap-rich layer. In some embodiments, the trap-rich region has a trap density in the range of 10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 . In some embodiments, arsenic scattered within the crystal structure of the silicon in the high-resistivity base layer is generated by the step of holding the first silicon wafer having the arsenic solution on the first side at a controlled temperature for a controlled time. In some embodiments, a trap-rich region having a thickness in the range of 4 microns to 7 microns is generated by the step of holding the first silicon wafer having the arsenic solution on the first side at a controlled temperature for a controlled time. In some embodiments, the high-resistivity base layer has a thickness in the range of 550 to 650 microns. In some embodiments, the silicon dioxide layer has a thickness in the range of 2000 to 4000 angstroms. In some embodiments, a portion of the thickness of the second silicon wafer between the first side of the second silicon wafer and the cleavage plane is in the range of 2000 to 3500 angstroms.

Embodiments for Carrying Out the Invention

[0017] Among the advantages and improvements of the disclosed invention, other objects and advantages of the present invention will become apparent from the following description in conjunction with the accompanying drawings. Detailed embodiments of the present invention are disclosed herein. However, it will be understood that the disclosed embodiments are merely exemplary of the present invention, which may be embodied in various forms. Further, each of the examples given in connection with the various embodiments of the present invention is intended to be illustrative and not limiting.

[0018] Throughout this specification and the claims, the following terms, unless the context clearly dictates otherwise, shall have the meanings explicitly associated with them herein. As used herein, the terms "in one embodiment," "in an embodiment," and "in some embodiments" may, but do not necessarily, refer to the same embodiment. Further, the terms "in another embodiment" and "in some other embodiments" as used herein may, but do not necessarily, refer to different embodiments. Thus, as described below, the various embodiments of the present invention can be readily combined without departing from the scope or spirit of the present invention.

[0019] As used herein, the term "based on" is not exclusive and allows for being based on additional factors not recited, unless the context clearly dictates otherwise. Further, throughout this specification, the meanings of "a," "an," and "the" include plural references. The meaning of "in" includes both "in" and "on."

[0020] Unless otherwise defined, all terms (including technical and scientific terms used herein) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries shall be interpreted to have a meaning that coincides with the meaning in the context of the relevant art and this disclosure, and shall not be interpreted in an idealized or overly formal sense unless explicitly so defined.

[0021] This disclosure describes exemplary embodiments of a miniaturized wearable infusion device. It will be apparent to those skilled in the art that the general principles embodied in the exemplary devices may be embodied in other devices as well.

[0022] As used herein, the term "trap rich layer" or "trap rich region" refers to a layer or region with a high density of electrically active carrier traps. Incorporating a trap rich layer or region into an SOI substrate significantly reduces the lifetime and mobility of free charge carriers while maintaining the effective resistance of the substrate. In some embodiments, the trap rich layer or region has a trap density greater than 10 10 cm 2 eV -1 . In some embodiments, the trap rich layer or region has a trap density of 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 . In some embodiments, the trap rich layer or region has a trap density of 0.9×10 10 cm 2 eV -1 ~1.1×10 10 cm 2 eV -1 . In some embodiments, the trap rich layer or region has a trap density of 10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 . In some embodiments, the trap rich layer or region has a trap density of 10 10 cm 2 eV -1 ~1.5×10 10 cm 2 eV -1 . In some embodiments, the trap rich layer or region has a trap density of 10 10 cm2 eV -1 ~2×10 10 cm 2 eV -1 has a trap density of. In some embodiments, the trap-rich layer or region has a trap density of 0.5×10 10 cm 2 eV -1 ~10 10 cm 2 eV -1 has a trap density of.

[0023] FIG. 1 shows a schematic diagram of a first exemplary device 100. In some embodiments, device 100 may be referred to as a silicon-on-insulator substrate. In some embodiments, device 100 has a layered structure. In some embodiments, device 100 includes a handle wafer 110 having a first side 112 and a second side 114 opposite the first side 112. In some embodiments, handle wafer 110 includes high resistivity silicon. In some embodiments, handle wafer 110 includes another suitable high resistivity material. In some embodiments, handle wafer 110 includes a material having a resistivity in the range of 50 to 100 ohm-meters. In some embodiments, the thickness of the handle wafer is in the range of 500 to 700 microns.

[0024] In some embodiments, device 100 includes a trap-rich layer 120 having a first side 122 and a second side 124 opposite the first side 122. In some embodiments, the trap-rich layer 120 is disposed adjacent to the handle wafer 110 such that the first side 122 of the trap-rich layer 120 contacts the second side 114 of the handle wafer 110. In some embodiments, the trap-rich layer 120 includes silicon nitride (or silicon nitride or silicon nitride; silicon nitride). In some embodiments, the trap-rich layer 120 includes a silicon nitride layer disposed adjacent to the handle wafer 110. In some embodiments, the trap-rich layer 120 has a thickness in the range of 100 to 1000 angstroms. In some embodiments, the trap-rich layer 120 has a thickness in the range of 100 to 400 angstroms. In some embodiments, the trap-rich layer 120 has a thickness in the range of 400 to 700 angstroms. In some embodiments, the trap-rich layer 120 has a thickness in the range of 700 to 1000 angstroms. In some embodiments, the trap-rich layer 120 has a thickness in the range of 100 to 700 angstroms. In some embodiments, the trap-rich layer 120 has a thickness in the range of 400 to 1000 angstroms. In some embodiments, a change in the thickness of the trap-rich layer 120 results in a corresponding change in the frequency separation value of the RF device fabricated using the device 100. In some embodiments, an increase in the thickness of the trap-rich layer 120 results in an increase in the resistivity of the trap-rich layer 120, thereby providing a corresponding increase in the frequency separation of the RF device fabricated using the device 100. In some embodiments, conversely, a decrease in the thickness of the trap-rich layer 120 results in a decrease in the resistivity of the trap-rich layer 120, thereby providing a corresponding decrease in the frequency separation of the RF device fabricated using the device 100.

[0025] In some embodiments, device 100 includes a silicon dioxide (or silica or silicon oxide; “SiO2”) layer 130 having a first side 132 and a second side 134 opposite the first side 132. In some embodiments, the SiO2 layer 130 is positioned adjacent to the trap-rich layer 120 such that the first side 132 of the SiO2 layer 130 is in contact with the second side 124 of the trap-rich layer 120. In some embodiments, the SiO2 layer 130 has a thickness in the range of 1000 to 5000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 1000 to 2000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 2000 to 3000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 3000 to 4000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 4000 to 5000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 1000 to 3000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 2000 to 4000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 3000 to 5000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 1000 to 4000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 2000 to 5000 angstroms. In some embodiments, a change in the thickness of the SiO2 layer 130 results in a corresponding change in the resistivity and capacitance of the SiO2 layer 130. In some embodiments, an increase in the thickness of the SiO2 layer 130 results in an increase in the resistivity of the SiO2 layer 130 and a decrease in the capacitance of the SiO2 layer 130. In some embodiments, conversely, a decrease in the thickness of the SiO2 layer 130 results in a decrease in the resistivity of the SiO2 layer 130 and an increase in the capacitance of the SiO2 layer 130.In some embodiments, the increase in resistance caused by the increase in the resistivity of the SiO2 layer 130 lengthens the time until the signal reaches the voltage threshold (i.e., the "on" speed is slow), while the decrease in resistance caused by the decrease in the resistivity of the SiO2 layer 130 has the effect of shortening the time until the signal reaches the voltage threshold (i.e., the "on" speed is fast). In some embodiments, the increase in the capacitance of the SiO2 layer 130 has the effect of lengthening the time until the decreasing signal bleeds off to a point below the voltage threshold (i.e., the "off" speed is slow), while the decrease in the capacitance of the SiO2 layer 130 has the effect of shortening the time until the decreasing signal bleeds off to a point below the voltage threshold (i.e., the "off" speed is fast). In some embodiments, an amplifier fabricated using the device 100 having faster "on" and "off" speeds will have a higher operating speed.

[0026] In some embodiments, device 100 includes a transfer layer (or moving layer or transport layer or transfer layer) 140 having a first side 142 and a second side 144 opposite the first side 142. In some embodiments, transfer layer 140 is disposed adjacent to SiO2 layer 130 such that the first side 142 of transfer layer 140 is in contact with the second side 134 of SiO2 layer 130. In some embodiments, transfer layer 140 has a thickness in the range of 500 to 5000 angstroms. In some embodiments, transfer layer 140 has a thickness in the range of 500 to 2000 angstroms. In some embodiments, transfer layer 140 has a thickness in the range of 2000 to 3500 angstroms. In some embodiments, transfer layer 140 has a thickness in the range of 3500 to 5000 angstroms. In some embodiments, transfer layer 140 has a thickness in the range of 500 to 3500 angstroms. In some embodiments, transfer layer 140 has a thickness in the range of 2000 to 5000 angstroms. In some embodiments, an increase in the thickness of transfer layer 140 results in an increase in the voltage threshold of the RF device fabricated using device 100. In some embodiments, conversely, a decrease in the thickness of transfer layer 140 results in a decrease in the voltage threshold of the RF device fabricated using device 100. In some embodiments, transfer layer 140 includes a silicon wafer.

[0027] FIG. 2 shows a flowchart of an exemplary method 200 for fabricating device 100. FIGS. 3A-3H show various intermediate products that exist during the implementation of exemplary method 200, and FIG. 3I shows the final product resulting from the implementation of exemplary method 200. In step 210, a first silicon wafer and a second silicon wafer are provided. In some embodiments, the thickness of each of the first silicon wafer and the second silicon wafer ranges from 500 to 700 microns. In some embodiments, the first silicon wafer is referred to herein as the handle wafer. As described above with reference to FIG. 1, in some embodiments, the handle wafer is high resistivity silicon. FIG. 3A shows a schematic view of the first silicon wafer and the second silicon wafer provided in step 210.

[0028] In process 220, a silicon nitride layer is deposited on the handle wafer provided in process 210. In some embodiments, the silicon nitride layer is deposited using a high-density plasma chemical vapor deposition (“HDPCVD”) process. It will be understood by those skilled in the art that HDPCVD is a specific form of plasma-enhanced chemical vapor deposition (“PECVD”) that uses either an inductively coupled plasma (“ICP”) source or an electron cyclotron resonance source to generate a higher plasma density than a standard PECVD system. In some embodiments, the HDPCVD process of process 220 is performed using an ICP source. In some embodiments, the HDPCVD process of process 220 is performed by introducing a mixture of multiple gas flows onto the handle wafer. In some embodiments, the gas mixture includes a flow of nitrogen (e.g., N2) gas, a flow of silane (e.g., SiH4), and a flow of argon (e.g., Ar). In some embodiments, the relative flow rates of the N2 gas, silane gas, and argon gas are varied to control the properties of the deposited film, such as the refractive index. For example, in some embodiments, a 1:1 flow rate ratio between the N2 gas and the silane gas provides a refractive index of 1.46, and the refractive index can be increased or decreased by changing this ratio. In some embodiments, increasing the flow rate of the silane gas compared to the flow rate of the N2 gas increases the silicon content of the silicon nitride layer, thereby decreasing the refractive index of the deposited film. In some embodiments, conversely, decreasing the flow rate of the silane gas compared to the flow rate of the N2 gas decreases the silicon content of the silicon nitride layer, thereby increasing the refractive index of the deposited film. FIG. 3B shows a schematic view of a first silicon wafer and a second silicon wafer on which a silicon nitride layer has been deposited after the implementation of process 220.

[0029] In some embodiments, the HDPCVD process of step 220 is carried out using a configured pressure. In some embodiments, the pressure is 5 millitorr to 20 millitorr. In some embodiments, the pressure is 5 millitorr to 10 millitorr. In some embodiments, the pressure is 10 millitorr to 15 millitorr. In some embodiments, the pressure is 15 millitorr to 20 millitorr. In some embodiments, the pressure is 5 millitorr to 15 millitorr. In some embodiments, the pressure is 10 millitorr to 20 millitorr. In some embodiments, the pressure is 7.5 millitorr to 12.5 millitorr. In some embodiments, the pressure is 9 millitorr to 11 millitorr. In some embodiments, the pressure is about 10 millitorr. In some embodiments, the pressure is 10 millitorr. In some embodiments, the pressure is 10 millitorr to 14 millitorr. In some embodiments, the pressure is 11 millitorr to 13 millitorr. In some embodiments, the pressure is about 12 millitorr. In some embodiments, the pressure is 12 millitorr. In some embodiments, changing the pressure can change the degree of film uniformity. For example, in some embodiments, a pressure of 12 millitorr produces a generally uniform film with about 1% non-uniformity and a slight bias towards the center of the wafer. In some embodiments, changing the pressure can change the velocity from the center to the edge, and as a result, it may be possible to adjust the uniformity. In some embodiments, the change in pressure is an area of influence (or sphere), resulting in a change corresponding to a device sphere where charge is shielded outside. In some embodiments, an increase in the pressure used during the HDPCVD process of step 220 produces a larger device sphere, and as a result, the deposition rate at the edge increases compared to the center. Conversely, in some embodiments, a decrease in the pressure used during the HDPCVD process of step 220 produces a smaller device sphere, and as a result, the deposition rate at the edge decreases compared to the center. As a result, in some embodiments, the pressure used during the HDPCVD process of step 220 can be adjusted to adjust the uniformity of the deposited film.

[0030] In some embodiments, the HDPCVD process of step 220 is performed using an ICP source operating at a configured ICP power (or power). In some embodiments, the ICP power is between 65 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 105 watts. In some embodiments, the ICP power is between 105 watts and 145 watts. In some embodiments, the ICP power is between 145 watts and 185 watts. In some embodiments, the ICP power is between 185 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 145 watts. In some embodiments, the ICP power is between 105 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, changing the ICP power changes the degree of film uniformity. In some embodiments, the change in ICP power is a range of influence, resulting in a corresponding change to the device sphere where charge is shielded outside that range. In some embodiments, an increase in the ICP power used during the HDPCVD process of step 220 produces smaller device spheres, thereby resulting in a decrease in the deposition rate at the edges compared to the center. Conversely, in some embodiments, a decrease in the ICP power used during the HDPCVD process of step 220 produces larger device spheres, thereby resulting in an increase in the deposition rate at the edges compared to the center. As a result, in some embodiments, the ICP power used during the HDPCVD process of step 220 can be adjusted to adjust the uniformity of the deposited film.

[0031] In some embodiments, the HDPCVD process of step 220 is performed using a configured bias power (or bias power or bias force). In some embodiments, the bias power is from 0 to 100 watts. In some embodiments, the bias power is from 0 watts to 25 watts. In some embodiments, the bias power is from 25 watts to 50 watts. In some embodiments, the bias power is from 50 watts to 75 watts. In some embodiments, the bias power is from 75 watts to 100 watts. In some embodiments, the bias power is from 0 watts to 50 watts. In some embodiments, the bias power is from 25 watts to 75 watts. In some embodiments, the bias power is from 50 watts to 100 watts. In some embodiments, the bias power is from 0 watts to 75 watts. In some embodiments, the bias power is from 25 watts to 100 watts. In some embodiments, changing the bias power changes the density of the film. In some embodiments, changing the bias power changes the proportion of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, an increase in bias power increases the velocity of hydrogen in the plasma state, thereby producing a film with a lower hydrogen content. In some embodiments, conversely, a decrease in bias power decreases the velocity of hydrogen in the plasma state, thereby producing a film with a higher hydrogen content. In some embodiments, changing the bias power changes the uniformity of the film. In some embodiments, increasing the bias power increases the electrode field generated from the lower electrode, thereby increasing the uniformity of the film. In some embodiments, conversely, decreasing the bias power decreases the electrode field generated from the lower electrode, thereby decreasing the uniformity of the film.

[0032] In some embodiments, the HDPCVD process of step 220 is performed using a handle wafer maintained at a configured temperature. In some embodiments, the temperature is from 100 degrees Celsius to 250 degrees Celsius. In some embodiments, the temperature is from 100 degrees Celsius to 150 degrees Celsius. In some embodiments, the temperature is from 150 degrees Celsius to 200 degrees Celsius. In some embodiments, the temperature is from 200 degrees Celsius to 250 degrees Celsius. In some embodiments, the temperature is from 100 degrees Celsius to 200 degrees Celsius. In some embodiments, the temperature is from 150 degrees Celsius to 250 degrees Celsius. In some embodiments, changing the temperature of the handle wafer changes the proportion of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser, and films with higher hydrogen content are less dense. In some embodiments, increasing the temperature of the handle wafer decreases the hydrogen content of the film. In some embodiments, conversely, decreasing the temperature of the handle wafer increases the hydrogen content of the film. In some embodiments, changing the handle wafer temperature changes the film deposition rate. In some embodiments, increasing the temperature of the handle wafer decreases the RF energy required to decompose silane gas into silicon and hydrogen, increases the recombination time, thereby increasing the deposition rate. Conversely, in some embodiments, decreasing the temperature of the handle wafer increases the RF energy required to decompose silane gas into silicon and hydrogen, shortens the recombination time, thereby decreasing the deposition rate.

[0033] In some embodiments, the HDPCVD process of step 220 is carried out at a configured flow rate of N2 gas. In some embodiments, the flow rate of N2 gas is in the range of 20 to 35 standard cubic centimeters per minute (sccm). In some embodiments, the flow rate of N2 gas is in the range of 20 to 25 sccm. In some embodiments, the flow rate of N2 gas is in the range of 25 to 30 sccm. In some embodiments, the flow rate of N2 gas is in the range of 30 to 35 sccm. In some embodiments, the flow rate of N2 gas is in the range of 20 to 30 sccm. In some embodiments, the flow rate of N2 gas is in the range of 25 to 35 sccm.

[0034] In some embodiments, the HDPCVD process of step 220 is carried out at a configured flow rate of silane gas. In some embodiments, the flow rate of silane gas is in the range of 20 to 35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20 to 25 sccm. In some embodiments, the flow rate of silane gas is in the range of 25 to 30 sccm. In some embodiments, the flow rate of silane gas is in the range of 30 to 35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20 to 30 sccm. In some embodiments, the flow rate of silane gas is in the range of 25 to 35 sccm.

[0035] In some embodiments, the HDPCVD process of step 220 is carried out at a configured flow rate of argon gas. In some embodiments, the flow rate of argon gas is in the range of 20 to 35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20 to 25 sccm. In some embodiments, the flow rate of argon gas is in the range of 25 to 30 sccm. In some embodiments, the flow rate of argon gas is in the range of 30 to 35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20 to 30 sccm. In some embodiments, the flow rate of argon gas is in the range of 25 to 35 sccm.

[0036] In some embodiments, the parameters of the HDPCVD process of step 220 are configured to provide a controlled deposition rate of the silicon nitride layer on the handle wafer. In some embodiments, the deposition rate of the silicon nitride layer is 300 to 500 angstroms per minute. In some embodiments, the deposition rate of the silicon nitride layer is 350 to 450 angstroms per minute. In some embodiments, the deposition rate of the silicon nitride layer is 375 to 425 angstroms per minute. In some embodiments, the deposition rate of the silicon nitride layer is about 400 angstroms per minute. In some embodiments, the deposition rate of the silicon nitride layer is 400 angstroms per minute.

[0037] In some embodiments, the parameters of the HDPCVD process of step 220 are configured to provide a controlled thickness of the silicon nitride layer on the handle wafer. In some embodiments, the parameters of the HDPCVD process of step 220 are configured to provide a thickness of the silicon nitride layer that is 300 to 500 angstroms. In some embodiments, the thickness of the silicon nitride layer is 350 to 450 angstroms. In some embodiments, the thickness of the silicon nitride layer is 375 to 425 angstroms. In some embodiments, the thickness of the silicon nitride layer is about 400 angstroms. In some embodiments, the thickness of the silicon nitride layer is 400 angstroms. In some embodiments, the HDPCVD process of step 220 is performed for 1 minute.

[0038] Continuing to refer to FIG. 2, in step 230, a silicon dioxide layer is deposited on the handle wafer so as to cover the silicon nitride layer deposited in step 220. In some embodiments, the silicon dioxide layer is deposited by using an HDPCVD process. In some embodiments, the HDPCVD process of step 230 is implemented using an ICP source. In some embodiments, the HDPCVD process of step 230 is implemented by introducing a mixture of a plurality of gas flows into the handle wafer provided with the deposited silicon nitride layer. In some embodiments, the gas mixture includes a flow of oxygen gas (e.g., O2), a flow of silane (e.g., SiH4), and a flow of argon (e.g., Ar). In some embodiments, the HDPCVD process of step 230 is substantially a continuation of the HDPCVD process of step 220, but is for substituting oxygen gas used in step 230 for nitrogen gas used in step 220. FIG. 3C shows a schematic diagram of a first silicon wafer on which silicon nitride and silicon dioxide are deposited after the implementation of step 230 and a second silicon wafer.

[0039] In some embodiments, the HDPCVD process of step 230 is carried out using a configured pressure. In some embodiments, the pressure is from 5 millitorr to 20 millitorr. In some embodiments, the pressure is from 5 millitorr to 10 millitorr. In some embodiments, the pressure is from 10 millitorr to 15 millitorr. In some embodiments, the pressure is from 15 millitorr to 20 millitorr. In some embodiments, the pressure is from 5 millitorr to 15 millitorr. In some embodiments, the pressure is from 10 millitorr to 20 millitorr. In some embodiments, changing the pressure can change the degree of film uniformity. For example, in some embodiments, a pressure of 12 millitorr produces a generally uniform film with about 1% non-uniformity and a slight bias towards the center of the wafer. In some embodiments, changing the pressure can change the rate from the center to the edge, thereby making it possible to adjust the uniformity. In some embodiments, the change in pressure is the area of influence, resulting in a change corresponding to the device sphere where the charge is shielded outside. In some embodiments, an increase in the pressure used during the HDPCVD process of step 230 produces a larger device sphere, thereby resulting in an increase in the deposition rate at the edge compared to the center. Conversely, in some embodiments, a decrease in the pressure used during the HDPCVD process of step 230 produces a smaller device sphere, thereby resulting in a decrease in the deposition rate at the edge compared to the center. As a result, in some embodiments, the pressure used during the HDPCVD process of step 230 can be adjusted to adjust the uniformity of the deposited film.

[0040] In some embodiments, the HDPCVD process of step 230 is performed using an ICP source operating at a configured ICP power. In some embodiments, the ICP power is between 65 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 105 watts. In some embodiments, the ICP power is between 105 watts and 145 watts. In some embodiments, the ICP power is between 145 watts and 185 watts. In some embodiments, the ICP power is between 185 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 145 watts. In some embodiments, the ICP power is between 105 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, when the ICP power is changed, the degree of film uniformity changes. In some embodiments, the change in ICP power is an area of influence, resulting in a corresponding change to the device sphere where charges are shielded outside of it. In some embodiments, an increase in the ICP power used during the HDPCVD process of step 230 produces smaller device spheres, thereby resulting in a decrease in deposition rate at the edges compared to the center. Conversely, in some embodiments, a decrease in the ICP power used during the HDPCVD process of step 230 produces larger device spheres, thereby resulting in an increase in deposition rate at the edges compared to the center. As a result, in some embodiments, the ICP power used during the HDPCVD process of step 230 can be adjusted to adjust the uniformity of the deposited film.

[0041] In some embodiments, the HDPCVD process of step 230 is performed using a configured bias power. In some embodiments, the bias power is from 0 watts to 100 watts. In some embodiments, the bias power is from 0 watts to 25 watts. In some embodiments, the bias power is from 25 watts to 50 watts. In some embodiments, the bias power is from 50 watts to 75 watts. In some embodiments, the bias power is from 75 watts to 100 watts. In some embodiments, the bias power is from 0 watts to 50 watts. In some embodiments, the bias power is from 25 watts to 75 watts. In some embodiments, the bias power is from 50 watts to 100 watts. In some embodiments, the bias power is from 0 watts to 75 watts. In some embodiments, the bias power is from 25 watts to 100 watts. In some embodiments, changing the bias power changes the density of the film. In some embodiments, changing the bias power changes the proportion of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, an increase in bias power increases the velocity of hydrogen in the plasma state, thereby producing a film with a lower hydrogen content. In some embodiments, conversely, a decrease in bias power decreases the velocity of hydrogen in the plasma state, thereby producing a film with a higher hydrogen content. In some embodiments, changing the bias power changes the uniformity of the film. In some embodiments, increasing the bias power increases the electrode field generated from the lower electrode, thereby increasing the uniformity of the film. In some embodiments, conversely, decreasing the bias power decreases the electrode field generated from the lower electrode, thereby decreasing the uniformity of the film.

[0042] In some embodiments, the HDPCVD process of step 230 is performed using a handle wafer maintained at a configured temperature. In some embodiments, the temperature is between 100 degrees Celsius and 250 degrees Celsius. In some embodiments, the temperature is between 100 degrees Celsius and 150 degrees Celsius. In some embodiments, the temperature is between 150 degrees Celsius and 200 degrees Celsius. In some embodiments, the temperature is between 200 degrees Celsius and 250 degrees Celsius. In some embodiments, the temperature is between 100 degrees Celsius and 200 degrees Celsius. In some embodiments, the temperature is between 150 degrees Celsius and 250 degrees Celsius. In some embodiments, changing the handle wafer temperature changes the proportion of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser, and films with higher hydrogen content are less dense. In some embodiments, increasing the temperature of the handle wafer decreases the hydrogen content of the film. In some embodiments, conversely, decreasing the temperature of the handle wafer increases the hydrogen content of the film. In some embodiments, changing the handle wafer temperature results in a change in the deposition rate of the film. In some embodiments, increasing the temperature of the handle wafer decreases the RF energy required to decompose silane gas into silicon and hydrogen, increases the recombination time, and thereby increases the deposition rate. Conversely, in some embodiments, decreasing the temperature of the handle wafer increases the RF energy required to decompose silane gas into silicon and hydrogen, shortens the recombination time, and thereby decreases the deposition rate.

[0043] In some embodiments, the HDPCVD process of step 230 is carried out at a configured flow rate of O2 gas. In some embodiments, the flow rate of O2 gas is in the range of 20 - 35 sccm. In some embodiments, the flow rate of O2 gas is in the range of 20 - 25 sccm. In some embodiments, the flow rate of O2 gas is in the range of 25 - 30 sccm. In some embodiments, the flow rate of O2 gas is in the range of 30 - 35 sccm. In some embodiments, the flow rate of O2 gas is in the range of 20 - 30 sccm. In some embodiments, the flow rate of O2 gas is in the range of 25 - 35 sccm.

[0044] In some embodiments, the HDPCVD process of step 230 is carried out at a configured flow rate of silane gas. In some embodiments, the flow rate of silane gas is in the range of 20 - 35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20 - 25 sccm. In some embodiments, the flow rate of silane gas is in the range of 25 - 30 sccm. In some embodiments, the flow rate of silane gas is in the range of 30 - 35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20 - 30 sccm. In some embodiments, the flow rate of silane gas is in the range of 25 - 35 sccm.

[0045] In some embodiments, the HDPCVD process of step 230 is carried out at a configured flow rate of argon gas. In some embodiments, the flow rate of argon gas is in the range of 20 - 35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20 - 25 sccm. In some embodiments, the flow rate of argon gas is in the range of 25 - 30 sccm. In some embodiments, the flow rate of argon gas is in the range between 30 - 35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20 - 30 sccm. In some embodiments, the flow rate of argon gas is in the range of 25 - 35 sccm.

[0046] In some embodiments, the parameters of the HDPCVD process of step 230 are configured to provide a controlled deposition rate of the silicon dioxide layer on the handle wafer. In some embodiments, the deposition rate of the silicon dioxide layer is 900 to 1100 angstroms per minute. In some embodiments, the deposition rate of the silicon dioxide layer is 950 to 1050 angstroms per minute. In some embodiments, the deposition rate of the silicon dioxide layer is 975 to 1025 angstroms per minute. In some embodiments, the deposition rate of the silicon dioxide layer is about 1000 angstroms per minute. In some embodiments, the deposition rate of the silicon dioxide layer is 1000 angstroms per minute.

[0047] In some embodiments, the parameters of the HDPCVD process in step 230 are configured to provide a controlled thickness of the silicon dioxide layer on the handle wafer. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 2000 angstroms. In some embodiments, the thickness of the silicon dioxide is from 2000 to 2500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2500 to 3000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 3000 to 3500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 3500 to 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 4000 to 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 4500 to 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 2500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2000 to 3000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2500 to 3500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 3000 to 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 3500 to 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 4000 to 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 3000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2000 to 3500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2500 to 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 3000 to 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 3500 to 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 3500 angstroms.In some embodiments, the thickness of the silicon dioxide layer is from 2000 to 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2500 to 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 3000 to 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2000 to 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2500 to 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2000 to 5000 angstroms. In some embodiments, the HDPCVD process of step 230 is performed for a period of between 2 and 3 minutes to achieve a controlled thickness of the silicon dioxide layer.

[0048] Continuing to refer to FIG. 2, in step 240, a hydrogen implant is implanted into the second wafer. In some embodiments, the hydrogen implant is arranged to define a cleavage plane in the second wafer. In some embodiments, the cleavage plane defines the desired thickness of the second silicon wafer after completion of method 200. In some embodiments, the hydrogen implant is implanted using an ion implantation device. In some embodiments, the ion implantation device is an ion implantation device such as those commercialized by Nissin Ion Equipment Co., Ltd. of Kyoto, Japan. In some embodiments, the ion implantation device is configured to emit a beam of hydrogen ions. In some embodiments, the ion implantation device is configured to operate at a power of 5000 volts to 1 megavolt. In some embodiments, the desired thickness ranges from 500 to 5000 angstroms. In some embodiments, the desired thickness ranges from 500 to 2000 angstroms. In some embodiments, the desired thickness ranges from 2000 to 3500 angstroms. In some embodiments, the desired thickness ranges from 3500 to 5000 angstroms. In some embodiments, the desired thickness ranges from 500 to 3500 angstroms. In some embodiments, the desired thickness ranges from 2000 to 5000 angstroms. In some embodiments, the implanted hydrogen creates displacement defects in the form of interstitial atoms, vacancies, and complexes. In some embodiments, such defects create regions with a number of broken bonds called plateletlets. In some embodiments, hydrogen is trapped on these surfaces, passivating the broken bonds. FIG. 3D shows a schematic view of the first silicon wafer with the silicon nitride layer and the silicon dioxide layer deposited after the implementation of step 240, and the second silicon wafer implanted with the hydrogen implant.

[0049] Continuing to refer to FIG. 2, in step 250, the surface of the silicon dioxide layer deposited in step 230 is activated. In some embodiments, the activation is plasma activation implemented by impinging the surface of the silicon dioxide layer with short-lived chemical species generated within the plasma volume to initiate a chemical reaction at the surface and enable adhesion. In some embodiments, the activation is low-pressure plasma activation bonding at a pressure in the range of 0.1 to 100 Pa. FIG. 3E shows a schematic view of a first silicon wafer on which a silicon nitride and an activated silicon dioxide layer are deposited after the implementation of step 250, and a second silicon wafer into which a hydrogen implant has been implanted.

[0050] Continuing to refer to FIG. 2, in step 260, the first silicon wafer (on which a silicon nitride layer and a silicon dioxide layer are deposited) is bonded to a second silicon wafer such that the activated surface of the silicon dioxide layer faces the second silicon wafer, and after cleavage along the cleavage plane defined by hydrogen implantation, the desired portion of the second silicon wafer (i.e., the portion having the thickness described above) remains adjacent to the first silicon wafer. FIG. 3F shows a schematic view of the bonding of the first silicon wafer on which a silicon nitride layer and an activated silicon dioxide layer are deposited and the second silicon wafer into which a hydrogen implant has been implanted in accordance with the implementation of step 260.

[0051] Continuing to refer to FIG. 2, in step 270, the joined first silicon wafer and second silicon wafer are subjected to a low-temperature annealing process. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 250 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 to 300 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 300 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 350 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 300 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 300 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 degrees Celsius to 400 degrees Celsius. In some embodiments, the time of the annealing process is 1 hour to 8 hours. In some embodiments, during the annealing process, the trapped hydrogen described above with reference to step 240 dissociates from the complex and diffuses into the platelet to form H2 molecules. In some embodiments, due to the increase in pressure, the platelet expands within the minute cracks that join together in the same plane, causing delamination of the material. FIG. 3G shows a schematic diagram of the annealing process of step 270.

[0052] Continuing to refer to FIG. 2, in step 280, the joined first and second silicon wafers are placed under tension (i.e., tension is applied to pull the first and second silicon wafers apart from each other). In some embodiments, the tension is a force sufficient to generate a tension in the range of 10 to 60 pounds per square inch across the entire joined area. FIG. 3H shows a schematic diagram of the tensioning process of step 280.

[0053] Continuing to refer to FIG. 2, in step 290, the second silicon wafer is struck at the cleavage plane defined by hydrogen implantation. In some embodiments, to create a cleavage wave, a thin blade-like element is used to apply a force in the range of 5 to 10 pounds per square inch across the target area to strike the second silicon wafer. In some embodiments, the thin blade-like element is any suitable object having a suitable width. In some embodiments, the suitable width is about 50 microns. As a result of this striking, a portion of the second silicon wafer (which may be referred to herein as the "donor wafer") disposed between the hydrogen implant and the first silicon wafer remains attached to the first silicon wafer (which may be referred to herein as the "handle wafer"), and the remaining portion of the second silicon wafer is cleaved. Following this cleavage step, the final completed wafer is manufactured. FIG. 3I shows a schematic diagram of the completed wafer and the removed portion of the second silicon wafer after the implementation of step 290.

[0054] FIG. 4 shows a schematic diagram of a second exemplary device 400. In some embodiments, device 400 may be referred to as a silicon-on-insulator (SOI) substrate. In some embodiments, device 400 has a layered structure. In some embodiments, device 400 includes a handle wafer 410 having a first side 412 and a second side 414 opposite the first side 412. In some embodiments, handle wafer 410 includes high resistivity silicon. In some embodiments, handle wafer 410 includes another suitable high resistivity material. In some embodiments, handle wafer 410 includes a material having a resistivity in the range of 50 to 100 ohm-meters. In some embodiments, the thickness of the handle wafer is in the range of 500 to 700 microns. In some embodiments, the thickness of the handle wafer is in the range of 550 to 650 microns.

[0055] In some embodiments, device 400 includes a trap-rich layer 420 having a first side 422 and a second side 424 opposite the first side 422. In some embodiments, the trap-rich layer 420 is positioned within handle wafer 410 such that the first side 422 of the trap-rich layer 420 is positioned between the first side 412 and the second side 414 of handle wafer 410, and the second side 424 of the trap-rich layer 420 is disposed on the second side 414 of handle wafer 410. In some embodiments, the trap-rich layer 420 includes arsenic. In some embodiments, the trap-rich layer 420 includes diffused arsenic. In some embodiments, the trap-rich layer 420 includes a trap-rich arsenic region disposed within handle wafer 510 (e.g., diffused into its second side 414), e.g., a region where arsenic is scattered within the crystal structure of handle wafer 410. In some embodiments, the trap-rich layer 420 has a thickness in the range of 1 to 10 microns. In some embodiments, the trap-rich layer 420 has a thickness in the range of 1 to 4 microns. In some embodiments, the trap-rich layer 420 has a thickness in the range of 4 to 7 microns. In some embodiments, the trap-rich layer 420 has a thickness in the range of 7 to 10 microns. In some embodiments, the trap-rich layer 420 has a thickness in the range of 1 to 7 microns. In some embodiments, the trap-rich layer 420 has a thickness in the range of 4 to 10 microns. In some embodiments, a change in the thickness of the trap-rich layer 420 results in a corresponding change in the charge dissipation of the trap-rich layer 420. In some embodiments, the diffused arsenic forms broken bonds within the silicon lattice of the handle wafer, thereby providing a faster dissipation path and a faster dissipation rate. As a result, in some embodiments, lower frequencies produce a deeper (or larger) current flow, where an increase in the thickness of the trap-rich layer 420 results in a chip suitable for lower operating frequencies. In some embodiments, conversely, higher frequencies produce a shallower (or smaller) current flow, where a decrease in the thickness of the trap-rich layer 420 results in a chip suitable for higher operating frequencies.

[0056] In some embodiments, device 400 includes a silicon dioxide (“SiO2”) layer 430 having a first side 432 and a second side 434 opposite the first side 432. In some embodiments, the SiO2 layer 430 is disposed adjacent to the trap-rich layer 420 such that the first side 432 of the SiO2 layer 430 is adjacent to the second side 424 of the trap-rich layer 420. In some embodiments, the SiO2 layer 430 has a thickness in the range of 1000 to 5000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 1000 to 2000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 2000 to 3000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 3000 to 4000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 4000 to 5000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 1000 to 3000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 2000 to 4000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 3000 to 5000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 1000 to 4000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 2000 to 5000 angstroms. In some embodiments, a change in the thickness of the SiO2 layer 430 results in a corresponding change in the resistivity and capacitance of the SiO2 layer 430. In some embodiments, an increase in the thickness of the SiO2 layer 430 results in an increase in the resistivity of the SiO2 layer 430 and a decrease in the capacitance of the SiO2 layer 430. In some embodiments, conversely, a decrease in the thickness of the SiO2 layer 430 results in a decrease in the resistivity of the SiO2 layer 430 and an increase in the capacitance of the SiO2 layer 430.In some embodiments, the increase in resistance caused by the increase in the resistivity of the SiO2 layer 430 has the effect of increasing the time until the signal reaches the voltage threshold (i.e., the "on" speed is slower), while the decrease in resistance caused by the decrease in the resistivity of the SiO2 layer 430 has the effect of decreasing the time until the signal reaches the voltage threshold (i.e., the "on" speed is faster). In some embodiments, the increase in the capacitance of the SiO2 layer 430 has the effect of generating a longer time until the decaying signal bleeds off to a point where it is below the voltage threshold (i.e., the "off" speed is slower), while the decrease in the capacitance of the SiO2 layer 430 has the effect of generating a shorter time until the decaying signal bleeds off to a point where it is lower than the voltage threshold (i.e., the "off" speed is faster). In some embodiments, an amplifier fabricated using the device 400 with faster "on" and "off" speeds has a higher operating speed.

[0057] In some embodiments, device 400 includes a transfer layer 440 having a first side 442 and a second side 444 opposite the first side 442. In some embodiments, the transfer layer 440 is disposed adjacent to the SiO2 layer 430 such that the first side 442 of the transfer layer 440 is adjacent to the second side 434 of the SiO2 layer 430. In some embodiments, the transfer layer 440 has a thickness in the range of 500 to 5000 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 500 to 2000 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 2000 to 3500 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 3500 to 5000 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 500 to 3500 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 2000 to 5000 angstroms. In some embodiments, an increase in the thickness of the transfer layer 440 results in an increase in the voltage threshold of the RF device fabricated using the device 400. In some embodiments, conversely, a decrease in the thickness of the transfer layer 440 results in a decrease in the voltage threshold of the RF device fabricated using the device 400. In some embodiments, the transfer layer 440 includes a silicon wafer.

[0058] FIG. 5 shows a flowchart of an exemplary method 500 for fabricating device 400. FIGS. 6A-6H show various intermediate products that exist during the implementation of exemplary method 500, and FIG. 6I shows the final product of the implementation of exemplary method 500. In step 510, a first silicon wafer and a second silicon wafer are provided. In some embodiments, the thickness of each of the first silicon wafer and the second silicon wafer ranges from 500 to 700 microns. In some embodiments, the first silicon wafer is referred to herein as a handle wafer. As described above with reference to FIG. 4, in some embodiments, the handle wafer comprises high resistivity silicon. FIG. 6A shows a schematic view of the first silicon wafer and the second silicon wafer provided in step 510.

[0059] In step 520, an arsenic layer is diffused into the handle wafer provided in step 510. In some embodiments, the arsenic layer is applied by spin coating a liquid colloidal solution containing arsenic onto the handle wafer, followed by diffusing the arsenic into the handle wafer. In some embodiments, the liquid colloidal solution contains arsenic-doped glass. In some embodiments, the liquid colloidal solution is a solution commercialized under the trade name As-0200 by Desert Silicon of Tempe, Arizona. In some embodiments, the diffusion occurs for a controlled period and at a controlled temperature to produce a diffused arsenic layer having a desired depth. In some embodiments, when a dopant (e.g., arsenic) diffuses into a silicon crystal (e.g., the handle wafer provided in step 510), the silicon crystal consists of a solid lattice of atoms through which the dopant needs to move. The dopant can continue to diffuse as long as the concentration gradient is balanced or until the temperature drops and the dopant atoms can no longer move. As a result, a longer period during which diffusion can occur results in a diffused arsenic layer having a greater depth, and a higher controlled temperature during the diffusion process results in a diffused arsenic layer having a greater depth.

[0060] In some embodiments, the diffusion process of step 520 is performed using a configured temperature. In some embodiments, the temperature is from 700 degrees Celsius to 1200 degrees Celsius. In some embodiments, the temperature is from 800 degrees Celsius to 1200 degrees Celsius. In some embodiments, the temperature is from 900 degrees Celsius to 1200 degrees Celsius. In some embodiments, the temperature is from 1000 degrees Celsius to 1200 degrees Celsius. In some embodiments, the temperature is from 1100 degrees Celsius to 1200 degrees Celsius. In some embodiments, the temperature is from 700 degrees Celsius to 1100 degrees Celsius. In some embodiments, the temperature is from 800 degrees Celsius to 1100 degrees Celsius. In some embodiments, the temperature is from 900 degrees Celsius to 1100 degrees Celsius. In some embodiments, the temperature is from 1000 degrees Celsius to 1100 degrees Celsius. In some embodiments, the temperature is from 700 degrees Celsius to 1000 degrees Celsius. In some embodiments, the temperature is from 800 degrees Celsius to 1000 degrees Celsius. In some embodiments, the temperature is from 900 degrees Celsius to 1000 degrees Celsius. In some embodiments, the temperature is from 700 degrees Celsius to 900 degrees Celsius. In some embodiments, the temperature is from 800 degrees Celsius to 900 degrees Celsius. In some embodiments, the temperature is from 700 degrees Celsius to 800 degrees Celsius. In some embodiments, as described above, as the temperature increases, the depth of the diffused arsenic layer increases, and as the temperature decreases, the depth of the diffused arsenic layer decreases. As a result, in some embodiments, the temperature used during the diffusion process of step 520 can be adjusted to adjust the depth of the trap-rich layer. Thereby, characteristics (e.g., the charge dissipation and the frequency of the device described above) corresponding to the depth of the trap-rich layer can be adjusted.

[0061] In some embodiments, the diffusion process of step 520 is performed by diffusing arsenic for a configured period. In some embodiments, the period is from 5 hours to 20 hours. In some embodiments, the period is from 8 hours to 20 hours. In some embodiments, the period is from 11 hours to 20 hours. In some embodiments, the period is from 14 hours to 20 hours. In some embodiments, the period is from 17 hours to 20 hours. In some embodiments, the period is from 5 hours to 17 hours. In some embodiments, the period is from 8 hours to 17 hours. In some embodiments, the period is from 11 hours to 17 hours. In some embodiments, the period is from 14 hours to 17 hours. In some embodiments, the period is from 5 hours to 14 hours. In some embodiments, the period is from 8 hours to 14 hours. In some embodiments, the period is from 11 hours to 14 hours. In some embodiments, the period is from 5 hours to 11 hours. In some embodiments, the period is from 8 hours to 11 hours. In some embodiments, the period is from 5 hours to 8 hours. In some embodiments, as described above, an increase in the period during which diffusion occurs results in an increase in the depth of the diffused arsenic layer, while a decrease in the period during which diffusion occurs results in a decrease in the depth of the diffused arsenic layer. As a result, in some embodiments, the period during which diffusion occurs during the diffusion process of step 520 can be adjusted to adjust the depth of the trap-rich layer. Thereby, characteristics (e.g., the dissipation of charge and the frequency of the device described above) corresponding to the depth of the trap-rich layer can be adjusted. FIG. 6B shows a schematic diagram of a first silicon wafer with a diffused arsenic layer and a second silicon wafer after the implementation of step 520. FIG. 7A shows an exemplary state (or rendering) of the arsenic concentration in the first silicon wafer after the implementation of step 520. FIG. 7B shows a graph of the arsenic concentration versus depth in the exemplary state of FIG. 7A. From FIGS. 7A and 7B, it can be seen that arsenic penetrates to a depth within the first silicon wafer (e.g., to a depth of 1 micron to 10 microns as described above), the concentration of arsenic is maximum at the surface of the first silicon wafer, and decreases below the surface.

[0062] In some embodiments, instead of applying arsenic by coating it on a silicon wafer and diffusing the arsenic into the silicon wafer, arsenic is applied to the silicon wafer by ion implantation. In some embodiments, the ion implantation process includes emitting a beam of high-energy arsenic ions onto the handle wafer provided in step 510. In some embodiments, by emitting such a beam, the arsenic penetrates and remains within the handle wafer. In some embodiments, the collisions between arsenic ions and the atoms of the silicon lattice during such a process cause strain and weakening of the crystal structure of the silicon. In some embodiments, to address such strain, an annealing process is performed following the emission of the beam of high-energy arsenic ions. FIG. 7C shows an exemplary state of the arsenic concentration in the first silicon wafer after application by ion implantation. FIG. 7D shows a graph of the arsenic concentration versus depth in the exemplary state of FIG. 7C. From FIGS. 7C and 7D, it can be seen that the arsenic penetrates to a depth within the first silicon wafer (e.g., up to a depth of 1 micron to 10 microns as described above), the concentration of the arsenic is maximized slightly below the surface, and decreases both towards the surface and further below the surface.

[0063] Continuing to refer to FIG. 5, in step 530, a silicon dioxide layer is deposited on the handle wafer to cover the arsenic layer diffused into the handle wafer in step 520. In some embodiments, the silicon dioxide layer is deposited by using an HDPCVD process. In some embodiments, the HDPCVD process of step 530 is implemented using an inductively coupled plasma (“ICP”) source. In some embodiments, the HDPCVD process of step 530 is implemented by introducing a mixture of a plurality of gas flows into the handle wafer in which the arsenic layer is diffused. In some embodiments, the gas mixture includes a flow of oxygen gas (e.g., O2), a flow of silane (e.g., SiH4), and a flow of argon (e.g., Ar). FIG. 6C shows a schematic view of a first silicon wafer in which the arsenic layer is diffused internally and the silicon dioxide layer is deposited after the implementation of step 530, and a second silicon wafer.

[0064] In some embodiments, the HDPCVD process of step 530 is performed using a configured pressure. In some embodiments, the pressure is 5 millitorr to 20 millitorr. In some embodiments, the pressure is 5 millitorr to 10 millitorr. In some embodiments, the pressure is 10 millitorr to 15 millitorr. In some embodiments, the pressure is 15 millitorr to 20 millitorr. In some embodiments, the pressure is 5 millitorr to 15 millitorr. In some embodiments, the pressure is 10 millitorr to 20 millitorr. In some embodiments, changing the pressure can change the degree of film uniformity. For example, in some embodiments, a pressure of 12 millitorr produces a generally uniform film with about 1% non-uniformity and a slight bias towards the center of the wafer. In some embodiments, changing the pressure can change the rate from the center to the edge, thereby making it possible to adjust the uniformity. In some embodiments, the change in pressure is the area of influence and results in a change corresponding to the device sphere where the charge is shielded outside. In some embodiments, an increase in the pressure used during the HDPCVD process of step 530 produces a larger device sphere, thereby resulting in an increase in the deposition rate at the edge compared to the center. Conversely, in some embodiments, a decrease in the pressure used during the HDPCVD process of step 530 produces a smaller device sphere, thereby resulting in a decrease in the deposition rate at the edge compared to the center. As a result, in some embodiments, the pressure used during the HDPCVD process of step 530 can be adjusted to adjust the uniformity of the deposited film.

[0065] In some embodiments, the HDPCVD process of step 530 is performed using an ICP source operating at a configured ICP power. In some embodiments, the ICP power is between 65 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 105 watts. In some embodiments, the ICP power is between 105 watts and 145 watts. In some embodiments, the ICP power is between 145 watts and 185 watts. In some embodiments, the ICP power is between 185 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 145 watts. In some embodiments, the ICP power is between 105 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, a change in the ICP power results in a change in the degree of film uniformity. In some embodiments, the change in the ICP power is the scope of influence, resulting in a corresponding change to the device sphere where charges are shielded outside thereof. In some embodiments, an increase in the ICP power used during the HDPCVD process of step 530 produces smaller device spheres, thereby resulting in a decrease in the deposition rate at the edge compared to the center. Conversely, in some embodiments, a decrease in the ICP power used during the HDPCVD process of step 530 produces larger device spheres, thereby resulting in an increase in the deposition rate at the edge compared to the center. As a result, in some embodiments, the ICP power used during the HDPCVD process of step 530 can be adjusted to adjust the uniformity of the deposited film.

[0066] In some embodiments, the HDPCVD process of step 530 is performed using a configured bias power. In some embodiments, the bias power is from 0 to 100 watts. In some embodiments, the bias power is from 0 watts to 25 watts. In some embodiments, the bias power is from 25 watts to 50 watts. In some embodiments, the bias power is from 50 watts to 75 watts. In some embodiments, the bias power is from 75 watts to 100 watts. In some embodiments, the bias power is from 0 watts to 50 watts. In some embodiments, the bias power is from 25 watts to 75 watts. In some embodiments, the bias power is from 50 watts to 100 watts. In some embodiments, the bias power is from 0 watts to 75 watts. In some embodiments, the bias power is from 25 watts to 100 watts. In some embodiments, changing the bias power changes the density of the film. In some embodiments, changing the bias power changes the proportion of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, an increase in bias power increases the velocity of hydrogen in the plasma state, thereby producing a film with a lower hydrogen content. In some embodiments, conversely, a decrease in bias power decreases the velocity of hydrogen in the plasma state, thereby producing a film with a higher hydrogen content. In some embodiments, changing the bias power changes the uniformity of the film. In some embodiments, increasing the bias power increases the electrode field generated from the lower electrode, thereby increasing the uniformity of the film. In some embodiments, conversely, decreasing the bias power decreases the electrode field generated from the lower electrode, thereby decreasing the uniformity of the film.

[0067] In some embodiments, the HDPCVD process of step 530 is performed using a handle wafer maintained at a configured temperature. In some embodiments, the temperature is between 100 degrees Celsius and 250 degrees Celsius. In some embodiments, the temperature is between 100 degrees Celsius and 150 degrees Celsius. In some embodiments, the temperature is between 150 degrees Celsius and 200 degrees Celsius. In some embodiments, the temperature is between 200 degrees Celsius and 250 degrees Celsius. In some embodiments, the temperature is between 100 degrees Celsius and 200 degrees Celsius. In some embodiments, the temperature is between 150 degrees Celsius and 250 degrees Celsius. In some embodiments, changing the handle wafer temperature changes the proportion of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser, and films with higher hydrogen content are less dense. In some embodiments, increasing the temperature of the handle wafer decreases the hydrogen content of the film. In some embodiments, conversely, decreasing the temperature of the handle wafer increases the hydrogen content of the film. In some embodiments, changing the handle wafer temperature changes the film deposition rate. In some embodiments, increasing the temperature of the handle wafer decreases the RF energy required to decompose silane gas into silicon and hydrogen, increases the recombination time, and thereby increases the deposition rate. Conversely, in some embodiments, decreasing the temperature of the handle wafer increases the RF energy required to decompose silane gas into silicon and hydrogen, shortens the recombination time, and thereby decreases the deposition rate.

[0068] In some embodiments, the HDPCVD process of step 530 is carried out at a configured flow rate of O2 gas. In some embodiments, the flow rate of O2 gas is in the range of 20 - 35 sccm. In some embodiments, the flow rate of O2 gas is in the range of 20 - 25 sccm. In some embodiments, the flow rate of O2 gas is in the range of 25 - 30 sccm. In some embodiments, the flow rate of O2 gas is in the range of 30 - 35 sccm. In some embodiments, the flow rate of O2 gas is in the range between 20 - 30 sccm. In some embodiments, the flow rate of O2 gas is in the range of 25 - 35 sccm.

[0069] In some embodiments, the HDPCVD process of step 530 is carried out at a configured flow rate of silane gas. In some embodiments, the flow rate of silane gas is in the range of 20 - 35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20 - 25 sccm. In some embodiments, the flow rate of silane gas is in the range of 25 - 30 sccm. In some embodiments, the flow rate of silane gas is in the range of 30 - 35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20 - 30 sccm. In some embodiments, the flow rate of silane gas is in the range of 25 - 35 sccm.

[0070] In some embodiments, the HDPCVD process of step 530 is carried out at a configured flow rate of argon gas. In some embodiments, the flow rate of argon gas is in the range of 20 - 35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20 - 25 sccm. In some embodiments, the flow rate of argon gas is in the range of 25 - 30 sccm. In some embodiments, the flow rate of argon gas is in the range of 30 - 35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20 - 30 sccm. In some embodiments, the flow rate of argon gas is in the range of 25 - 35 sccm.

[0071] In some embodiments, the parameters of the HDPCVD process of step 530 are configured to provide a controlled deposition rate of the silicon dioxide layer on the handle wafer. In some embodiments, the deposition rate of the silicon dioxide layer is 900 - 1100 angstroms per minute. In some embodiments, the deposition rate of the silicon dioxide layer is 950 - 1050 angstroms per minute. In some embodiments, the deposition rate of the silicon dioxide layer is 975 - 1025 angstroms per minute. In some embodiments, the deposition rate of the silicon dioxide layer is about 1000 angstroms per minute. In some embodiments, the deposition rate of the silicon dioxide layer is 1000 angstroms per minute.

[0072] In some embodiments, the parameters of the HDPCVD process of step 530 are configured to provide a controlled thickness of the silicon dioxide layer on the handle wafer. In some embodiments, the thickness of the silicon dioxide layer is 1500 - 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 1500 - 2000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 2000 - 2500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 2500 - 3000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 3000 - 3500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 3500 - 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 4000 - 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 4500 - 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 1500 - 2500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 2000 - 3000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 2500 - 3500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 3000 - 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 3500 - 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 4000 - 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 1500 - 3000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 2000 - 3500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 2500 - 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 3000 - 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 3500 - 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is 1500 - 3500 angstroms.In some embodiments, the thickness of the silicon dioxide layer is from 2000 to 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2500 to 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 3000 to 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2000 to 4500 angstroms. In some embodiments, the silicon dioxide layer is from 2500 to 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 1500 to 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is from 2000 to 5000 angstroms. In some embodiments, the HDPCVD process of step 530 is performed for 2 to 3 minutes to achieve a controlled thickness of the silicon dioxide layer.

[0073] Continuing to refer to FIG. 5, in step 540, a hydrogen implant is implanted into the second wafer. In some embodiments, the hydrogen implant is arranged to define a cleavage plane in the second wafer. In some embodiments, the cleavage plane defines the desired thickness of the second silicon wafer after completion of method 500. In some embodiments, the hydrogen implant is implanted using an ion implantation device. In some embodiments, the ion implantation device is an ion implantation device such as those commercialized by Nissin Ion Equipment Co., Ltd. of Kyoto, Japan. In some embodiments, the ion implantation device is configured to emit a beam of hydrogen ions. In some embodiments, the ion implantation device is configured to operate at a power of 5000 volts to 1 megavolt. In some embodiments, the desired thickness ranges from 500 to 5000 angstroms. In some embodiments, the desired thickness ranges from 500 to 2000 angstroms. In some embodiments, the desired thickness ranges from 2000 to 3500 angstroms. In some embodiments, the desired thickness ranges from 3500 to 5000 angstroms. In some embodiments, the desired thickness ranges from 500 to 3500 angstroms. In some embodiments, the desired thickness ranges from 2000 to 5000 angstroms. In some embodiments, the implanted hydrogen creates displacement defects in the form of interstitial atoms, vacancies, and complexes. In some embodiments, such defects create regions with a number of broken bonds called plateletlets. In some embodiments, hydrogen is trapped on these surfaces, passivating the broken bonds. FIG. 6D shows a schematic diagram of a first silicon wafer with an arsenic layer diffused therein and a silicon dioxide layer deposited thereon, and a second silicon wafer implanted with a hydrogen implant, after the implementation of step 540.

[0074] Continuing to refer to FIG. 5, in step 550, the surface of the silicon dioxide layer deposited in step 530 is activated. In some embodiments, the activation is plasma activation implemented by impacting the surface of the silicon dioxide layer with short-lived chemical species generated within the plasma volume to cause a chemical reaction on the surface and enable adhesion. In some embodiments, the activation is low-pressure plasma activation bonding at a pressure in the range of 0.1 to 100 Pa. FIG. 6E shows a schematic diagram of a first silicon wafer in which an arsenic layer has diffused internally and an activated silicon dioxide layer has been deposited after the implementation of step 550, and a second silicon wafer into which a hydrogen implant has been implanted.

[0075] Continuing to refer to FIG. 5, in step 560, the first silicon wafer (in which an arsenic layer has diffused internally and a silicon dioxide layer has been deposited) is bonded to a second silicon wafer (having a hydrogen implant therein) with the activated surface of the silicon dioxide layer facing the second silicon wafer, and after cleavage along the cleavage plane defined by the hydrogen implantation, the desired portion of the second silicon wafer (i.e., the portion having the thickness described above) remains adjacent to the first silicon wafer. FIG. 6F shows a schematic diagram of the bonding of a first silicon wafer in which an arsenic layer has diffused internally and an activated silicon dioxide layer has been deposited and a second silicon wafer into which a hydrogen implant has been implanted in accordance with the implementation of step 560.

[0076] Continuing to refer to FIG. 5, in step 570, the joined first silicon wafer and second silicon wafer are subjected to a low-temperature annealing process. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 250 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 to 300 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 300 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 350 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 300 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 300 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 degrees Celsius to 400 degrees Celsius. In some embodiments, the time of the annealing process is from 1 hour to 8 hours. In some embodiments, during the annealing process, the trapped hydrogen described above with reference to step 540 dissociates from the complex and diffuses into the platelet to form H2 molecules. In some embodiments, due to the increase in pressure, the platelet expands within the minute cracks where they bond together in the same plane, causing delamination of the material. FIG. 6G shows a schematic diagram of the annealing process of step 570.

[0077] Continuing to refer to FIG. 5, in step 580, the joined first and second silicon wafers are placed under tension (i.e., tension is applied to pull the first and second silicon wafers apart from each other). In some embodiments, the tension is a force sufficient to generate a tension in the range of 10 to 60 pounds per square inch across the entire joined area. FIG. 6H shows a schematic diagram of the tensioning process of step 580.

[0078] Continuing to refer to FIG. 5, in step 590, the second silicon wafer is struck at the cleavage plane defined by hydrogen implantation. In some embodiments, a thin blade-like element is used to apply a force in the range of 5 to 10 pounds per square inch across the target area to strike the second silicon wafer in order to generate a cleavage wave. In some embodiments, the thin blade-like element is any suitable object having a suitable width. In some embodiments, the suitable width is about 50 microns. As a result of this striking, a portion of the second silicon wafer (which may be referred to herein as the "donor wafer") disposed between the hydrogen implant and the first silicon wafer remains attached to the first silicon wafer (which may be referred to herein as the "handle wafer"), and the remaining portion of the second silicon wafer is cleaved. Following this cleavage step, the final completed wafer is manufactured. FIG. 6I shows a schematic diagram of the completed wafer and the removed portion of the second silicon wafer after the implementation of step 590.

[0079] In some embodiments, an exemplary substrate (e.g., the above-described device 100 with reference to FIG. 1, a substrate fabricated according to the method 200 shown in FIG. 2, the above-described device 400 with reference to FIG. 4, and / or a substrate fabricated according to the method 500 shown in FIG. 5) includes a trap-rich layer (e.g., the silicon nitride layer of device 100 or the diffused arsenic layer of device 400), and (in the case of the silicon nitride layer of device 100) the trap-rich layer is disposed within the substrate at a position in contact with the upper surface of the handle wafer, or (in the case of the arsenic layer of device 400) the trap-rich layer is disposed within the upper surface of the handle wafer. In some embodiments, such an exemplary substrate is suitable for use in the manufacture of RF systems. In some embodiments, the trap-rich layer operates to trap carriers, i.e., parasitic currents that can be induced by RF radiation. Thus, in some embodiments, chip designers can integrate various functions (e.g., switches, power amplifiers, antenna tuners, etc.) on the same chip without having currents induced by interfering functions, so such substrates are suitable for use in the manufacture of RF systems.

[0080] Prior art for forming an SOI substrate suitable for use in the manufacture of RF systems includes a step of depositing a trap-rich layer on a handle wafer before bonding the handle wafer to an active silicon wafer. For example, a layer of polysilicon can be used in such techniques. However, since the high-temperature front-end-of-line ("FEOL") process adversely affects the crystal structure of the polysilicon wafer at the interface with the handle wafer and degrades the trap characteristics of the polysilicon layer, the SOI substrate formed using this process has thermally unstable properties. In some embodiments, the exemplary embodiments prevent such thermal instability problems. In some embodiments, the exemplary embodiments reduce the manufacturing costs associated with depositing a trap-rich material such as polysilicon on the handle wafer.

[0081] In some embodiments, a silicon-on-insulator substrate includes a layered structure that, in order, includes (1) a high-resistivity base layer having a first side and a second side opposite the first side, (2) a silicon dioxide layer disposed on the first side of the high-resistivity base layer, and (3) a transfer layer disposed on the silicon dioxide layer. The high-resistivity base layer includes (a) silicon and (b) a trap-rich region including arsenic diffused within the first side of the high-resistivity base layer. This trap-rich region has a trap density in the range of (i) a thickness in the range of 1 to 10 microns and (ii) 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 . The high-resistivity base layer has a resistivity in the range of 50 to 100 ohm-meters.

[0082] In some embodiments, a method includes providing a first silicon wafer having a first side and a second side; applying a sufficient amount of arsenic to a first surface of the first silicon wafer to diffuse the arsenic into the first side of the first silicon wafer to create a trap-rich region, where the thickness of the trap-rich region is in the range of 1 to 10 microns and the trap-rich region is 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1having a trap density in the range of); depositing a silicon dioxide layer on a first side of a first silicon wafer using a high density plasma chemical vapor deposition (HDPCVD) process (in this step, the HDPCVD process uses a flow of oxygen gas, a flow of silane gas, and a flow of argon gas); providing a second silicon wafer having a second side opposite the first side; introducing a hydrogen implant into the second silicon wafer to define a cleavage plane; activating the silicon dioxide layer; contacting the first side of the second silicon wafer with the activated silicon dioxide layer, thereby creating a bonded wafer; annealing the bonded wafer; applying a tension to the wafer bonded in one direction such that the first silicon wafer and the second silicon wafer are separated from each other; and cleaving the second silicon wafer along the cleavage plane, thereby creating a silicon-on-insulator substrate.

[0083] In some embodiments, the method comprises providing a first silicon wafer having a first side and a second side; depositing a silicon nitride layer on the first side of the first silicon wafer using a first high-density plasma chemical vapor deposition (HDPCVD) process, wherein the first HDPCVD process uses an inductively coupled plasma source that is operated at a power in the range of 65 watts to 225 watts during the first HDPCVD process, the first HDPCVD process uses a flow of oxygen gas, a flow of silane gas, and a flow of argon gas, the flow rate of the nitrogen gas flow during the first HDPCVD process is in the range of 20 to 35 sccm, the flow rate of the silane gas flow is in the range of 20 to 35 sccm, the flow rate of the argon gas flow is in the range of 20 to 35 sccm, the first HDPCVD process is carried out at a pressure in the range of 5 millitorr to 20 millitorr, the first HDPCVD process is carried out using a bias power in the range of 0 to 100 watts, the first HDPCVD process is carried out on the first silicon wafer maintained at a temperature in the range of 100 to 250 degrees Celsius, the deposition rate of the silicon nitride layer is in the range of 300 to 500 angstroms per minute, the thickness of the silicon nitride layer is in the range of 300 to 500 angstroms, and the silicon nitride layer has a density of 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1It is a trap-rich layer having a trap density in the range of (); depositing a silicon dioxide layer on the silicon nitride layer using a second HDPCVD process (where the second HDPCVD process uses an inductively coupled plasma source, and the inductively coupled plasma source operates at a power in the range of 65 watts to 225 watts during the second HDPCVD process, the second HDPCVD process uses a flow of oxygen gas, a flow of silane gas, and a flow of argon gas, the flow rate of the flow of oxygen gas during the second HDPCVD process is in the range of 20 to 35 sccm, the flow rate of the flow of silane gas during the second HDPCVD process is in the range of 20 to 35 sccm, the flow rate of the flow of argon gas during the second HDPCVD process is in the range of 20 to 35 sccm, the second HDPCVD process is carried out at a pressure in the range of 5 millitorr to 20 millitorr, the second HDPCVD process is carried out using a bias power in the range of 0 to 100 watts, the second HDPCVD process is carried out using a first silicon wafer maintained at a temperature in the range of 100 to 250 degrees Celsius, the deposition rate of the silicon dioxide layer is in the range of 900 to 1100 angstroms / minute, and the thickness of the silicon dioxide layer is in the range of 1500 to 5000 angstroms); providing a second silicon wafer having a first side and a second side opposite the first side; introducing a hydrogen implant into the second silicon wafer to define a cleavage plane (where a partial thickness of the second silicon wafer between the first side of the second silicon wafer and the cleavage plane is in the range of 500 to 5000 angstroms); activating the silicon dioxide layer (where the activation step includes low-pressure plasma activation bonding at a pressure in the range of 0.1 to 100 Pa); contacting the first side of the second silicon wafer with the activated silicon dioxide layer, thereby producing a bonded wafer; annealing the bonded wafer (where the annealing is carried out at a temperature in the range of 200 to 400 degrees Celsius for a period in the range of 1 hour to 8 hours).applying a tension to a wafer in which a first silicon wafer and a second silicon wafer are joined in one direction so as to be separated from each other; and striking an edge of the second silicon wafer to cleave the second silicon wafer along a cleavage plane, thereby producing a silicon-on-insulator substrate.

[0084] All functional equivalents known in the art of such materials and methods are intended to be included in the present invention. The terms and expressions used herein are used as terms of description and not of limitation, and in the use of such terms and expressions, there is no intention to exclude equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention as claimed. Accordingly, although the invention has been specifically disclosed by preferred embodiments and optional features, modifications and variations of the concepts disclosed herein may be made by those skilled in the art, and it is understood that such modifications and variations are within the scope of this disclosure.

[0085] Although some embodiments of the present invention have been described, these embodiments are merely illustrative and not restrictive, and it is understood that many modifications may become apparent to those skilled in the art. For example, all dimensions described herein are provided by way of example only, are illustrative, and are not intended to be limiting.

Claims

1. (1) a high resistivity base layer having a first side and a second side opposite the first side; (2) a silicon dioxide layer positioned on a first side of the high resistivity base layer; and (3) a transfer layer positioned on the silicon dioxide layer; In particular, the layer structure includes a layer structure including, in order, The high resistivity base layer is (a) silicon, and (b) a trap rich region comprising arsenic diffused into a first side of the high resistivity base layer; The trap rich region is (i) a thickness in the range of 1 to 10 microns; and (ii) 0.8×10 １０ cm ２ eV －１ ~1.2 x 10 １０ cm ２ eV －１ and having a trap density in the range The high resistivity base layer is (a) low efficiency in the range of 50 to 100 ohm-meters; and (b) having a thickness in the range of 500 to 700 microns; the silicon dioxide layer having a thickness in the range of 1000 to 5000 angstroms; A silicon-on-insulator substrate, wherein the transfer layer comprises a silicon wafer and has a thickness in the range of 500 to 5000 angstroms.

2. The trap rich region is 10 １０ cm ２ eV －１ ~1.2 x 10 １０ cm ２ eV －１ 10. The silicon-on-insulator substrate of claim 1 having a trap density in the range of

3. 2. The silicon-on-insulator substrate of claim 1 , wherein the trap rich regions comprise arsenic interspersed within a crystalline structure of the silicon of the high resistivity base layer.

4. 2. The silicon-on-insulator substrate of claim 1 , wherein the trap rich region has a thickness in the range of 4 microns to 7 microns.

5. The silicon-on-insulator substrate of claim 1 , wherein the high resistivity base layer has a thickness in the range of 550 to 650 microns.

6. 2. The silicon-on-insulator substrate of claim 1, wherein the silicon dioxide layer has a thickness in the range of 2000 to 4000 Angstroms.

7. The silicon-on-insulator substrate of claim 1 , wherein the transfer layer has a thickness in the range of 2000 to 3500 Angstroms.

8. Providing a first silicon wafer having a first side and a second side; applying an arsenic solution, the arsenic solution being a liquid colloidal solution, to the first side of the first silicon wafer; maintaining the first silicon wafer with the arsenic solution on the first side at a controlled temperature for a controlled time to cause diffused arsenic on the first side of the first silicon wafer and create a trap rich region; depositing a silicon dioxide layer on a first side of the first silicon wafer using a high density plasma chemical vapor deposition (HDPCVD) process; providing a second silicon wafer having a first side and a second side opposite the first side; introducing a hydrogen implant into the second silicon wafer to define a cleavage plane; activating the silicon dioxide layer; contacting a first side of the second silicon wafer with an activated silicon dioxide layer to produce a unitary wafer; annealing the integrated wafer; applying tension to the unidirectionally integrated wafers to separate the first and second silicon wafers from each other; and striking an edge of the second silicon wafer to cleave the second silicon wafer at the cleavage plane, thereby producing a silicon-on-insulator substrate. Including, In the step of holding the first silicon wafer, the controlled time is in a range of 5 hours to 20 hours; the controlled temperature is in the range of 700 to 1200 degrees Celsius; a thickness of the trap rich region in the range of 1 to 10 microns; The trap rich region is 0.8×10 １０ cm ２ eV －１ ~1.2 x 10 １０ cm ２ eV －１ and having a trap density in the range depositing the silicon dioxide layer, the HDPCVD process using an inductively coupled plasma source, the inductively coupled plasma source being driven at a power in the range of 65 watts to 225 watts; the HDPCVD process using an oxygen gas flow, a silane gas flow, and an argon gas flow; the flow rate of the oxygen gas flow is in the range of 20 to 35 sccm; the flow rate of the silane gas flow is in the range of 20-35 sccm; the argon gas flow rate is in the range of 20-35 sccm; said HDPCVD process being carried out at a pressure ranging from 5 mTorr to 20 mTorr; said HDPCVD process being carried out with a bias power in the range of 0 to 100 watts; performing the HDPCVD process with the first silicon wafer held at a temperature in the range of 100-250 degrees Celsius; the deposition rate of said silicon dioxide layer is in the range of 900 to 1100 angstroms per minute; the thickness of said silicon dioxide layer is in the range of 1500 to 5000 angstroms; introducing a hydrogen implant into the second silicon wafer, wherein a thickness of a portion of the second silicon wafer between the first side and the cleavage surface of the second silicon wafer is in a range of 500 to 5000 angstroms; the step of activating the silicon dioxide layer comprises low pressure plasma activated bonding at a pressure in the range of 0.1 to 100 Pa; The method of claim 1, wherein in the step of annealing the integrated wafer, the annealing is carried out at a temperature ranging from 200 to 400 degrees Celsius for a time ranging from 1 hour to 8 hours.

9. 9. The method of claim 8, wherein applying the arsenic solution to the first side of the first silicon wafer comprises spin-coating the arsenic solution onto the first side of the first silicon wafer.

10. The method of claim 8 , wherein the liquid colloidal solution comprises arsenic-infused glass.

11. 9. The method of claim 8, wherein the flow rates of the oxygen gas flow, the silane gas flow, and the argon gas flow are identical to one another.

12. 9. The method of claim 8, wherein the oxygen gas flow rate, the silane gas flow rate, and the argon gas flow rate are selected to control the refractive index of the silicon dioxide layer.

13. 9. The method of claim 8, wherein the controlled time period is selected to control charge dissipation of the trap rich layer.

14. The trap rich region is 10 １０ cm ２ eV －１ ~1.2 x 10 １０ cm ２ eV －１ The method of claim 8 , having a trap density in the range of

15. 9. The method of claim 8, wherein the step of holding the first silicon wafer having an arsenic solution on the first side at a controlled temperature for a controlled time produces arsenic interspersed within the crystalline structure of the silicon of the high resistivity base layer.

16. 10. The method of claim 8, wherein holding the first silicon wafer with an arsenic solution on the first side at a controlled temperature for a controlled time produces trap rich regions having a thickness in the range of 4 microns to 7 microns.

17. The method of claim 8, wherein the high resistivity base layer has a thickness in the range of 550 to 650 microns.

18. The method of claim 8, wherein the silicon dioxide layer has a thickness in the range of 2000 to 4000 Angstroms.

19. 2. The silicon-on-insulator substrate of claim 1, wherein a thickness of the portion of the second silicon wafer between the first side and the cleaved surface of the second silicon wafer is in the range of 2000 to 3500 angstroms.

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