Package structure

Abstract

To provide a package structure that can effectively reduce the probability of the product failure while achieving the thinness of product performance.SOLUTION: A package structure 100 includes a first layer 110, a second layer 120 and a third layer 130. The second layer includes an outer frame 121, a resonator 122 and a chip 123. The second layer is arranged between the first layer and third layer. The outer frame, first layer and third layer constitute a rectangular storage part 10. The resonator and chip are located in the rectangular accommodation part. The chip is located on one side of the resonator and electrically connected to the third layer and resonator through a plurality of conductive components 123C on the chip. The chip further may be located below the resonator.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a package structure.

Background Art

[0002] With the development trend of high stability, miniaturization, thinning of crystal frequency devices, and wafer-level package (WLP) technology, the arrangement relationship of components has become important. For example, when arranging a chip on the outer surface of a wafer-level package structure, it is common to use underfill to coat conductive components (such as gold balls). However, the above method cannot effectively protect the conductive components (for example, defects occur due to the inability to reliably coat), which may lead to product defects along with the defects during subsequent processes.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Since the conductive components cannot be effectively protected (for example, defects occur due to the inability to reliably coat), there is a possibility of bringing product defects along with the defects during subsequent processes.

Means for Solving the Problems

[0004] The present invention provides a package structure that can effectively reduce the probability of product defects and at the same time achieve thinning of product performance.

[0005] The package structure of the present invention includes a first layer, a second layer, and a third layer. The second layer includes an outer frame, a resonator, and a chip. The second layer is disposed between the first layer and the third layer. The outer frame, the first layer, and the third layer constitute a rectangular accommodation portion. The resonator and the chip are located within the rectangular accommodation portion. The chip is located on one side of the resonator, and the chip is electrically connected to the third layer and the resonator via a plurality of conductive components thereon.

[0006] The package structure of the present invention includes a first layer, a second layer, and a third layer. The second layer includes an outer frame, a resonator, and a chip. The second layer is disposed between the first layer and the third layer. The outer frame, the first layer, and the third layer constitute a rectangular accommodation portion. The resonator and the chip are located within the rectangular accommodation portion. The chip is located below the resonator, and the chip is electrically connected to the third layer and the resonator via a plurality of conductive components thereon.

Advantages of the Invention

[0007] As described above, through the design of the laminated structure and the rectangular accommodation portion, the present invention can reliably seal the resonator and the chip, ensuring that the conductive components on the chip are completely protected. Therefore, the probability of product defects can be effectively reduced, and at the same time, the thinning of product performance can be achieved.

[0008] To facilitate the understanding of the above features and advantages of the present invention, the embodiments in conjunction with the drawings will be described in detail below.

Brief Description of the Drawings

[0009]

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MODE FOR CARRYING OUT THE INVENTION

[0010] In the following detailed description, for purposes of explanation and not limitation, exemplary embodiments are set forth in order to provide a thorough understanding of the various principles of the present invention. However, it will be apparent to those skilled in the art who enjoy the benefits of the present invention that the present invention can be practiced in other embodiments different from the specific details disclosed herein. Further, descriptions of well-known devices, methods, and materials may be omitted so as not to obscure the description of the various principles of the present invention.

[0011] Hereinafter, exemplary embodiments of the present invention will be fully described with reference to the drawings. However, the present invention should not be construed as being limited to the embodiments described herein, since the present invention can be implemented in many different forms. In the drawings, for clarity, the sizes and thicknesses of regions, components, and layers are not drawn to actual scale. For ease of understanding, in the following description, the same elements will be described with the same reference symbols.

[0012] The directional terms used herein (e.g., up, down, right, left, front, back, top, and bottom) are used merely with reference to the drawings and do not mean absolute directionality.

[0013] It should be understood that terms such as "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part.

[0014] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0015] FIG. 1 is a schematic external view of a package structure according to one embodiment of the present invention. FIG. 2 is a schematic exploded view of FIG. 1. FIG. 3 is a schematic side view of the interior of FIG. 1. FIGS. 4A, 4B, 4C, 4D, 4E, and 4F are schematic top views from the bottom of the third layer to the top of the first layer of FIG. 2, respectively. FIG. 5 is a schematic cross-sectional view along the section line A-A' after stacking FIGS. 4A to 4F. FIG. 6 is a schematic cross-sectional view along the section line B-B' after stacking FIGS. 4A to 4F. FIG. 7 is a schematic cross-sectional view along the section line C-C' after stacking FIGS. 4A to 4F. Here, FIG. 3 is a side portion viewed from the direction D after assembly in FIG. 2.

[0016] Referring to FIGS. 1 to 3, in the present embodiment, the package structure 100 includes a first layer 110, a second layer 120, and a third layer 130. The second layer 120 is disposed between the first layer 110 and the third layer 130, and the second layer 120 includes an outer frame 121, a resonator 122, and a chip 123. It should be noted that FIG. 2 merely clearly shows the bonding position of the chip 123 by an exploded view and does not show that it is included in the third layer 130. As shown in FIG. 3, after assembly, the chip 123 is included in the second layer 120.

[0017] In some embodiments, chip 123 is an integrated circuit (IC), and its types include, but are not limited to, application specific integrated circuits (ASICs) and integrated circuits (ICs) manufactured by semiconductor technology.

[0018] Furthermore, the outer frame 121, the first layer 110, and the third layer 130 form a rectangular accommodating portion 10. The resonator 122 and the chip 123 are located within the rectangular accommodating portion 10, and the chip 123 is located on one side of the resonator 122. Here, the chip 123 is electrically connected to the third layer 130 and the resonator 122 via a plurality of conductive components 123C on the chip 123. Therefore, due to the laminated structure and the design of the rectangular accommodating portion 10, the present invention can reliably seal the resonator 122 and the chip 123 and ensure that the conductive components 123C on the chip 123 are completely protected. Thereby, the probability of product defects can be effectively reduced, and at the same time, the thinning of product performance can be achieved. Here, the conductive component 123C may be a gold ball or the like. Since the conductive component 123C in the structure of this embodiment does not come into contact with air, there is no underfill. Furthermore, as shown in FIG. 3, the above-mentioned rectangular accommodating portion 10 has a square structure instead of an L-shaped or convex shape.

[0019] Furthermore, when facing subsequent processes such as a molding process, the rectangular accommodating portion 10 can reduce the probability of product defects in which the conductive component 123C is deformed or damaged at the interface due to the stress generated from the process in order to comprehensively protect the conductive component 123C. Since the chip does not protrude on the outer surface of the package structure, the thickness of the package structure 100 can be reduced to meet the requirement of thinning, but the present invention is not limited thereto.

[0020] In this embodiment, as shown in FIG. 2, both the first layer 110 and the third layer 130 are rectangular solid structures (not U-shaped, inverted U-shaped, or similar). That is, since neither the first layer 110 nor the third layer 130 has grooves, the difficulty in joining the stacked structure can be reduced. At the same time, since the etching process for forming grooves can be omitted, the process can be simplified, but the present invention is not limited thereto.

[0021] In some embodiments, since the materials of the first layer 110, the outer frame 121, the resonator 122, and the third layer 130 are made of quartz, the package structure 100 may be a wafer-level package quartz oscillator. For example, both the first layer 110 and the third layer 130 may be circuit boards, while the resonator 122 and the outer frame 121 may be an integrated structure. That is, as shown in FIGS. 4C and 4D, the outer frame 121 is directly and physically connected to the resonator 122. There is no bonding interface between the outer frame 121 and the resonator 122. Therefore, since an adhesive such as a bonding adhesive can be omitted, the manufacturing cost and process can be saved, but the present invention is not limited thereto. Here, in FIGS. 4C and 4D, the resonator 122 is physically connected to only one side of the outer frame 121. However, in an embodiment not shown, the resonator may be physically connected to at least two or more (for example, three or four) sides of the outer frame according to actual design requirements.

[0022] In some embodiments, the package structure 100 can be formed by the following steps. First, the circuits and components required for each layer are formed on three respective crystal wafers through appropriate processes (e.g., photolithography processes). A plurality of chips 123 are arranged on the wafers and used as the third layer 130. Next, the three crystal wafers are joined to each other via a joining material (such as the joining component 20 in FIG. 5, e.g., an appropriate adhesive material), and then a singulation or dicing process is performed to separate the plurality of package structures 100. Here, a gap between adjacent wafers is generated by the joining component 20.

[0023] In some embodiments, the opposing upper surface 121t and bottom surface 121b of the outer frame 121 are in direct contact with the first layer 110 and the third layer 130, respectively. Since the thickness of the resonator 122 and the thickness of the chip 123 do not exceed the thickness of the outer frame 121, the resonator 122 and the chip 123 do not directly contact the first layer 110, but the present invention is not limited thereto.

[0024] In some embodiments, the package structure 100 is composed of only the first layer 110, the second layer 120, and the third layer 130, but the present invention is not limited thereto.

[0025] To make the circuit layout within the package structure 100 described above clearer and easier to understand, it will be described in detail below with reference to FIGS. 4A - 4F and FIGS. 5 - 7. However, this is not for limiting the circuit layout of the present invention. As long as the chip 123 is electrically connected to the third layer 130 and the resonator 122 via the conductive component 123C thereon, all are within the scope of the present invention.

[0026] Here, FIG. 4A corresponds to the circuit layout of the bottom 130b of the third layer 130, FIG. 4B corresponds to the circuit layout of the top 130t of the third layer 130, FIG. 4C corresponds to the circuit layout of the bottom 120b of the second layer 120, FIG. 4D corresponds to the circuit layout of the top 120t of the second layer 120, FIG. 4E corresponds to the circuit layout of the bottom 110b of the first layer 110, FIG. 4F corresponds to the circuit layout of the top 110t of the first layer 110, and FIGS. 5 to 7 are diagrams obtained by stacking these drawings vertically and taking a cross-section.

[0027] In this embodiment, the first layer 110, the second layer 120, and the third layer 130 are electrically connected to each other via a plurality of vias as shown in FIGS. 4A, 4B, and 7, for example. Conductive components (not shown) of the chip 123 disposed on the surface of the top 130t of the third layer 130 via a flip chip can be bonded to bonding pads C1, C2, C3, C4, C5, and C6. The bonding pads C1, C2, C3, C4, C5, and C6 are located on the surface of the top 130t of the third layer 130. Here, the bonding pads C1, C2, C3, and C4 physically contact and are electrically connected to vias V1, V2, V3, and V4 that penetrate the third layer 130, respectively. Thereafter, the vias V1, V2, V3, and V4 physically contact downward and are electrically connected to the circuit of the bottom 130b of the third layer 130.

[0028] On the one hand, as shown in FIGS. 4B to 4D and FIGS. 5 to 7, the bonding pad C5 and the bonding pad C6 are electrically connected to vias V5 and V6 that penetrate the second layer 120 through the circuits on the upper part 130t of the third layer 130, respectively. The vias V5 and V6 physically contact and are electrically connected to the circuits on the upper part 120t of the second layer 120. Here, the vias V5 and V6 are electrically connected to the second electrode E2 of the resonator 122 located at the bottom 120b of the second layer 120 and the first electrode E1 of the resonator 122 located at the upper part 120t of the second layer 120 through other circuits.

[0029] Next, as shown in FIGS. 4E to 4F and FIGS. 5 to 7, the circuits on the upper part 120t of the second layer 120 are electrically connected to vias V7 and V8 that penetrate the first layer 110. The vias V7 and V8 physically contact and are electrically connected to the circuits on the upper part 110t of the first layer 110, and the series connection path of the internal circuits of the package structure 100 is completed. Here, the bonding pads C1, C2, C3, C4, C5, C6, and the vias V1, V2, V3, V4, V5, V6, V7, V8 can be formed of a suitable conductive material (for example, copper).

[0030] It should be noted that the circuit regions not shown are merely illustrated exemplarily, and these circuits can be added, canceled, or adjusted according to actual design requirements. Therefore, these circuits are not used to limit the present invention.

[0031] In this embodiment, the resonator 122 and the chip 123 are located on the same horizontal plane. That is, the orthographic projection of the resonator 122 on the third layer 130 does not overlap with the orthographic projection of the chip 123 on the third layer 130. Therefore, since the thickness of the second layer 120 can be reduced, it has the advantage of further thinning, but the present invention is not limited thereto. In other embodiments, different structural relationships may exist between the resonator 122 and the chip 123. Another structural relationship will be further described below.

[0032] It should be noted that the reference numbers and some content of the above-described embodiments are used in the following embodiments. The same or similar reference numbers are used to indicate the same or similar components, and for the same technical content, the description will be omitted. For the omitted detailed description, reference can be made to the above-described embodiments, so it will not be described in detail in the following embodiments.

[0033] FIG. 8 is a schematic external view of a package structure according to another embodiment of the present invention. FIG. 9 is a schematic exploded view of FIG. 8. FIG. 10 is a schematic side view of the interior of FIG. 8. FIG. 11 is a schematic top view of the upper part of the third layer of FIG. 8.

[0034] Referring to FIGS. 8 to 11, compared with the package structure 100 of the above-described embodiment, in this embodiment, the chip 223 of the second layer 220 of the package structure 200 is located below the resonator 122. That is, the orthographic projection of the resonator 122 on the third layer 130 partially overlaps the orthographic projection of the chip 223 on the third layer 130. Therefore, the thickness of the second layer 220 of the package structure 200 is greater than the thickness of the second layer 120 of the package structure 100. Furthermore, compared with the package structure 100, the package structure 200 of this embodiment can provide another design flexibility by using a relatively large chip 223 as shown in FIG. 11, but the present invention is not limited thereto. It should be noted that FIG. 9 merely clearly shows the bonding position of the chip 223 by an exploded view and does not show that it is included in the third layer 130. As shown in FIG. 10, after assembly, the chip 223 is included in the second layer 220.

[0035] In this embodiment, the corresponding connection relationships between bonding pads C1, C2, C3, C4, C5, C6 and vias V1, V2, V3, V4, V5, V6 are similar to those in FIG. 4B. Other parts not shown can also be designed with a circuit configuration similar to that in FIGS. 4A and 4C to 4F, so the description is omitted here.

[0036] It should be noted that the above two embodiments are merely exemplary. The present invention does not limit the configuration relationship between the resonator and the chip. It is only necessary that the chip is arranged in the stacked structure and a complete protection effect can be achieved within the scope of the present invention.

[0037] As described above, through the design of the stacked structure and the rectangular accommodating portion, the present invention can reliably seal the resonator and the chip, ensuring that the conductive components on the chip are completely protected. Therefore, the probability of product defects can be effectively reduced, and at the same time, the thinning of product performance can be achieved.

[0038] The present invention has been described in detail with reference to the above embodiments, but these are not intended to limit the present invention. It will be understood by those skilled in the art that changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the following claims.

Industrial Applicability

[0039] The package structure can be applied to the field of crystal frequency devices.

Explanation of Reference Numerals

[0040] 10 Rectangular accommodating portion 20 Bonding component 100, 200 Package structure 110 First layer 110b, 120b, 130b Bottom 110t, 120t, 130t Top The second layer of 120 and 220 121 Outer frame 121t Top surface 121b Bottom surface 122 Resonator 123, 223 Chips 123C Conductive component The third layer of 130 E1 The first electrode E2 The second electrode C1, C2, C3, C4, C5, C6 Bonding pads D Direction V1, V2, V3, V4, V5, V6, V7, V8 Vias

Claims

1. A first layer; a second layer including an outer frame, a resonator, and a chip; a third layer, the second layer being disposed between the first layer and the third layer; wherein the outer frame, the first layer, and the third layer form a rectangular accommodating portion, the resonator and the chip are located within the rectangular accommodating portion, the chip is located on one side of the resonator, and the chip is electrically connected to the third layer and the resonator via a plurality of conductive components on the chip.

2. The package structure of claim 1 , wherein the first layer, the outer frame, the resonator, and the third layer are made of quartz crystal.

3. The package structure of claim 2 , wherein the resonator and the outer frame are an integral structure.

4. The package structure of claim 1 , wherein the first layer, the second layer, and the third layer are electrically connected to each other through a plurality of vias.

5. The package structure of claim 1 , wherein the resonator and the chip are located on the same horizontal plane.

6. A first layer; a second layer including an outer frame, a resonator, and a chip; a third layer, the second layer being disposed between the first layer and the third layer; wherein the outer frame, the first layer, and the third layer form a rectangular accommodating portion, the resonator and the chip are located within the rectangular accommodating portion, the chip is located below the resonator, and the chip is electrically connected to the third layer and the resonator via a plurality of conductive components on the chip.

7. 7. The package structure of claim 6, wherein the first layer, the outer frame, the resonator, and the third layer are constructed from quartz crystal.

8. The package structure of claim 7 , wherein the resonator and the outer frame are an integral structure.

9. The package structure of claim 6 , wherein the first layer, the second layer, and the third layer are electrically connected to each other through a plurality of vias.

10. The package structure of claim 6 , wherein an orthogonal projection of the resonator on the third layer partially overlaps an orthogonal projection of the chip on the third layer.

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