Plasma processing method

Abstract

To provide technique capable of shortening the time required for adjusting the shape of a mask.SOLUTION: A plasma processing method includes (a) a step of preparing a substrate on a substrate support portion in a chamber of a plasma processing apparatus, (b) a step of forming a deposit on the substrate while applying a negative voltage to an upper electrode disposed above the substrate support, and (c) a step of etching the deposit using plasma generated from a processing gas while applying a negative voltage to the upper electrode. The power level of source high-frequency power in (c) is equal to or lower than the power level of source high-frequency power in (b). The level of the electric bias in (c) is higher than the level of the electric bias in (b), or no electric bias is supplied to the substrate support portion in (b). The absolute value of the negative voltage applied to the upper electrode in (b) is set to a value greater than the absolute value of the negative voltage applied to the upper electrode in (c).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to a plasma processing method.

Background Art

[0002] Patent Document 1 discloses a plasma etching method. In a first period, a first RF power is supplied so that etching is dominant. In a second period, a second RF power is supplied so that deposition is dominant. In the first period, a bias voltage is supplied. The first RF power and the second RF power are supplied alternately.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure provides a technique capable of shortening the time for shaping a mask.

Means for Solving the Problems

[0005] In one exemplary embodiment, a plasma processing method includes: (a) a step of preparing a substrate on a substrate support in a chamber of a plasma processing apparatus, the substrate including a film containing silicon and oxygen and a resist mask provided on the film; (b) a step of forming a deposit on the substrate while applying a negative voltage to an upper electrode disposed above the substrate support, the deposit being supplied from a plasma generated from a processing gas containing a gas component containing fluorine and carbon in the chamber; and (c) a step of etching the deposit using the plasma generated from the processing gas while applying a negative voltage to the upper electrode. In (c), the power level of the source high-frequency power used to generate the plasma from the processing gas is equal to or lower than the power level of the source high-frequency power used to generate the plasma from the processing gas in (b). The level of the electrical bias supplied to the substrate support in (c) is higher than the level of the electrical bias supplied to the substrate support in (b), or the electrical bias is not supplied to the substrate support in (b). The absolute value of the negative voltage applied to the upper electrode in (b) is set to a value larger than the absolute value of the negative voltage applied to the upper electrode in (c).

Advantages of the Invention

[0006] According to one exemplary embodiment, the time for adjusting the shape of the mask can be shortened.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, various exemplary embodiments will be described in detail with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals.

[0009] FIG. 1 is a flowchart of a plasma processing method according to one exemplary embodiment. The plasma processing method shown in FIG. 1 (hereinafter referred to as "method MT") is performed to adjust the shape of a mask of a substrate in a plasma processing apparatus.

[0010] FIG. 2 is a diagram for explaining a configuration example of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support unit 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. Further, the plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas discharge port for discharging gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 described later, and the gas discharge port is connected to an exhaust system 40 described later. The substrate support unit 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0011] The plasma generation unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), surface wave plasma (SWP), or the like.

[0012] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to execute various processes described in the present disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 so as to execute the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is realized by, for example, a computer 2a. The processing unit 2a1 may be configured to perform various control operations by reading a program from the storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or may be acquired via a medium when necessary. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 and executed. The medium may be various storage media readable by the computer 2a, or may be a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a RAM (Random Access Memory), a ROM (Read Only Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).

[0013] Hereinafter, a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1 will be described. FIG. 3 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0014] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. Further, the plasma processing apparatus 1 includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a shower head 13. The substrate support unit 11 is disposed in the plasma processing chamber 10. The shower head 13 is disposed above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a part of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the side wall 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded. The substrate support unit 11 is electrically insulated from the housing of the plasma processing chamber 10.

[0015] The substrate support unit 11 includes a main body unit 111 and a ring assembly 112. The main body unit 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of the substrate W. The annular region 111b of the main body unit 111 surrounds the central region 111a of the main body unit 111 in a plan view. The substrate W is disposed on the central region 111a of the main body unit 111, and the ring assembly 112 is disposed on the annular region 111b of the main body unit 111 so as to surround the substrate W on the central region 111a of the main body unit 111. Accordingly, the central region 111a is also referred to as a substrate support surface for supporting the substrate W, and the annular region 111b is also referred to as a ring support surface for supporting the ring assembly 112.

[0016] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have the annular region 111b. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member.

[0017] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge ring is formed of a conductive material or an insulating material, and the cover ring is formed of an insulating material.

[0018] Further, the substrate support 11 may include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are disposed within the ceramic member 1111a of the electrostatic chuck 1111. Further, the substrate support 11 may include a heat transfer gas supply unit configured to supply a heat transfer gas to a gap between the back surface of the substrate W and the central region 111a.

[0019] The shower head 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The shower head 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas introduction ports 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the plurality of gas introduction ports 13c. Further, the shower head 13 includes at least one upper electrode. Note that the gas introduction unit may include, in addition to the shower head 13, one or more side gas injectors (SGI) attached to one or more openings formed in the side wall 10a.

[0020] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas from the corresponding gas source 21 to the shower head 13 via the corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Further, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of at least one processing gas.

[0021] The exhaust system 40 may be connected to, for example, a gas discharge port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is adjusted by the pressure regulating valve. The vacuum pump may include a turbo molecular pump, a dry pump, or a combination thereof.

[0022] The power supply system 30 includes a high-frequency power supply 31 and a bias power supply 32. The high-frequency power supply 31 constitutes the plasma generation unit 12 in one embodiment. The high-frequency power supply 31 is configured to generate source high-frequency power RF. The source high-frequency power RF has a source frequency f RF That is, the source high-frequency power RF has a frequency of the source frequency fRF It has a sinusoidal waveform. The source frequency f RF can be a frequency within the range of 13 MHz to 100 MHz. The high-frequency power supply 31 is electrically connected to the high-frequency electrode via a matcher 33 and is configured to supply the source high-frequency power RF to the high-frequency electrode. The high-frequency electrode may be provided within the substrate support portion 11. The high-frequency electrode may be at least one electrode provided within the conductive member or ceramic member 1111a of the base 1110. Alternatively, the high-frequency electrode may be an upper electrode. When the source high-frequency power RF is supplied to the high-frequency electrode, plasma is generated from the gas within the plasma processing chamber 10.

[0023] The matcher 33 has a variable impedance. The variable impedance of the matcher 33 is set to reduce the reflection from the load of the source high-frequency power RF. The matcher 33 can be controlled, for example, by the control unit 2.

[0024] The bias power supply 32 is electrically coupled to the substrate support portion 11. The bias power supply 32 is electrically connected to a bias electrode within the substrate support portion 11 and is configured to supply an electrical bias EB to the bias electrode. The bias electrode may be at least one electrode provided within the conductive member or ceramic member 1111a of the base 1110. The bias electrode may be common with the high-frequency electrode. When the electrical bias EB is supplied to the bias electrode, ions from the plasma are attracted to the substrate W.

[0025] The electrical bias EB has a waveform period and is periodically supplied from the bias power supply 32 to the bias electrode. The waveform period of the electrical bias EB is defined by the bias frequency. The bias frequency is, for example, a frequency of 100 kHz or more and 50 MHz or less. The time length of the waveform period of the electrical bias EB is the reciprocal of the bias frequency.

[0026] The electrical bias EB may be a bias high-frequency power having a bias frequency. That is, the electrical bias EB may have a sinusoidal waveform whose frequency is the bias frequency. In this case, the bias power supply 32 is electrically connected to the bias electrode via the matching unit 34. The variable impedance of the matching unit 34 is set to reduce reflection from the load of the bias high-frequency power.

[0027] Alternatively, the electrical bias EB may include a voltage pulse. The voltage pulse is applied to the bias electrode within the waveform period. The voltage pulse is periodically applied to the bias electrode at a time interval having the same length as the time length of the waveform period. The waveform of the voltage pulse can be a rectangular wave, a triangular wave, or any waveform. The polarity of the voltage of the voltage pulse is set so as to generate a potential difference between the substrate W and the plasma and draw ions from the plasma into the substrate W. The voltage pulse may be a pulse of negative voltage or a pulse of negative DC voltage. When the electrical bias EB includes a voltage pulse, the plasma processing apparatus 1 may not include the matching unit 34.

[0028] Incidentally, hereinafter, the level of the electrical bias EB may be described. When the electrical bias EB is a bias high-frequency power, the level of the electrical bias EB is the power level of the bias high-frequency power. When the electrical bias EB includes a voltage pulse, the level of the electrical bias EB is the absolute value of the negative voltage level of the voltage pulse.

[0029] The power supply system 30 may further include a trigger signal generator 30c. The trigger signal generator 30c supplies a trigger signal to each of the high-frequency power supply 31 and the bias power supply 32. The output timing of the trigger signal supplied to each of the high-frequency power supply 31 and the bias power supply 32 can be specified by the control unit 2. The high-frequency power supply 31 generates the source high-frequency power RF or changes its power level at the timing according to the supplied trigger signal. Also, the bias power supply 32 generates the electrical bias EB or changes its level at the timing according to the supplied trigger signal.

[0030] The power supply system 30 may further include a power supply 35. The power supply 35 is electrically connected to the upper electrode. In one embodiment, the upper electrode includes a top plate 13p. The top plate 13p defines the internal space of the plasma processing chamber 10 from above. That is, the top plate 13p is in contact with the internal space of the plasma processing chamber 10. The top plate 13p may be formed of silicon. The power supply 35 is configured to apply a negative voltage NV (for example, a negative DC voltage) to the upper electrode. The power supply 35 outputs a negative voltage NV to the upper electrode or changes the absolute value of its voltage level at a timing according to a trigger signal given from a trigger signal generator 30c. The output timing of the trigger signal given to the power supply 35 can be specified by the control unit 2.

[0031] Hereinafter, the method MT will be described with reference to FIGS. 4(a) to 4(d) and FIG. 5 together with FIG. 1. Also, the control of each part of the plasma processing apparatus 1 by the control unit 2 will be described. Each of FIGS. 4(a) to 4(d) is a partially enlarged cross-sectional view of an example substrate related to each step of a plasma processing method according to one exemplary embodiment. FIG. 5 is a timing chart related to a plasma processing method according to one exemplary embodiment. Hereinafter, the method MT will be described by taking the case where the plasma processing apparatus 1 is used as an example. Note that the method MT may be performed using a plasma processing apparatus different from the plasma processing apparatus 1.

[0032] As shown in FIG. 1, the method MT includes a step STa, a step STb, and a step STc.

[0033] (Step STa) In step STa, a substrate W is prepared on the substrate support 11 in the plasma processing chamber 10 of the plasma processing apparatus 1 (see FIG. 3). The steps of the method MT performed after step STa are performed with the substrate W placed on the substrate support 11.

[0034] As shown in Fig. 4(a), the substrate W includes a film EF containing silicon and oxygen and a resist mask PR. The substrate W may further include a base region UR. The film EF is a film to be etched after the method MT. The film EF is provided on the base region UR. The film EF may be a dielectric film containing silicon and oxygen. The film EF may be a silicon oxide film (SiO2 film) or a silicon oxynitride film (SiON film). The film EF may be a low dielectric constant film such as a SiOC film or a SiOCH film. The resist mask PR is provided on the film EF. The resist mask PR has a pattern that is transferred to the film EF by etching. That is, the resist mask PR provides one or more openings. The resist mask PR may provide a plurality of openings having different dimensions (CD: Critical Dimension). Each opening may be a hole or a trench. The resist mask PR may be an EUV resist mask or an ArF resist mask. The resist mask PR may be a metal-containing film. The base region UR may be a carbon-containing film. The carbon-containing film may be a SOC (Spin On Carbon) film.

[0035] (Step STb) Step STb is performed after Step STa and before Step STc. Step STb is performed during a period P1 (see Fig. 5). The period P1 may be 50 to 9000 μs. In Step STb, a deposit DP is formed on the substrate W while applying a negative voltage NV to the upper electrode disposed above the substrate support 11 (see Fig. 4(b)). The deposit DP is supplied from the plasma generated from the processing gas in the plasma processing chamber 10. The deposit DP may contain carbon and fluorine.

[0036] The processing gas in process STb is a gas having deposition properties. The processing gas contains a fluorine-containing gas. The processing gas may contain a gas component containing fluorine and carbon. This gas component may be a fluorocarbon gas such as C4F8 gas. That is, the fluorine-containing gas may be a fluorocarbon gas. Further, in addition to or instead of the fluorocarbon gas, this gas component may contain a hydrofluorocarbon gas. Alternatively, the processing gas may contain a fluorine-containing gas and a carbon-containing gas. Examples of the fluorine-containing gas include NF3 gas. Examples of the carbon-containing gas include hydrocarbon gases such as methane. The processing gas may further contain one or more of a hydrogen-containing gas (for example, hydrogen gas), a nitrogen-containing gas (for example, nitrogen gas), an oxygen-containing gas (for example, oxygen gas), and a noble gas (for example, Ar gas).

[0037] In process STb, the control unit 2 controls the gas supply unit 20 so as to supply the processing gas into the plasma processing chamber 10. In process STb, the control unit 2 controls the exhaust system 40 so as to set the pressure in the plasma processing chamber 10 to a specified pressure. In process STb, the control unit 2 controls the high-frequency power supply 31 so as to supply the source high-frequency power RF to the high-frequency electrode in order to generate plasma from the processing gas. In process STb, the control unit 2 may control the bias power supply 32 so as not to supply the electrical bias EB to the bias electrode. Alternatively, in process STb, the control unit 2 may control the bias power supply 32 so as to supply the electrical bias EB to the bias electrode.

[0038] In process STb, a negative voltage NV is applied to the upper electrode. In process STb, positive ions are attracted from the plasma in the plasma processing chamber 10 to the top plate 13p (see FIG. 3). As a result, the substance (for example, silicon) constituting the top plate 13p is released. The substance released from the top plate 13p combines with the fluorine species in the plasma, reducing the amount of fluorine species in the plasma.

[0039] In step STb, the control unit 2 controls the power supply 35 to apply a negative voltage NV to the upper electrode. Note that in step STc as well, a negative voltage NV is applied to the upper electrode. The absolute value of the negative voltage NV applied to the upper electrode in step STb is set to a value larger than the absolute value of the negative voltage NV applied to the upper electrode in step STc.

[0040] In one embodiment, the ion energy supplied to the substrate W in step STb may be smaller than the ion energy supplied to the substrate W in step STc described later, or may be equal to or greater than the ion energy supplied to the substrate W in step STc.

[0041] (Step STc) Next, as shown in FIG. 1, in method MT, step STc is performed. In one embodiment, step STc is performed after step STb. In one embodiment, step STc is performed during period P2 (see FIG. 5). Period P2 is a period after or following period P1. Period P2 may be 50 to 9000 μs.

[0042] In step STc, while applying a negative voltage NV to the upper electrode disposed above the substrate support portion 11, the deposit DP is etched using the plasma generated from the processing gas in the plasma processing chamber 10 (see (c) of FIG. 4). In step STc, by trimming the deposit DP, the shape of the resist mask PR covered by the deposit DP is adjusted. In step STc, plasma may be generated from the above-described processing gas. That is, in step STc, the same processing gas as that used in step STb may be used. Gas switching may not be performed between step STb and step STc.

[0043] In step STc, the control unit 2 controls the gas supply unit 20 to supply the processing gas into the plasma processing chamber 10. In step STc, the control unit 2 controls the exhaust system 40 to set the pressure in the plasma processing chamber 10 to a specified pressure.

[0044] In step STc, the control unit 2 controls the high-frequency power supply 31 to supply the source high-frequency power RF to the high-frequency electrode in order to generate plasma from the process gas. In one embodiment, the power level of the source high-frequency power RF used in step STb may be equal to or higher than the power level of the source high-frequency power RF used in step STc.

[0045] In step STc, the control unit 2 controls the bias power supply 32 to supply the electrical bias EB to the bias electrode. In one embodiment, the level of the electrical bias EB used in step STc may be higher than the level of the electrical bias EB used in step STb.

[0046] In step STc, a negative voltage NV is applied to the upper electrode. In step STc, the control unit 2 controls the power supply 35 to apply the negative voltage NV to the upper electrode.

[0047] The method MT may end after step STc. In one embodiment, the cycle CY including steps STb and STc may be repeated. The cycle CY may include only steps STb and STc. The length of one cycle of the cycle CY may be 200 to 10,000 μs (microseconds).

[0048] Each change in the power level of the source high-frequency power RF and the level of the electrical bias EB in the cycle CY may be synchronized with each other. For example, the period P1 during which the power level of the source high-frequency power RF is the first power level and the period P1 during which the level of the electrical bias EB is the first level may be synchronized with each other. Also, the period P2 during which the power level of the source high-frequency power RF is the second power level below the first power level and the period P2 during which the level of the electrical bias EB is the second level higher than the first level may be synchronized with each other.

[0049] Further, the change in the level of the negative voltage NV in the cycle CY may be synchronized with the change in the power level of the source high-frequency power RF. For example, the period P1 during which the power level of the source high-frequency power RF is at the first power level and the period P1 during which the level of the negative voltage NV is at the first level may be synchronized with each other. For example, the period P2 during which the power level of the source high-frequency power RF is at the second power level and the period P2 during which the level of the negative voltage NV is at the second level may be synchronized with each other. In the negative voltage NV, the absolute value of the second level is smaller than the absolute value of the first level.

[0050] The repetition frequency of the cycle CY may be 0.1 Hz or more and 1.0 kHz or less. The repetition frequency of the cycle CY may be 1.2 Hz or more and may be 5.1 kHz or less.

[0051] In the cycle CY, the control unit 2 controls the high-frequency power supply 31 and the bias power supply 32 so as to sequentially change at least one of the power level of the source high-frequency power RF and the level of the electrical bias EB to two different levels from each other. Further, in the cycle CY, the control unit 2 may control the power supply 35 so as to sequentially change the level (absolute value of the voltage level) of the negative voltage NV applied to the upper electrode to two different levels.

[0052] When the cycle CY is repeated, as shown in FIG. 1, the method MT further includes a step STJ. In the step STJ, it is determined whether or not a stop condition is satisfied. The stop condition is satisfied when the number of executions of the cycle CY reaches a predetermined number. When it is determined in the step STJ that the stop condition is not satisfied, the cycle CY is performed again. When it is determined in the step STJ that the stop condition is satisfied, the method MT may end. After the method MT, as shown in FIG. 4(d), the film EF may be etched using the plasma generated in the plasma processing chamber 10.

[0053] According to method MT, since the absolute value of the negative voltage NV applied to the upper electrode in process STb is large, the deposition rate of the deposit DP can be increased in process STb. On the other hand, since the absolute value of the negative voltage NV applied to the upper electrode in process STc is small, the etching rate of the deposit DP can be increased in process STc. When the deposition rate of the deposit DP in process STb is high, by shortening the time of process STb, the time (total duration of processes STb and STc) for shaping the resist mask PR can be shortened. Therefore, throughput can be improved in the processing of the substrate W. Also, since the absolute value of the negative voltage NV applied to the upper electrode in process STb is large, the C / F ratio (ratio of carbon atoms to fluorine atoms) in the deposit DP can be increased. Such a deposit DP has high etching resistance. Thus, in process STc, damage to the resist mask PR can be suppressed, and an increase in the surface roughness of the resist mask PR can be suppressed. Furthermore, since the absolute value of the negative voltage NV applied to the upper electrode in process STc is small, the deposit DP can be etched even when the ion energy incident on the substrate W is lowered. Therefore, in process STc, damage to the resist mask PR can be suppressed, and an increase in the surface roughness of the resist mask PR can be suppressed.

[0054] Hereinafter, with reference to FIGS. 6 and 7(a) to 7(d), a plasma processing method according to another exemplary embodiment will be described. FIG. 6 is a flowchart of a plasma processing method according to another exemplary embodiment. Each of FIGS. 7(a) to 7(d) is a partially enlarged cross-sectional view of an example substrate related to each step of a plasma processing method according to another exemplary embodiment. Hereinafter, the plasma processing method shown in FIG. 6 (hereinafter referred to as "method MTA") will be described by taking as an example the case where the plasma processing apparatus 1 is used. Note that method MTA may be performed using a plasma processing apparatus different from the plasma processing apparatus 1.

[0055] The method MTA is applied to the substrate W shown in FIG. 7(a). As shown in FIG. 7(a), the substrate W includes a base region UR, a film EF1, a mask MHM, a silicon oxide film OXM, an organic film OF, a film EF, and a resist mask PR.

[0056] The base region UR is, for example, an etching stop layer. The base region UR may have a laminated structure including an aluminum oxide film and a SiCN film. The film EF1 is provided on the base region UR. The film EF1 is a dielectric film and may contain silicon and oxygen. In one embodiment, the film EF1 may include a low-k dielectric film LKF. The film EF1 may have a laminated structure including a low-k dielectric film LKF and a silicon oxide film OXF. Note that the low-k dielectric film LKF may be a SiOCH film.

[0057] The mask MHM is a metal hard mask and is provided on the film EF1. The mask MHM has a pattern that is transferred to the film EF1 by etching. That is, the mask MHM provides one or more openings. The mask MHM may contain at least one metal selected from the group consisting of titanium, tungsten, molybdenum, and ruthenium. The mask MHM is formed of, for example, titanium nitride. The mask MHM may be formed of other metal-containing materials.

[0058] The silicon oxide film OXM is provided on the top of the mask MHM. The organic film OF is provided so as to cover the silicon oxide film OXM, the mask MHM, and the film EF1. The film EF is provided on the organic film OF. The film EF is a silicon-containing film containing silicon and oxygen. The film EF may be an antireflection film. The resist mask PR is provided on the film EF. The resist mask PR is patterned using photolithography technology. The resist mask PR provides one or more openings in order to form recesses (e.g., trenches or holes) in the film EF at the portions exposed from the mask MHM.

[0059] Returning to FIG. 6, method MTA includes step STa. In step STa of method MTA, similarly to step STa of method MT, a substrate W (see (a) of FIG. 7) is prepared on the substrate support portion 11 in the plasma processing chamber 10 of the plasma processing apparatus 1. The steps of method MTA performed after step STa are performed with the substrate W placed on the substrate support portion 11.

[0060] In method MTA, after step STa, step ST1 is performed. In step ST1, the shape of the resist mask PR is adjusted. In step ST1, steps STb and STc of method MT are performed. In step ST1, the cycle CY including steps STb and STc may be repeated.

[0061] In step ST1, the control unit 2 controls the gas supply unit 20 to supply the processing gas into the plasma processing chamber 10. In step ST1, the control unit 2 controls the exhaust system 40 to set the pressure in the plasma processing chamber 10 to a specified pressure. In step ST1, the control unit 2 controls the high-frequency power supply 31 to supply the source high-frequency power RF to the high-frequency electrode in order to generate plasma from the processing gas. In step ST1, the control unit 2 may control the bias power supply 32 to supply the electrical bias EB to the bias electrode or not to supply the electrical bias EB to the bias electrode. In step ST1, the control unit 2 may control the power supply 35 to supply a negative voltage NV to the upper electrode.

[0062] Next, step ST2 is performed. In step ST2, the film EF is etched. By step ST2, the pattern of the resist mask PR is transferred to the film EF. In step ST2, plasma is generated from the etching gas in the plasma processing chamber 10 for etching the film EF. The etching gas used in step ST2 includes a fluorocarbon gas and a noble gas (e.g., Ar gas).

[0063] In step ST2, the control unit 2 controls the gas supply unit 20 to supply the etching gas into the plasma processing chamber 10. In step ST2, the control unit 2 controls the exhaust system 40 to set the pressure in the plasma processing chamber 10 to a specified pressure. In step ST2, the control unit 2 controls the high-frequency power supply 31 to supply the source high-frequency power RF to the high-frequency electrode in order to generate plasma from the etching gas. In step ST2, the control unit 2 may control the bias power supply 32 to supply the electrical bias EB to the bias electrode.

[0064] Next, step ST3 is performed. In step ST3, the organic film OF is etched. By step ST3, as shown in Fig. 7(b), the pattern of the film EF is transferred to the organic film OF. In step ST3, plasma is generated from the etching gas in the plasma processing chamber 10 for etching the organic film OF. The etching gas used in step ST3 contains an oxygen-containing gas (e.g., oxygen gas). Alternatively, the etching gas used in step ST3 may contain nitrogen gas and hydrogen gas.

[0065] In step ST3, the control unit 2 controls the gas supply unit 20 to supply the etching gas into the plasma processing chamber 10. In step ST3, the control unit 2 controls the exhaust system 40 to set the pressure in the plasma processing chamber 10 to a specified pressure. In step ST3, the control unit 2 controls the high-frequency power supply 31 to supply the source high-frequency power RF to the high-frequency electrode in order to generate plasma from the etching gas. In step ST3, the control unit 2 may control the bias power supply 32 to supply the electrical bias EB to the bias electrode.

[0066] Next, step ST4 is performed. In step ST4, the film EF1 is etched. By step ST4, as shown in Fig. 7(c), the pattern of the organic film OF is transferred to the film EF1, and recesses are formed in the film EF1.

[0067] In step ST4, the control unit 2 controls the gas supply unit 20 to supply the etching gas into the plasma processing chamber 10. In step ST4, the control unit 2 controls the exhaust system 40 to set the pressure in the plasma processing chamber 10 to a specified pressure. In step ST4, the control unit 2 controls the high-frequency power supply 31 to supply the source high-frequency power RF to the high-frequency electrode in order to generate plasma from the etching gas. In step ST4, the control unit 2 may control the bias power supply 32 to supply the electrical bias EB to the bias electrode.

[0068] Next, step ST5 is performed. In step ST5, the organic film OF is removed. In step ST5, plasma is generated from the ashing gas in the plasma processing chamber 10 to remove the organic film OF. The ashing gas used in step ST5 includes an oxygen-containing gas (for example, oxygen gas and / or CO gas).

[0069] In step ST5, the control unit 2 controls the gas supply unit 20 to supply the ashing gas into the plasma processing chamber 10. In step ST5, the control unit 2 controls the exhaust system 40 to set the pressure in the plasma processing chamber 10 to a specified pressure. In step ST5, the control unit 2 controls the high-frequency power supply 31 to supply the source high-frequency power RF to the high-frequency electrode in order to generate plasma from the etching gas.

[0070] Next, step ST6 is performed. In step ST6, as shown in FIG. 7(d), the film EF1 is further etched to increase the depth of the concave portion.

[0071] According to method MTA, the same operational effects as those of method MT can be obtained. According to method MTA, by shortening the time of step STb during step ST1, the time for shaping the resist mask PR can be shortened.

[0072] Although various exemplary embodiments have been described above, various omissions, substitutions, and changes may be made without being limited to the above-described exemplary embodiments. Also, it is possible to form other embodiments by combining elements in different embodiments.

[0073] Hereinafter, various experiments conducted for the evaluation of method MT and method MTA will be described. The experiments described below do not limit the present disclosure.

[0074] A plurality of sample substrates including a photoresist film were prepared. Using the plasma processing apparatus 1, the sample substrates were processed with plasma generated from a processing gas containing a gas component containing fluorine and carbon. By changing the source high-frequency power (HF) for generating the plasma and the electrical bias (LF) supplied to the substrate support portion, the ion energy incident on the substrate was changed. Also, the negative voltage applied to the upper electrode was changed to three values of -150 V, -450 V, and -900 V. For each sample substrate after plasma processing, the thickness of the photoresist film was measured to calculate the change amount of the photoresist film. Using the plasma processing time (1 minute) and the change amount of the photoresist film, the etching rate (nm / min) of the photoresist film was calculated and converted to the etching rate per 500 μs. The results are shown in FIG. 8.

[0075] FIG. 8 is a graph showing an example of the relationship between ion energy and etching rate. The vertical axis represents the etching rate of the photoresist film (1×10 -5It shows (nm / 500 μs). A positive value on the vertical axis indicates that the photoresist film has been etched. A negative value on the vertical axis indicates that a deposit has been formed on the photoresist film. The horizontal axis shows the ion energy (eV) incident on the substrate. As shown in FIG. 8, as the ion energy increases, etching tends to be dominant. Also, as the absolute value of the negative voltage applied to the upper electrode increases, deposition tends to be dominant. Therefore, in the deposition process, it can be seen that increasing the absolute value of the negative voltage applied to the upper electrode can increase the deposition rate without increasing the ion energy (see region AR1 in FIG. 8). On the other hand, in the etching process, it can be seen that decreasing the absolute value of the negative voltage applied to the upper electrode can increase the etching rate without increasing the ion energy (see region AR2 in FIG. 8).

[0076] From the above description, it will be understood that the various embodiments of the present disclosure have been described herein for the purpose of illustration and that various changes can be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the appended claims.

Description of Reference Numerals

[0077] 1... Plasma processing apparatus, 10... Plasma processing chamber, 11... Substrate support part, EF... Film, DP... Deposit, PR... Resist mask, W... Substrate.

Claims

【Claim 1】 (a) A step of preparing a substrate on a substrate support in a chamber of a plasma processing apparatus, the substrate including a film containing silicon and oxygen and a resist mask provided on the film; and (b) A step of forming a deposit on the substrate while applying a negative voltage to an upper electrode disposed above the substrate support, the deposit being supplied from plasma generated from a processing gas containing a gas component containing fluorine and carbon in the chamber; and (c) A step of etching the deposit using the plasma generated from the processing gas while applying a negative voltage to the upper electrode; including In the step (c), the power level of the source high-frequency power used to generate the plasma from the processing gas is equal to or lower than the power level of the source high-frequency power used to generate the plasma from the processing gas in the step (b), In the step (c), the level of the electrical bias supplied to the substrate support is higher than the level of the electrical bias supplied to the substrate support in the step (b), or no electrical bias is supplied to the substrate support in the step (b), A plasma processing method, wherein the absolute value of the negative voltage applied to the upper electrode in the step (b) is set to a value larger than the absolute value of the negative voltage applied to the upper electrode in the step (c).

Images