Method for manufacturing thin film transistor

Abstract

To provide a method for manufacturing top gate thin film transistors that suppresses negative shift of threshold voltage after post annealing.SOLUTION: A method for manufacturing a top gate thin film transistor 1 includes: a patterning process for patterning a semiconductor layer 3 composed of an oxide semiconductor film deposited on a substrate 2 by photolithography; a first pre-annealing process for annealing the oxide semiconductor film after patterning; a pretreatment process for plasma processing the surface of the oxide semiconductor film (gate insulating layer 4) after annealing; and a gate insulating film deposition process for depositing a gate insulating film 4 on the oxide semiconductor film after plasma processing.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a thin film transistor.

Background Art

[0002] In recent years, development of thin film transistors using an In-Ga-Zn-O-based (IGZO) oxide semiconductor as a semiconductor layer (channel layer) has been actively carried out. For example, Patent Document 1 describes a method for manufacturing a top gate type thin film transistor in which a channel layer, a gate insulating layer, and a gate electrode are laminated in this order from the substrate side.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above-described method for manufacturing a top gate type thin film transistor, post-annealing treatment may be performed at the final stage of the manufacturing process for the purpose of improving the field effect mobility. However, there is a problem that the gate threshold voltage Vth of the thin film transistor obtained by this post-annealing treatment shifts negatively.

[0005] The present invention has been made in view of such problems, and the main object thereof is to provide a method for manufacturing a top gate type thin film transistor capable of suppressing a negative shift in the threshold voltage after post-annealing.

Means for Solving the Problems

[0006] That is, the method for manufacturing a thin film transistor of the present invention is a method for manufacturing a top gate type thin film transistor, including a patterning step of patterning an oxide semiconductor film formed on a substrate by photolithography, a first pre-annealing step of annealing the oxide semiconductor film after the patterning, a pre-treatment step of plasma-treating the surface of the oxide semiconductor film after the annealing, and a gate insulating film forming step of forming a gate insulating film on the oxide semiconductor film after the plasma treatment.

[0007] With such a manufacturing method, by annealing the oxide semiconductor film after the photolithography process and further plasma-treating its surface before forming the gate insulating film, carbon-based impurities (CO) contained in the photoresist remaining on the surface of the oxide semiconductor film can be removed. Thereby, the negative shift of the threshold voltage after post-annealing can be suppressed, and a stable threshold voltage (Vth) can be obtained.

[0008] As a specific embodiment of the pre-treatment step, a method of performing plasma treatment using plasma generated with O2 gas, N2 gas, or a mixed gas thereof as a process gas can be mentioned.

[0009] It is preferable that the gate insulating film forming step forms the gate insulating film by plasma CVD method. In this way, after generating plasma using a plasma treatment apparatus to perform plasma treatment, the gate insulating film can be formed as it is by changing the process gas species to be supplied without turning off the generated plasma, so that the processing time can be shortened.

[0010] It is preferable that the gate insulating film forming step includes a second pre-annealing step of annealing the oxide semiconductor film in an O2 atmosphere after forming the gate insulating film by plasma CVD method. By doing so, defects in the oxide semiconductor film caused by performing plasma treatment or film formation by plasma CVD method can be recovered by annealing treatment, and the resistance of the oxide semiconductor film necessary for TFT operation can be easily obtained.

[0011] In addition, the gate insulating film forming step forms the gate insulating film using plasma generated by applying high-frequency power to the antenna, and includes a first film forming step of forming the gate insulating film by applying a first high-frequency power of a predetermined magnitude to the antenna, and a second film forming step of forming the gate insulating film by applying a second high-frequency power greater than the first high-frequency power to the antenna after the first film forming step. By doing so, in the first film forming step where the applied high-frequency power is relatively small, plasma damage to the underlying oxide semiconductor film can be suppressed, and the reduction in the resistance of the oxide semiconductor film can be suppressed. In the second film forming step where the applied high-frequency power is relatively large, a film quality with excellent insulation can be obtained.

[0012] From the viewpoint of efficiently forming the gate insulating film while suppressing plasma damage to the oxide semiconductor film, it is preferable that the thickness of the gate insulating film formed by the second film forming step is larger than the thickness of the gate insulating film formed by the first film forming step.

Effect of the Invention

[0013] According to the present invention configured as described above, it is possible to provide a method for manufacturing a top-gate type thin film transistor capable of suppressing a negative shift in the threshold voltage after post-annealing.

Brief Description of the Drawings

[0014]

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Mode for Carrying Out the Invention

[0015] Hereinafter, a thin-film transistor 1 and a method for manufacturing the same according to an embodiment of the present invention will be described.

[0016] <1. Thin-film transistor 1> The thin-film transistor 1 of the present embodiment is a so-called top-gate type TFT that uses an oxide semiconductor for the channel. As shown in FIG. 1, this thin-film transistor 1 includes a semiconductor layer 3 as a channel layer, a gate insulating layer 4, and a gate electrode 5 laminated in this order from the substrate 2 side, and a source electrode 6 and a drain electrode 7 provided on both sides of the semiconductor layer 3.

[0017] The substrate 2 is made of an arbitrary material that can transmit light, and may be made of, for example, a resin material such as plastic (synthetic resin) such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic, polyimide, or a glass material.

[0018] The semiconductor layer 3 (channel layer) allows a current flowing between the source electrode 6 and the drain electrode 7 to pass through. The semiconductor layer 3 of this embodiment is made of an oxide semiconductor and contains, for example, an oxide of at least one element selected from In, Ga, Zn, Sn, Al, Ti, etc. as a main component. Specific examples of the material constituting the semiconductor layer 3 include, for example, In-Ga-Zn-O (IGZO), In-Al-Mg-O, In-Al-Zn-O, or In-Hf-Zn-O, etc. This semiconductor layer 3 is composed of an amorphous oxide semiconductor film. Although the semiconductor layer 3 of this embodiment has a single-layer structure, it is not limited to this, and it may also have a laminated structure formed by stacking a plurality of layers with different compositions and crystallinities.

[0019] The gate insulating layer 4 is composed of an arbitrary insulating material having high insulation properties. Here, it is composed of an insulating film (gate insulating film) containing SiO2 as a main component. Note that the material constituting the gate insulating layer 4 is not limited to this, and for example, it may be an insulating film containing one or more oxides selected from SiN x , SiON, Al2O3, Y2O3, Ta2O5, Hf2, etc. The gate insulating layer 4 may have a single-layer structure or a laminated structure of two or more layers of these insulating films.

[0020] The gate electrode 5 controls the carrier density in the semiconductor layer 3 by the gate voltage applied to the thin film transistor 1. This gate electrode 5 is composed of an arbitrary material having high conductivity and may be composed of, for example, one or more metals selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, etc. Also, it may be composed of a conductive film of a metal oxide such as Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), In-Ga-Zn-O (IGZO), etc. The gate electrode 5 may be composed of a single-layer structure or a laminated structure of two or more layers of these conductive films.

[0021] The source electrode 6 and the drain electrode 7 are formed to be spaced apart from each other so as to partially cover the surface of the semiconductor layer 3. The source electrode 6 and the drain electrode 7 are made of a material having high conductivity so as to function as electrodes, similar to the gate electrode 5. The source electrode 6 and the drain electrode 7 may have a single-layer structure made of a single material, or may have a laminated structure in which a plurality of layers made of different materials are stacked on each other.

[0022] <2. Manufacturing method of the thin film transistor 1> Next, a method for manufacturing the thin film transistor 1 having the above-described structure will be described. The manufacturing method of the thin film transistor 1 according to the present embodiment includes (1) a semiconductor layer forming step, (2) a gate insulating layer forming step, (3) a gate electrode forming step, (4) a source / drain electrode forming step, and (5) a post-annealing step. Hereinafter, each step will be described.

[0023] (1) Semiconductor layer forming step The semiconductor layer forming step includes (1-1) a film forming step of forming an oxide semiconductor film, (1-2) a patterning step of patterning the formed oxide semiconductor film, and (1-3) a first pre-annealing step of annealing the patterned oxide semiconductor film.

[0024] (1-1) Film forming step (oxide semiconductor film forming step) First, an oxide semiconductor film is formed on the substrate 2. The oxide semiconductor film may be formed by a known method. For example, an oxide semiconductor film may be formed by sputtering a conductive oxide sintered body such as InGaZnO as a target using inductively coupled plasma. Note that the present invention is not limited to this, and the oxide semiconductor film may be formed by other methods.

[0025] (1-2) Patterning step Next, the oxide semiconductor film formed on the substrate 2 is patterned by a photolithography process. Specifically, after applying a photoresist to the surface of the oxide semiconductor film, exposure, development, etc. are performed, and the resist is left only at the site to be the channel layer later. Then, the semiconductor layer 3 is formed by removing the uncoated portion by etching. As the etching method, dry etching using CF4 gas or the like may be performed, or wet etching using an acid such as HCl may be performed.

[0026] (1-3) First pre-annealing step In the first pre-annealing step, by annealing the oxide semiconductor film after the patterning step (after the photolithography process), carbon-based impurities (such as CO) contained in the photoresist remaining on the surface of the oxide semiconductor film are removed. The first pre-annealing step is preferably performed, for example, in an oxygen atmosphere at a temperature of 300°C or higher and 450°C or lower for 0.5 hours or more and 3 hours or less, and preferably performed at about 350°C for about 2 hours in an oxygen atmosphere.

[0027] (2) Gate insulating layer formation step After the first pre-annealing step, a gate insulating layer 4 is formed on the semiconductor layer 3 made of an oxide semiconductor film. The gate insulating layer formation step includes (2-1) a pretreatment step of plasma-treating the surface of the oxide semiconductor film, (2-2) a film formation step of forming a gate insulating film on the oxide semiconductor film, and (2-3) a second pre-annealing step of annealing the oxide semiconductor film after forming the gate insulating film.

[0028] (2-1) Pretreatment step Before the film formation step, by performing plasma treatment (specifically, plasma ashing) on the surface of the oxide semiconductor film, carbon-based impurities (such as CO) contained in the photoresist remaining on the surface of the oxide semiconductor film can be further removed.

[0029] Plasma treatment may be performed using an inductively coupled plasma processing apparatus 100 as illustrated in FIG. 2. Specifically, the plasma processing apparatus 100 includes a vacuum vessel 20 having an inner processing chamber 10 that is evacuated and into which a process gas G is introduced, an antenna 30 provided inside the processing chamber 10, and a high-frequency power supply 40 that applies a high frequency (13.56 MHz) to the antenna 30. When a high frequency is applied from the high-frequency power supply 40 to the antenna 30, a high-frequency magnetic field generated from the antenna 30 forms in the processing chamber 10, generating an induced electric field, thereby generating an inductively coupled plasma P.

[0030] Specifically, in this step, oxygen gas is supplied into the processing chamber 10 as a process gas, and in this state, a high frequency is applied to the antenna 30 to generate an inductively coupled plasma, and plasma treatment is performed. The time for performing the plasma treatment is preferably 5 seconds or more. Note that the process gas may be nitrogen gas or a mixed gas of nitrogen gas and oxygen gas. In this embodiment, the supply flow rate of the process gas is 400 sccm, the high-frequency power (RF power) applied to the antenna 30 is 1.3 kW, the pressure inside the processing chamber is 2.7 Pa, the processing time is 10 seconds, and the substrate temperature is 180° C., but these are not limited thereto and may be appropriately changed.

[0031] (2-2) Film formation step (gate insulating film formation step) After the plasma treatment, a gate insulating film is formed on the oxide semiconductor film. In this embodiment, a gate insulating film mainly composed of SiO2 is formed by a plasma CVD method using the plasma processing apparatus 100. This film formation step is preferably performed continuously from the pre-treatment step while maintaining the plasma generated in the processing chamber 10 of the plasma processing apparatus 100 (that is, without turning off the light).

[0032] In this film formation step, a mixed gas of silane gas (SiH4 gas) and oxygen gas is supplied into the processing chamber 10 as a process gas, and in this state, a high frequency is applied to the antenna 30 to generate an inductively coupled plasma. The film formation step of this embodiment includes a first film formation step and a second film formation step in which the high-frequency power applied to the antenna 30 is different from each other.

[0033] First, perform the first film formation process. In this first film formation process, apply a first high-frequency power of a predetermined magnitude to the antenna 30 to generate an inductively coupled plasma for film formation. The magnitude of the first high-frequency power to be applied is preferably the same as the magnitude of the high-frequency power applied to the antenna 30 in the pretreatment process. For example, 1.3 kW is preferable, but it is not limited thereto. In the present embodiment, the supply flow rate of the process gas is 150 sccm for silane gas, 400 sccm for oxygen gas, the pressure in the processing chamber is 2.7 Pa, the film formation time is 5 seconds, and the substrate temperature is 180°C. However, these are not limited and may be appropriately changed.

[0034] After the first film formation process, continuously (i.e., without turning off the plasma), perform the second film formation process. In the second film formation process, apply a second high-frequency power greater than the first high-frequency power to the antenna 30 to generate an inductively coupled plasma for film formation. Here, the second high-frequency power is set to 1.9 kW, but it is not limited thereto. In the present embodiment, the supply flow rate of the process gas is 150 sccm for silane gas, 200 sccm for oxygen gas, the pressure in the processing chamber is 2.7 Pa, the film formation time is 65 seconds, and the substrate temperature is 180°C. However, these are not limited and may be appropriately changed. Also, in the second film formation process, the film formation time is preferably longer than the film formation time of the first film formation process (for example, 65 seconds). Other conditions such as the pressure in the processing chamber and the substrate temperature are preferably the same as those in the first film formation process.

[0035] Also, the thickness of the gate insulating film (second layer) formed by the second film formation process is preferably greater than the thickness of the gate insulating film (first layer) formed by the first film formation process. In this case, the film thickness of the first layer is preferably 10 nm or less. The first layer can suppress plasma damage to the underlying semiconductor layer (IGZO film) and suppress the reduction in the resistance of the semiconductor layer. On the other hand, the second layer can obtain a film quality with excellent insulating properties. Further, the flow rate ratio of silane gas (SiH4) to the flow rate of oxygen gas (O2) in the process gas supplied in the second film formation process is preferably made larger than the same flow rate ratio in the first film formation process.

[0036] (2-3) Second pre-annealing process In the second pre-annealing process, after forming a gate insulating film by plasma CVD method, the oxide semiconductor film is annealed to recover the defects of the oxide semiconductor film generated by plasma and make it easier to obtain the resistance of the oxide semiconductor film required for TFT operation. The second pre-annealing process is preferably performed, for example, in an oxygen atmosphere at a temperature of 300 °C or higher and 450 °C or lower for 0.5 hours or more and 3 hours or less. For example, it is preferably performed at about 350 °C for about 2 hours in an oxygen atmosphere.

[0037] (3) Gate electrode formation process After performing the second pre-annealing process, a gate electrode 5 is formed on the gate insulating film. The method of forming the gate electrode 5 is not particularly limited, and it may be performed by a known method such as a vacuum evaporation method.

[0038] (4) Source / drain electrode formation process Then, a source electrode 6 and a drain electrode 7 are formed on the semiconductor layer 3. The formation of the source electrode 6 and the drain electrode 7 is not particularly limited and may be performed by any known method.

[0039] (5) Post-annealing process After forming all the components, post-annealing (heat treatment) is performed. This post-annealing may be performed, for example, in a nitrogen atmosphere at atmospheric pressure. The temperature inside the furnace during post-annealing is not particularly limited. For example, it is 150 °C or higher and 350 °C or lower, and 200 °C or higher is preferable. Also, the heat treatment time is not particularly limited. For example, it is 1 hour or more and 3 hours or less.

[0040] As described above, the thin film transistor 1 of the present embodiment can be obtained.

[0041] <3. Effects of the present embodiment> In the manufacturing method of the thin-film transistor 1 of this embodiment configured as described above, before forming the gate insulating film, the oxide semiconductor film after the photolithography process is annealed, and the surface thereof is further plasma-treated, whereby carbon-based impurities (CO) contained in the photoresist remaining on the surface of the oxide semiconductor film can be removed. As a result, a negative shift in the threshold voltage after post-annealing can be suppressed, and a stable threshold voltage (Vth) can be obtained.

[0042] The effects of the manufacturing method of the thin-film transistor 1 of this embodiment were confirmed by experiments.

[0043] · Experimental Example 1 Multiple top-gate type thin-film transistors (see FIG. 3) in which the semiconductor layer was made of IGZO, the gate insulating layer 4 was made of SiO2, and the gate electrode 5 was made of a laminate of Pt and Mo were fabricated under different manufacturing conditions, and their transfer characteristics were evaluated. The results are shown in FIGS. 4 to 6.

[0044] As can be seen from FIGS. 4 to 6, in the sample in which the semiconductor layer made of IGZO was patterned by a photolithography process, annealed (first pre-annealing process) before forming the gate insulating layer 4 (SiO2), and further plasma-treated on the surface of the semiconductor layer, it was confirmed that the negative shift of the gate threshold voltage Vth after post-annealing could be suppressed compared to the sample in which the first pre-annealing process was not performed.

[0045] · Experimental Example 2 In Experimental Example 2, multiple top-gate type thin-film transistors (see FIG. 3) in which the semiconductor layer was made of IGZO, the gate insulating layer 4 was made of SiO2, and the gate electrode 5 was made of a laminate of Pt and Mo were fabricated by changing the plasma treatment time (no plasma treatment, 5 seconds, 10 seconds, 15 seconds), and their transfer characteristics were evaluated. The results are shown in FIG. 7. As can be seen from FIG. 7, it was confirmed that a stable threshold voltage (Vth) could be obtained in the samples in which the plasma treatment (pretreatment) was performed for 5 seconds or more compared to the samples in which the plasma treatment (pretreatment) was not performed.

[0046] In Experimental Example 3, a top-gate type thin film transistor (see FIG. 3) was fabricated in which the semiconductor layer was made of an IGZO film, the gate insulating layer 4 was made of SiO2 in two layers (a first layer and a second layer), and the gate electrode 5 was made of a laminate of Pt and Mo. A plurality of such transistors were fabricated with different thicknesses of the first layer, and the sheet resistance and leakage current density of the semiconductor layer were evaluated. The results are shown in FIG. 8.

[0047] As can be seen from FIG. 8, it was confirmed that in the sample with the second layer formed, the reduction of the resistance of the semiconductor layer (IGZO film) can be suppressed compared to the sample without the first layer formed. Also, as shown in FIG. 9, by making the thickness of the first layer smaller than the thickness of the second layer, the leakage current density can be reduced, and by making the thickness of the first layer 10 nm or less, the leakage current density can be reduced to -6 (A / cm 2 ) or less.

[0048] <4. Other Modification Embodiments> Note that the present invention is not limited to the above-described embodiments. For example, in the manufacturing method of the above-described embodiment, the gate insulating film forming step included the first film forming step and the second film forming step, but is not limited thereto. In other embodiments, the gate insulating film forming step may perform film formation without changing the high-frequency power applied to the antenna 30 midway.

[0049] Also, in the manufacturing method of the above-described embodiment, the gate insulating layer forming step included the second pre-annealing step, but is not limited thereto. In the manufacturing methods of other embodiments, the gate insulating layer forming step may not include the second pre-annealing step.

[0050] Needless to say, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit thereof.

Description of Reference Numerals

[0051] 1 ··· Thin film transistor 2 ··· Substrate 3 ··· Semiconductor layer 4 ··· Gate insulating layer 5 ··· Gate electrode 6 ··· Source electrode 7 ··· Drain electrode

Claims

1. A method for manufacturing a top-gate type thin film transistor, comprising: A patterning step of patterning an oxide semiconductor film formed on a substrate by photolithography; A first pre-annealing step of annealing the patterned oxide semiconductor film; A pre-treatment step of plasma-treating the surface of the annealed oxide semiconductor film; A gate insulating film forming step of forming a gate insulating film on the oxide semiconductor film after the plasma treatment, the method for manufacturing a thin film transistor comprising the above steps.

2. The method for manufacturing a thin film transistor according to claim 1, wherein the pre-treatment step performs plasma treatment using plasma generated by using O ２ gas, N ２ gas or a mixed gas thereof as a process gas.

3. The method for manufacturing a thin film transistor according to claim 1, wherein the gate insulating film forming step forms the gate insulating film by plasma CVD method.

4. The method for manufacturing a thin film transistor according to claim 3, wherein the gate insulating film forming step includes a second pre-annealing step of annealing the oxide semiconductor film in an O ２ atmosphere after forming the gate insulating film by plasma CVD method.

5. The gate insulating film forming step forms the gate insulating film using plasma generated by applying high-frequency power to an antenna, A first film forming step of forming the gate insulating film by applying a first high-frequency power of a predetermined magnitude to the antenna; The method for manufacturing a thin film transistor according to claim 3, further comprising a second film forming step of forming the gate insulating film by applying a second high-frequency power greater than the first high-frequency power to the antenna after the first film forming step.

6. The manufacturing method of the thin film transistor according to claim 5, wherein the thickness of the gate insulating film formed by the second film forming step is larger than the thickness of the gate insulating film formed by the first film forming step.

7. The manufacturing method of the thin film transistor according to claim 6, wherein the thickness of the gate insulating film formed by the first film forming step is 10 nm or less.

8. The manufacturing method of the thin film transistor according to claim 1, wherein plasma treatment is performed for 5 seconds or more in the pretreatment step.

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