Printed circuit board

Abstract

To provide a printed circuit board including a glass layer, also, to provide a printed circuit board with improved warpage characteristics, and furthermore, to a provide printed circuit board that can improve reliability.SOLUTION: The present invention relates to a printed circuit board including a glass layer with cavities, a through-via having a through-portion penetrating the glass layer, and a protrusion portion protruding upwards from an upper surface of the glass layer, an electronic component disposed in the cavity, and a first insulating layer filling at least a portion of the cavity and covering at least a portion of the electronic component.SELECTED DRAWING: Figure 3a

Description

Technical Field

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] Recently, due to the development of technologies such as Artificial Intelligence (AI), multi-chip packages including memory chips such as High Bandwidth Memory (HBM) for geometrically increasing data processing, and processor chips such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC), and Field Programmable Gate Array (FPGA) have been used. Therefore, there is a demand for substrates having a large-area structure, and efforts have continued to overcome problems related to the control of flatness and warpage.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of several objects of the present invention is to provide a printed circuit board including a glass layer.

[0004] Another one of several objects of the present invention is to provide a printed circuit board with improved warpage characteristics.

[0005] Another one of several objects of the present invention is to provide a printed circuit board capable of improving reliability.

Means for Solving the Problems

[0006] One of the solutions proposed through the present invention is to provide a printed circuit board including a glass layer having a cavity, a through-hole penetrating the glass layer, a through-via having a protruding portion protruding on the glass layer, an electronic component disposed in the cavity, and a first insulating layer filling at least a part of the cavity and covering at least a part of the electronic component.

[0007] Another one of the solutions proposed through the present invention is to provide a printed circuit board including a glass layer, a through-hole penetrating the glass layer, and a through-via having a protruding portion protruding on the glass layer, wherein, in a cross-section, the width at the uppermost side of the through-hole is substantially the same as the width at the lowermost side of the protruding portion.

Advantages of the Invention

[0008] One of the various advantages of the present invention is that a printed circuit board including a glass layer can be provided.

[0009] Another one of the various advantages of the present invention is that a printed circuit board with improved warping characteristics can be provided.

[0010] Another one of the various advantages of the present invention is that a printed circuit board capable of improving reliability can be provided.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, the present invention will be described with reference to the accompanying drawings. The shape, size, etc. of the elements in the drawings can be exaggerated or reduced for a clearer explanation.

[0013] Electronic device FIG. 1 is a block diagram schematically showing an example of an electronic device system.

[0014] Referring to the drawings, the electronic device 1000 houses a main board 1010. On the main board 1010, chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected. These are also combined with other electronic components described later to form various signal lines 1090.

[0015] Examples of the chip-related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; logic chips such as an analog-digital converter and an ASIC (application-specific IC). However, it is not limited to these, and it goes without saying that other different forms of chip-related electronic components may be included. Also, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in a package form including the above-described chips and electronic components.

[0016] Examples of the network-related component 1030 include, but are not limited to, Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated for those and later generations. In addition to these, any of a number of other different wireless or wired standards and protocols may also be included. Needless to say, the network-related component 1030 may be combined with the chip-related component 1020 and used in combination with each other.

[0017] Examples of the other component 1040 include, but are not limited to, high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Condensers), and the like. In addition to these, passive elements in the form of chip components used for various other different applications may also be included. Needless to say, the other component 1040 may be combined with the chip-related component 1020 and / or the network-related component 1030 and used in combination with each other.

[0018] Depending on the type of the electronic device 1000, the electronic device 1000 can include other electronic components that are physically and / or electrically connected or not connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it is not limited thereto, and it may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a CD (compact disk), a DVD (digital versatile disk), etc. Needless to say, in addition to these, other electronic components used for various purposes according to the type of the electronic device 1000 may also be included.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, it is not limited thereto, and needless to say, it may be any other electronic device that processes data other than these.

[0020] FIG. 2 is a perspective view schematically showing an example of an electronic device.

[0021] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. Inside the smartphone 1100, a motherboard 1110 is housed, and various components 1120 are physically and / or electrically connected to such a motherboard 1110. Also, other components that may or may not be physically and / or electrically connected to the motherboard 1110, such as a camera module 1130 and / or a speaker 1140, are housed inside. Some of the components 1120 may be the chip-related components described above, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with built-in active components and / or passive components. On the other hand, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100 and may be other electronic devices as described above.

[0022] Printed circuit board FIGS. 3a and 3b are cross-sectional views schematically showing a printed circuit board according to an example.

[0023] Referring to FIGS. 3a and 3b, a printed circuit board according to an example can include a glass layer 110 having a cavity CA, a via 130 penetrating the glass layer 110, a first insulating layer 111 filling the cavity CA, and electronic components 201, 202 disposed in the cavity CA. The via 130 may penetrate at least a part of the glass layer 110 or may protrude from a part of the glass layer 110. That is, the via 130 can have a penetrating portion penetrating the glass layer 110 and a protruding portion protruding on the glass layer 110. The penetrating portion and the protruding portion of the via 130 may be integrally formed.

[0024] The printed circuit board according to an example includes a glass layer 110, so it can basically have excellent flatness, and furthermore, it can be advantageous for warpage control due to a low coefficient of thermal expansion (CTE) and the like. In particular, the printed circuit board according to an example can have the glass layer 110 as a core, so it can be advantageous for warpage control even at the stage of laminating other insulating layers. Also, due to the dielectric properties of the glass layer 110, for example, the characteristics of glass having variable properties of Dk 2.5 to 11, the number of layers of the printed circuit board can be reduced, and the design freedom can be further increased.

[0025] The glass layer 110 can be disposed on the outermost side of the printed circuit board. The printed circuit board according to an example may be a so-called coreless type substrate in which a first insulating layer 111 and / or a second insulating layer 112 are built up under the glass layer 110. The printed circuit board according to an example can be advantageous for controlling warpage characteristics even when manufacturing a coreless type substrate by disposing the glass layer 110 on the outermost side. In particular, in the case of a large-area coreless type substrate, there is a high possibility of defects due to warpage, and when realizing a fine circuit or manufacturing a multi-layer substrate, even a slight warpage may cause defects in the substrate. However, the printed circuit board according to an example can be advantageous for controlling warpage characteristics because the glass layer 110 is disposed on the outermost side and the glass layer 110 is exposed on the upper side of the printed circuit board. However, it is not limited thereto, and other means for protecting the glass layer 110 on the completed substrate can be further included, but in this case as well, the glass layer 110 can be disposed on the uppermost side among the build-up layers.

[0026] The printed circuit board according to one example includes a glass layer 110 as a component of the board and can form part of a build-up layer. This is clearly different from a glass interposer in which a glass layer 110 having a cavity CA is separately manufactured and connected by soldering or the like. In the printed circuit board according to one example, the glass layer 110 and the first insulating layer 111 can be positioned to be in contact with each other, and the first via layer 131 formed on the glass layer 110 can be in direct contact with the through via 130. In addition, details regarding the arrangement relationship among the glass layer 110, the first insulating layer 111, the first wiring layer 121, and the first via layer 131 in the printed circuit board according to one example will be described later.

[0027] The glass layer 110 can include glass, which is an amorphous solid. The glass can include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited thereto, and alternative glass materials such as fluorine glass, phosphate glass, chalcogen glass, etc. can also be used as the material of the glass layer 110. Further, in order to form glass having specific physical properties, other additives can be further included. Such additives can include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements as well as other elements. The glass layer 110 is a layer distinguishable from materials including glass fiber (Glass Fiber, Glass Cloth, Glass Fabric), etc., such as CCL (Copper Clad Laminate), PPG (Prepreg), etc., and can be understood as, for example, plate glass.

[0028] The glass layer 110 can have a cavity CA. The cavity CA can penetrate the upper and lower surfaces of the glass layer 110 and can have an upward tapered shape. That is, the cavity CA can have a tapered shape such that the width at the upper surface of the glass layer 110 is narrower than the width at the lower surface, which can be the result of forming the cavity CA from the lower side to the upper side of the glass layer 110. On the other hand, without necessarily being limited to this, the cavity CA may have a tapered shape such that the width at the lower surface of the glass layer 110 is narrower than the width at the upper surface, and may be formed such that the width at the central portion of the glass layer 110 is narrower than the widths at the upper and lower surfaces respectively, and may be formed such that the width at the central portion is the narrowest. This can be the result of forming the cavity CA in the glass layer 110 and then attaching it to a carrier to manufacture a substrate. In the cavity CA, the first electronic component 201 and / or the second electronic component 202 can be mounted. The first electronic component 201 and the second electronic component 202 are arranged on the outermost side of the printed circuit board and can be connected to other electronic components such as the first semiconductor chip 301 and / or the second semiconductor chip 302. At this time, the first electronic component 201 and the second electronic component 202 are arranged in the cavity CA and can be embedded by the first insulating layer 111 and protrude to the outermost side.

[0029] A printed circuit board according to an example can include a through hole 130 that penetrates the glass layer 110. The through hole 130 may penetrate the upper and lower surfaces of the glass layer 110, and a part of the through hole 130 may protrude above the glass layer 110. That is, the through hole 130 can have a through portion that penetrates the glass layer 110 and a protruding portion that protrudes from the glass layer 110. At this time, the through portion and the protruding portion may be integrally formed.

[0030] The through via 130 can contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can contain copper (Cu), but is not limited thereto. The through via 130 can include an electrolytic plating layer (or electroplated copper). However, it is not limited thereto, and the through via can further include an electroless plating layer (or electroless copper) disposed along the inner wall of the through hole. Instead of the electroless plating layer (or electroless copper), a sputtering layer can be included, or both can be included as needed. On the other hand, without being limited thereto, the through via 130 can include a sintered layer and / or a fired layer. Preferably, the through via 130 can be formed by electrolytic plating using a carrier seed, but can also be formed by electrolytic plating after electroless plating and / or sputtering on the via hole, or can be formed by a method of filling a paste containing a metal substance and then sintering and firing.

[0031] The through via 130 may protrude from the upper surface of the glass layer 110 and may not protrude from the lower surface of the glass layer 110. That is, the upper surface of the through via 130 is located higher than the upper surface of the glass layer 110, and the through portion of the through via 130 can protrude above the glass layer 110. Also, the lower surface of the through via 130 can be substantially coplanar with the lower surface of the glass layer 110. Therefore, in an example, the printed circuit board has a through via 130 that protrudes above the glass layer 110 and can be substantially coplanar with the glass layer 110 on the lower side.

[0032] This can be the result of attaching a glass layer 110 with through-holes formed thereon to a resist in the stage of forming through-vias 130, further removing a part of the resist corresponding to the through-holes, forming the through-vias, and then removing the resist. Therefore, the through-via 130 can protrude on the side where the resist is formed, and on the side opposite to the side where the resist is formed, the through-via 130 can have a surface substantially coplanar with the glass layer 110. This is a structural difference that can occur in the manufacturing method of the glass layer 110 and the through-via 130, and is different from a through-via structure in which both sides protrude from the glass layer and is also different from a through-via structure in which both sides are coplanar with the glass layer.

[0033] The through-via 130 of a printed circuit board according to an example has a protruding portion protruding above the glass layer 110. Therefore, the through-via 130 can be connected to other electronic components. In particular, because it has a structure protruding from the glass layer 110, it can also perform the function of a post. That is, the upper side of the through-via 130 protrudes from the glass layer 110, and it can be easier to couple with electronic components such as semiconductor chips. On the other hand, since the lower surface of the through-via 130 is substantially coplanar with the lower surface of the glass layer 110, bending or unevenness cannot occur in the stage of laminating the first insulating layer 111 and / or the second insulating layer 112 to form a build-up layer. Therefore, undulation can be prevented from occurring in the build-up stage, and the flatness can be improved.

[0034] On the other hand, in the case of the through via 130 of the printed circuit board according to one example, in a cross section, the width at the uppermost side of the through portion can be substantially the same as the width at the lowermost side of the protruding portion. The width at the uppermost side of the through portion and the width at the lowermost side of the protruding portion can be measured by photographing a cross-sectional cut in the stacking direction of the printed circuit board with a scanning microscope or the like so as to pass through the central axis of the via. That the width at the uppermost side of the through portion and the width at the lowermost side of the protruding portion can be substantially the same can mean that the through portion and the protruding portion are continuously formed. This can be the result of forming the second through hole that penetrates the resist after the glass layer 110 in which the first through hole is formed is disposed on the resist, and then forming the through via 130 so as to simultaneously fill the first through hole and the second through hole. At this time, after forming the glass layer 110 in which the first through hole is formed in the resist, in order to form the second through hole corresponding to the first through hole, the width of the first through hole at the boundary between the first through hole and the second through hole can be substantially the same as the width of the second through hole. Therefore, the widths at the boundary between the protruding portion and the through portion of the through via 130 can be substantially the same as each other, and the through portion and the protruding portion can be integrated. This is different from the case where a land portion is formed at the stage of forming the through via 130 in the glass layer 110, and the through via 130 of the printed circuit board according to one example may not be extended so as to contact the upper surface of the glass layer 110. However, this means that it is different from the case where a land portion is formed on the upper surface of the glass layer 110, and the arrangement due to errors or the like in the manufacturing stage caused by the second through hole formed in the resist in the manufacturing stage of the printed circuit board having a wider width than the first through hole formed in the glass layer 110 may not be included.

[0035] The penetrating portion and the protruding portion of the through via 130 may be integrally formed. That is, the through via 130 does not form a protruding portion protruding on the glass layer 110 in a separate process after forming a penetrating portion penetrating the glass layer 110. Instead, after forming the through via 130 so as to simultaneously fill the respective through holes formed in the resist and the glass layer, the resist is removed. Therefore, the protruding portion and the penetrating portion of the through via 130 can be integrally formed. That is, the penetrating portion and the protruding portion of the through via 130 are merely for convenience of distinction depending on whether their respective positions are inside or outside the glass layer 110, and there may be a case where no boundary can be seen between the penetrating portion and the protruding portion.

[0036] The through via 130 can have an upward taper shape. On the other hand, in FIGS. 3a and 3b, the through via 130 is shown as having a substantially upward taper shape, but is not necessarily limited thereto. The through via 130 can have substantially the same shape as the cavity CA. Here, substantially the same shape means that when observed through a scanning microscope or an optical microscope based on the polished or cut cross-section of the printed circuit board, the taper directions are substantially the same, and it can mean that the width size relationships at the upper, central, and lower sides are similar. This can be the result of simultaneously performing the step of forming the cavity CA in the glass layer 110 at the stage of forming the through hole in the glass layer 110 to form the through via 130. At this time, since the penetrating portion and the protruding portion of the through via 130 can be integrally formed at the same stage, the penetrating portion and the protruding portion of the through via 130 can have a taper shape with substantially a certain direction and degree. This means that the penetrating portion and the protruding portion may have a taper shape such that they have substantially the same inclination and slope with respect to the upper surface of the glass layer.

[0037] On the one hand, since the printed circuit board according to one example does not form the protruding portion of the via 130 by a method of removing a part of the upper surface of the glass layer 110, the upper surface and the lower surface of the glass layer 110 can have substantially the same surface roughness. However, it is not necessarily limited to this, and since the lower surface of the glass layer 110 may be processed so as to be substantially coplanar with the lower surface of the via 130, they can also have different surface roughnesses. However, even in this case, the upper surface of the glass layer 110 is not processed to form a surface roughness.

[0038] In the cavity CA of the glass layer 110, the first electronic component 201 and / or the second electronic component 202 can be mounted. The first electronic component 201 and the second electronic component 202 may each be various types of electronic components, and may be active components and / or passive components, etc. In the case of active components, they may be various types of integrated circuit (IC) dies in which hundreds to millions or more circuits are integrated in one chip. The passive component may be a chip-type capacitor such as an MLCC (Multi-Layer Ceramic Capacitor) like a silicon capacitor, or may be a chip-type inductor such as a PI (Power Inductor), etc. However, it is not limited to this, and other types of active components and / or passive components may also be arranged. Also, the first electronic component 201 and / or the second electronic component 202 may be a bridge for die-to-die connection. The bridge may be a silicon bridge, or may be in the form of a semiconductor chip in which a fine circuit is realized on a silicon wafer. On the other hand, without being limited to this, the first electronic component 201 and / or the second electronic component 202 may be a so-called organic bridge containing an organic insulating material. Thus, there is no limitation on the content regarding the first electronic component 201 and the second electronic component 202, and any component or element that can be connected to the printed circuit board and perform functions, such as being mounted on the printed circuit board or embedded in the printed circuit board, can be used without limitation. The first electronic component 201 can connect the second electronic component 202 to different semiconductor chips from each other, or can be connected to one semiconductor chip to transmit and receive power or signals.

[0039] The first electronic component 201 and the second electronic component 202 can each include a metal pillar 203. The metal pillar 203 can contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can include copper (Cu), but is not limited thereto.

[0040] Similar to the through-via 130, at least a part of the metal pillar 203 can protrude from the printed circuit board. That is, the metal pillar 203 can function as a path for protruding from the first insulating layer 111 configured to embed the metal pillar 203 and being electrically connected to other components. That is, the metal pillar 203 can have a structure protruding more than the first insulating layer 111, and the upper surface of the metal pillar 203 can be positioned higher than the upper surface of the first insulating layer 111 and the upper surface of the glass layer 110 and have a protruding structure. Also, the upper surface of the metal pillar 203 can be substantially coplanar with the upper surface of the through-via 130. That is, since the through-via 130 and the metal pillar 203 can each function as a means for connecting to the semiconductor chip in the printed circuit board, it can be advantageous in connection with other components such as the semiconductor chip that the through-via 130 and the metal pillar 203 have protruding surfaces of the same height. An example of the printed circuit board is that after forming a glass layer with a cavity CA formed on the resist, after mounting the first electronic component 201 and the second electronic component 202, the through-via 130 is formed, and a recess in which a part of the through-via 130 is removed can be formed at the stage of removing the seed of the carrier substrate, and as a result of performing a grinding or polishing process so that the upper surface of the through-via 130 and the upper surface of the metal pillar 203 can be substantially coplanar at the stage of removing the resist. This will be described in more detail later in the manufacturing method of the printed circuit board.

[0041] On the one hand, in FIGS. 3a and 3b, for the first electronic component 201 and the second electronic component 202, it is shown that each includes a metal pillar 203 on the upper side and is connected to the first via layer 131 on the lower side, and both the upper surface and the lower surface are shown as active surfaces. However, it is not limited thereto, and the upper sides of the first electronic component 201 and the second electronic component 202 may be active surfaces and the lower sides may be non-active surfaces. In this case, the lower surface, which is the non-active surface of the electronic component, is not connected to the first via layer 131 and can be connected to the outside via the metal pillar 203 located on the upper side. Note that it is not limited thereto, and the first electronic component 201 and the second electronic component 202 may also have only the lower surface as an active surface. At this time, the electronic component may not include the metal pillar 203. In this case, the electronic component is not directly connected to the outside and can be connected via other wirings of the printed circuit board.

[0042] The first insulating layer 111 can fill the cavity CA, is arranged to extend to the lower surface of the glass layer 110, and can be arranged on the glass layer 110. That is, the first insulating layer 111 is a build-up layer arranged on the glass layer 110, is formed to fill the cavity CA, and can cover at least a part of the first electronic component 201 and the second electronic component 202 arranged in the cavity CA, and can also be arranged on the lower surface of the glass layer 110.

[0043] The first insulating layer 111 can contain an organic insulating material. The organic insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with the resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film), PPG (Prepreg), etc., but is not limited thereto, and other polymer materials may also be used. Also, the insulating material may be a photosensitive insulating material such as PID (Photo Imageable Dielectric). Further, the insulating material may include an adhesive sheet such as BS (Bonding Sheet).

[0044] The upper surface of the first insulating layer 111 and the upper surface of the glass layer 110 can be substantially coplanar with each other. Referring to FIGS. 3a and 3b, the upper surface of the first insulating layer 111 can mean the upper surface in the portion of the first insulating layer 111 that fills the cavity CA of the glass layer 110, and can mean the upper surface of the portion of the first insulating layer 111 that is adjacent to the upper surface of the glass layer 110 and is exposed to the outside. In the manufacturing method of the printed circuit board, after forming a resist on the carrier substrate, forming the glass layer 110 with the cavity CA formed therein, and then forming the first insulating layer 111 so as to fill the cavity CA, since the upper surface of the first insulating layer 111 cannot be formed above the resist exposed by the cavity CA, the upper surface of the first insulating layer 111 can be substantially coplanar with the upper surface of the glass layer 110.

[0045] On the one hand, the printed circuit board according to one example does not form the protruding portion of the through via 130 by removing a part of the upper surface of the first insulating layer 111. Therefore, the upper surface of the first insulating layer 111 can have substantially the same surface roughness as the side surface of the first insulating layer 111 disposed on the inner wall of the cavity CA or the lower surface of the first insulating layer 111. However, it is not necessarily limited to this. Since the lower surface of the first insulating layer 111 may be processed to be substantially coplanar with the lower surface of the through via 130, they can also have different surface roughnesses from each other. However, even in this case, the upper surface of the first insulating layer 111 is not processed to form a surface roughness.

[0046] The printed circuit board according to one example can include a first wiring layer 121 disposed on the first insulating layer 111, and can include a first via layer 131 penetrating at least a part of the first insulating layer 111. The first via layer 131 can be a configuration for connecting the first wiring layer 121 and the through via 130 to each other, and at least a part of the first via layer 131 can be in contact with the through via 130. That is, the first via layer 131 can be disposed on the lower surface of the glass layer 110 and can be distinguished from the through via 130, and the first via layer 131 can have an interface with the through via 130.

[0047] The first wiring layer 121 can contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can contain copper (Cu), but is not limited thereto. The first wiring layer 121 can perform various functions according to the respective design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. These patterns can each have various forms such as a line, a plane, a pad, etc. The first wiring layer 121 and the second wiring layer 122 can each include an electroless plating layer (or electroless copper) and an electroplating layer (or electroplated copper). Alternatively, it can include a metal foil (or copper foil) and an electroplating layer (or electroplated copper). Alternatively, it can include a metal foil (or copper foil), an electroless plating layer (or electroless copper), and an electroplating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer may be included, or both may be included as necessary.

[0048] The first wiring layer 121 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or a subtractive process, but is not limited thereto, and any process that can form a circuit in a printed circuit board can be used without limitation. Also, the first wiring layer 121 may be formed by different processes according to the application, design, etc.

[0049] The first via layer 131 can contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can contain copper (Cu), but is not limited thereto. The first via layer 131 can include filled vias that fill the via holes respectively, but can also include conformal vias arranged along the wall surfaces of the via holes. The first via layer 131 can perform various functions according to the design. For example, it can include ground vias, power vias, signal vias, etc.

[0050] At least a part of the first via layer 131 can connect the through via 130 and the first wiring layer 121 to each other, and a part of the first via layer 131 can also connect the first electronic component 201 or the second electronic component 202 and the first wiring layer 121 to each other. At this time, the first electronic component 201 or the second electronic component 202 can be respectively connected to the upper side and the lower side, and the upper surface and the lower surface can be respectively active surfaces. However, it is not necessarily limited thereto, and the first via layer 131 may not be connected to the first electronic component 201 or the second electronic component 202. In this case, the upper side of the first electronic component 201 or the second electronic component 202 may be the active surface. In this case, the first electronic component 201 or the second electronic component 202 may be directly connected to an element such as a semiconductor chip on the upper side. A part of the first via layer 131 and the first wiring layer connected to the first electronic component 201 or the second electronic component 202 can have a finer structure than the other part of the first via layer 131 and the first wiring layer connected to the through via 130, but is not necessarily limited thereto.

[0051] On the other hand, a printed circuit board according to an example includes a second insulating layer 112 disposed on a first insulating layer 111, a second wiring layer 122 disposed on the second insulating layer 112, and a second via layer 132 that penetrates at least a part of the second insulating layer 112 so as to connect the second wiring layer 122 and the first wiring layer 121 to each other or to connect the second wiring layers 122 to each other.

[0052] The second insulating layer 112 can include an organic insulating material. The organic insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with these resins. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may also be used. Further, the insulating material may be a photosensitive insulating material such as PID (Photo Imageable Dielectric). Further, the insulating material may include an adhesive sheet such as BS (Bonding Sheet). The second insulating layer 112 can include substantially the same insulating material as the first insulating layer 111, and the first insulating layer 111 and the second insulating layer 112 can each be disposed as a build-up insulating layer for build-up. However, it is not limited thereto, and the first insulating layer 111 and the second insulating layer 112 can include different insulating materials from each other.

[0053] The second wiring layer 122 can contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can contain copper (Cu), but is not limited thereto. The second wiring layer 122 can perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. These patterns can each have various forms such as lines, planes, pads, etc. The second wiring layer 122 can include an electroless plating layer (or electroless copper) and an electrolytic plating layer (or electroplated copper). Alternatively, it can include a metal foil (or copper foil) and an electrolytic plating layer (or electroplated copper). Alternatively, it can include a metal foil (or copper foil), an electroless plating layer (or electroless copper), and an electrolytic plating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer can be included, or both can be included as needed.

[0054] The second via layer 132 can contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, it can contain copper (Cu), but is not limited thereto. The second via layer 132 can include filled vias that fill the via holes, or can also include conformal vias arranged along the wall surfaces of the via holes. The second via layer 132 can perform various functions according to the design. For example, it can include ground vias, power vias, signal vias, etc. The second via layer 132 can each include an electroless plating layer (or electroless copper) and an electrolytic plating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer can be included, or both can be included as needed.

[0055] Each of the second wiring layer 122 and the second via layer 132 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive process, but is not limited thereto, and any process that can form circuits and vias in a printed circuit board can be used without limitation.

[0056] On the other hand, a printed circuit board according to an example may further include a solder resist layer 140 on the second insulating layer 112. The solder resist layer 140 is disposed on the outermost side of the printed circuit board and can protect the printed circuit board from the outside. A known solder resist can be used for the solder resist layer 140, and the solder resist layer 140 can include a liquid or film-type solder resist, but is not limited thereto, and other types of insulating materials may be used, and may include a thermosetting resin and an inorganic filler dispersed in the thermosetting resin, but may not include glass fibers. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but is not limited thereto, and other polymer materials may be used as necessary. The solder resist layer 140 can have openings, and at least a part of the second wiring layer 122 can be exposed through the openings. The second wiring layer 122 exposed through the openings can be connected to elements such as semiconductor chips, and can also be connected to a motherboard, a main board, or other printed circuit boards. The wiring layer exposed through the openings functions as a pad, and a surface treatment layer may be further formed on the pad as necessary.

[0057] Although a printed circuit board according to an example is shown with the second insulating layer 112 and the second wiring layer 122 each being composed of four layers, the number of layers of the second insulating layer 112 and the second wiring layer 122 can be various.

[0058] Referring to FIG. 3b, the through via 130 can be connected to the first semiconductor chip 301 and the second semiconductor chip 302 via the connecting member 400, and the first semiconductor chip 301 and the second semiconductor chip 302 can be directly connected to the through portion of the through via 130 and the metal pillar 203. At this time, a part of the first semiconductor chip 301 may be connected to the through via 130, and the other part may be connected to the first electronic component 201 via the metal pillar 203. Also, a part of the second semiconductor chip 302 may be connected to the through via 130, and the other part may be connected to the first electronic component 201 via the metal pillar 203, and still another part may be connected to the second electronic component 202 via the metal pillar 203. That is, the first semiconductor chip 301 and the second semiconductor chip 302 can be electrically connected to each other via the first electronic component 201. At this time, the first electronic component 201 can function as a bridge for interconnecting the first semiconductor chip 301 and the second semiconductor chip 302, and the second electronic component 202 can be utilized as a function of being connected to the second semiconductor chip 302 to supply power to the second semiconductor chip 302.

[0059] The first semiconductor chip 301 and the second semiconductor chip 302 can each include an integrated circuit (IC) die in which hundreds to millions or more of elements are integrated within one chip. At this time, the integrated circuit may be, for example, a logic chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application processor (e.g., AP), an analog-to-digital converter, an ASIC (application-specific IC), etc., but is not limited thereto, and may also be a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, a high bandwidth memory (HBM), or a power management IC (PMIC), etc. Of course. For example, the first semiconductor chip 301 can include a logic chip such as a GPU, and the second semiconductor chip 302 can include a memory chip such as an HBM. Alternatively, the first semiconductor chip 301 and the second semiconductor chip 302 may be split logic chips that are split by die splitting and have different cores from each other.

[0060] The first semiconductor chip 301 and the second semiconductor chip 302 may each be formed based on an active wafer. In this case, as the base material forming each main body, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used. Various circuits may be formed in the main body. Connection pads can be formed on each main body, and the connection pads can contain conductive substances such as aluminum (Al) and copper (Cu). The first semiconductor chip 301 and the second semiconductor chip 302 may be bare dies. In this case, metal bumps may be arranged on the connection pads. Alternatively, the first semiconductor chip 301 and the second semiconductor chip 302 may be packaged dies. In this case, a redistribution layer can be further formed on the connection pads, and metal bumps can be arranged on the redistribution layer.

[0061] The first semiconductor chip 301 and the second semiconductor chip 302 can be connected to the through-hole via 130 and / or the metal pillar 203 through the connecting member 400. The connecting member 400 may be formed of a low-melting-point metal, such as solder such as tin (Sn)-aluminum (Al)-copper (Cu), but is not limited thereto. The connecting member 400 may be formed as a multilayer or a single layer. When formed as a multilayer, it can include copper pillars and solder formed on the semiconductor chip. When formed as a single layer, it can include tin-silver solder or copper, but is not limited thereto. In addition, as long as it is a means that can play a mediating role so that semiconductor chips or electronic components, etc. are mounted on a printed circuit board and electrically connected, it can be used without limitation. In FIG. 3b, two semiconductor chips are shown as being mounted, but it is not limited thereto, and more semiconductor chips may be mounted, and more semiconductor chips may be die-to-die connected by the first electronic component 201.

[0062] On the one hand, the printed circuit board according to an example is not limited to the configuration shown in FIGS. 3a and 3b, and may further include other general configurations of the printed circuit board. That is, it can further include configurations that can be used by those with ordinary knowledge in the technical field. For example, it may further include means for protecting the glass layer disposed on the uppermost side, or configurations such as improving the bonding force with the semiconductor chip by surface treatment of the protruding portions of the through vias 130 and the protruding portions of the metal pillars 203 may be further added.

[0063] FIGS. 4a and 4b are cross-sectional views schematically showing a printed circuit board according to another example.

[0064] Referring to FIGS. 4a and 4b, the first electronic component 201 and / or the second electronic component 202 of the printed circuit board according to another example can each include a metal pillar 203 on the upper and lower sides. That is, the first electronic component 201 and / or the second electronic component 202 of the printed circuit board according to another example have both sides as active surfaces, and the metal pillar 203 disposed below the first electronic component 201 and / or the second electronic component 202 can be connected to the first wiring layer 121 via the first via layer 131. At this time, after mounting the first electronic component 201 and / or the second electronic component 202 in the cavity CA and embedding them in the first insulating layer 111, the first via layer 131 and the first wiring layer 121 are formed to connect to the first wiring layer 121. Therefore, the metal pillar 203 disposed below the first electronic component 201 and / or the second electronic component 202 can be disposed in contact with the first via layer 131, and the metal pillar 203 and the first via layer 131 can be directly connected.

[0065] On the other hand, in the printed circuit board according to another example of FIGS. 4a and 4b, for the description other than the content related to the first electronic component 201 and the second electronic component 202, it can be applied in the same way as the description of the printed circuit board according to an example, so the repeated description is omitted.

[0066] FIG. 5a and FIG. 5b are cross-sectional views schematically showing a printed circuit board according to yet another example.

[0067] Referring to FIGS. 5a and 5b, in a printed circuit board according to yet another example, the first via layer 131 can be omitted, and the through via 130 and the metal pillar 203 can be directly connected to the first wiring layer 121. That is, the through via 130 and the metal pillar 203 can be arranged to contact the first wiring layer 121.

[0068] This can be the result of embedding the first electronic component 201 and the second electronic component 202 in the cavity CA and then planarizing the first insulating layer 111 and the glass layer 110. When planarizing the first insulating layer 111 by removing a part of the first insulating layer 111 disposed on the glass layer 110, the first wiring layer 121 can be directly formed on the through via 130 and the metal pillar 203. That is, the first insulating layer 111 is formed to fill the inside of the cavity CA, but may not extend on the lower surface of the glass layer 110, and the lower surface of the first insulating layer 111 may be substantially coplanar with the lower surface of the glass layer 110. In a printed circuit board according to yet another example, by omitting the first wiring layer, the total thickness of the printed circuit board is reduced, and a thinner printed circuit board can be realized. At this time, since the printed circuit board includes the glass layer 110, flatness is ensured by the glass layer 110 at the stage of planarizing the first insulating layer 111, and processing stability can be achieved.

[0069] On the other hand, in the printed circuit board according to yet another example of FIGS. 5a and 5b, descriptions other than those related to the first insulating layer 111 and the first wiring layer 121 can be applied in the same manner as the descriptions of the printed circuit board according to one example and the printed circuit board according to yet another example, and thus duplicate descriptions are omitted.

[0070] Method for manufacturing a printed circuit board FIGS. 6a to 6k are cross-sectional views schematically showing a method for manufacturing a printed circuit board according to one example.

[0071] Referring to FIG. 6a, the method for manufacturing a printed circuit board may include the step of forming a first through hole h1 and a cavity CA in the glass layer 110.

[0072] The first through hole h1 is hereinafter the position where the through portion of the through via 130 is formed, and the cavity can be the area where the first electronic component 201 and the second electronic component 202 are mounted. At this time, in FIG. 6a, the first through hole h1 and the cavity CA are shown as having an upward taper shape, and the first through hole h1 and the cavity CA are represented as being formed from the lower side to the upper side, but it is not limited thereto, and they may have a downward taper shape, or may have a taper shape in the direction of the central portion on both sides, as described above. The method for forming the first through hole h1 and the cavity CA can be used without limitation as long as it is a method for processing the glass layer 110 to form the first through hole h1 and the cavity CA. For example, if it is a processing method for forming TGV (Through Glass Via), it can be used without limitation.

[0073] Referring to FIG. 6b, the method for manufacturing a printed circuit board may include the step of bonding the glass layer 110 after forming a resist PR on the carrier substrate C.

[0074] The carrier substrate C is for supporting it when forming an insulating layer, a wiring layer, etc., and can be formed of an insulating material or a metal material. In FIG. 6b, the carrier substrate C is shown as including an insulating material C0 and a seed C1 disposed below the insulating material C0, but it is not necessarily limited thereto, and the seed C1 may be included above and below the insulating material C0 respectively. That is, the carrier substrate C is an example of one case, and the carrier substrate C can be used by those having ordinary knowledge in the technical field, and can be used as a support substrate and can be detached or removed later, and can be used in the present invention without particular limitation.

[0075] The resist PR can use a known dry film and can be used without limitation as long as it contains a photosensitive insulating material and can form a second through-hole, a part of which is removed through an exposure and development process in a later stage. The resist PR preferably contains a positive type photosensitive insulating material. When it contains a positive type photosensitive insulating material, the photopolymer polymer bonds in the exposed part may break, and the part where the photopolymer polymer bonds are broken is removed in the subsequent development process, so it may be more suitable for forming the second through-hole h2 in the region corresponding to the region where the first through-hole h1 is formed. The resist PR can be formed on the lower surface of the carrier substrate C by laminating, and the glass layer 110 can be attached and bonded before the resist PR is cured, but it is not necessarily limited to this, and the glass layer 110 and the resist PR can also be bonded by further including an adhesion means between the resist PR and the glass layer 110.

[0076] Referring to FIG. 6c, the method for manufacturing a printed circuit board may include a step of disposing a first electronic component 201 and a second electronic component 202 in the cavity CA. The first electronic component 201 and the second electronic component 202 can be mounted on the resist PR located in the cavity CA. At this time, since the resist PR may be before curing, when the first electronic component 201 and the second electronic component 202 are mounted, the metal pillar 203 can protrude more than the upper surface of the cavity CA, which is the mounting surface. That is, at least a part of the resist PR can be arranged so as to be recessed as if at least a part of the resist PR is penetrated. Then, a step of curing the resist PR can be performed, and the electronic component and the glass layer 110 can be arranged and fixed on the resist PR.

[0077] Referring to FIG. 6d, the method for manufacturing a printed circuit board may include a step of exposing the resist PR.

[0078] At this time, the mask M can be used to selectively expose the resist PR. Since the resist PR contains a positive-type photosensitive insulating material, the region for processing the second through-hole h2 can be opened and exposed. That is, the region where the first electronic component 201 and the second electronic component 202 are arranged can be blocked by the mask M, and exposure can be performed so that the second through-hole h2 can be formed corresponding to the first through-hole h1 region. On the other hand, in FIG. 6d, the mask M is shown as being arranged only in the cavity CA region, but it is not necessarily limited to this. Considering the transparency of the glass layer 110, only the region where the first through-hole h1 is formed can be opened, and the remaining regions of the glass layer 110 can also be blocked by the mask M.

[0079] Referring to FIG. 6e, the method for manufacturing a printed circuit board can include a step of developing the resist PR.

[0080] At this time, the resist PR in the exposed region can be removed to form the second through-hole h2. The second through-hole h2 may be formed corresponding to the first through-hole h1, or may be formed to penetrate the top and bottom of the resist PR. By the second through-hole h2 penetrating the top and bottom of the resist PR, the seed C1 can be exposed by the first through-hole h1 and the second through-hole h2.

[0081] Referring to FIG. 6f, the method for manufacturing a printed circuit board can include a step of forming the through-via 130.

[0082] The through via 130 can be formed by performing electrolytic plating using the seed C1 of the carrier substrate C as a plating seed. Since the resist PR can function as a plating resist, the electrolytic plating can be performed only at the second through hole h2, and the through via 130 can be formed so as to fill the second through hole h2 and the first through hole h1. On the other hand, since the metal pillars 203 of the first electronic component 201 and the second electronic component 202 do not completely penetrate the resist PR, the metal pillars 203 can be kept not in contact with the seed C1, and even at the stage of forming the through via 130 using the seed C1, the metal pillars 203 can be maintained in a state of not being electrically connected by the resist PR. On the other hand, the method of forming the through via 130 is not limited to this. After separately forming a seed on the inner walls of the first through hole h1 and the second through hole h2 by electroless plating or sputtering, electrolytic plating may be performed, or after filling a paste containing a metallic substance and then firing, any method of forming a through via can be used without limitation as long as it is a method of forming a through via.

[0083] Referring to FIG. 6g, the method of manufacturing a printed circuit board may include a step of forming a first insulating layer 111 and a step of forming a first wiring layer 121 and a first via layer 131.

[0084] The first insulating layer 111 can cover the first electronic component 201 and the second electronic component 202 and fill the cavity CA. At this time, the first insulating layer 111 can also be disposed on the glass layer 110 so as to cover at least a part of the lower surface of the glass layer 110 together. As a method of forming the first insulating layer 111, a known method of laminating insulating layers can be used.

[0085] After forming the first insulating layer 111, the first wiring layer 121 and the first via layer 131 can be formed. A part of the first via layer 131 can be in contact with the through via 130, and another part of the first via layer 131 can be in contact with the first electronic component 201 and the second electronic component 202. As a method for forming the first wiring layer 121 and the first via layer 131, known methods for forming interlayer connections and wiring patterns can be used.

[0086] Referring to FIG. 6h, the method for manufacturing a printed circuit board can include the steps of forming a second insulating layer 112, a second wiring layer 122, and a second via layer 132, and can include the step of forming a solder resist layer 140 on the lower side of the second insulating layer 112.

[0087] For the second insulating layer 112, the second wiring layer 122, and the second via layer 132, known build-up layer lamination methods for printed circuit boards can be used, and known methods can also be used to form the solder resist layer 140.

[0088] Referring to FIGS. 6i and 6j, the method for manufacturing a printed circuit board can include the step of removing the carrier substrate C. The step of removing the carrier substrate C may be performed step by step or simultaneously for the steps of removing the insulating material C0 and removing the seed C1.

[0089] Referring to FIG. 6i, the insulating material C0 of the carrier substrate C can be removed. As a method for removing the insulating material C0 of the carrier substrate C, known insulating layer removal methods can be used, and known detach methods for the carrier substrate C can be used.

[0090] Referring to FIG. 6j, the seed C1 of the carrier substrate C can be removed. As a method for removing the seed C1, a known method for removing a metal layer or a metal foil can be used. At this time, in the step of removing the seed C1, a part of the through hole 130 can be removed together by an etching solution or the like. However, since the resist PR may not react in the step of removing the seed C1, a recess R may be formed in the region where a part of the through hole 130 is removed. At this time, the depth of the recess R may be substantially the same as the distance between the metal pillar 203 and the upper surface of the resist PR, and the upper surface of the through hole 130 may be substantially coplanar with the upper surface of the metal pillar 203, but it is not necessarily limited to this.

[0091] Referring to FIG. 6k, the method for manufacturing a printed circuit board can include a step of removing the resist PR.

[0092] The step of removing the resist PR can be performed by exposing and developing the entire surface of the resist PR, but it is not necessarily limited to this, and any known resist removal method can be used without limitation.

[0093] After removing the resist PR, the method can further include a step of planarizing the protruding portions of the through hole 130 and the metal pillar 203, whereby the through hole 130 and the metal pillar 203 can be substantially coplanar.

[0094] On the other hand, in FIGS. 6a to 6k, the step of manufacturing a printed circuit board only on the lower side with reference to the carrier substrate C is shown. However, the seed C1 is also disposed on the upper side of the insulating material C0 of the carrier substrate C, and the printed circuit board can also be formed on both sides of the carrier substrate C. In this case, the method for manufacturing a printed circuit board can further manufacture a substrate symmetric with respect to the carrier substrate C.

[0095] Note that the manufacturing method of the printed circuit board according to one example is not limited to the content shown in FIGS. 6a to 6k, and those having ordinary knowledge in the technical field may further include a method of forming an available configuration.

[0096] On the other hand, the manufacturing method of the printed circuit board according to another example corresponds to the difference depending on whether the first electronic component 201 and the second electronic component 202 have the metal pillars 203 on the upper and lower sides. Therefore, the manufacturing method of the printed circuit board according to another example can be performed in the same manner as the printed circuit board according to one example, and the detailed description thereof is omitted.

[0097] FIGS. 7a to 7d are cross-sectional views schematically showing a part of the manufacturing method of the printed circuit board according to still another example. FIGS. 7a to 7d can respectively correspond to FIGS. 6e to 6h among the manufacturing methods of the printed circuit board according to one example. In the first electronic component 201 and the second electronic component 202, the presence or absence of the inclusion of the metal pillar 203 may be different, the arrangement of the first insulating layer 111 is different, the first via layer 131 is omitted, and the arrangement of the first wiring layer 121 may be different from that of the printed circuit board according to one example.

[0098] Referring to FIG. 7a, in the printed circuit board according to still another example, the first electronic component 201 and the second electronic component 202 can include the metal pillars 203 on the upper and lower sides. Regarding the method of arranging the first electronic component 201 and the second electronic component 202 in the cavity CA and forming the second through hole h2, the same description as the manufacturing method of the printed circuit board according to one example can be applied.

[0099] Referring to FIG. 7b, the through via 130 can be formed, and the same description as the manufacturing method of the printed circuit board according to one example can be applied thereto.

[0100] Referring to FIG. 7c, the printed circuit board according to still another example can include a step of forming the first insulating layer 111 and a step of forming the first wiring layer 121 on the lower surface of the glass layer 110 and the lower surface of the first insulating layer 111.

[0101] The step of forming the first insulating layer 111 can be performed after the step of laminating the first insulating layer 111 and removing a part of the first insulating layer 111 disposed below the glass layer 110. That is, after laminating the first insulating layer 111, it can be performed by a method of removing a portion protruding from the lower surface of the glass layer 110. Therefore, the first insulating layer 111 is disposed to fill the cavity CA, and the lower surface of the first insulating layer 111 can be formed to be substantially coplanar with the lower surface of the glass layer 110. At this time, the method of removing a part of the first insulating layer 111 can be performed by etching such as grinding or plasma etching, but is not limited thereto, and other known methods such as polishing can also be used.

[0102] The step of forming the first wiring layer 121 can be performed by forming wiring layers on the lower surface of the glass layer 110 and the lower surface of the first insulating layer 111, respectively. Since the lower surface of the first insulating layer 111 has a flat surface, and the lower surface of the glass layer 110 is also substantially coplanar with the lower surface of the first insulating layer 111 and can have a flat surface, the first wiring layer 121 can be formed. At this time, a part of the first wiring layer 121 formed on the lower surface of the glass layer 110 may be formed to be in contact with the through via 130, and a part of the first wiring layer 121 formed on the lower surface of the first insulating layer 111 may be formed to be in contact with the metal pillar 203. That is, in a manufacturing method of a printed circuit board according to still another example, since the step of forming the first via layer 131 can be omitted, the step of forming via holes in the first insulating layer 111 can be omitted to simplify the process, and since the first insulating layer 111 is not extended to the lower surface of the glass layer 110, the printed circuit board can be made thinner.

[0103] Referring to FIG. 7d, it can include the step of forming a second insulating layer 112, a second wiring layer 122, and a second via layer 132 on the lower surface of the glass layer 110 and on the lower surface of the first insulating layer 111, and the step of forming a solder resist layer 140. Since the first insulating layer 111 does not extend to the lower surface of the glass layer 110, a part of the second insulating layer 112 can be in contact with the lower surface of the glass layer 110, and the other part can be in contact with the first insulating layer 111. Regarding the step of forming the second insulating layer 112, the second wiring layer 122, and the second via layer 132, since the same description as that of a method for manufacturing a printed circuit board according to an example can be applied, it is omitted.

[0104] In addition, among the methods for manufacturing a printed circuit board according to still another example, except for the above-described steps, the steps similar to those of the method for manufacturing a printed circuit board according to an example can also be applied to a printed circuit board according to still another example. Therefore, the overlapping description regarding this is omitted.

[0105] In the present invention, the expressions "cover" and "cover with" can include not only the case of covering entirely but also the case of covering at least a part, and can include not only the case of directly covering but also the case of indirectly covering. Also, the expression "fill" can include not only the case of completely filling but also the case of generally filling, for example, the case where there are some voids or voids.

[0106] In the present invention, it can be determined including substantially process errors, position deviations, errors during measurement, etc. that occur in the manufacturing process. For example, "substantially perpendicular" can include not only the case of being completely perpendicular but also the case of being almost perpendicular. Also, being substantially "coplanar" can include not only the case of existing on exactly the same plane but also the case of existing on almost the same plane.

[0107] In the present invention, "the same insulating material" can mean not only the case of being exactly the same insulating material but also including the same type of insulating material. Therefore, although the composition of the insulating materials is substantially the same, their specific composition ratios may differ slightly.

[0108] In the present invention, the meaning in the cross-section can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed in a side view. Further, the meaning on the plane can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed in a top view or a bottom view.

[0109] In the present invention, "lower side, lower part, lower surface", etc. are used, for the sake of convenience, to mean the downward direction based on the cross-section of the drawing, and "upper side, upper part, upper surface", etc. are used to mean the opposite direction. However, this is only a definition of direction for the sake of explanation, and it goes without saying that the scope of rights in the claims is not particularly limited by such descriptions of direction, and the concept of up / down can be changed at any time.

[0110] In the present invention, "connected" includes not only being directly connected, but also being indirectly connected through an adhesive layer or the like. Further, "electrically connected" is a concept that includes both the case of being physically connected and the case of not being connected. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the said component. In some cases, within the scope not departing from the scope of rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0111] The expression "an example" used in the present invention does not mean the same embodiment as each other, but is provided to emphasize and explain each unique feature different from each other. However, the above-mentioned examples do not exclude being realized in combination with the features of other examples. For example, even if a matter described in a specific example is not described in another example, in another example, as long as there is no description contrary to or contradictory to that matter, it can be understood as related to the description of another example.

[0112] The terms used in the present invention are used merely for the purpose of illustration and are not intended to limit the present invention. At this time, singular expressions include plural expressions unless the context clearly indicates a different meaning.

Explanation of Reference Numerals

[0113] 110: Glass layer CA: Cavity 111: First insulating layer 112: Second insulating layer 121: First wiring layer 122: Second wiring layer 130: Through via 131: First via layer 132: Second via layer 140: Solder resist layer 201, 202: First and second electronic components 203: Metal pillar 301, 302: First and second semiconductor chips 400: Connecting member C: Carrier substrate C0: Insulating material C1: Seed PR: Resist M: Mask R: Recess h1: First through hole h2: Second through hole 1000: Electronic device 1010: Main board 1020: Chip-related components 1030: Network-related components 1040: Other components 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Components 1121: Component package 1130: Camera module 1140: Speaker

Claims

1. a glass layer having a cavity; a through via having a penetrating portion penetrating the glass layer and a protruding portion protruding above the glass layer; an electronic component disposed within the cavity; a first insulating layer filling at least a portion of the cavity and covering at least a portion of the electronic component.

2. The printed circuit board of claim 1 , wherein the through portion and the protrusion are integral.

3. The first insulating layer is disposed to extend onto a lower surface of the glass layer. The printed circuit board of claim 1 .

4. a first wiring layer disposed on the first insulating layer; The printed circuit board according to claim 3 , further comprising: a first via layer penetrating at least a portion of the first insulating layer so as to contact at least a portion of the through via and connect the first wiring layer and the through via to each other.

5. a second insulating layer disposed on the first insulating layer; a second wiring layer disposed on the second insulating layer; 5. The printed circuit board of claim 4, further comprising: a second via layer penetrating at least a portion of the second insulating layer to connect the second wiring layer and the first wiring layer to each other or to connect the second wiring layers to each other.

6. the electronic component includes a metal pillar; The printed circuit board of claim 1 , wherein the metal pillar protrudes above the first insulating layer.

7. The printed circuit board of claim 6 , wherein a top surface of the metal pillar is substantially coplanar with a top surface of the penetration portion of the through via.

8. The printed circuit board according to claim 7 , wherein the metal pillars are disposed above and below the electronic component, respectively.

9. The printed circuit board of claim 1 , wherein a bottom surface of the through via is substantially coplanar with a bottom surface of the glass layer.

10. 2. The printed circuit board of claim 1, wherein a top surface of the first insulating layer is substantially coplanar with a top surface of the glass layer.

11. 2. The printed circuit board of claim 1, wherein a lower surface of the first insulating layer is substantially coplanar with a lower surface of the glass layer.

12. a first wiring layer at least a portion of which is disposed on the lower surface of the glass layer; The printed circuit board according to claim 11 , wherein at least a portion of the first wiring layer contacts the through via.

13. A glass layer; a through via having a penetrating portion penetrating the glass layer and a protruding portion protruding above the glass layer; A printed circuit board, wherein, in cross section, the width of the penetrating portion at its uppermost side is substantially the same as the width of the protruding portion at its lowermost side.

14. The printed circuit board of claim 13 , wherein the penetration and the protrusion are integral.

15. a lower surface of the penetration is substantially coplanar with a lower surface of the glass layer; The printed circuit board of claim 13 , wherein an upper surface of the protrusion protrudes beyond an upper surface of the glass layer.

16. The printed circuit board of claim 13 , wherein the through via has a substantially upwardly tapered shape.

17. a cavity extending through at least a portion of the glass layer; The printed circuit board of claim 13 , wherein the cavity and the through via are tapered in substantially the same direction.

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