Memory device

Abstract

To provide a memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cash memory are connected to each other with a short wiring, and which has small signal transmission delay and low power consumption.SOLUTION: For example, an Si transistor is formed using a single crystal silicon substrate, and a NAND flash memory is formed using the Si transistor. Since an OS transistor can be formed by means of a thin film method or the like, if a cash memory is configured using an OS transistor, the cash memory can be provided above a NAND flash memory in a lamination manner. By forming a NAND flash memory and a cash memory in a same chip, the NAND flash memory and a controller, also the controller and the cash memory are connected with each other through short wiring lines.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory device. In particular, it relates to a memory device (also referred to as a semiconductor memory device or a memory) that utilizes semiconductor characteristics.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

Background Art

[0003] As a non-volatile memory device used in information processing devices such as personal computers (PCs), servers, and data centers, hard disk drives (HDDs) have been used for many years. In recent years, however, solid state drives (SSDs), which are lightweight, have no physical moving parts, and can read and write data at high speeds, have become increasingly popular.

[0004] Many SSDs are composed of a NAND-type flash memory and a controller. The flash memory is a non-volatile memory device that stores data electrically. In addition, an SSD may have a cache memory (also referred to as a buffer memory), which makes the data write operation particularly faster. DRAM (Dynamic Random Access Memory) or SRAM (Static RAM) is used for the cache memory of the SSD. DRAM and SRAM are volatile memory devices. Note that memory devices that utilize semiconductor characteristics, such as DRAM, SRAM, and flash memory, are referred to as semiconductor memory devices (also referred to as memories) in this specification and the like.

[0005] On the one hand, a transistor having an oxide semiconductor or a metal oxide in a channel formation region of the transistor (also referred to as an oxide semiconductor transistor or an OS (Oxide Semiconductor) transistor) is known. The OS transistor has a characteristic that the drain current (also referred to as the off-current) when the transistor is in the off state is very small (see, for example, Non-Patent Documents 1 and 2), and has attracted attention. Further, DRAM is a storage device in which a memory cell is composed of one transistor and one capacitive element, and stores data by accumulating charges in the capacitive element. Therefore, by using the OS transistor in the memory cell of DRAM, the stored data can be held for a long time.

[0006] In addition, in the oxide semiconductor, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 3). Non-Patent Document 1 and Non-Patent Document 3 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.

Prior Art Documents

Non-Patent Documents

[0007] [Non-Patent Document 1] S.Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys., vol.53, 04ED18 (2014). [Non-Patent Document 2] K.Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol.51, 021201 (2012). [Non-Patent Document 3] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 4] S. Maeda et al., “A 20ns-Write 45ns-Read and 10 14 -Cycle Endurance Memory Module Composed of 60nm Crystalline Oxide Semiconductor Transistors”, ISSCC 2018, SESSION 30, EMERGING MEMORIES, 30.4, p.484-486

Summary of the Invention

Problems to be Solved by the Invention

[0008] An SSD, for example, is manufactured by soldering a NAND flash memory, a controller, and a cache memory to a printed circuit board as electronic components. That is, the NAND flash memory, the controller, and the cache memory are separate chips, and they are electrically connected by wirings provided on the printed circuit board.

[0009] However, the wirings provided on the printed circuit board are longer than the wirings within individual chips, and there are problems such as large signal transmission delays and large power consumption due to parasitic capacitance and the like. In particular, there was a significant impact between the NAND flash memory and the controller, and between the controller and the cache memory, where a large amount of data travels at high speed. In addition, the NAND flash memory requires a high voltage for writing and erasing, and it was difficult to fabricate the NAND flash memory and the cache memory on the same chip because of differences in the thickness of the insulator and the like.

[0010] One aspect of the present invention is to provide a storage device in which a NAND flash memory, a controller, and a cache memory are connected by short wirings. Or, one aspect of the present invention is to provide a storage device in which a NAND flash memory and a cache memory are fabricated on the same chip. Or, one aspect of the present invention is to provide an SSD in which a NAND flash memory, a controller, and a cache memory are connected by short wirings and which has low power consumption.

[0011] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it suffices if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will naturally become clear from the description in the specification, claims, drawings, etc., and it is possible to extract these other problems from the description in the specification, claims, drawings, etc.

Means for Solving the Problems

[0012] One aspect of the present invention is an information processing apparatus having a first layer and a second layer. An arithmetic processing unit is provided in the first layer, and a memory cell unit is provided in the second layer. The arithmetic processing unit has a function of performing arithmetic processing and a function of driving or controlling the memory cell unit. The memory cell unit has a function of holding stored data in a state where no power is supplied, the memory cell unit has a random access function, and at least a part of the second layer is provided laminated above the first layer.

[0013] Also, in the above aspect, the first layer has a single crystal silicon substrate, and the arithmetic processing unit has a first transistor formed on the single crystal silicon substrate. The memory cell unit has a second transistor, and the second transistor has a metal oxide in a channel formation region.

[0014] Also, in the above-described embodiment, the first layer has an SOI substrate, and the arithmetic processing unit has a first transistor formed on the SOI substrate. The memory cell section has a second transistor, and the second transistor has a metal oxide in the channel formation region.

[0015] Also, one embodiment of the present invention is a memory device having a first layer, a second layer, and a third layer. A circuit is provided in the first layer, a first memory cell section is provided in the second layer, and a second memory cell section is provided in the third layer. The circuit has a function of driving or controlling the first memory cell section and the second memory cell section. The first memory cell section has a function of holding stored data for a longer time than the second memory cell section in a state where no power is supplied. The second memory cell section has a function of writing and reading data at a speed faster than that of the first memory cell section. At least a part of the second layer is laminated above the first layer, and at least a part of the third layer is laminated above the second layer.

[0016] Also, in the above-described embodiment, the first layer has a single crystal silicon substrate, and the circuit has a first transistor formed on the single crystal silicon substrate. The second memory cell section has a second transistor, and the second transistor has a metal oxide in the channel formation region.

[0017] Also, in the above-described embodiment, the first layer has an SOI substrate, and the circuit has a first transistor formed on the SOI substrate. The second memory cell section has a second transistor, and the second transistor has a metal oxide in the channel formation region.

[0018] Also, one embodiment of the present invention is an operation method of the memory device in the above-described embodiment. The circuit performs a writing operation of storing data input to the memory device in the second memory cell section, and reads the data stored in the second memory cell section by the writing operation and stores it in the first memory cell section.

[0019] Also, one embodiment of the present invention is a memory device having a first layer, a second layer, and a third layer. A circuit is provided in the first layer, a first memory cell portion is provided in the second layer, and a second memory cell portion is provided in the third layer. The circuit has a function of driving or controlling the first memory cell portion and the second memory cell portion. The first memory cell portion has a function of holding stored data for a longer time than the second memory cell portion in a state where no power is supplied. The second memory cell portion has a function of writing and reading data at a speed faster than that of the first memory cell portion. At least a part of the second layer is laminated above the first layer, and at least a part of the third layer is laminated above the second layer. The circuit has a function of performing a first operation of storing data input to the memory device in the second memory cell portion, and a function of performing a second operation of reading the data stored in the second memory cell portion by the first operation and storing it in the first memory cell portion.

[0020] Also, one embodiment of the present invention is a memory device having a first layer, a second layer, and a third layer. A first circuit is provided in the first layer, a first memory cell portion is provided in the second layer, and a second memory cell portion is provided in the third layer. The second memory cell portion has a second circuit and a memory cell array. The first circuit has a function of driving or controlling the first memory cell portion and the second circuit. The second circuit has a function of writing data to the memory cell array and a function of reading data from the memory cell array. The first memory cell portion has a function of holding stored data for a longer time than the second memory cell portion in a state where no power is supplied. The second memory cell portion has a function of writing and reading data at a speed faster than that of the first memory cell portion. At least a part of the second layer is laminated above the first layer, and at least a part of the third layer is laminated above the second layer.

[0021] Also, in the above embodiment, the first layer has a single crystal silicon substrate, and the circuit has a first transistor formed on the single crystal silicon substrate. The second memory cell portion has a second transistor, and the second transistor has a metal oxide in a channel formation region.

[0022] Also, in the above aspect, the first layer has a SOI substrate, and the circuit has a first transistor formed on the SOI substrate. The second memory cell portion has a second transistor, and the second transistor has a metal oxide in the channel formation region.

[0023] Also, one aspect of the present invention is a memory device having a first layer, a second layer, and a third layer. A circuit is provided in the first layer, a memory cell portion is provided in the second layer, and a first RF block circuit is provided in the third layer. The circuit has a function of driving or controlling the memory cell portion and the first RF block circuit, the memory cell portion has a function of holding stored data in a state where no power is supplied, at least a part of the second layer is provided laminated above the first layer, and at least a part of the third layer is provided laminated above the second layer.

[0024] Also, one aspect of the present invention is an information processing system having the memory device in the above aspect and a central management unit. The central management unit has a central processing unit and a second RF block circuit, and the memory device is electrically connected to the central processing unit via the first RF block circuit and the second RF block circuit.

[0025] Also, one aspect of the present invention is an electronic device having the information processing device in the above aspect.

[0026] Also, one aspect of the present invention is an electronic device having the memory device in the above aspect.

[0027] Also, in the above aspect, the electronic device is a computer, a supercomputer, a smartphone, or an IoT terminal device.

Advantages of the Invention

[0028] According to one embodiment of the present invention, a storage device can be provided in which a NAND flash memory, a controller, and a controller and a cache memory are connected by short wirings. Alternatively, according to one embodiment of the present invention, a storage device can be provided in which a NAND flash memory and a cache memory are fabricated on the same chip. Alternatively, according to one embodiment of the present invention, an SSD with low power consumption can be provided in which a NAND flash memory, a controller, and a controller and a cache memory are connected by short wirings.

[0029] Note that the description of these effects does not preclude the existence of other effects. Also, one embodiment of the present invention does not necessarily have to have all of these effects. Other effects will be naturally apparent from the description in the specification, claims, drawings, etc., and it is possible to extract these other effects from the description in the specification, claims, drawings, etc.

Brief Description of the Drawings

[0030]

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DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different forms, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0032] Also, a plurality of the following embodiments can be combined as appropriate. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0033] In the drawings attached to this specification, components are classified by function and shown as block diagrams as independent blocks from each other. However, actual components are difficult to completely separate by function, and one component may be related to a plurality of functions.

[0034] Also, in the drawings and the like, the size, layer thickness, region, etc. may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings.

[0035] Also, in the drawings and the like, the same elements, elements having the same or similar functions, elements of the same material, or elements formed simultaneously may be given the same reference numerals, and repeated description thereof may be omitted.

[0036] Also, in this specification and the like, the term "film" and the term "layer" can be interchanged with each other. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0037] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" do not limit the positional relationship of components to being "directly above" or "directly below". For example, in the expression "a gate electrode on a gate insulating layer", components other than the gate insulating layer and the gate electrode are not excluded even if they are included between the gate insulating layer and the gate electrode.

[0038] In addition, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components and do not numerically limit them.

[0039] In addition, in this specification and the like, when the same reference numeral is used for a plurality of elements, when it is particularly necessary to distinguish them, the reference numeral may be described with an identification symbol such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL is described as wiring GL[2].

[0040] In addition, in this specification and the like, "electrically connected" includes cases where it is connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical action" includes electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitance elements, and other elements having various functions. Also, even when expressed as "electrically connected", in an actual circuit, there may be a case where there is no physical connection part and only the wiring extends.

[0041] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa.

[0042] In addition, in this specification and the like, the "terminal" in an electric circuit refers to a part where input (or output) of current or potential and reception (or transmission) of a signal are performed. Therefore, a part of a wiring or an electrode may function as a terminal.

[0043] Generally, a "capacitive element" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. Also, in this specification and the like, the "capacitive element" includes not only those having a configuration in which two electrodes face each other with an insulator in between, but also those having a configuration in which two wirings face each other with an insulator in between, or those in which two wirings are arranged with an insulator in between.

[0044] Also, in this specification and the like, the "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, the ground potential). Therefore, the voltage and the potential difference can be used interchangeably.

[0045] Also, in this specification and the like, a transistor is an element having at least three terminals including a source, a drain, and a gate. And it has a channel formation region between the source (source terminal, source region, or source electrode) and the drain (drain terminal, drain region, or drain electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0046] Also, the functions of the source and the drain may be interchanged when using transistors with different polarities or when the direction of current changes in the circuit operation. Therefore, in this specification and the like, the terms of the source and the drain can be used interchangeably.

[0047] Also, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state, unless otherwise specified, for an n-channel type transistor means a state where the gate voltage Vgs with respect to the source is lower than the threshold voltage Vth, and for a p-channel type transistor means a state where the gate voltage Vgs with respect to the source is higher than the threshold voltage Vth. That is, in some cases, the off-current of an n-channel type transistor refers to the drain current when the gate voltage Vgs with respect to the source is lower than the threshold voltage Vth.

[0048] In the above description of the off-current, the drain and the source may be read interchangeably. That is, the off-current may refer to the source current when the transistor is in the off state. Also, in the same sense as the off-current, there is a case where it is referred to as the leakage current. Also, in this specification and the like, the off-current may refer to the current flowing between the source and the drain when the transistor is in the off state.

[0049] Also, in this specification and the like, the on-current may refer to the current flowing between the source and the drain when the transistor is in the on state (also referred to as the conducting state).

[0050] Also, in this specification and the like, metal oxide means a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like.

[0051] For example, when a metal oxide is used in the channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the metal oxide has at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be called a metal oxide semiconductor. That is, a transistor having a metal oxide in the channel formation region can be called an "oxide semiconductor transistor" or an "OS transistor". Similarly, a "transistor using an oxide semiconductor" is also a transistor having a metal oxide in the channel formation region.

[0052] In addition, in this specification and the like, a metal oxide having nitrogen may sometimes be referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride. Details of the metal oxide will be described later.

[0053] (Embodiment 1) In this embodiment, a configuration example of a memory device according to one aspect of the present invention will be described.

[0054] <Configuration Example of Memory Device> FIG. 1A is a schematic perspective view showing a configuration example of a memory device 100 according to one aspect of the present invention. The memory device 100 includes a layer 10, layers 20_1 to 20_l (l is an integer of 2 or more), a layer 30, a layer 40, and a wiring EW.

[0055] In this specification and the like, in order to distinguish a plurality of elements having the same function, symbols such as "_1" or [_2] are used. That is, when referring to any one of the layers 20_1 to 20_l, the description is made using the symbol of the layer 20, and when it is necessary to specify one, the description is made using symbols such as layer 20_1 and layer 20_2.

[0056] As shown in FIG. 1A, the memory device 100 has a structure in which layer 20_1 is laminated above layer 10, layer 20_k+1 (where k is an integer from 1 to l-1) is laminated above layer 20_k, layer 30 is laminated above layer 20_l, and layer 40 is laminated above layer 30.

[0057] In the memory device 100, the first memory device is constituted by layer 10, layers 20_1 to 20_l, and layer 30, and the second memory device is constituted by layer 10, layer 30, and layer 40. Here, the first memory device can be, for example, a three-dimensional NAND flash memory. The second memory device can use, for example, an OS transistor in the memory cell part to be described later.

[0058] Note that the first memory device is not limited to a three-dimensional NAND flash memory, and may be a two-dimensional NAND flash memory or a NOR flash memory. Also, a memory device using non-volatile memory elements such as MRAM (Magnetoresistive RAM), PRAM (Phase change RAM), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM), or a combination of the above memory devices may be used.

[0059] Circuits that can function by utilizing semiconductor characteristics are provided in layer 10, layers 20_1 to 20_l, and layer 40. Circuit OSC is provided in layer 10, memory cell part MCL is provided in layers 20_1 to 20_l, and memory cell part OMCL is provided in layer 40. Layer 30 is a wiring layer in which wirings are formed. That is, the first memory device has memory cell part MCL, and the second memory device has memory cell part OMCL.

[0060] FIG. 1B is a schematic perspective view in which wiring EW related to layers 20_1 to 20_l and layer 20 is omitted from FIG. 1A, showing the positional relationship among circuit OSC, memory cell section MCL, and memory cell section OMCL. In the drawings described in this specification and the like, the main signal flow is indicated by arrows or lines, and power supply lines and the like may be omitted.

[0061] Circuit OSC functions as a drive circuit or a control circuit for memory cell section MCL and memory cell section OMCL. Memory cell section MCL has a plurality of memory cells in layers 20_1 to 20_l, and data writing and reading are performed by a writing circuit, a reading circuit, etc. included in circuit OSC. Similarly, memory cell section OMCL has a plurality of memory cells in layer 40, and data writing and reading are performed by a writing circuit, a reading circuit, etc. included in circuit OSC.

[0062] Circuit OSC is configured using transistors formed on substrate SUB. As substrate SUB, for example, a single crystal semiconductor substrate made of silicon, silicon carbide, etc., a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, etc. can be used. Also, for substrate SUB, an SOI substrate, a substrate provided with semiconductor elements such as strained transistors and FIN type transistors on a semiconductor substrate, a glass substrate such as barium borosilicate glass and aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used. Further, a flexible substrate (flexible substrate) may be used for substrate SUB. In this embodiment, the case where a single crystal silicon substrate is used for substrate SUB will be described. Note that a transistor having silicon in the channel formation region is called an Si transistor.

[0063] The circuit OSC and the memory cell section MCL are electrically connected by the wiring EW and the layer 30. The wiring EW has a function of electrically connecting the circuit OSC and the layer 30, and a function of electrically connecting the memory cells included in the memory cell section MCL and the layer 30. Note that the wiring EW can be one or more types of wirings selected from signal lines, power supply lines for supplying a fixed potential, bit lines (such as write bit lines and read bit lines), and word lines. Similarly, the circuit OSC and the memory cell section OMCL are also electrically connected by the wiring EW and the layer 30.

[0064] When an OS transistor is used for the memory cell section OMCL, since the OS transistor can be formed by a technique such as a thin film method, the memory cell section OMCL can be provided laminated above the circuit OSC and the memory cell section MCL. Specifically, the circuit OSC and the memory cell section MCL can be configured using Si transistors, and the memory cell section OMCL can be configured using OS transistors above them. Note that the OS transistor is a transistor having a metal oxide in a channel formation region.

[0065] Also, the memory cell section OMCL can be manufactured by a process different from that of the circuit OSC and the memory cell section MCL. Since the formation temperature of the OS transistor is lower than that of the Si transistor, by configuring the memory cell section OMCL using the OS transistor, the influence of heat on the Si transistors included in the circuit OSC and the memory cell section MCL can be reduced. Further, since the memory cell section OMCL overlaps above the circuit OSC and the memory cell section MCL, an increase in the circuit area of the storage device 100 can be suppressed.

[0066] Next, a configuration example of the circuit OSC and the memory cell section MCL will be described. FIG. 2 is a block diagram showing a configuration example of the circuit OSC and the memory cell section MCL.

[0067] <Memory cell section MCL> The memory cell section MCL has a memory cell array MCA. The memory cell array MCA has a plurality of strings SRG. The string SRG is electrically connected to the wiring BL. The string SRG has a plurality of transistors CTr electrically connected in series, and a selection transistor BTr and a transistor STr. Note that one transistor CTr functions as a cell transistor and is included in the memory cell MC included in the string SRG.

[0068] Generally, a cell transistor is a transistor that operates with normally-on characteristics and has a control gate and a charge storage layer. The charge storage layer is provided in a region overlapping with the channel formation region via a tunnel insulating film, and the control gate is provided in a region overlapping with the charge storage layer via a blocking film. The cell transistor generates a tunnel current by applying a write potential to the control gate and applying a predetermined potential to one of the first terminal or the second terminal of the cell transistor, and electrons are injected from the channel formation region of the cell transistor into the charge storage layer. As a result, in the cell transistor in which electrons are injected into the charge storage layer, the threshold voltage increases. Note that a floating gate may be used instead of the charge storage layer.

[0069] The channel formation regions of the transistor BTr, the transistor CTr, and the transistor STr preferably have any one of, for example, silicon, germanium, gallium arsenide, silicon carbide (SiC), a metal oxide described in Embodiment 5, or a plurality of materials selected from the above.

[0070] In particular, in the channel formation region, when one or more metal oxides selected from indium, element M (as element M, for example, aluminum, gallium, yttrium, tin, etc.), and zinc are included, the metal oxide may function as a wide-gap semiconductor, and the transistors BTr, CTr, and STr in which the metal oxide is included in the channel formation region have the characteristic that the off-current is very small. That is, since the leakage current in the transistors BTr, CTr, and STr in the off state can be reduced, the power consumption of the memory device may be reduced.

[0071] In FIG. 2, an example in which the transistors BTr and STr are formed in the memory cell portion MCL is shown, but the transistors BTr and STr may be formed in the circuit OSC.

[0072] The memory cell array MCA has a plurality of memory cells MC in the string SRG. The plurality of memory cells MC are arranged in a matrix (also referred to as a matrix). The memory cell array MCA in FIG. 2 has m memory cells MC in one column, n memory cells MC in one row, and a total of m×n memory cells MC (m and n are integers of 2 or more). Also, in FIG. 2, the memory cell MC located at the i-th row and j-th column (i is an integer from 1 to m, and j is an integer from 1 to n) is denoted as MC[i,j]. However, in FIG. 2, only the memory cells MC[1,1], MC[i,1], MC[m,1], MC[1,j], MC[i,j], MC[m,j], MC[1,n], MC[i,n], and MC[m,n] are illustrated, and the illustration of the other memory cells MC is omitted.

[0073] The wiring WL, wiring BL, wiring CL, wiring BSL, and wiring SSL shown in FIG. 2 correspond to the wiring EW shown in FIG. 1. The wiring WL is a plurality of word lines, and each of the wiring WLs is electrically connected to the memory cell MC for each row. Also, the wiring BL is a plurality of bit lines, and each of the wiring BLs is electrically connected to the memory cell MC for each column. Also, the wiring CL is a power supply line.

[0074] Next, the connection configuration of the string SRG electrically connected to the wiring BL will be described. One of the source or drain of the transistor BTr is electrically connected to the wiring BL, and one of the source or drain of the transistor STr is electrically connected to the wiring CL. The other of the source or drain of the transistor BTr is electrically connected to one end of a plurality of transistors CTr electrically connected in series, and the other of the source or drain of the transistor STr is electrically connected to the other end of a plurality of transistors CTr electrically connected in series.

[0075] The wiring BSL and wiring SSL function as wiring for selecting a string to which an operation such as writing, reading, or erasing is performed. The wiring BSL is electrically connected to the gate of the transistor BTr included in the memory cell portion MCL, and the wiring SSL is electrically connected to the gate of the transistor STr included in the memory cell portion MCL.

[0076] In FIG. 2, the memory cell portion MCL is configured such that one string SRG is electrically connected to one wiring BL, but one aspect of the present invention is not limited to this. For example, as shown in FIG. 3, the memory cell portion MCL may be configured such that a plurality of strings SRG are electrically connected to one wiring BL. Note that in the block diagram of FIG. 3, the memory cell portion MCL and a part of the circuit OSC are illustrated.

[0077] <Circuit OSC> The circuit OSC includes a control circuit CTR, a circuit PRPH, a circuit ORPH, and an output circuit OUTP. The control circuit CTR receives, for example, a control signal CS (such as a clock signal, chip enable signal, write enable signal, address signal, etc.) and a data signal WDATA from outside the storage device 100.

[0078] The control circuit CTR has functions of accessing the circuit PRPH to write data to the memory cell section MCL and reading data from the memory cell section MCL. Also, the control circuit CTR has functions of accessing the circuit ORPH to write data to the memory cell section OMCL and reading data from the memory cell section OMCL.

[0079] When a write command by the control signal CS and the data signal WDATA are input from outside the storage device 100, the control circuit CTR first writes the data signal WDATA to the memory cell section OMCL. Next, it reads the data written from the memory cell section OMCL and writes the read data to the memory cell section MCL. That is, the memory cell section OMCL functions as a cache memory for the memory cell section MCL. Note that the control circuit CTR may have a function of directly writing to the memory cell section MCL without going through the memory cell section OMCL, such as when the data amount of the data signal WDATA is small.

[0080] When a read command by the control signal CS is input from outside the storage device 100, the control circuit CTR reads data from the memory cell section MCL (if the data exists in the memory cell section OMCL, it may be read from the memory cell section OMCL) and outputs it to the output circuit OUTP. The output circuit OUTP outputs a data signal RDATA to the outside of the storage device 100. Note that the write command and the read command are assumed to include an address signal.

[0081] Further, when the control circuit CTR reads data from the memory cell unit MCL, it may have a function of performing error detection and correction (also referred to as ECC: Error Check and Correct). The memory cell unit OMCL can also function as a cache memory when the control circuit CTR performs error detection and correction. Note that the signals processed by the control circuit CTR and the functions of the control circuit CTR are not limited to these, and other signals may be input (or output) as necessary, and the control circuit CTR may have other functions.

[0082] That is, the control circuit CTR writes the data signal WDATA input from outside the storage device 100 to the memory cell unit OMCL via the wiring EW, reads the written data from the memory cell unit OMCL via the wiring EW, and writes the read data to the memory cell unit MCL via the wiring EW again. Since the data signal WDATA input from outside the storage device 100 moves via the wiring EW in the storage device 100, the data movement distance is short.

[0083] The storage device 100 has a memory cell unit OMCL that can be used as a cache memory. Since the data movement distance is short, it has features such as a small signal transmission delay and the ability to operate at high speed, and can suppress an increase in power consumption due to parasitic capacitance and the like.

[0084] Further, the circuit PRPH has, for example, a circuit WLD, a circuit BLD, and a circuit CVC. The circuit WLD functions as a word line driver circuit and is electrically connected to the wiring WL. The circuit BLD functions as a bit line driver circuit and is electrically connected to the wiring BL. The circuit CVC functions as a power supply that generates a constant potential and outputs the constant potential, and is electrically connected to the wiring CL. Note that the circuit CVC may not be included in the circuit PRPH, and may be provided outside the storage device 100, for example. In this case, the storage device 100 is configured such that a constant potential is supplied to the memory cell unit MCL from the outside.

[0085] Circuit ORPH has, for example, circuit OWLD and circuit OBLD. Circuit OWLD functions as a word line driver circuit and is electrically connected to wiring wwl and wiring rwl. Circuit OBLD functions as a bit line driver circuit and is electrically connected to wiring wbl and wiring rbl.

[0086] <Memory cell section OMCL> Next, a configuration example of the memory cell section OMCL will be described. FIG. 4 is a block diagram showing a configuration example of the memory cell section OMCL.

[0087] The memory cell section OMCL has a total of s×t memory cells OMC, with s cells in one column and t cells in one row (s and t are integers of 2 or more). The memory cells OMC are arranged in a matrix. In FIG. 4, the memory cell OMC located at p rows and r columns (p is an integer from 1 to s, and r is an integer from 1 to t) is denoted as OMC[p,r]. However, in FIG. 4, only the memory cells OMC[1,1], OMC[p,1], OMC[s,1], OMC[1,r], OMC[p,r], OMC[s,r], OMC[1,t], OMC[p,t], and OMC[s,t] are illustrated, and the illustration of other memory cells OMC is omitted.

[0088] Wiring wwl and wiring rwl correspond to the wiring EW shown in FIG. 1, and each of wiring wwl and wiring rwl is electrically connected to the memory cell OMC for each row. That is, each of the memory cells OMC[p,1] to OMC[p,t] is electrically connected to circuit OWLD via wiring wwl(p) and wiring rwl(p). Also, wiring wbl and wiring rbl correspond to the wiring EW shown in FIG. 1, and each of wiring wbl and wiring rbl is electrically connected to the memory cell OMC for each column. That is, each of the memory cells OMC[1,r] to OMC[s,r] is electrically connected to circuit OBLD via wiring wbl(r) and wiring rbl(r).

[0089] FIG. 5A is a circuit diagram showing a configuration example of a memory cell OMC. The memory cell OMC includes a transistor M11, a transistor M12, and a capacitor element C11.

[0090] One of the source or drain of the transistor M11 is electrically connected to the gate of the transistor M12 and one terminal of the capacitor element C11, the other of the source or drain of the transistor M11 is electrically connected to the wiring wbl, and the gate of the transistor M11 is electrically connected to the wiring wwl. One of the source or drain of the transistor M12 is electrically connected to the wiring rbl, and the other of the source or drain of the transistor M12 is electrically connected to the wiring rwl. The other terminal of the capacitor element C11 is electrically connected to the wiring CAL. The wiring CAL functions as a wiring for applying a predetermined potential to the other terminal of the capacitor element C11. Also, a connection portion where one of the source or drain of the transistor M11, the gate of the transistor M12, and one terminal of the capacitor element C11 are electrically connected is referred to as a node N11.

[0091] Note that in this specification and the like, in order to describe the input / output of signals and potentials between components, expressions such as "terminal" are used, but in an actual circuit, there may be no physical connection portion such as a "terminal", and it may be only electrically connected by wiring or electrodes.

[0092] In the memory cell OMC, the wiring wbl functions as a write bit line, the wiring rbl functions as a read bit line, the wiring wwl functions as a write word line, and the wiring rwl functions as a read word line. The transistor M11 has a function as a switch that makes the node N11 and the wiring wbl conductive or non-conductive.

[0093] Data writing is performed by applying a high-level potential to wiring wwl to turn transistor M11 on and electrically connecting node N11 and wiring wbl. Specifically, when transistor M11 is on, a potential corresponding to the data to be written is applied to wiring wbl, and this potential is written to node N11. Thereafter, a low-level potential is applied to wiring wwl to turn transistor M11 off, thereby holding the potential of node N11.

[0094] Data reading is performed by applying a predetermined potential to wiring rbl, then putting wiring rbl in an electrically floating state, and applying a low-level potential to wiring rwl. Hereinafter, applying a predetermined potential to wiring rbl and then putting wiring rbl in a floating state is expressed as precharging wiring rbl.

[0095] For example, by precharging wiring rbl with potential Vdd, transistor M12 has a potential difference between its source and drain, and the current flowing between the source and drain of transistor M12 is determined by the potential held at node N11. Therefore, the potential held at node N11 can be read by reading the potential change of wiring rbl when wiring rbl is in a floating state.

[0096] The row in which memory cell OMC for writing data is arranged is selected by applying a high-level potential to wiring wwl, and the row in which memory cell OMC for reading data is arranged is selected by applying a low-level potential to wiring rwl. Conversely, for the row in which memory cell OMC for not writing data is arranged, a low-level potential is applied to wiring wwl, and for the row in which memory cell OMC for not reading data is arranged, the same potential as the potential for precharging wiring rbl is applied to wiring rwl, so that it can be made non-selective.

[0097] For transistors M11 and M12, an OS transistor can be used. Since the OS transistor has a very small off-current, by using the OS transistor for transistor M11, the potential written to node N11 can be held for a long time. That is, the data written to memory cell OMC can be held for a long time. Or, by using the OS transistor for transistor M11, memory cell OMC may reduce the capacitance of capacitor C11. Or, by using the OS transistor for transistor M11, memory cell OMC may be configured not to have capacitor C11 as shown in FIG. 5B. When memory cell OMC does not have capacitor C11, the potential written to node N11 is held by the gate capacitance of transistor M12 or the like.

[0098] Transistors M11 and M12 may have a back gate (also referred to as a second gate, bottom gate). For example, when transistor M11 has a back gate, by applying a predetermined potential to the back gate of transistor M11, the threshold voltage of transistor M11 can be increased or decreased. Or, by electrically connecting the back gate of transistor M11 to the gate of transistor M11 (also referred to as the first gate, top gate, front gate with respect to the back gate), the on-current of transistor M11 can be increased.

[0099] Specifically, by increasing the potential applied to the back gates of transistors M11 and M12, the threshold voltage shifts negatively, and by decreasing the potential applied to the back gates of transistors M11 and M12, the threshold voltage shifts positively. By shifting the threshold voltage negatively, the on-current of the transistor can be increased, and the memory cell OMC can operate at high speed. By shifting the threshold voltage positively, the off-current of the transistor can be reduced, and the memory cell OMC can hold data for a long time. Alternatively, different potentials may be applied to the back gates of transistors M11 and M12. For example, the potential applied to the back gate of transistor M11 may be decreased, and the potential applied to the back gate of transistor M12 may be increased.

[0100] Alternatively, transistors other than the OS transistor may be used for transistors M11 and M12. For transistors M11 and M12, transistors with a small off-current are preferred. For example, transistors having a semiconductor with a large bandgap in the channel formation region can be used. The semiconductor with a large bandgap may refer to a semiconductor having a bandgap of 2.2 eV or more. Examples include silicon carbide, gallium nitride, diamond, and the like.

[0101] The memory cell OMC is a gain cell type memory cell composed of two transistors and one capacitor element or two transistors. The gain cell type memory cell can operate as a memory by amplifying the stored charge with the nearest transistor even when the capacitance for storing charge is small. In addition, the gain cell type memory cell can read the stored data without destroying it (non-destructive readout).

[0102] Alternatively, the memory cell OMC may be composed of one transistor and one capacitor element. The memory cell OMC shown in FIG. 5C has a transistor M13 and a capacitor element C12.

[0103] One of the source or drain of transistor M13 is electrically connected to one terminal of capacitor element C12, the other of the source or drain of transistor M13 is electrically connected to wiring abl, and the gate of transistor M13 is electrically connected to wiring awl. The other terminal of capacitor element C12 is electrically connected to wiring CAL. A connection part where one of the source or drain of transistor M13 and one terminal of capacitor element C12 are electrically connected is referred to as node N12.

[0104] For transistor M13, similar to transistors M11 and M12, an OS transistor can be used. Also, in memory cell OMC shown in FIG. 5C, wiring abl functions as a bit line and wiring awl functions as a word line.

[0105] By configuring memory cell OMC as shown in FIG. 5C, while the arrangement density of memory cell OMC can be improved, data reading becomes destructive reading. Also, regardless of whether the memory cell OMC included in memory cell part OMCL is the memory cell OMC shown in FIGS. 5A, 5B, and 5C, memory cell part OMCL can randomly access memory cell OMC.

[0106] <Circuit BLD and circuit OBLD> Circuit BLD and circuit OBLD included in circuit OSC will be described more specifically. FIG. 6 is a block diagram showing a configuration example of a part of circuit OSC. FIG. 6 more specifically shows a configuration example of circuit BLD, a configuration example of circuit OBLD, and the signal flow in circuit OSC, with the output circuit OUTP, circuit CVC, etc. omitted from the circuit OSC shown in FIG. 2.

[0107] Circuit BLD can be configured to have, for example, a column decoder CD, a write circuit WC, a sense amplifier SA, and an output circuit OPC.

[0108] The column decoder CD has a function of selecting a wiring BL to which a memory cell MC to be written or read is electrically connected according to an address signal AD acquired from a control circuit CTR. Here, the address signal AD is an internal signal of a circuit OSC and is a signal corresponding to the address signal included in a control signal CS. Also, the address signal AD is sent to a circuit WLD. The circuit WLD has a function of driving a wiring BSL, a wiring WL, and a wiring SSL, and has a function of selecting a wiring WL to which a memory cell MC to be written or read is electrically connected according to the address signal AD.

[0109] The write circuit WC has a function of supplying a potential corresponding to a data signal WD supplied from the control circuit CTR to the wiring BL selected by the column decoder CD. Here, the data signal WD is an internal signal of the circuit OSC and is a signal corresponding to a data signal ORD or a data signal WDATA.

[0110] Also, the sense amplifier SA has a function of amplifying a data signal read from the wiring BL. Note that the amplified data signal is output to the control circuit CTR as a data signal RD via an output circuit OPC. The control circuit CTR outputs a signal corresponding to the data signal RD to an output circuit OUTP.

[0111] The circuit OBLD can be configured to have, for example, a column decoder OCD, a write circuit OWC, a precharge circuit OPR, a sense amplifier OSA, and an output circuit OOPC.

[0112] The column decoder OCD has a function of selecting wiring wbl and wiring rbl to which a memory cell OMC to be written or read is electrically connected according to an address signal OAD acquired from the control circuit CTR. Here, the address signal OAD is an internal signal of the circuit OSC. Also, the address signal OAD is sent to the circuit OWLD. The circuit OWLD has a function of driving the wiring wwl and the wiring rwl, and has a function of selecting the wiring wwl and the wiring rwl to which a memory cell OMC to be written or read is electrically connected according to the address signal OAD.

[0113] The write circuit OWC has a function of supplying a potential corresponding to a data signal OWD supplied from the control circuit CTR to the wiring wbl selected by the column decoder OCD. Here, the data signal OWD is an internal signal of the circuit OSC and is a signal corresponding to the data signal WDATA.

[0114] Also, the precharge circuit OPR has a function of precharging the wiring rbl, and the sense amplifier OSA has a function of amplifying the data signal read from the wiring rbl. The amplified data signal is output to the control circuit CTR as a data signal ORD via the output circuit OOPC. The control circuit CTR outputs a signal corresponding to the data signal ORD to the write circuit WC or the output circuit OUTP.

[0115] Note that the components of the circuit BLD and the circuit OBLD are not limited to these, and other components may be added or unnecessary components may be reduced as needed. Also, the functions of the circuit BLD and the circuit OBLD are not limited to these, and they may have other functions or unnecessary functions may be reduced.

[0116] <Configuration Example 2 of the Storage Device> In the memory device 100 described above, the circuit OSC has a control circuit CTR, a circuit PRPH, a circuit ORPH, and an output circuit OUTP (see FIG. 2). Although it has been described that the circuit OSC is provided in layer 10, the circuit ORPH included in the circuit OSC may be provided in layer 40.

[0117] FIG. 7A is a schematic perspective view showing a configuration example of the memory device 100 when the circuit ORPH is provided in layer 40. Note that, similar to FIG. 1B, FIG. 7A omits the wirings EW related to layers 20_1 to 20_l and layer 20 from FIG. 1A.

[0118] In FIG. 7A, the circuit OSC has a control circuit CTR, a circuit PRPH, and an output circuit OUTP, the circuit ORPH has a circuit OWLD and a circuit OBLD, and the circuit ORPH is provided in layer 40 together with the memory cell portion OMCL.

[0119] When the memory cell portion OMCL provided in layer 40 is configured using OS transistors, the circuit ORPH can also be configured using OS transistors. n-channel transistors have been put into practical use as OS transistors. When the circuit ORPH is configured using OS transistors, the circuit ORPH can be a unipolar circuit using n-channel transistors. Note that a configuration example when the circuit ORPH is a unipolar circuit using n-channel transistors can be referred to, for example, in Non-Patent Document 4.

[0120] When the circuit ORPH is provided in layer 40, the control circuit CTR can write the data signal WDATA input from the outside of the memory device 100 to the memory cell portion OMCL via the wiring EW, and write the data read from the memory cell portion OMCL to the memory cell portion MCL via layer 30 and the wiring EW. That is, since the number of times data moves via the wiring EW can be reduced, the data movement distance can be made shorter than that of the memory device 100 shown in FIG. 1B.

[0121] <Configuration Example 3 of Memory Device> In the memory device 100 described above, it may be configured not to have the layer 40. FIG. 7B is a schematic perspective view showing a configuration example of the memory device 110. The memory device 110 shown in FIG. 7B has a configuration without the layer 40 as compared with the memory device 100 shown in FIG. 1A.

[0122] Since the memory device 110 does not have the layer 40, it is configured not to have the memory cell part OMCL. Further, in the memory cell part MCL of the memory device 110, the channel formation regions of the transistor BTr, the transistor CTr, and the transistor STr have a metal oxide. By having a metal oxide in the channel formation regions of the transistor BTr, the transistor CTr, and the transistor STr, a part of the first memory device can be used as a cache memory. Therefore, the memory device 110 does not require a second memory device having a function as a cache memory, and the memory device 110 can have a configuration without the layer 40. Similarly, the memory device 110 can have a configuration without the circuit ORPH.

[0123] In this specification etc., a three-dimensional structure NAND type flash memory having a metal oxide in the channel formation regions of the transistor BTr, the transistor CTr, and the transistor STr is called "3D OS NAND". Also, a three-dimensional structure NAND type flash memory using Si transistors for the transistor BTr, the transistor CTr, and the transistor STr is called "3D NAND". For example, the memory device 100 described above is 3D NAND, and the memory device 110 is 3D OS NAND.

[0124] Although a circuit configuration example of 3D OS NAND will be described later, 3D OS NAND enables random access and has a characteristic that the off-current of the OS transistor is very small. Therefore, 3D OS NAND can retain information written over a period of one year or more, and even ten years or more, even when the power supply is stopped. Thus, 3D OS NAND can also be regarded as a non-volatile memory.

[0125] In addition, since the amount of charge written in 3D OS NAND is difficult to change over a long period of time, 3D OS NAND can hold not only binary (1-bit) but also multi-value (multi-bit) information.

[0126] In addition, since 3D OS NAND writes charge to the node via an OS transistor, a high voltage that was required in conventional flash memory is not necessary, and a high-speed write operation can also be realized. Also, the erase operation before data rewriting performed in flash memory is not required in 3D OS NAND. Further, since charge injection and extraction to the floating gate or charge trapping layer are not performed, 3D OS NAND can perform substantially unlimited times of data writing and reading. 3D OS NAND has less degradation and higher reliability compared to conventional flash memory.

[0127] In addition, 3D OS NAND does not involve structural changes at the atomic level like magnetoresistive memory (MRAM) or resistive random access memory (ReRAM). Therefore, 3D OS NAND has better rewrite resistance than magnetoresistive memory and resistive random access memory.

[0128] Also, the off-current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Also, the on-current is difficult to decrease even in a high-temperature environment. A storage device including an OS memory operates stably even in a high-temperature environment and has high reliability. In addition, the OS transistor has a high breakdown voltage between the source and the drain. By using the OS transistor for the transistors constituting a semiconductor device, a semiconductor device that operates stably and has good reliability can be realized even in a high-temperature environment.

[0129] Table 1 shows a comparison table between a 3D NAND type storage device and a 3D OS NAND type storage device.

[0130]

Table 1

[0131] Further, the storage device 110 can be a flash memory having an arithmetic processing function by using an arithmetic processing device such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) in the control circuit CTR of the circuit OSC. The storage device 110 shown in FIG. 8 is a 3D OS NAND having functions as a CPU, a NAND flash memory, and a cache memory (also referred to as an information processing device). That is, the CPU, the NAND flash memory, and the function as a cache memory can be fabricated on the same chip.

[0132] FIG. 8 shows a state in which a host 150 manages a plurality of storage devices 110 (3D OS NAND). Each storage device 110 has an arithmetic processing function and can parallelize writing and reading to and from the flash memory and the cache memory. That is, as shown in FIG. 8, by the host 150 managing a plurality of storage devices 110, an information processing system that realizes non-Neumann computing can be constructed.

[0133] Note that the present embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0134] (Embodiment 2) In the present embodiment, a configuration example of a storage device according to one aspect of the present invention and a configuration example of an information processing system including the storage device will be described.

[0135] FIG. 9A is a perspective schematic view showing a configuration example of a storage device 100A according to one aspect of the present invention. The storage device 100A includes a layer 10, layers 20_1 to 20_l (l is an integer of 2 or more), a layer 30, a layer 40A, and a wiring EW.

[0136] As shown in FIG. 9A, the memory device 100A has a structure in which a layer 20_1 is laminated and provided above the layer 10, a layer 20_k+1 (where k is an integer from 1 to l-1) is laminated and provided above the layer 20_k, a layer 30 is laminated and provided above the layer 20_l, and a layer 40A is laminated and provided above the layer 30.

[0137] The configurations of the layer 10, the layers 20_1 to 20_l, the layer 30, and the wiring EW are the same as those in the first embodiment, and detailed descriptions thereof are omitted.

[0138] In the memory device 100A, an OS transistor can be used for the layer 40A. Further, for the transistors included in the layer 40A, transistors having a compound semiconductor such as GaN can be used.

[0139] Circuits that can function by utilizing semiconductor characteristics are provided in the layer 10, the layers 20_1 to 20_l, respectively. A circuit OSC is provided in the layer 10, and a memory cell portion MCL is provided in the layers 20_1 to 20_l. The layer 30 is a wiring layer in which wirings are formed. That is, the first memory device has a memory cell portion MCL.

[0140] Circuits that can function by utilizing semiconductor characteristics are provided in the layer 40A, and an RF (Radio Frequency) block circuit RFBL and a coil (also referred to as an inductor) COIL are provided in the layer 40A.

[0141] The coil COIL has a function of performing high-frequency wireless communication by near-field magnetic field coupling. The coil COIL can use, for example, a spiral coil or the like. The RF block circuit RFBL is a circuit having a function of transmitting and receiving data via the coil COIL to and from another circuit block. In the description of the present embodiment, the RF block circuit RFBL may include the coil COIL.

[0142] FIG. 9B is a schematic perspective view in which wirings EW related to layers 20_1 to 20_l and layer 20 are omitted from FIG. 9A, showing the positional relationship among circuit OSC, memory cell section MCL, and RF block circuit RFBL and coil COIL.

[0143] The configurations of circuit OSC and memory cell section MCL are the same as those in Embodiment 1, and detailed descriptions thereof are omitted.

[0144] RF block circuit RFBL and coil COIL are electrically connected to circuit OSC and memory cell section MCL by wiring EW and layer 30.

[0145] When an OS transistor is used for RF block circuit RFBL, the OS transistor is a thin film transistor. Coil COIL is a conductor that can be used for wirings and the like. Therefore, RF block circuit RFBL and coil COIL can be provided by being stacked above circuit OSC and memory cell section MCL. Specifically, circuit OSC and memory cell section MCL can be configured using Si transistors, and RF block circuit RFBL can be configured using OS transistors above them. Note that the OS transistor is a transistor having a metal oxide in a channel formation region.

[0146] Also, RF block circuit RFBL can be fabricated by a process different from that of circuit OSC and memory cell section MCL. Since the formation temperature of the OS transistor is lower than that of the Si transistor, by configuring RF block circuit RFBL using the OS transistor, the influence of heat on the Si transistors included in circuit OSC and memory cell section MCL can be reduced. Further, since RF block circuit RFBL and coil COIL can be superimposed above circuit OSC and memory cell section MCL, an increase in the circuit area of memory device 100A can be suppressed.

[0147] Next, a configuration example of the storage device 100A including the RF block circuit RFBL will be described. FIG. 10A is a block diagram showing a configuration example of the storage device 100A.

[0148] In the block diagram shown in FIG. 10A, the storage device 100A includes an RF block circuit RFBL, a circuit OSC, and a memory cell section MCL. As described in the first embodiment, the circuit OSC has a function of performing arithmetic processing on data written to the memory cell section MCL or data read from the memory cell section MCL. In addition, the circuit OSC has a function of driving or controlling the RF block circuit RFBL. Therefore, in FIG. 10A, an arithmetic unit PU is illustrated inside the circuit OSC. The arithmetic unit PU has a circuit corresponding to the FTL (Flash Translation Layer), or a circuit that performs a function of error detection and correction (also referred to as ECC: Error Check and Correct).

[0149] The circuit block of the storage device 100A illustrated in FIG. 10A can transmit and receive data to and from a central processing unit CPU provided with the RF block circuit RFBL via the RF block circuit RFBL and a coil COIL (not shown). The storage device 100A has a function of performing operations of writing and reading data of the memory cell section MCL, arithmetic operations of data of the memory cell section MCL, and wireless communication operations of data with an external device.

[0150] The storage device 100A of the present embodiment can be used in combination with a central management unit 200A including the central processing unit CPU and the RF block circuit RFBL illustrated in FIG. 10B to form an information processing system 300A with reduced power consumption. The central management unit 200A has a function of controlling so as to distribute memory operations such as data reading and writing among a plurality of storage devices 100A.

[0151] The information processing system 300A illustrated in FIG. 10B can transmit and receive data between the central management unit 200A and a plurality of storage devices 100A. When the storage devices 100A each having a memory cell portion MCL and an arithmetic unit PU are arranged in a distributed manner, an electrical connection by a near-field magnetic field using a coil can be achieved between the distributed storage devices 100A and the central management unit 200A. In the distributed storage devices 100A, memory operations such as data reading and writing can be performed in a distributed manner.

[0152] In the configuration of FIG. 10B, the distance between the central processing unit CPU and the storage device 100A can be reduced. The central processing unit CPU can be electrically connected to the plurality of storage devices 100A to enable data transfer. Since a serial bus is not required between the central processing unit CPU and the plurality of storage devices 100A, the overall power consumption can be reduced. Since an electrical connection using magnetic field coupling by a near-field magnetic field is possible between the central processing unit CPU and the storage device 100A, the alignment accuracy as in the case of connection between metal electrodes by microbumps can be made unnecessary.

[0153] FIG. 11 is a perspective schematic view showing a configuration example of the central management unit 200A. The central management unit 200A has layers 10B, 30B, and 40B.

[0154] As shown in FIG. 11, the central management unit 200A has a structure in which the layer 30B is laminated and provided above the layer 10B, and the layer 40B is laminated and provided above the layer 30B.

[0155] In the central management unit 200A, the layer 40B can use OS transistors. By adopting a configuration using OS transistors, similar to the storage device 100A, it is possible to adopt a configuration including a memory cell unit that functions as a cache memory or a storage memory. Also, by adopting a configuration in which the layer 40B uses OS transistors, the RF block circuit RFBL can be configured. Note that the RF block circuit RFBL may be configured using a transistor having a compound semiconductor such as GaN.

[0156] In the layer 10B and the layer 30B, circuits that can function by utilizing semiconductor characteristics are provided, respectively. In the layer 10B, a circuit that functions as a central processing unit CPU is provided. The layer 10B is provided with a CPU composed of Si transistors. The layer 30B is a wiring layer in which wirings are formed.

[0157] In the layer 40B, similar to the above-described layer 40A, the RF block circuit RFBL and the coil COIL are provided.

[0158] FIGS. 12A and 12B are perspective schematic views showing a configuration example of the information processing system 300A. As shown in FIG. 12A, in the information processing system 300A, the layer 40A of the storage device 100A and the layer 40B of the central management unit 200A are bonded so as to face each other and integrated as shown in FIG. 12B. As described above, between the central management unit 200A and the storage device 100A, since an electrical connection using magnetic field coupling by a near-field magnetic field is possible, the alignment accuracy in the case of connection between metal electrodes by microbumps can be made unnecessary.

[0159] Note that the present embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0160] (Embodiment 3) In this embodiment, a circuit configuration example of the memory cell unit MCL of the storage device 110 according to one embodiment of the present invention will be described.

[0161] FIG. 22A shows a circuit diagram of a memory cell portion MCL of a memory device 110 according to an embodiment of the present invention. The memory cell portion MCL has a configuration including a plurality of memory elements 410 between a transistor 431 and a transistor 432. FIG. 22B shows a circuit diagram of the memory element 410. The memory element 410 has a transistor 411 and a transistor 412.

[0162] In the present embodiment and the like, the first memory element 410 is denoted as memory element 410[1], and the n-th memory element 410 (n is an integer of 3 or more) is denoted as memory element 410[n]. Also, the i-th memory element 410 (i is an integer greater than or equal to 2 and less than n) is denoted as memory element 410[i]. When explaining matters common to the memory elements 410[1] to 410[n], it may be simply denoted as "memory element 410".

[0163] Also, in the present embodiment and the like, the transistor 411 included in the first memory element 410 is denoted as transistor 411[1], the transistor 411 included in the i-th memory element 410 is denoted as transistor 411[i], and the transistor 411 included in the n-th memory element 410 is denoted as transistor 411[n]. When explaining matters common to the transistors 411[1] to 411[n], it may be simply denoted as "transistor 411". The transistor 412 and a node 413 described later are also denoted in the same manner as the transistor 411.

[0164] <Configuration Example of Memory Device> A circuit configuration example of the memory cell section MCL shown in Fig. 22A will be described in detail. One of the source or drain of the transistor 411[1] included in the memory element 410[1] is electrically connected to the wiring WBL, and the other is electrically connected to the node 413[1]. The gate of the transistor 411[1] is electrically connected to the terminal 421[1]. One of the source or drain of the transistor 412[1] is electrically connected to the transistor 431, and the other is electrically connected to one of the source or drain of the transistor 412[2]. The gate of the transistor 412[1] is electrically connected to the node 413[1]. The back gate of the transistor 412[1] is electrically connected to the terminal 422[1].

[0165] Also, one of the source or drain of the transistor 431 is electrically connected to the wiring RBL, and the other is electrically connected to one of the source or drain of the transistor 412[1]. The gate of the transistor 431 is electrically connected to the terminal 433. Note that the wiring WBL and the wiring RBL correspond to the wiring BL shown in Fig. 2. The wiring WBL is used for data writing, and the wiring RBL is used for data reading.

[0166] One of the source or drain of the transistor 411[2] included in the memory element 410[2] is electrically connected to the node 413[1], and the other is electrically connected to the node 413[2]. The gate of the transistor 411[2] is electrically connected to the terminal 421[2]. One of the source or drain of the transistor 412[2] is electrically connected to the other of the source or drain of the transistor 412[1], and the gate is electrically connected to the node 413[2]. The back gate of the transistor 412[2] is electrically connected to the terminal 422[2].

[0167] One of the source or drain of the transistor 411[i] included in the memory element 410[i] is electrically connected to a node 413[i - 1] (not shown), and the other is electrically connected to the node 413[i]. The gate of the transistor 411[i] is electrically connected to the terminal 421[i]. One of the source or drain of the transistor 412[i] is electrically connected to one or the other of the source or drain of the transistor 412[i - 1] (not shown). The gate of the transistor 412[i] is electrically connected to the node 413[i], and the back gate of the transistor 412[i] is electrically connected to the terminal 422[i].

[0168] One of the source or drain of the transistor 411[n] included in the memory element 410[n] is electrically connected to a node 413[n - 1] (not shown). The other of the source or drain of the transistor 411[n] is electrically connected to the node 413[n]. The gate of the transistor 411[n] is electrically connected to the terminal 421[n].

[0169] Also, one of the source or drain of the transistor 412[n] is electrically connected to either the source or drain of the transistor 412[n - 1] (not shown). The other of the source or drain of the transistor 412[n] is electrically connected to the transistor 432. The gate of the transistor 412[n] is electrically connected to the node 413[n], and the back gate of the transistor 412[n] is electrically connected to the terminal 422[n].

[0170] Also, one of the source or drain of the transistor 432 is electrically connected to the other of the source or drain of the transistor 412[n]. The other of the source or drain of the transistor 432 is electrically connected to the wiring SL. The gate of the transistor 432 is electrically connected to the terminal 434.

[0171] The memory cell portion MCL of the memory device 110 shown in FIG. 22A has n memory elements 410 between the transistor 431 and the transistor 432, and the transistors 411[1] to 411[n] are connected in series while sharing the source and drain between adjacent transistors. Also, the transistors 412[1] to 412[n] are also connected in series while sharing the source and drain between adjacent transistors.

[0172] In this way, the structure in which the memory elements 410 are arranged while sharing the source and drain between adjacent transistors may be referred to as a "string", "cell string", or "memory cell string". For example, one memory cell portion MCL may be referred to as "one string" or simply "string". Note that "string", "cell string", and "memory cell string" may also be used as units of reference.

[0173] 〔Memory Element〕 The memory element 410 (see FIG. 22B) has a function of holding the potential (charge) written to the node 413. Specifically, a voltage that turns on the transistor 411 is supplied to the gate of the transistor 411, and charge for setting the node 413 to a predetermined voltage is supplied to the node 413 via the source and drain of the transistor 411. Thereafter, a voltage that turns off the transistor 411 is supplied to the gate of the transistor 411. By turning off the transistor 411, the charge written to the node 413 can be held.

[0174] The semiconductor layers of the transistor 411 and the transistor 412 can be used singly or in combination, such as single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor. As the semiconductor material, for example, silicon, germanium, etc. can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductor, and nitride semiconductor may be used. The same applies to the transistors 431 and 432.

[0175] Note that the semiconductor layers used for the transistor may be stacked. When stacking the semiconductor layers, semiconductors having different crystal states may be used, or different semiconductor materials may be used.

[0176] In particular, the transistor 411 is preferably an OS transistor. Since the oxide semiconductor has a band gap of 2 eV or more, the off-current is extremely small. When an OS transistor is used for the transistor 411, the charge written in the node 413 can be retained for a long period. When an OS transistor is used for the transistor 411, the memory element 410 can be called an "OS memory".

[0177] The OS memory can retain the written information for a period of one year or more, and even ten years or more, even when the power supply is stopped. Therefore, the OS memory can also be regarded as a nonvolatile memory.

[0178] In addition, since the amount of charge written in the OS memory hardly changes over a long period, the OS memory can retain not only binary (1-bit) but also multi-valued (multi-bit) information.

[0179] In addition, since the OS memory is a method of writing charge to a node via an OS transistor, the high voltage required for a conventional flash memory is not necessary, and a high-speed writing operation can also be realized. Further, the erasing operation before data rewriting performed in the flash memory is not necessary for the OS memory. In addition, since charge injection and extraction to the floating gate or charge trapping layer are not performed, the OS memory can perform substantially unlimited writing and reading of data. The OS memory has less deterioration and higher reliability compared to a conventional flash memory.

[0180] In addition, the OS memory does not involve a structural change at the atomic level like a magnetic resistance memory (MRAM) or a resistive change memory (ReRAM). Therefore, the OS memory is more resistant to rewriting than the magnetic resistance memory and the resistive change memory.

[0181] In addition, in an OS transistor, the off-current hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200° C. or lower. Also, the on-current hardly decreases even in a high-temperature environment. A memory device including an OS memory operates stably even in a high-temperature environment and can provide high reliability. Further, an OS transistor has a high breakdown voltage between the source and the drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that operates stably and has good reliability can be realized even in a high-temperature environment.

[0182] Also, as shown in FIG. 22C, a transistor having a back gate may be used as the transistor 411 included in the memory element 410. FIG. 22C shows an example in which the gate and the back gate of the transistor 411 are electrically connected.

[0183] Also, as shown in FIG. 22D, a capacitor 425 may be provided between the node 413 and the terminal 423. When the capacitor 425 is provided, it is preferable to supply a fixed potential to the terminal 423. By providing the capacitor 425, the potential fluctuation of the node 413 can be suppressed, and the reliability of the memory cell unit MCL can be improved. In particular, when the memory element 410 stores multi-valued information, it is preferable to provide the capacitor 425 in the memory element 410.

[0184] Also, in the memory element 410 shown in FIG. 22B, an OS transistor and an Si transistor can be used in combination for the transistor 411 and the transistor 412. FIG. 36A shows an example in which an OS transistor is used for the transistor 411 and the transistor 412. In FIGS. 36A to 36D, in order to clarify that a transistor is an OS transistor, "OS" is appended to the circuit symbol of the transistor, and in order to clarify that a transistor is an Si transistor, "Si" is appended to the circuit symbol of the transistor.

[0185] FIG. 36B shows an example in which an OS transistor is used for transistor 411 and an Si transistor is used for transistor 412. The memory element 410 shown in FIGS. 36A and 36B uses an OS transistor for transistor 411, so that, as described above, the written information can be retained for a long time even when the power supply is stopped, multi-valued information can be retained as well as binary information, and high reliability can be obtained even in a high-temperature environment. Further, the memory element 410 shown in FIG. 36B can improve the read speed by using an Si transistor for transistor 412.

[0186] Note that, as shown in FIG. 36C, depending on the purpose or application, etc., an Si transistor may be used for transistor 411 and an OS transistor may be used for transistor 412. Further, as shown in FIG. 36D, depending on the purpose or application, etc., Si transistors may be used for both transistor 411 and transistor 412.

[0187] <Operation Example of Memory Device> An operation example of the memory cell part MCL will be described with reference to the drawings. In the present embodiment, a memory cell part MCL including four memory elements 410 will be exemplarily described.

[0188] 〔Write Operation〕 In the present embodiment, an operation example in the case where an H potential is written to the memory element 410[1], the memory element 410[2], and the memory element 410[4], and an L potential is written to the memory element 410[3] will be described. FIG. 23A is a timing chart for explaining the write operation. FIGS. 24A, 24B, 25A, 25B, and 26 are circuit diagrams for explaining the write operation.

[0189] As an initial state, it is assumed that an L potential is written to the memory elements 410[1] to 410[4]. Further, it is assumed that an L potential is supplied to the wirings WL[1] to WL[4], the wirings CL[1] to CL[4], the terminal 433, the terminal 434, the wiring SL, and the wiring RBL.

[0190] [Period T1] During period T1, an H potential is supplied to wirings WL[1] to WL[4] and wiring WBL (see Fig. 24A). Then, the potentials of nodes 413[1] to 413[4] become the H potential. Therefore, transistors 412[1] to 412[4] turn on.

[0191] [Period T2] During period T2, an L potential is supplied to wiring WL[4] (see Fig. 24B). Then, transistor 411[4] turns off, and the charge written in node 413[4] is retained. Here, a charge corresponding to the H potential is retained. Also, an L potential is supplied to wiring WBL. Then, the potentials of nodes 413[1] to 413[3] become the L potential. Therefore, transistors 412[1] to 412[3] turn off.

[0192] [Period T3] During period T3, an L potential is supplied to wiring WL[3] (see Fig. 25A). Then, transistor 411[3] turns off, and the charge written in node 413[3] is retained. Here, a charge corresponding to the L potential is retained. Also, an H potential is supplied to wiring WBL. Then, the potentials of nodes 413[1] and 413[2] become the H potential. Therefore, transistors 412[1] and 412[2] turn on.

[0193] [Period T4] During period T4, an L potential is supplied to wiring WL[2] (see Fig. 25B). Then, transistor 411[2] turns off, and the charge written in node 413[2] is retained. Here, a charge corresponding to the H potential is retained.

[0194] [Period T5] During period T5, an L potential is supplied to wiring WL[1] (see FIG. 26). Then, transistor 411[1] turns off, and the charge written to node 413[1] is retained. Here, a charge corresponding to the H potential is retained. In this way, information can be written to memory elements 410[1] to 410[4].

[0195] [Read operation] In the present embodiment, an example of the read operation of the information held in memory elements 410[2] among the information held in memory elements 410[1] to 410[4] will be described. It is assumed that an H potential is held in memory element 410[2]. FIG. 23B is a timing chart for explaining the read operation. FIGS. 27A, 27B, 28A, and 28B are circuit diagrams for explaining the read operation.

[0196] [Period T6] During period T6, an H potential is supplied to wirings CL[1] to CL[4] and terminal 433, turning on transistors 412[1] to 412[4] and transistor 431 (see FIG. 27A). Also, the wiring RBL is precharged to the H potential, putting the wiring RBL in a floating state.

[0197] [Period T7] During period T7, an L potential is supplied to wiring CL[2] (see FIG. 27B). Since an H potential is held at node 413[2], transistor 412[2] remains on.

[0198] [Period T8] During period T8, an H potential is supplied to terminal 434, turning on transistor 432 (see FIG. 28A). Since transistors 412[1] to 412[4] are all on, wiring RBL and wiring SL are electrically connected, and the potential of wiring RBL changes to the L potential.

[0199] When the potential of node 413[2] is at the L potential, if the L potential is supplied to wiring CL[2], transistor 412[2] turns off. In this case, even if transistor 432 turns on, the potential of wiring RBL remains at the H potential. By knowing the potential change of wiring RBL, the information held in memory element 410 can be known.

[0200] That is, in period T8, by setting the potential of the wiring CL corresponding to the memory element 410 to be read out to the L potential, the information held in the memory element 410 can be read out.

[0201] [Period T9] In period T9, an L potential is supplied to wirings CL[1] to CL[4], terminal 433, and terminal 434 (see FIG. 28B). Then, transistors 412[1], 412[2], 412[4], transistor 431, and transistor 432 turn off.

[0202] The memory cell section MCL shown in this embodiment and the like functions as a NAND type memory device.

[0203] Note that data with a high rewrite frequency can be stored in the memory element 410 close to the wiring WBL, thereby shortening the time required for data writing (rewriting). That is, the data writing (rewriting) speed can be increased. By operating in this way, the 3D OS NAND can be operated like a RAM.

[0204] Note that this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0205] (Embodiment 4) In this embodiment, a configuration example of the transistor constituting the memory device 100 described in the above embodiment will be described. FIG. 13 shows a cross-sectional configuration example of layers 10 and 20, and FIG. 14 shows a cross-sectional configuration example of layers 20 and 40. In this embodiment, a case where a single-crystalline silicon substrate is used for the substrate SUB, a NAND-type memory element having a three-dimensional structure is provided in layer 20, and an OS transistor is formed in layer 40 will be described.

[0206] In FIGS. 13 and 14, a transistor 300 is formed in layer 10, transistors 700, a plurality of transistors 800, and a transistor 900 are formed in layer 20, and a transistor 500 is formed in layer 40.

[0207] Note that the transistor 700 corresponds to the transistor BTr in FIG. 2, the transistor 800 corresponds to the transistor CTr in FIG. 2, and the transistor 900 corresponds to the transistor STr in FIG. 2. Also, the transistor 300 is one of the transistors constituting the circuit OSC, the transistor 500 corresponds to the transistor M11, and the capacitor element 600 corresponds to the capacitor element C11.

[0208] In addition to the first gate (also referred to as a top gate, a front gate, or simply a gate), the transistor 500 has a second gate (also referred to as a bottom gate or a back gate). The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. Since the transistor 500 has a characteristic of extremely small off-current, in the above embodiment, by using this as the transistor M11, the data written in the memory cell OMC can be held for a long time.

[0209] FIG. 15A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 15B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 15C is a cross-sectional view of the transistor 300 in the channel width direction. As shown in FIGS. 13 and 14, in the memory device 100 described in this embodiment, the layer 20 is provided above the layer 10, and the layer 40 is provided above the layers 20 and 10.

[0210] <Configuration example of layer 10> The transistor 300 is provided on a substrate 311 and has a semiconductor region 313 composed of a conductor 316, an insulator 315, and a part of the substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b.

[0211] As shown in FIG. 15C, in the transistor 300, the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with the conductor 316 via the insulator 315. In this way, by making the transistor 300 a Fin type, the effective channel width is increased, so that the on characteristics of the transistor 300 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

[0212] Note that the transistor 300 may be either a p-channel type or an n-channel type.

[0213] In regions where the channel of the semiconductor region 313 is formed, regions in the vicinity thereof, source regions, or drain regions, such as the low-resistance regions 314a and 314b, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaN (gallium nitride), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs, GaAlAs, etc., the transistor 300 may be a HEMT (High Electron Mobility Transistor).

[0214] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron.

[0215] The conductor 316 that functions as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as arsenic and phosphorus, or an element that imparts p-type conductivity such as boron.

[0216] Note that since the work function is determined by the material of the conductor, the Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to laminate and use a metal material such as tungsten or aluminum for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0217] Note that the transistor 300 shown in FIG. 13 is an example and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and driving method.

[0218] Over the transistor 300, the insulators 320, 322, 324, and 326 are sequentially stacked and provided.

[0219] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0220] The insulator 322 may have a function as a planarization film that planarizes the step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0221] In addition, for the insulator 324, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 or the like into the region where the transistor 500 is provided.

[0222] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a chemical vapor deposition (CVD) method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0223] The amount of hydrogen desorption can be analyzed using, for example, the temperature-programmed desorption gas analysis (TDS (Thermal Desorption Spectroscopy) analysis) method. For example, the amount of hydrogen desorption of the insulator 324 is such that in the TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 324, is 10×10 15 atoms / cm 2 or less, preferably 5×10 15 atoms / cm 2 or less.

[0224] Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0225] In addition, conductors 328, conductors 330, etc. are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductor 328 and the conductor 330 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be given the same reference numeral collectively for a plurality of structures. Also, in this specification, etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0226] As materials for each plug and wiring (such as conductor 328 and conductor 330), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used singly or in a laminated manner. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form with a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0227] Although omitted in FIG. 13, a wiring layer may be provided on insulator 326 and conductor 330. For example, it is preferable to provide an insulator having a barrier property against hydrogen, similar to insulator 324, on insulator 326 and conductor 330, and to form a conductor having a barrier property against hydrogen on the insulator. By forming a conductor having a barrier property against hydrogen in the opening of the insulator having a barrier property against hydrogen, transistor 300 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0228] As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from transistor 300 can be suppressed while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator having a barrier property against hydrogen. In FIG. 13, an insulator 350 having a barrier property against hydrogen is provided on insulator 326 and conductor 330.

[0229] <Configuration Example of Layer 20> Layer 20 shown in FIG. 13 is provided above layer 10. Further, layer 20 has insulators 111 to 117, insulator 121, insulator 122, insulator 131, insulator 132, insulator 133, conductors 151 to 156, and semiconductors 141 to 143 above layer 10.

[0230] The insulator 111 is provided above the layer 10. When the insulator 111 functions as an underlayer film, the insulator 111 is preferably formed, for example, by a film-forming method with good flatness.

[0231] As the insulator 111, for example, a material containing silicon oxide or silicon oxynitride can be used. Also, for example, an insulator containing a material selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. can be used in a single layer or a laminate.

[0232] The conductor 151 is provided laminated on the insulator 111. The conductor 151 may function as the wiring CL in FIG. 2.

[0233] As the conductor 151, for example, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used. Further, a conductive material containing a metal element and oxygen included in the metal oxide described in Embodiment 5 may be used. Also, a conductive material containing a metal element such as titanium, tantalum, etc. and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride, tantalum nitride, etc. may be used. Also, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon, etc. may be used. Also, for example, indium gallium zinc oxide containing nitrogen, etc. may be used. By using such materials, it may be possible to capture hydrogen or water mixed in from surrounding insulators or the like.

[0234] There is no particular limitation on the method for forming the conductor 151. For example, film formation can be performed by a sputtering method, a CVD method (including a thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method, a PECVD method, etc.), an MBE (Molecular Beam Epitaxy) method, an atomic layer deposition (ALD) method, a PLD (Pulsed Laser Deposition) method, etc.

[0235] On the conductor 151, an insulator 112, a conductor 152, an insulator 113, a conductor 153, and an insulator 114 are sequentially laminated and provided. Also, above the insulator 114, a conductor 154, an insulator 115, a conductor 155, an insulator 116, a conductor 156, and an insulator 117 are provided.

[0236] As the insulators 112 to 117, for example, the same material as the insulator 111 can be used. Further, as the insulators 112 to 117, for example, a material with a low dielectric constant is preferably used. By using a material with a low dielectric constant as the insulators 112 to 117, the capacitance values of the parasitic capacitances generated by the conductors 152 to 156 and the insulators 112 to 117 can be reduced. Therefore, the driving speed of the memory cell portion MCL can be improved.

[0237] There is no particular limitation on the method for forming the insulators 112 to 117. For example, film formation can be performed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like.

[0238] The conductor 152 functions as the gate of the transistor 900 (transistor STr in FIG. 2) and the wiring SSL in FIG. 2. Further, the conductors 153 to 155 function as the gates of the plurality of transistors 800 (transistors CTr in FIG. 2) and the wiring WL in FIG. 2. Further, the conductor 156 functions as the gate of the transistor 700 (transistor BTr in FIG. 2) and the wiring BSL in FIG. 2.

[0239] As the conductors 152 to 156, for example, the same material as the conductor 151 can be used. Further, as the method for forming the conductors 152 to 156, the same method as the conductor 151 can be used.

[0240] Further, openings are provided in the insulators 112 to 117 and the conductors 152 to 156. The insulators 121, 122, 131 to 133, and the semiconductors 141 to 143 are provided in the openings.

[0241] The semiconductor 141 is provided so as to contact the side surfaces and the bottom surface of a part of the opening. Specifically, the semiconductor 141 is provided on a part of the conductor 151 and is provided so as to cover a part of the insulator 112 on the side surface of the opening.

[0242] As the semiconductor 141, for example, it is preferable to use silicon in which impurities are diffused. As the impurities, n-type impurities (donors) can be used. As the n-type impurities, for example, phosphorus, arsenic, etc. can be used. Also, p-type impurities (acceptors) can be used as the impurities. As the p-type impurities, for example, boron, aluminum, gallium, etc. can be used. Also, as the silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon, etc. can be used. Further, as the semiconductor 141, other than silicon, metal oxides with a high carrier density may be applicable in some cases. Also, compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. may be applicable in some cases.

[0243] Note that the materials applied to the semiconductors 142 and 143 described later are preferably the same materials as the semiconductor 141, and in some cases, it is preferable that the carrier density of the semiconductor 142 is lower than that of the semiconductors 141 and 143.

[0244] For example, when applying silicon in which p-type impurities are diffused as the semiconductor 141, after forming the semiconductor 141 on the conductor 151, it is preferable to add p-type impurities such as boron, aluminum, gallium, etc. to the semiconductor 141. Thereby, a p-type region is formed in the semiconductor 141. Also, for example, when applying silicon in which n-type impurities are diffused, after forming the semiconductor 141 on the conductor 151, it is preferable to add n-type impurities such as phosphorus, arsenic, etc. to the semiconductor 141. Thereby, an n-type region is formed in the semiconductor 141.

[0245] Also, when applying a metal oxide as an example of the semiconductor 141, after forming the semiconductor 141 on the conductor 151, it is preferable to add a metal element or the like to the semiconductor 141. Thereby, the carrier density in the semiconductor 141 can be increased. In particular, when applying the metal oxide described in Embodiment 5 as the semiconductor 141, an n-type region (n + region) is formed in the semiconductor 141. Further, instead of adding a metal element or the like to the semiconductor 141, heat treatment may be performed after adding water, hydrogen, or the like to cause oxygen deficiency in the semiconductor 141. Since an n-type region is formed in the region where oxygen deficiency occurs in the semiconductor 141, as a result, the carrier density of the semiconductor 141 increases.

[0246] The insulator 121 is provided so as to be in contact with a part of the side surface of the opening. Specifically, the insulator 121 is provided so as to cover a part on the semiconductor 141 and the conductor 152 on the side surface of the opening.

[0247] The insulator 121 functions as a gate insulating film of the transistor 900.

[0248] As the insulator 121, for example, silicon oxide, silicon oxynitride, or the like can be used. In particular, when a metal oxide is used as the semiconductor 142 described later, the insulator 121 is preferably a material that releases oxygen by heating. By providing the oxygen-containing insulator 121 in contact with the metal oxide applied as the semiconductor 142, the oxygen deficiency in the metal oxide can be reduced, and the reliability of the transistor 900 can be improved.

[0249] The film formation method of the insulator 121 is not particularly limited, but since the insulator 121 is formed on the side surface of the opening provided in the insulator 112, the conductor 152, and the insulator 113, a film formation method with high film covering property is required. Examples of the film formation method with high film covering property include the ALD method.

[0250] The insulator 131 is provided so as to contact a part of the side surface of the opening. Specifically, the insulator 131 is provided so as to cover the conductors 153 to 155 on the side surface of the opening. Therefore, the insulator 131 is provided so as to also cover the insulators 114 and 115 on the side surface of the opening.

[0251] The insulator 132 is provided so as to contact the insulator 131. Further, the insulator 133 is provided so as to contact the insulator 132. That is, the insulators 131 to 133 are laminated in order from the side surface of the opening toward the center.

[0252] The insulator 131 functions as the gate insulating film of the transistor 800. Further, the insulator 132 functions as the charge storage layer of the transistor 800. Further, the insulator 133 functions as the tunnel insulating film of the transistor 800.

[0253] As the insulator 131, for example, silicon oxide or silicon oxynitride is preferably used. Further, as the insulator 131, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium can be used. Further, the insulator 131 may be an insulator in which these are laminated. By making the insulator 131 thicker than the insulator 133, charge can be transferred from the semiconductor 142, which will be described later, to the insulator 132 through the insulator 133.

[0254] As the insulator 132, for example, silicon nitride or silicon oxynitride can be used. However, the materials applicable to the insulator 132 are not limited to these.

[0255] As the insulator 133, for example, silicon oxide or silicon oxynitride is preferably used. Further, as the insulator 133, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium may be used. Further, the insulator 133 may be an insulator in which these are laminated.

[0256] In addition, in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Further, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0257] The insulator 122 is provided so as to be in contact with a part of the side surface of the opening. Specifically, it is provided so as to cover the conductor 156 on the side surface of the opening.

[0258] The insulator 122 functions as a gate insulating film of the transistor 700.

[0259] As the insulator 122, for example, the same material as the insulator 121 can be used. Also, as the method for forming the insulator 122, the same method as that for the insulator 121 can be used.

[0260] The semiconductor 142 is provided so as to be in contact with the side surfaces of the formed insulator 121, insulator 133, and insulator 122 in the opening.

[0261] The semiconductor 142 functions as a channel formation region of the transistors 700, 800, 900, and as a wiring for electrically connecting the transistors 700, 800, 900 in series.

[0262] As the semiconductor 142, for example, silicon is preferably used. Also, as the silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used. Further, as the semiconductor 142, metal oxides may be applicable in addition to silicon. Also, compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe may be applicable.

[0263] After the semiconductor 141, semiconductor 142, insulator 121, insulator 122, insulator 131, insulator 132, and insulator 133 are formed in the opening, the semiconductor 143 is provided to fill the opening. Specifically, the semiconductor 143 is provided to contact the insulator 122 and the semiconductor 142 and to contact the side surface of the insulator 117.

[0264] As the semiconductor 143, for example, it is preferable to use the same material as the semiconductor 141. Therefore, it is preferable that the polarities of the semiconductor 141 and the semiconductor 143 are equal.

[0265] Note that the memory device 100 according to one embodiment of the present invention is not limited to the configuration of the NAND type memory element included in the memory cell unit MCL shown in FIG. 13. The NAND type memory element applied to the memory device 100 may have a configuration different from the NAND type memory element shown in FIG. 13.

[0266] <Configuration Example 2 of Layer 20> The cross-sectional configuration example of the layer 10 and the layer 20 shown in FIG. 21 is a configuration example in which the layer 20 in FIG. 13 is modified. Specifically, the layer 20 shown in FIG. 21 is a configuration example of the memory device 110 (3D OS NAND) described in the first embodiment.

[0267] In the layer 20 shown in FIG. 21, as an example, the memory cell MC included in the three-dimensional structure NAND type memory element has a transistor RTr, a transistor WTr, and a capacitor CS.

[0268] Also, the layer 20 shown in FIG. 21 is provided above the layer 10 in the same manner as the layer 20 in FIG. 13. Further, the layer 20 has insulators 211 to 216, insulators 240 to 242, conductors 221, conductors 222, conductors 250 to 252, semiconductors 231, and semiconductors 232 above the layer 10.

[0269] The insulator 240 is provided above the layer 10. Therefore, the insulator 350 located below the insulator 240 is preferably formed by a film formation method with good flatness. Also, it is preferable that CMP processing is performed on the insulator 350.

[0270] As the insulator 240, for example, a material applicable to the insulator 111 can be used.

[0271] The insulator 241 is provided laminated on the insulator 240. As the insulator 241, for example, a material applicable to the insulator 111 can be used in the same manner as the insulator 240.

[0272] Also, a conductor 250 is embedded in the insulator 240, and a conductor 251 is embedded in the insulator 241. The conductor 250 and the conductor 251 have functions as plugs or wirings. Also, similar to FIG. 13, conductors having functions as plugs or wirings shown in FIG. 21 may be given the same reference numeral in a lump for a plurality of structures. Also, in this specification and the like, a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0273] As the conductor 250 and the conductor 251, for example, materials applicable to the conductor 328 and the conductor 330 can be used.

[0274] The insulator 211 is provided on the insulator 241. Also, the conductor 221 is provided on the insulator 211. Also, the insulator 212 is provided on the conductor 221. Also, the conductor 222 is provided on the insulator 212. That is, the insulator 211, the conductor 221, the insulator 212, and the conductor 222 are laminated in this order (these are referred to as a laminate). Also, the layer 20 shown in FIG. 21 has as many laminates as the number of memory cells MC included in one string.

[0275] Also, in the manufacturing process of the memory device shown in FIG. 21, openings are provided in the insulator 211, the conductor 221, the insulator 212, and the conductor 222 by forming a resist mask and performing an etching process or the like. At this time, the conductor 221 is selectively removed so that a concave portion is formed by the insulator 211, the conductor 221, and the insulator 212. In this case, it is preferable that the conductor 221 be made of a material having an etching rate higher than that of the insulator 211, the insulator 212, and the conductor 222.

[0276] Note that the resist mask can be formed by appropriately using, for example, a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced. Also, for the etching process, either a dry etching method or a wet etching method may be used, or both may be used.

[0277] Also, although details will be described later, an insulator 213, a semiconductor 231, an insulator 214, an insulator 215, a semiconductor 232, and a conductor 223 are formed in this order in the opening formed by the etching process.

[0278] As the insulator 211 and the insulator 212, for example, it is preferable to use a film having a barrier property that prevents hydrogen and impurities from diffusing. Therefore, as the insulator 211 and the insulator 212, for example, the same material as the insulator 111 can be used.

[0279] As the conductor 221 and the conductor 222, for example, it is preferable to use a material applicable to the conductor 151. In particular, as the conductor 221 and the conductor 222, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen.

[0280] On the side surface of the opening formed by the above-described etching process, an insulator 213 and a semiconductor 231 are formed in this order. Also, an insulator 214 is formed so as to fill the concave portion of the opening.

[0281] As a method for forming the insulator 214, for example, first, the insulator 214 is formed on the side surface of the opening so that the recess of the opening is filled, and then a part of the insulator 214 is removed by an etching process while leaving the insulator 214 in the recess and exposing the semiconductor 231.

[0282] As the insulator 213, for example, silicon oxide or silicon oxynitride can be used. Further, as the insulator 213, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium can be used. Also, the insulator 213 may be an insulator in which these are laminated.

[0283] As the semiconductor 231, it is preferable to use the metal oxide described in Embodiment 5. In this embodiment, hereinafter, it is assumed that a metal oxide is applied as the semiconductor 231.

[0284] Further, before forming the insulator 214, by performing heat treatment on the formed semiconductor 231 in an oxygen atmosphere, oxygen can be supplied to the metal oxide of the semiconductor 231. Then, after forming the insulator 214, by performing a supply process of impurities or the like to the metal oxide of the semiconductor 231, the resistance of the exposed region of the semiconductor 231 can be reduced. That is, the region of the semiconductor 231 in contact with the insulator 214 becomes a high-resistance region, and the region of the semiconductor 231 not in contact with the insulator 214 becomes a low-resistance region.

[0285] Further, examples of the supply process of impurities or the like to the metal oxide of the semiconductor 231 include forming a conductor on the side surface of the opening and removing the conductor after filling the recess of the opening with the insulator 214. When the conductive film contacts the metal oxide of the semiconductor 231, the metal element contained in the conductive film may diffuse into the semiconductor 231 to form a metal compound with the constituent elements of the semiconductor 231. A low-resistance region is formed in the semiconductor 231 by this metal compound.

[0286] As the insulator 214, it is preferable that it does not form a compound with the components contained in the semiconductor 231 at the interface with the previously formed semiconductor 231 and in the vicinity of the interface. Specifically, for example, silicon oxide or the like can be used as the insulator 214.

[0287] Thereafter, an insulator 215, a semiconductor 232, an insulator 216, and a conductor 223 are sequentially formed on the formation surfaces of the insulator 213 and the insulator 214. It is assumed that the opening provided in the laminate is filled by the formation of the conductor 223.

[0288] As the insulator 215 and the insulator 216, for example, it is preferable to use a material applicable to the insulator 213.

[0289] As the semiconductor 232, for example, similarly to the semiconductor 231, it is preferable to use the metal oxide described in Embodiment 5. In particular, it is preferable to use CAAC-OS, which will be described later, as the metal oxide. For example, when polycrystalline silicon is used for the semiconductor 231 and the semiconductor 232, the electron trap density increases due to the grain boundaries that can be formed in the polycrystalline silicon, and the transistor characteristics may vary greatly. On the other hand, since no clear grain boundaries are confirmed in CAAC-OS, variations in transistor characteristics can be suppressed.

[0290] As the conductor 223, for example, it is preferable to use a material applicable to the conductor 151. In particular, as the conductor 223, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen.

[0291] An insulator 242 is provided on the upper part of the formed string. As the insulator 242, for example, a material applicable to the insulator 111 can be used.

[0292] In addition, a conductor 252 is embedded in the insulator 242. The conductor 252 has a function as a plug or wiring. As the conductor 252, for example, materials applicable to the conductor 328 and the conductor 330 can be used.

[0293] By performing the above-described steps, the layer 20 of the memory device 110 described in Embodiment 1 can be fabricated.

[0294] Note that the wiring WL shown in FIG. 2 corresponds to the conductors 221 and 222. The conductor 221 is used during data writing, and the conductor 222 is used during data reading.

[0295] Therefore, a capacitor CS is configured with the conductor 222 as one electrode, the region of the insulator 213 in contact with the conductor 222 as a dielectric, and the region of the semiconductor 231 overlapping the conductor 222 as the other electrode. Also, a transistor RTr is configured with the region of the semiconductor 231 overlapping the conductor 222 as a gate, the region of the insulator 215 overlapping the conductor 222 as a gate insulating film, the region of the semiconductor 232 overlapping the conductor 222 as a channel formation region, the region of the insulator 216 overlapping the conductor 222 as a gate insulating film, and the region of the conductor 223 overlapping the conductor 222 as a back gate. Further, a transistor WTr is configured with the conductor 221 as a gate, the insulator 213 overlapping the conductor 221 as a gate insulating film, and the region of the semiconductor 231 overlapping the conductor 221 as a channel formation region.

[0296] Note that insulators, conductors, semiconductors, etc. disclosed in this specification and the like can be formed by a PVD (Physical Vapor Deposition) method or a CVD method. Examples of the PVD method include a sputtering method, a resistance heating evaporation method, an electron beam evaporation method, a PLD method, etc. Examples of the CVD method include a plasma CVD method and a thermal CVD method. In particular, examples of the thermal CVD method include an MOCVD method and an ALD method.

[0297] Since the thermal CVD method is a film-forming method that does not use plasma, it has the advantage that defects are not generated due to plasma damage. In the thermal CVD method, a source gas and an oxidizing agent may be simultaneously introduced into the chamber, the inside of the chamber may be under atmospheric pressure or reduced pressure, and the reaction may be carried out near or on the substrate to deposit a film on the substrate.

[0298] Also, in the ALD method, the inside of the chamber may be under atmospheric pressure or reduced pressure, and source gases for the reaction may be sequentially introduced into the chamber, and film formation may be carried out by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced simultaneously with or after the first source gas so that the plurality of types of source gases do not mix, and the second source gas is introduced. When an inert gas is introduced simultaneously, the inert gas serves as a carrier gas, and an inert gas may also be introduced simultaneously when the second source gas is introduced. Alternatively, after discharging the first source gas by evacuation instead of introducing an inert gas, the second source gas may be introduced. The first source gas adsorbs on the surface of the substrate to form a first thin layer, and reacts with the second source gas introduced later, and the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is reached while controlling the gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, and it is suitable for manufacturing fine FETs.

[0299] Thermal CVD methods such as MOCVD and ALD can form various films such as the metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. Also, not limited to these combinations, triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0300] For example, when forming a hafnium oxide film by a film-forming apparatus using ALD, two types of gases, a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH3)2]4)) and ozone (O3) as an oxidizing agent, are used. Also, as other materials, there are tetrakis(ethylmethylamide)hafnium and the like.

[0301] For example, when forming an aluminum oxide film by a film-forming apparatus using ALD, two types of gases, a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)) and H2O as an oxidizing agent, are used. Also, as other materials, there are tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

[0302] For example, when forming a silicon oxide film by a film-forming apparatus using ALD, hexachlorodisilane is adsorbed on the film-forming surface, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed substance.

[0303] For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF6 gas and H2 gas are sequentially and repeatedly introduced to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0304] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, and then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer. Further, thereafter, Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, a mixed oxide layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed using these gases. Note that H2O gas obtained by bubbling water with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(CH3)2 gas may be used.

[0305] <Configuration example of layer 40> Above the insulator 117, the insulator 382 and the insulator 384 are sequentially stacked and provided (see FIG. 13 or FIG. 14). Further, a conductor 386 is formed on the insulator 382 and the insulator 384. The conductor 386 has a function as a plug or a wiring. Note that the conductor 386 can be provided using the same material as the conductor 328 and the conductor 330.

[0306] On the insulator 384, the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are sequentially stacked and provided. Any one of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a material that is barrier against oxygen and hydrogen.

[0307] For example, for the insulator 510 and the insulator 514, it is preferable to use a film having a barrier property that prevents hydrogen and impurities from diffusing into the region where the transistor 500 is provided from, for example, the region where the substrate 311 or the transistor 300 is provided. Therefore, the same material as that of the insulator 324 can be used.

[0308] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor device having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor device may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0309] Further, as a film having a barrier property against hydrogen, for example, for the insulator 510 and the insulator 514, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0310] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable to be used as a protective film for the transistor 500.

[0311] Further, for example, for the insulator 512 and the insulator 516, the same material as that of the insulator 320 can be used. In addition, by using a material having a relatively low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 512 and the insulator 516, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0312] In addition, a conductor 518, a conductor (conductor 503) that constitutes the transistor 500, etc. are embedded in the insulators 510, 512, 514, and 516. Note that the conductor 518 has a function as a plug connected to the capacitor element 600 or a wiring. The conductor 518 can be provided using the same material as the conductors 328 and 330.

[0313] In particular, the conductor 518 in the region in contact with the insulators 510 and 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0314] A transistor 500 is provided above the insulator 516.

[0315] As shown in FIGS. 15A and 15B, the transistor 500 includes a conductor 503 disposed so as to be embedded in the insulators 514 and 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed by overlapping between the conductors 542a and 542b, a conductor 560 disposed in the opening, an insulator 550 disposed between the oxide 530b, the conductors 542a, 542b, and the insulator 580 and the conductor 560, and an oxide 530c disposed between the oxide 530b, the conductors 542a, 542b, and the insulator 580 and the insulator 550.

[0316] Also, as shown in FIGS. 15A and 15B, it is preferable that an insulator 544 is disposed between the oxides 530a, 530b, the conductors 542a, 542b, and the insulator 580. Also, as shown in FIGS. 15A and 15B, the conductor 560 preferably has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 15A and 15B, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550.

[0317] Note that hereinafter, the oxides 530a, 530b, and 530c may be collectively referred to as the oxide 530. Also, the conductors 542a and 542b may be collectively referred to as the conductor 542.

[0318] Note that in the transistor 500, a configuration in which three layers of the oxides 530a, 530b, and 530c are laminated in a region where a channel is formed and in its vicinity is shown, but the present invention is not limited thereto. For example, a single layer of the oxide 530b, a two-layer structure of the oxides 530b and 530a, a two-layer structure of the oxides 530b and 530c, or a laminated structure of four or more layers may be provided. Also, in the transistor 500, the conductor 560 is shown as a two-layer laminated structure, but the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a laminated structure of three or more layers. Also, the transistor 500 shown in FIGS. 14, 15A, and 15B is an example and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and driving method.

[0319] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or the drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-alignedly selected with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing an alignment margin, and the occupied area of the transistor 500 can be reduced. Thereby, miniaturization and high integration of the memory device can be achieved.

[0320] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductors 542a and 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560, the conductor 542a, and the conductor 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be obtained.

[0321] The conductor 560 may function as the first gate electrode. Also, the conductor 503 may function as the second gate electrode. In that case, the Vth of the transistor 500 can be controlled by independently changing the potential applied to the conductor 503 without linking it to the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the Vth of the transistor 500 can be made greater than 0V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0322] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Thereby, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, the structure of the transistor that electrically surrounds the channel formation region by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0323] Also, in this specification and the like, the S-channel structure has the feature that the side surfaces and peripheries of the oxide 530 in contact with the conductors 542a and 542b that function as source and drain electrodes are of the same I-type as the channel formation region. Further, since the side surfaces and peripheries of the oxide 530 in contact with the conductors 542a and 542b are in contact with the insulator 544, they can be of the I-type similar to the channel formation region. In this specification and the like, the I-type can be treated in the same manner as the high-purity intrinsic type described later. Also, the S-channel structure disclosed in this specification and the like is different from the Fin-type structure and the planar-type structure. By adopting the S-channel structure, the resistance to the short-channel effect can be enhanced, in other words, a transistor in which the short-channel effect is less likely to occur can be obtained.

[0324] Also, the conductor 503 has the same configuration as the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.

[0325] The insulators 520, 522, 524, and 550 function as gate insulating films.

[0326] Here, as the insulator 524 in contact with the oxide 530, it is preferable to use an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved.

[0327] Specifically, as the insulator having an excess oxygen region, it is preferable to use an oxide material in which some oxygen desorbs upon heating. The oxide that desorbs oxygen upon heating means that in TDS analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0328] Also, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate).

[0329] Since the insulator 522 has a function of suppressing the diffusion of oxygen and impurities, the oxygen possessed by the oxide 530 does not diffuse to the insulator 520 side, which is preferable. Also, it is possible to suppress the reaction of the conductor 503 with the oxygen possessed by the insulator 524 and the oxide 530.

[0330] The insulator 522 preferably uses a single layer or a laminate of insulators including, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0331] In particular, it is preferable to use an insulator containing one or both of the oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to permeate). As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0332] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. The above insulators may be laminated with silicon oxide, silicon oxynitride, or silicon nitride and used.

[0333] Also, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Also, by combining the insulator of the high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0334] Note that the insulator 520, the insulator 522, and the insulator 524 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to a structure composed of the same material, and a laminated structure composed of different materials may also be used.

[0335] For the transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, tin, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Also, an In-Ga oxide or an In-Zn oxide may be used as the oxide 530.

[0336] Note that the formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method, an ALD method, or a CVD method such as an MOCVD method. The metal oxide that functions as an oxide semiconductor will be described in other embodiments.

[0337] Also, for the transistor 500, it is preferable to use a metal oxide with a low carrier density. When reducing the carrier density of the metal oxide, the impurity concentration in the metal oxide may be lowered and the density of defect levels may be lowered. In this specification, etc., a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0338] In particular, hydrogen contained in a metal oxide may react with oxygen bonded to a metal atom to form water, thereby forming oxygen vacancies in the metal oxide. When the channel formation region in the metal oxide contains oxygen vacancies, the transistor may exhibit normally-on characteristics. Furthermore, a defect in which hydrogen enters an oxygen vacancy may function as a donor, and electrons as carriers may be generated. Also, a part of hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have normally-on characteristics.

[0339] A defect in which hydrogen enters an oxygen vacancy may function as a donor of the metal oxide. However, it is difficult to quantitatively evaluate such a defect. Therefore, in a metal oxide, it may be evaluated by carrier density instead of donor density. Thus, in this specification and the like, as a parameter of the metal oxide, carrier density assuming a state where no electric field is applied may be used instead of donor density. That is, the "carrier density" described in this specification and the like may be able to be paraphrased as "donor density".

[0340] Therefore, when using a metal oxide for the oxide 530, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 less than, preferably less than 1×10 19 atoms / cm 3 less than, more preferably less than 5×10 18 atoms / cm 3 less than, even more preferably less than 1×10 18 atoms / cm 3 less than. By using a metal oxide with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0341] In addition, when a metal oxide is used for the oxide 530, the carrier density of the metal oxide in the channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 even more preferably less than 1×10 16 cm -3 even more preferably less than 1×10 13 cm -3 even more preferably less than 1×10 12 cm -3 even more preferably less than 1×10 -9 cm -3 The lower limit of the carrier density of the metal oxide in the channel formation region is not particularly limited, but for example, it can be 1×10

[0342] In addition, when a metal oxide is used for the oxide 530, when the conductor 542 (conductor 542a and conductor 542b) is in contact with the oxide 530, oxygen in the oxide 530 may diffuse into the conductor 542 and the conductor 542 may be oxidized. When the conductor 542 is oxidized, the probability that the conductivity of the conductor 542 decreases is high. Note that the diffusion of oxygen in the oxide 530 into the conductor 542 can be rephrased as the conductor 542 absorbing oxygen in the oxide 530.

[0343] In addition, when oxygen in the oxide 530 diffuses into the conductor 542 (conductor 542a and conductor 542b), a heterolayer may be formed between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b. Since the heterolayer contains more oxygen than the conductor 542, it is presumed that the heterolayer has insulating properties. At this time, the three-layer structure of the conductor 542, the heterolayer, and the oxide 530b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly composed of the MIS structure.

[0344] Note that the different layers are not limited to being formed between the conductor 542 and the oxide 530b. For example, the different layers may be formed between the conductor 542 and the oxide 530c, or may be formed between the conductor 542 and the oxide 530b and between the conductor 542 and the oxide 530c.

[0345] In addition, as the metal oxide that functions as the channel formation region in the oxide 530, it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0346] In addition, the semiconductor material that can be used for the oxide 530 is not limited to the above-mentioned metal oxide. As the oxide 530, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer-like substance that functions as a semiconductor (also referred to as an atomic layer substance, a two-dimensional material, etc.) as the semiconductor material. In particular, it is suitable to use a layer-like substance that functions as a semiconductor as the semiconductor material.

[0347] Here, in this specification and the like, the layer-like substance is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer-like substance has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0348] Examples of the layer material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for the elements belonging to Group 16 and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0349] As the oxide 530, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenides applicable as the oxide 530 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0350] By having the oxide 530a under the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b. Also, by having the oxide 530c on the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b.

[0351] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a. Further, the oxide 530c can use a metal oxide that can be used for the oxide 530a or the oxide 530b.

[0352] Further, it is preferable that the energy of the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinities of the oxide 530a and the oxide 530c are smaller than the electron affinity of the oxide 530b.

[0353] Here, at the junction of the oxide 530a, the oxide 530b, and the oxide 530c, the energy level of the lower end of the conduction band changes smoothly. In other words, the energy level of the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c can also be said to change continuously or be continuously joined. To achieve this, it is advisable to reduce the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c.

[0354] Specifically, by having the oxide 530a, the oxide 530b, and the oxide 530c have a common element (as the main component) other than oxygen, a mixed layer with a low density of defect levels can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is preferable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a and the oxide 530c.

[0355] At this time, the main path of carriers becomes the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the density of defect levels at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0356] On the oxide 530b, conductors 542 (conductor 542a and conductor 542b) that function as a source electrode and a drain electrode are provided. As the conductor 542, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, an alloy containing the above-described metal elements as components, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0357] Also, as shown in FIG. 15A, regions 543 (regions 543a and 543b) may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542 and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Further, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0358] By providing the conductor 542 so as to be in contact with the oxide 530, the oxygen concentration in region 543 may be reduced. Further, a metal compound layer containing the metal contained in the conductor 542 and the components of the oxide 530 may be formed in region 543. In such a case, the carrier density in region 543 increases, and region 543 becomes a low-resistance region.

[0359] The insulator 544 is provided so as to cover the conductor 542 and suppresses the oxidation of the conductor 542. At this time, the insulator 544 covers the side surfaces of the oxide 530 and the insulator 524 and is provided so as to be in contact with the insulator 522. Alternatively, the insulator 544 may not be in contact with the insulator 522, and the insulator 524 may be provided between the insulator 522 and the insulator 544. In that case, the insulator 544 covers the side surface of the oxide 530 and is provided so as to be in contact with the insulator 524.

[0360] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. Further, silicon nitride may be used as the insulator 544.

[0361] In particular, as the insulator 544, it is preferable to use an insulator containing one or both of aluminum and hafnium oxides, such as aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in the heat treatment in a later process. Note that when the conductor 542 is a material having oxidation resistance or a material whose conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component and may be appropriately designed according to the required transistor characteristics.

[0362] The insulator 550 functions as a gate insulating film. The insulator 550 is preferably disposed in contact with the inside (upper surface and side surfaces) of the oxide 530c. The insulator 550 is preferably formed using an insulator that releases oxygen upon heating. For example, in TDS analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower.

[0363] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0364] By providing an insulator that releases oxygen upon heating as insulator 550 in contact with the upper surface of oxide 530c, oxygen can be effectively supplied from insulator 550, through oxide 530c, to the channel formation region of oxide 530b. Also, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 550 is reduced. The film thickness of insulator 550 is preferably 1 nm or more and 20 nm or less.

[0365] Further, in order to efficiently supply the excess oxygen possessed by insulator 550 to oxide 530, a metal oxide may be provided between insulator 550 and conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from insulator 550 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 550 to conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to oxide 530 can be suppressed. Also, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0366] Conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 15A and 15B, but it may also have a single-layer structure or a laminated structure of three or more layers.

[0367] For conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By conductor 560a having a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of conductor 560b by the oxygen contained in insulator 550 and a decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0368] In addition, the conductor 560b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0369] The insulator 580 is provided on the conductor 542 via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later process.

[0370] Also, by providing the insulator 580 that releases oxygen upon heating in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0371] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. Thereby, the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0372] When miniaturizing a memory device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the film thickness of the conductor 560 is increased, the conductor 560 can have a shape with a high aspect ratio. In the present embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, it can be formed without collapsing the conductor 560 during the process.

[0373] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By forming the insulator 574 by sputtering, an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0374] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0375] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film with a thickness of 0.5 nm or more and 3.0 nm or less. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0376] Also, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. Similar to the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0377] Further, conductors 540a and 540b are disposed in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductors 540a and 540b are provided to face each other with conductor 560 interposed therebetween. Conductors 540a and 540b have the same configuration as conductors 546 and 548 described later.

[0378] An insulator 582 is provided on insulator 581. It is preferable to use a material having barrier properties against oxygen and hydrogen for insulator 582. Therefore, the same material as insulator 514 can be used for insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for insulator 582.

[0379] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent the entry of impurities such as hydrogen and moisture into transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting transistor 500. Therefore, it is suitable for use as a protective film for transistor 500.

[0380] An insulator 586 is provided on insulator 582. The same material as insulator 320 can be used for insulator 586. Also, by using a material having a relatively low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used for insulator 586.

[0381] Further, conductors 546, conductors 548, etc. are embedded in insulator 520, insulator 522, insulator 544, insulator 580, insulator 574, insulator 581, insulator 582, and insulator 586.

[0382] The conductors 546 and 548 function as plugs that connect to the capacitor element 600 and the transistor 500, or as wirings. The conductors 546 and 548 can be provided using the same materials as the conductors 328 and 330.

[0383] Subsequently, a capacitor element 600 is provided above the transistor 500. The capacitor element 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0384] Also, a conductor 612 may be provided on the conductors 546 and 548. The conductor 612 functions as a plug that connects to the transistor 500, or as a wiring. The conductor 610 functions as an electrode of the capacitor element 600. Note that the conductors 612 and 610 can be formed simultaneously.

[0385] For the conductors 612 and 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) having the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be applied.

[0386] In FIG. 14, the conductors 612 and 610 are shown as a single-layer structure, but the present invention is not limited to this configuration, and a laminated structure of two or more layers may be used. For example, between a conductor having barrier properties and a conductor having high conductivity, a conductor having barrier properties and a conductor having high adhesiveness to the conductor having high conductivity may be formed.

[0387] The conductor 620 is provided so as to overlap with the conductor 610 via the insulator 630. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Also, when forming simultaneously with other structures such as conductors, Cu (copper), Al (aluminum), or the like, which are low-resistance metal materials, may be used.

[0388] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be provided using the same material as the insulator 320. Also, the insulator 650 may function as a planarization film that covers the uneven shape below it.

[0389] By using this structure, in a memory device having an OS transistor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, an OS transistor with a large on-current can be provided. Alternatively, an OS transistor with a small off-current can be provided. Alternatively, in a memory device having an OS transistor, miniaturization or high integration can be achieved.

[0390] <Structural example of a transistor> Note that the transistor 500 shown in this embodiment is not limited to the above structure. Hereinafter, structural examples that can be used for the transistor 500 will be described.

[0391] <Structural example 1 of a transistor> A structural example of the transistor 510A will be described with reference to FIGS. 16A, 16B, and 16C. FIG. 16A is a top view of the transistor 510A. FIG. 16B is a cross-sectional view of the portion indicated by the dashed line L1 - L2 in FIG. 16A. FIG. 16C is a cross-sectional view of the portion indicated by the dashed line W1 - W2 in FIG. 16A. In the top view of FIG. 16A, some elements are omitted for clarity of the drawing.

[0392] In FIGS. 16A, 16B, and 16C, transistor 510A, insulators 511, 512, 514, 516, 580, 582, and 584 that function as interlayer films are shown. Also shown are conductors 546 (conductor 546a and conductor 546b) that are electrically connected to transistor 510A and function as contact plugs, and conductor 503 that functions as wiring.

[0393] Transistor 510A includes conductors 560 (conductor 560a and conductor 560b) that function as a first gate electrode, conductors 505 (conductor 505a and conductor 505b) that function as a second gate electrode, insulator 550 that functions as a first gate insulating film, insulators 521, 522, and 524 that function as a second gate insulating film, oxides 530 (oxide 530a, oxide 530b, and oxide 530c) having regions where channels are formed, conductor 542a that functions as one of a source or a drain, conductor 542b that functions as the other of the source or the drain, and insulator 545.

[0394] Also, as shown in FIG. 16B, in transistor 510A, oxide 530c, insulator 550, and conductor 560 are disposed via insulator 545 within an opening provided in insulator 580. Also, oxide 530c, insulator 550, and conductor 560 are disposed between conductor 542a and conductor 542b.

[0395] Insulators 511 and 512 function as interlayer films.

[0396] As the interlayer film, insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used in a single layer or as a laminate. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulators and used.

[0397] For example, the insulator 511 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, it is preferable to use an insulating material for the insulator 511 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate). Further, for example, aluminum oxide, silicon nitride, etc. may be used as the insulator 511. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side rather than through the insulator 511.

[0398] For example, the insulator 512 preferably has a lower dielectric constant than the insulator 511. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0399] The conductor 503 is formed to be embedded in the insulator 512. Here, the height of the upper surface of the conductor 503 and the height of the upper surface of the insulator 512 can be made approximately the same. Although the conductor 503 is shown as a single-layer structure, the present invention is not limited thereto. For example, the conductor 503 may have a multi-layer film structure of two or more layers. Note that it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503.

[0400] In the transistor 510A, the conductor 560 may function as a first gate electrode. Also, the conductor 505 may function as a second gate electrode. In that case, by independently changing the potential applied to the conductor 505 without linking it to the potential applied to the conductor 560, the threshold voltage of the transistor 510A can be controlled. In particular, by applying a negative potential to the conductor 505, the threshold voltage of the transistor 510A can be made greater than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 505 can make the drain current smaller when the potential applied to the conductor 560 is 0 V than when no potential is applied.

[0401] Also, for example, by providing the conductor 505 and the conductor 560 in a superimposed manner, when a potential is applied to the conductor 560 and the conductor 505, the electric field generated from the conductor 560 and the electric field generated from the conductor 505 are connected, and the channel formation region formed in the oxide 530 can be covered.

[0402] That is, the channel formation region can be electrically surrounded by the electric field of the conductor 560 having the function as the first gate electrode and the electric field of the conductor 505 having the function as the second gate electrode. That is, similar to the transistor 500 described above, it has an S-channel structure.

[0403] Insulators 514 and 516 function as interlayer films in the same manner as insulator 511 or insulator 512. For example, insulator 514 preferably functions as a barrier film that suppresses impurities such as water or hydrogen from entering transistor 510A from the substrate side. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen and water from the substrate side to the transistor 510A side through insulator 514. Also, for example, insulator 516 preferably has a lower dielectric constant than insulator 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0404] Conductor 505 that functions as the second gate has conductor 505a formed in contact with the inner wall of the opening of insulator 514 and insulator 516, and conductor 505b is further formed inside. Here, the height of the upper surfaces of conductor 505a and conductor 505b can be made approximately the same as the height of the upper surface of insulator 516. Note that in transistor 510A, a configuration in which conductor 505a and conductor 505b are laminated is shown, but the present invention is not limited to this. For example, conductor 505 may be provided in a single-layer or a laminated structure of three or more layers.

[0405] Here, for conductor 505a, it is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Note that in this specification and the like, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0406] For example, when conductor 505a has a function of suppressing the diffusion of oxygen, it is possible to suppress conductor 505b from being oxidized and the conductivity from decreasing.

[0407] Also, when the conductor 505 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 505b. In that case, the conductor 503 does not necessarily have to be provided. Although the conductor 505b is illustrated as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the above-mentioned conductive material.

[0408] The insulators 521, 522, and 524 have a function as a second gate insulating film.

[0409] Also, the insulator 522 preferably has a barrier property. By having the barrier property, the insulator 522 functions as a layer that suppresses the intrusion of impurities such as hydrogen from the peripheral portion of the transistor 510A into the transistor 510A.

[0410] For the insulator 522, it is preferable to use, for example, a single layer or a laminate of an insulator containing aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxynitride containing aluminum and hafnium, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0411] Also, the insulator 521 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 521 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0412] In FIGS. 16B and 16C, a three-layer stacked structure is shown as the second gate insulating film, but a stacked structure of two layers or less or four layers or more may be used. In that case, it is not limited to a stacked structure made of the same material, and a stacked structure made of different materials may be used.

[0413] The oxide 530 having a region that functions as a channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. By having the oxide 530a under the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a into the oxide 530b can be suppressed. Also, by having the oxide 530c on the oxide 530b, diffusion of impurities from a structure formed above the oxide 530c into the oxide 530b can be suppressed. As the oxide 530, an oxide semiconductor which is one of the metal oxides described above can be used.

[0414] Note that the oxide 530c is preferably provided in an opening provided in the insulator 580 via the insulator 545. When the insulator 545 has a barrier property, diffusion of impurities from the insulator 580 into the oxide 530 can be suppressed.

[0415] One side of the conductor 542 functions as a source electrode and the other side functions as a drain electrode.

[0416] As the conductor 542a and the conductor 542b, metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys mainly composed of these can be used. In particular, metal nitride films such as tantalum nitride are preferable because they have a barrier property against hydrogen or oxygen and high oxidation resistance.

[0417] In addition, although a single-layer structure was shown in Fig. 16B, a laminated structure of two or more layers may also be used. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may also be used.

[0418] In addition, there is a three-layer structure in which a titanium film or a titanium nitride film is provided, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film is provided, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon, and the like. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0419] In addition, a barrier layer may be provided on the conductor 542. The barrier layer is preferably made of a material having barrier properties against oxygen or hydrogen. With this configuration, oxidation of the conductor 542 can be suppressed when the insulator 545 is formed.

[0420] For the barrier layer, for example, a metal oxide can be used. In particular, it is preferable to use an insulating film having barrier properties against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide. Also, silicon nitride formed by CVD may be used.

[0421] By having the barrier layer, the range of material selection for the conductor 542 can be widened. For example, for the conductor 542, a material with low oxidation resistance but high conductivity, such as tungsten or aluminum, can be used. Also, for example, a conductor that is easy to film or process can be used.

[0422] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably provided in an opening provided in the insulator 580 via the oxide 530c and the insulator 545.

[0423] As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. In that case, the insulator 550 may have a laminated structure, similar to the second gate insulating film. By forming an insulator functioning as a gate insulating film into a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a laminated structure that is thermally stable and has a high relative dielectric constant can be formed.

[0424] The conductor 560 that functions as a first gate electrode has a conductor 560a and a conductor 560b on the conductor 560a. It is preferable to use a conductive material for the conductor 560a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms, similar to the conductor 505a. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0425] Since the conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

[0426] As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, an oxide semiconductor that can be used as the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0427] It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 560b. Also, since the conductor 560 functions as a wiring, it is preferable to use a conductor with high conductivity for the conductor 560b. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductor 560b may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material may be used.

[0428] An insulator 545 is disposed between the insulator 580 and the transistor 510A. The insulator 545 is preferably made of an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can also be used.

[0429] By having the insulator 545, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 to the oxide 530b through the oxide 530c and the insulator 550. Also, it is possible to suppress the oxidation of the conductor 560 by the excess oxygen contained in the insulator 580.

[0430] The insulator 580, the insulator 582, and the insulator 584 function as interlayer films.

[0431] Similar to the insulator 514, the insulator 582 preferably functions as a barrier insulating film that suppresses the entry of impurities such as water or hydrogen from the outside into the transistor 510A.

[0432] Also, similar to the insulator 516, it is preferable that the insulator 580 and the insulator 584 have a lower dielectric constant than the insulator 582. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0433] Also, the transistor 510A may be electrically connected to other structures via plugs and wirings such as the conductor 546 embedded in the insulator 580, the insulator 582, and the insulator 584.

[0434] Also, as the material of the conductor 546, similar to the conductor 505, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used alone or in a laminated form. For example, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0435] For example, as the conductor 546, by using a laminated structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity, diffusion of impurities from the outside can be suppressed while maintaining the conductivity as a wiring.

[0436] By having the above structure, an OS transistor with a large on-current can be provided. Alternatively, an OS transistor with a small off-current can be provided. Alternatively, in a memory device having an OS transistor, fluctuations in electrical characteristics can be suppressed and reliability can be improved.

[0437] <Example Structure 2 of Transistor> A structural example of the transistor 510B will be described with reference to FIGS. 17A, 17B, and 17C. FIG. 17A is a top view of the transistor 510B. FIG. 17B is a cross-sectional view of the portion indicated by the dashed line L1 - L2 in FIG. 17A. FIG. 17C is a cross-sectional view of the portion indicated by the dashed line W1 - W2 in FIG. 17A. In the top view of FIG. 17A, some elements are omitted for clarity of the drawing.

[0438] Transistor 510B is a modified example of transistor 510A. Therefore, to avoid repeating the description, mainly the differences from the above transistor will be described.

[0439] In transistor 510A, a part of insulator 545 is provided within an opening provided in insulator 580 and is provided so as to cover the side surface of conductor 560. On the other hand, in transistor 510B, an opening is formed by removing a part of insulator 580 and insulator 545.

[0440] Also, an insulating body 576 (insulating body 576a and insulating body 576b) having a barrier property may be disposed between conductor 546 and insulating body 580. By providing insulating body 576, it is possible to suppress the reaction of oxygen in insulating body 580 with conductor 546 and the oxidation of conductor 546.

[0441] When using an oxide semiconductor as oxide 530, it preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for oxide 530a, the atomic ratio of element M in the constituent elements is preferably larger than the atomic ratio of element M in the constituent elements in the metal oxide used for oxide 530b. Also, in the metal oxide used for oxide 530a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Further, in the metal oxide used for oxide 530b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for oxide 530a. Also, oxide 530c can use a metal oxide that can be used for oxide 530a or oxide 530b.

[0442] Oxide 530a, oxide 530b, and oxide 530c preferably have crystallinity, and in particular, it is preferable to use CAAC-OS. Oxides having crystallinity such as CAAC-OS have few impurities and defects (such as oxygen deficiencies) and have a dense structure with high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from oxide 530b by the source electrode or the drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from oxide 530b can be reduced, so transistor 510B is stable against a high temperature (or thermal budget) in the manufacturing process.

[0443] Note that one or both of oxide 530a and oxide 530c may be omitted. Oxide 530 may be a single layer of oxide 530b. When oxide 530 is a laminate of oxide 530a, oxide 530b, and oxide 530c, it is preferable that the energy of the lower end of the conduction band of oxide 530a and oxide 530c is higher than the energy of the lower end of the conduction band of oxide 530b. In other words, it is preferable that the electron affinity of oxide 530a and oxide 530c is smaller than the electron affinity of oxide 530b. In this case, it is preferable to use a metal oxide that can be used for oxide 530a for oxide 530c. Specifically, in the metal oxide used for oxide 530c, it is preferable that the atomic ratio of element M in the constituent elements is larger than the atomic ratio of element M in the constituent elements in the metal oxide used for oxide 530b. Also, in the metal oxide used for oxide 530c, it is preferable that the atomic ratio of element M to In is larger than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Further, in the metal oxide used for oxide 530b, it is preferable that the atomic ratio of In to element M is larger than the atomic ratio of In to element M in the metal oxide used for oxide 530c.

[0444] Here, the energy level of the conduction band minimum changes gradually at the junction of the oxide 530a, the oxide 530b, and the oxide 530c. In other words, it can be said that the energy level of the conduction band minimum at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c.

[0445] Specifically, the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element other than oxygen (as a main component), so that a mixed layer with a low defect level density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like. The oxide 530c may also have a laminated structure. For example, a laminated structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a laminated structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide can be used. In other words, a laminated structure of an In-Ga-Zn oxide and an oxide not containing In may be used as the oxide 530c.

[0446] Specifically, as the oxide 530a, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] may be used. As the oxide 530b, a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] may be used. As the oxide 530c, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], Ga:Zn = 2:1 [atomic ratio], or Ga:Zn = 2:5 [atomic ratio] may be used. Specific examples of the case where the oxide 530c has a laminated structure include a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and Ga:Zn = 2:1 [atomic ratio], a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and Ga:Zn = 2:5 [atomic ratio], a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and gallium oxide, etc.

[0447] At this time, the main path of carriers becomes the oxide 530b. By configuring the oxide 530a and the oxide 530c as described above, the density of defect energy levels at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be lowered. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 510B can obtain a high on-current and high frequency characteristics. When the oxide 530c has a laminated structure, in addition to the effect of lowering the density of defect energy levels at the interface between the oxide 530b and the oxide 530c described above, it is expected to suppress the diffusion of the constituent elements of the oxide 530c to the insulator 550 side. More specifically, since the oxide 530c has a laminated structure and an oxide containing no In is positioned above the laminated structure, the In that can diffuse to the insulator 550 side can be suppressed. Since the insulator 550 functions as a gate insulator, if In diffuses, the characteristics of the transistor deteriorate. Therefore, by forming the oxide 530c into a laminated structure, it is possible to provide a highly reliable memory device.

[0448] The oxide 530 preferably uses a metal oxide that functions as an oxide semiconductor. For example, as the metal oxide that forms the channel region of the oxide 530, those having a bandgap of 2 eV or more, preferably 2.5 eV or more are preferably used. By using a metal oxide with a large bandgap in this way, the off-current of the transistor can be reduced. By using such a transistor, a low-power consumption memory device can be provided.

[0449] <Example Structure 3 of Transistor> The structure example of the transistor 510C will be described with reference to FIGS. 18A and 18B. The transistor 510C is a modified example of the transistor 500. Therefore, in order to avoid repeating the description, mainly the differences from the above transistor will be described. Note that the configuration shown in FIGS. 18A and 18B can also be applied to other transistors included in the memory device according to one embodiment of the present invention, such as the transistor 300.

[0450] FIG. 18A is a cross-sectional view of the transistor 510C in the channel length direction, and FIG. 18B is a cross-sectional view of the transistor 510C in the channel width direction. The transistor 510C shown in FIGS. 18A and 18B is different from the transistor 500 shown in FIGS. 15A and 15B in that it has the insulators 402 and 404, and in that the insulator 550 is composed of the insulator 550a and the insulator 550b. Also, an insulator 551 is provided in contact with the side surface of the conductor 540a, an insulator 551 is provided in contact with the side surface of the conductor 540b, a conductor 572a is provided in contact with the upper surface of the conductor 542a, a conductor 532a is provided in contact with the upper surface of the region 543a, a conductor 572b is provided in contact with the upper surface of the conductor 542b, and a conductor 532b is provided in contact with the upper surface of the region 543b. These are different from the transistor 500 shown in FIGS. 15A and 15B. Further, it is different from the transistor 500 shown in FIGS. 15A and 15B in that it does not have the insulator 520 and the oxide 530c.

[0451] In the transistor 510C shown in FIGS. 18A and 18B, an insulator 402 is provided on an insulator 512. Further, an insulator 404 is provided on an insulator 574 and on the insulator 402.

[0452] In the transistor 510C shown in FIGS. 18A and 18B, insulators 514, 516, 522, 544, 580, and 574 are patterned, and the insulator 404 has a structure that covers them. That is, the insulator 404 is in contact with the upper surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the upper surface of the insulator 402, respectively. Thereby, the oxide 530 etc. are isolated from the outside by the insulator 404 and the insulator 402.

[0453] It is preferable that the insulators 402 and 404 have a high function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.) or water molecules. For example, it is preferable to use silicon nitride or silicon oxynitride, which are materials having high hydrogen barrier properties, as the insulators 402 and 404. Thereby, since the diffusion of hydrogen etc. into the oxide 530 can be suppressed, the deterioration of the characteristics of the transistor 510C can be suppressed. Therefore, in a memory device having an OS transistor, the reliability can be improved.

[0454] For the insulator 550a, silicon oxide, silicon oxynitride, etc. can be used, and for the insulator 550b, for example, hafnium oxide, etc. can be used. Thereby, the oxidation of the conductor 560 can be suppressed. Also, for the conductors 572a and 572b, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. can be used, and for the conductors 532a and 532b, for example, the metal oxide used for the oxide 530a can be used. Thereby, the oxidation of the conductors 542a and 542b can be suppressed.

[0455] Insulator 551 is provided in contact with insulator 581, insulator 404, insulator 574, insulator 580, and insulator 544. Insulator 551 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as insulator 551, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which is a material with high hydrogen barrier properties. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is suitable for use as insulator 551. By using a material with high hydrogen barrier properties as insulator 551, it is possible to suppress the diffusion of impurities such as water or hydrogen from insulator 580 etc. through conductor 540a and conductor 540b to oxide 530. Also, it is possible to suppress the absorption of oxygen contained in insulator 580 by conductor 540a and conductor 540b. As described above, the reliability of the memory device having the OS transistor can be enhanced.

[0456] <Structure Example 4 of Transistor> A structure example of transistor 510D will be described with reference to FIGS. 19A and 19B. Transistor 510D is a modified example of transistor 500. Therefore, in order to prevent repetition of the description, mainly the differences from the above transistor will be described. Note that the configuration shown in FIGS. 19A and 19B can also be applied to other transistors included in the memory device according to one embodiment of the present invention, such as transistor 300.

[0457] Figures 19A and 19B are modified examples of the transistor shown in Figures 15A and 15B. Figure 19A is a cross-sectional view of the transistor in the channel length direction, and Figure 19B is a cross-sectional view of the transistor in the channel width direction. The transistors shown in Figures 19A and 19B are different from the transistor 500 shown in Figures 15A and 15B in that they have insulators 402 and 404. Also, the insulators 551 are provided in contact with the side surfaces of the conductors 540a and 540b, which is different from the transistor 500 shown in Figures 15A and 15B. Further, they are different from the transistor 500 shown in Figures 15A and 15B in that they do not have the insulator 520. Furthermore, the oxide 530c has a two-layer structure of the oxide 530c1 and the oxide 530c2, which is different from the transistor shown in Figures 15A and 15B.

[0458] In the transistor 510D shown in Figures 19A and 19B, the insulator 402 is provided on the insulator 512. Also, the insulator 404 is provided on the insulator 574 and on the insulator 402.

[0459] In the transistor 510D shown in Figures 19A and 19B, the insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and the insulator 404 has a structure that covers them. That is, the insulator 404 is in contact with the upper surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the upper surface of the insulator 402, respectively. Thereby, the oxide 530 etc. are isolated from the outside by the insulators 404 and 402.

[0460] The insulators 402 and 404 preferably have a high function of suppressing the diffusion of hydrogen (e.g., at least one of a hydrogen atom, a hydrogen molecule, etc.) or water molecules. For example, as the insulators 402 and 404, it is preferable to use silicon nitride or silicon oxynitride, which are materials with high hydrogen barrier properties. Thereby, the diffusion of hydrogen or the like into the oxide 530 can be suppressed, so that the characteristics of the transistor 510D can be prevented from degrading. Therefore, in a memory device having an OS transistor, the reliability can be enhanced.

[0461] The insulator 551 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 551 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as the insulator 551, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which is a material with high hydrogen barrier properties. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is suitable for use as the insulator 551. By using a material with high hydrogen barrier properties as the insulator 551, the diffusion of impurities such as water or hydrogen from the insulator 580 or the like through the conductors 540a and 540b into the oxide 530 can be suppressed. Also, the absorption of oxygen contained in the insulator 580 by the conductors 540a and 540b can be suppressed. As described above, the reliability of a memory device having an OS transistor can be enhanced.

[0462] The oxide 530c1 is in contact with the upper surface of the insulator 522, the side surface of the insulator 524, the side surface of the oxide 530a, the upper surface and the side surface of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 is in contact with the insulator 550.

[0463] As the oxide 530c1, for example, an In-Zn oxide can be used. Further, as the oxide 530c2, the same material as the material that can be used for the oxide 530c when the oxide 530c has a single-layer structure can be used. For example, as the oxide 530c2, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, an atomic ratio of Ga:Zn = 2:1, or an atomic ratio of Ga:Zn = 2:5 can be used.

[0464] By forming the oxide 530c into a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-current of the transistor can be increased compared to the case where the oxide 530c has a single-layer structure. Therefore, the transistor can be, for example, a power MOS transistor. Note that the oxide 530c included in the transistors shown in FIGS. 15A and 15B can also be formed into a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0465] The transistors shown in FIGS. 19A and 19B can be applied to, for example, the transistor 500, the transistor 300, or both of them.

[0466] Note that the configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0467] (Embodiment 5) In this embodiment, an oxide semiconductor which is a kind of metal oxide will be described.

[0468] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Further, in addition to those, it is preferable that one or more selected from aluminum, gallium, yttrium, tin, etc. are contained. Also, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0469] <Classification of crystal structures> First, the classification of crystal structures in oxide semiconductors will be described with reference to Fig. 20A. Fig. 20A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

[0470] As shown in Fig. 20A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Also, CAAC, nc, and CAC (cloud - aligned composite) are included in "Crystalline". Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Also, single crystal and poly crystal are included in "Crystal".

[0471] Note that the structure within the thick frame shown in Fig. 20A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, this structure can be paraphrased as a structure that is energetically unstable "Amorphous" and is completely different from "Crystal".

[0472] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained from the grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 20B. Note that the GIXD method is also called the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained from the GIXD measurement shown in FIG. 20B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 20B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 20B is 500 nm.

[0473] In FIG. 20B, the horizontal axis is 2θ [deg.], and the vertical axis is intensity [a.u.]. As shown in FIG. 20B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected in the vicinity of 2θ = 31°. Note that, as shown in FIG. 20B, the peak in the vicinity of 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0474] Also, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 20C. FIG. 20C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 20C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0475] As shown in FIG. 20C, a plurality of spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0476] <<Structure of Oxide Semiconductor>> Note that when focusing on the crystal structure, an oxide semiconductor may be classified differently from that in FIG. 20A. For example, an oxide semiconductor can be divided into a single-crystalline oxide semiconductor and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystalline oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0477] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0478] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0479] Note that each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0480] In the In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0481] When a structural analysis is performed on the CAAC-OS film using, for example, an XRD apparatus, in the out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in the vicinity thereof. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0482] Also, for example, in the electron diffraction pattern of the CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0483] When observing the crystal region from the specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be an irregular hexagon. Also, in the above-mentioned strain, there may be lattice arrangements such as pentagons and heptagons. In CAAC-OS, even in the vicinity of the strain, no distinct grain boundaries can be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the strain of the lattice arrangement. This is presumably because CAAC-OS can tolerate strain due to the non-dense arrangement of oxygen atoms in the a-b plane direction and the change in the interatomic bond distance due to the substitution of metal atoms.

[0484] A crystal structure in which distinct grain boundaries are confirmed is called a so-called polycrystal. Grain boundaries serve as recombination centers, and there is a high possibility that carriers are captured, causing a decrease in the on-current of the transistor and a decrease in the field-effect mobility. Therefore, CAAC-OS in which no distinct grain boundaries are confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor. To form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0485] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is unlikely to occur. Also, since the crystallinity of the oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, it can also be said that CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (or thermal budgets) in the manufacturing process. Therefore, when CAAC-OS is used for the OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0486] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Further, nc-OS has no regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when performing structural analysis on an nc-OS film using an XRD apparatus, in an Out-of-plane XRD measurement using θ / 2θ scan, no peak indicating crystallinity is detected. Further, when performing electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam having a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam having a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0487] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity compared with nc-OS and CAAC-OS. Further, a-like OS has a higher hydrogen concentration in the film compared with nc-OS and CAAC-OS.

[0488] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that CAC-OS relates to the material constitution.

[0489] [CAC-OS] CAC-OS is, for example, a component of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0490] Furthermore, CAC-OS is a composite metal oxide having a structure in which the material is separated into a first region and a second region to form a mosaic state, and the first region is a structure distributed in the film (hereinafter also referred to as a cloud state). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0491] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0492] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the first region can be rephrased as a region mainly composed of In. The second region can be rephrased as a region mainly composed of Ga.

[0493] Note that there may be cases where no clear boundary can be observed between the above first region and the above second region.

[0494] For example, in CAC-OS in In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (first region) and the region mainly composed of Ga (second region) are unevenly distributed and have a mixed structure.

[0495] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, so that a switching function (on / off function) can be imparted to CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximally enhanced. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching operation can be realized.

[0496] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0497] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0498] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0499] For the transistor, it is preferable to use an oxide semiconductor with a low carrier density (more specifically, refer to Embodiment 4). When reducing the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be decreased, and the density of defect levels may be decreased. In this specification and the like, when the impurity concentration is low and the density of defect levels is low, it is referred to as highly pure intrinsic or substantially highly pure intrinsic. In some cases, an oxide semiconductor with a low carrier density is called a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0500] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0501] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap levels may become unstable.

[0502] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0503] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0504] In the oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon (concentration obtained by SIMS) near the interface with the oxide semiconductor are 2×10 18 atoms / cm3 Hereinafter, it is preferably 2×10 17 atoms / cm 3 or less.

[0505] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0506] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0507] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible (more specifically, refer to Embodiment 4).

[0508] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0509] Note that the configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments, etc.

[0510] (Embodiment 6) In this embodiment, an example of a semiconductor wafer on which a memory device or the like shown in the above embodiment is formed and an electronic component in which the memory device is incorporated are shown.

[0511] <Semiconductor wafer> First, an example of a semiconductor wafer on which a memory device or the like is formed will be described with reference to FIG. 29A.

[0512] The semiconductor wafer 4800 shown in FIG. 29A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that, on the upper surface of the wafer 4801, the portion where there is no circuit portion 4802 is a spacing 4803, which is a dicing region.

[0513] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. Further, thereafter, the surface of the wafer 4801 on the side opposite to the side where the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. By this process, warpage and the like of the wafer 4801 can be reduced, and miniaturization as a component can be achieved.

[0514] As the next process, a dicing process is performed. Dicing is performed along the scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by the dashed line. Note that the spacing 4803 is preferably provided such that a plurality of scribe lines SCL1 are parallel to facilitate the dicing process, a plurality of scribe lines SCL2 are parallel, and the scribe line SCL1 and the scribe line SCL2 are perpendicular.

[0515] By performing the dicing process, the chip 4800a as shown in FIG. 29B can be cut out from the semiconductor wafer 4800. The chip 4800a includes a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between adjacent circuit portions 4802 may be approximately the same length as the kerf of the scribe line SCL1 or the kerf of the scribe line SCL2.

[0516] Note that the shape of the element substrate according to one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 29A. For example, a rectangular semiconductor wafer may be used. The shape of the element substrate can be appropriately changed according to the manufacturing process of the element and the apparatus for manufacturing the element.

[0517] <Electronic component> Fig. 29C shows a perspective view of the electronic component 4700 and the substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in Fig. 29C has a chip 4800a inside a mold 4711. As the chip 4800a, a storage device or the like according to an aspect of the present invention can be used.

[0518] Fig. 29C omits a part to show the inside of the electronic component 4700. The electronic component 4700 has lands 4712 outside the mold 4711. The lands 4712 are electrically connected to electrode pads 4713, and the electrode pads 4713 are electrically connected to the chip 4800a by wires 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined, and each is electrically connected on the printed circuit board 4702 to complete the mounting substrate 4704.

[0519] Fig. 29D shows a perspective view of the electronic component 4730. The electronic component 4730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). On a package substrate 4732 (printed circuit board) of the electronic component 4730, an interposer 4731 is provided, and a semiconductor device 4735 and a plurality of storage devices 4710 are provided on the interposer 4731.

[0520] As the storage device 4710, for example, a chip 4800a, the storage device described in the above embodiment, a high bandwidth memory (HBM), or the like can be used. Further, as the semiconductor device 4735, integrated circuits such as a CPU, a GPU, an FPGA, and a storage device can be used. In this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

[0521] As the package substrate 4732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 4731, a silicon interposer, a resin interposer, or the like can be used.

[0522] The interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Further, the interposer 4731 has a function of electrically connecting an integrated circuit provided on the interposer 4731 to an electrode provided on the package substrate 4732. For these reasons, the interposer may be referred to as a "rewiring substrate" or an "intermediate substrate". Further, a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode. Also, in a silicon interposer, a TSV (Through Silicon Via) can be used as the through electrode.

[0523] It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wirings, which is difficult in a resin interposer.

[0524] In HBM, it is necessary to connect many wirings in order to realize a wide memory bandwidth. For this reason, fine and high-density wiring formation is required for the interposer on which HBM is mounted. Therefore, it is preferable to use a silicon interposer for the interposer on which HBM is mounted.

[0525] Also, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to a difference in the coefficient of thermal expansion between the integrated circuit and the interposer hardly occurs. Also, since the silicon interposer has high surface flatness, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer hardly occurs. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0526] Also, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 4730. When providing a heat sink, it is preferable to align the heights of the integrated circuits provided on the interposer 4731. For example, in the electronic component 4730 shown in the present embodiment, it is preferable to align the heights of the storage device 4710 and the semiconductor device 4735.

[0527] In order to mount the electronic component 4730 on another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. FIG. 29D shows an example in which the electrodes 4733 are formed of solder balls. By providing solder balls in a matrix pattern at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 4733 may be formed of conductive pins. By providing conductive pins in a matrix pattern at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0528] The electronic component 4730 can be mounted on another substrate using various mounting methods not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J - leaded package), or QFN (Quad Flat Non - leaded package) can be used.

[0529] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0530] (Embodiment 7) In the present embodiment, an application example of a storage device according to an aspect of the present invention will be described.

[0531] Generally, in semiconductor devices such as computers, various memory devices are used according to the application. Figure 30A shows various memory devices used in semiconductor devices by layer. The higher the memory device is located in the hierarchy, the faster the operating speed is required, and the lower the memory device is located in the hierarchy, the larger the memory capacity and the higher the recording density are required. In Figure 30A, from the top layer in order, it shows the memory that is mixed and mounted as a register in an arithmetic processing device such as a CPU, SRAM, DRAM, and 3D NAND memory.

[0532] The memory that is mixed and mounted as a register in an arithmetic processing device such as a CPU is used for temporarily storing calculation results and the like, so the access frequency from the arithmetic processing device is high. Therefore, a faster operating speed is required than the memory capacity. In addition, the register also has a function of holding the setting information of the arithmetic processing device and the like.

[0533] SRAM is used, for example, as a cache. The cache has a function of replicating and holding a part of the data held in the main memory. By replicating and holding the frequently used data in the cache, the access speed to the data can be increased. The memory capacity required for the cache is less than that of the main memory, but a faster operating speed is required than the main memory. In addition, the data rewritten in the cache is replicated and supplied to the main memory.

[0534] DRAM is used, for example, as the main memory. The main memory has a function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0535] 3D NAND memories are used, for example, in storage. Storage has the function of holding data that needs to be stored long-term, various programs used in arithmetic processing units, and the like. Therefore, storage is required to have a storage capacity larger than the operating speed and a high recording density. The recording density of the storage device used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0536] The storage device according to one aspect of the present invention has a high operating speed and can hold data for a long period of time. The storage device according to one aspect of the present invention can be suitably used as a storage device located in the boundary region 901 including both the layer where the cache is located and the layer where the main memory is located. Further, the storage device according to one aspect of the present invention can be suitably used as a storage device located in the boundary region 902 including both the layer where the main memory is located and the layer where the storage is located.

[0537] Further, the storage device according to one aspect of the present invention can be suitably used in both the layer where the main memory is located and the layer where the storage is located. Further, the storage device according to one aspect of the present invention can be suitably used in the layer where the cache is located. FIG. 30B shows the layers of various storage devices different from FIG. 30A.

[0538] In FIG. 30B, in order from the top layer, it shows the memory mixed as a register in an arithmetic processing unit such as a CPU, the SRAM used as a cache, and the 3D OS NAND memory. The storage device according to one aspect of the present invention can be used for the cache, the main memory, and the storage. When a high-speed memory of 1 GHz or more is required as the cache, the cache is mixed in an arithmetic processing unit such as a CPU.

[0539] Further, the storage device according to one aspect of the present invention may not be limited to the NAND type but may be the NOR type. Also, the NAND type and the NOR type may be used in combination.

[0540] The memory device according to one aspect of the present invention can be applied to, for example, memory devices of various electronic devices (such as information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game machines, etc.). It can also be used in image sensors, IoT (Internet of Things) terminal devices, healthcare, etc. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large-scale computers such as server systems.

[0541] An example of an electronic device having a memory device according to one aspect of the present invention will be described. FIGS. 31A to 31J and FIGS. 32A to 32E illustrate how the electronic component 4700 or the electronic component 4730 having the memory device is included in each electronic device.

[0542] [Mobile phone] The information terminal 5500 shown in FIG. 31A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0543] By applying the memory device according to one aspect of the present invention, the information terminal 5500 can hold temporary files (such as caches when using a web browser) generated during the execution of applications.

[0544] [Wearable terminal] Also, FIG. 31B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 has a housing 5901, a display unit 5902, operation switches 5903, 5904, a band 5905, etc.

[0545] Similar to the information terminal 5500 described above, the wearable terminal can hold temporary files generated during the execution of an application by applying the storage device according to one aspect of the present invention.

[0546] [Information terminal] Also, FIG. 31C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0547] Similar to the information terminal 5500 described above, the desktop information terminal 5300 can hold temporary files generated during the execution of an application by applying the storage device according to one aspect of the present invention.

[0548] In the above description, smartphones, wearable terminals, and desktop information terminals are illustrated in FIGS. 31A to 31C as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0549] [Household appliances] Also, FIG. 31D shows an electric refrigerator-freezer 5800 as an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0550] The storage device according to one aspect of the present invention can be applied to an electric refrigerator 5800. The electric refrigerator 5800 can transmit and receive information such as food stored in the electric refrigerator 5800 and the expiration date of the food to and from an information terminal or the like through the Internet or the like. The electric refrigerator 5800 can hold a temporary file generated when transmitting the information in the storage device.

[0551] In this example, an electric refrigerator is described as an electric appliance. Other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating and cooling appliance including an air conditioner, a washing machine, a dryer, and audio-visual equipment.

[0552] [Game machine] In addition, FIG. 31E shows a portable game machine 5200 which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display unit 5202, buttons 5203, and the like.

[0553] Furthermore, FIG. 31F shows a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. Note that the controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 31F, the controller 7522 can include a display unit for displaying game images, a touch panel, a stick, a rotary knob, a slide knob, etc., which serve as input interfaces other than buttons. Also, the controller 7522 is not limited to the shape shown in FIG. 31F, and the shape of the controller 7522 can be changed variously according to the game genre. For example, in a shooting game such as a first-person shooter (FPS), a controller shaped like a gun with a trigger as a button can be used. Also, for example, in a music game, a controller shaped like a musical instrument or a music device can be used. Furthermore, the stationary game machine can be configured to operate by a game player's gesture and / or voice, without using a controller, but instead equipped with a camera, a depth sensor, a microphone, etc.

[0554] In addition, the video of the game machine described above can be output by a display device such as a television set, a personal computer display, a game display, or a head-mounted display.

[0555] By applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, a low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so the influence of the heat on the circuit itself, the peripheral circuit, and the module can be minimized.

[0556] Furthermore, by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, it is possible to hold temporary files and the like necessary for calculations generated during the execution of the game.

[0557] Although a portable game machine is shown in FIG. 31E and a stationary game machine is shown in FIG. 31F as examples of game machines, the electronic device according to one aspect of the present invention is not limited thereto. Examples of the electronic device according to one aspect of the present invention include, for example, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), a pitching machine for batting practice installed in a sports facility, and the like.

[0558] [Mobile body] The storage device described in the above embodiment can be applied to a motor vehicle, which is a mobile body, and the periphery of the driver's seat of the motor vehicle.

[0559] FIG. 31G shows a motor vehicle 5700, which is an example of a mobile body.

[0560] Around the driver's seat of the motor vehicle 5700, there is an instrument panel that provides various information by displaying a speedometer, a tachometer, the driving distance, a fuel gauge, the gear state, the setting of the air conditioner, and the like. In addition, a display device for indicating those information may be provided around the driver's seat.

[0561] In particular, the display device can supplement the field of vision blocked by a pillar or the like and the blind spot of the driver's seat by projecting the video from an imaging device (not shown) provided in the motor vehicle 5700, thereby enhancing safety. That is, by displaying the image from the imaging device provided outside the motor vehicle 5700, the blind spot can be supplemented and safety can be enhanced.

[0562] Since the memory device described in the above embodiment can temporarily hold information, for example, it can be used to hold necessary temporary information in a system such as an automatic driving system of an automobile 5700, a road guidance system, or a danger prediction system. The display device may be configured to display temporary information such as road guidance and danger prediction. Further, it may be configured to hold the video of a driving recorder installed in the automobile 5700.

[0563] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include trains, monorails, ships, flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like.

[0564] [Camera] The memory device described in the above embodiment can be applied to a camera.

[0565] FIG. 31H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0566] By applying the memory device described in the above embodiment to the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to low power consumption, the influence on the circuit itself, the peripheral circuits, and the modules due to heat generation can be reduced.

[0567] [Video camera] The memory device described in the above embodiment can be applied to a video camera.

[0568] In FIG. 31I, a video camera 6300, which is an example of an imaging device, is illustrated. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The configuration may be such that the video on the display unit 6303 is switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0569] When recording the video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the memory device described above, the video camera 6300 can hold temporary files generated during encoding.

[0570] [ICD] The memory device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0571] FIG. 31J is a schematic cross-sectional view showing an example of an ICD. The ICD main body 5400 includes at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0572] The ICD main body 5400 is implanted into the body by surgery, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0573] The ICD main body 5400 has the function as a pacemaker and performs pacing on the heart when the heart rate deviates from the specified range. Also, when the heart rate is not improved by pacing (such as rapid ventricular tachycardia or ventricular fibrillation), treatment by electric shock is performed.

[0574] In order for the ICD main body 5400 to appropriately perform pacing and electric shock, it is necessary to constantly monitor the heart rate. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Also, the ICD main body 5400 can store data on the heart rate acquired by the sensor etc., the number of times and time of treatment by pacing, etc. in the electronic component 4700.

[0575] Also, power can be received by the antenna 5404, and the power is charged to the battery 5401. Also, by having a plurality of batteries in the ICD main body 5400, the safety can be increased. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.

[0576] Also, separately from the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals. For example, a system for monitoring heart activity may be configured so that physiological signals such as pulse, respiratory rate, heart rate, and body temperature can be confirmed by an external monitoring device.

[0577] [Expansion device for PC] The storage device described in the above embodiment can be applied to a computer such as a PC and an expansion device for an information terminal.

[0578] FIG. 32A shows an expansion device 6100 that can be carried and is externally attachable to a PC and equipped with a chip capable of storing information as an example of the expansion device. The expansion device 6100 can store information by the chip by being connected to the PC, for example, via a USB (Universal Serial Bus). Note that FIG. 32A illustrates the expansion device 6100 in a portable form, but the expansion device according to an aspect of the present invention is not limited thereto, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0579] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed in the housing 6101. A circuit for driving the storage device and the like described in the above embodiment is provided on the substrate 6104. For example, an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0580] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0581] FIG. 32B is a schematic diagram of the appearance of the SD card, and FIG. 32C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a writing circuit, a loader, a reading circuit, etc. provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.

[0582] By providing the electronic component 4700 also on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data of the electronic component 4700 can be read and written.

[0583] [SSD] The storage device described in the above embodiment can be applied to an SSD that can be attached to an electronic device such as an information terminal.

[0584] FIG. 32D is a schematic diagram of the appearance of the SSD, and FIG. 32E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. By providing the electronic component 4700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. A processor, an ECC circuit, etc. are incorporated in the controller chip 5156. Note that the circuit configurations of each of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a memory that functions as a work memory may also be provided in the controller chip 5156.

[0585] [Computer] The computer 5600 shown in FIG. 33A is an example of a large computer. A plurality of rack-mounted computers 5620 are stored in a rack 5610 in the computer 5600. Note that the computer 5600 may be referred to as a supercomputer.

[0586] The computer 5620 can have, for example, the configuration of the perspective view shown in FIG. 33B. In FIG. 33B, the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are respectively connected to the motherboard 5630.

[0587] The PC card 5621 shown in FIG. 33C is an example of a processing board equipped with a CPU, a GPU, a memory device, etc. The PC card 5621 has a board 5622. The board 5622 has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Although FIG. 33C shows semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, for those semiconductor devices, the descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below may be referred to.

[0588] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe, etc.

[0589] The connection terminals 5623, 5624, and 5625 can be used as interfaces for, for example, supplying power to and inputting signals to the PC card 5621. Also, for example, they can be used as interfaces for outputting signals calculated by the PC card 5621. Examples of the respective standards of the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Also, when outputting video signals from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark), etc.

[0590] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminals into sockets (not shown) provided on the board 5622.

[0591] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, a CPU, etc. As the semiconductor device 5627, for example, the electronic component 4730 can be used.

[0592] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of the semiconductor device 5628 include a storage device, etc. As the semiconductor device 5628, for example, the electronic component 4700 can be used.

[0593] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0594] By using the semiconductor device according to one aspect of the present invention in the above various electronic devices, etc., miniaturization, high-speed operation, or low power consumption of the electronic device can be achieved. Also, since the semiconductor device according to one aspect of the present invention consumes little power, heat generation from the circuit can be reduced. Therefore, the adverse effects of such heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Also, by using the semiconductor device according to one aspect of the present invention, an electronic device with stable operation even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be enhanced.

[0595] Next, a configuration example of a computer system applicable to the computer 5600 will be described. FIG. 34 is a diagram for explaining a configuration example of the computer system 7000. The computer system 7000 is configured to include software and hardware. Note that the hardware included in the computer system may be referred to as an information processing apparatus.

[0596] Examples of the software constituting the computer system 7000 include an operating system including a device driver, middleware, various development environments, an application program related to AI (AI Application), and an application program not related to AI (Application).

[0597] The device driver includes an application program for controlling external connection devices such as an auxiliary storage device, a display device, and a printer.

[0598] The hardware constituting the computer system 7000 includes a first arithmetic processing unit, a second arithmetic processing unit, and a first storage device. The second arithmetic processing unit also has a second storage device.

[0599] As the first arithmetic processing unit, for example, a central arithmetic processing unit such as a Noff OS CPU may be used. The Noff OS CPU has a storage means (for example, a non-volatile memory) using an OS transistor, and has a function of holding necessary information in the storage means and stopping the power supply to the central arithmetic processing unit when operation is not required. By using the Noff OS CPU as the first arithmetic processing unit, the power consumption of the computer system 7000 can be reduced.

[0600] As the second arithmetic processing unit, for example, a GPU, an FPGA, or the like can be used. Note that it is preferable to use an AI OS Accelerator as the second arithmetic processing unit. The AI OS Accelerator is configured using OS transistors and has arithmetic means such as a multiply-accumulate circuit. The AI OS Accelerator consumes less power than a general GPU or the like. By using the AI OS Accelerator as the second arithmetic processing unit, the power consumption of the computer system 7000 can be reduced.

[0601] It is preferable to use the storage device according to an aspect of the present invention as the first storage device and the second storage device. For example, it is preferable to use a 3D OS NAND type storage device. The 3D OS NAND type storage device can function as a cache, a main memory, and a storage. In addition, by using the 3D OS NAND type storage device, it becomes easy to realize a non-Neumann type computer system.

[0602] The 3D OS NAND type storage device consumes less power than a 3D NAND type storage device using Si transistors. By using the 3D OS NAND type storage device as the storage device, the power consumption of the computer system 7000 can be reduced. In addition, since the 3D OS NAND type storage device can function as a universal memory, the number of components for configuring the computer system 7000 can be reduced.

[0603] By configuring the semiconductor device constituting the hardware with a semiconductor device including OS transistors, it becomes easy to monolithically integrate the hardware including the central processing unit, the arithmetic processing unit, and the storage device. By monolithically integrating the hardware, not only miniaturization, weight reduction, and thinning are achieved, but also further reduction of power consumption becomes easy.

[0604] [IoT] The memory device according to one aspect of the present invention can be suitably used in a small-scale system such as an IoT terminal device (also called an endpoint microcomputer) in the field of IoT (Internet of Things), for example.

[0605] Fig. 35 shows an image diagram of factory automation as an application example of an endpoint microcomputer. Factory 884 is connected to cloud 883 via an Internet line. Also, cloud 883 is connected to home 881 and office 882 via an Internet line. The Internet line may be a wired communication method or a wireless communication method. For example, in the case of a wireless communication method, wireless communication conforming to a communication standard such as the 4th generation mobile communication system (4G) or the 5th generation mobile communication system (5G) may be performed using the memory device according to one aspect of the present invention in a communication device. Further, factory 884 may be connected to factories 885 and 886 via an Internet line.

[0606] Factory 884 has a master device (control device) 831. The master device 831 is connected to the cloud 883 and has a function of exchanging information. Also, the master device 831 is connected to a plurality of industrial robots 842 included in the IoT terminal device 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet (registered trademark), which is a kind of wired communication method, or local 5G, which is a kind of wireless communication method, may be used.

[0607] The factory manager can connect to factory 884 via cloud 883 from home 881 or office 882 and know the operating status and the like. Also, defective product / missing product check, storage location indication, tact time measurement, etc. can be performed.

[0608] In recent years, factories labeled as "smart factories" have been globally promoting the introduction of IoT into factories. In cases of smart factories, there have been reports of not only simple inspections and audits by endpoint microcontrollers but also cases of performing fault detection and anomaly prediction.

[0609] Small-scale systems such as endpoint microcontrollers often have low overall power consumption during operation, so the power reduction effect during standby operation by the storage device becomes significant. On the other hand, although immediacy may be required in the field of IoT integration, by using the storage device according to one aspect of the present invention, a high-speed return from standby operation can be achieved.

[0610] It should be noted that this embodiment can be appropriately combined with other embodiments shown in this specification.

Explanation of Reference Numerals

[0611] abl: Wiring, awl: Wiring, AD: Address signal, BL: Wiring, BLD: Circuit, BSL: Wiring, BTr: Transistor, CAL: Wiring, CD: Column decoder, CL: Wiring, COIL: Coil, CPU: Central processing unit, CTr: Transistor, CTR: Control circuit, C11: Capacitor element, C12: Capacitor element, CS: Control signal, CVC: Circuit, EW: Wiring, MC: Memory cell, MCA: Memory cell array, MCL: Memory cell section, M11: Transistor, M12: Transistor, M13: Transistor, N11: Node, N12: Node, OBLD: Circuit, OAD: Address signal, OCD: Column decoder, OMC: Memory cell, OMCL: Memory cell section, OOPC: Output circuit, OPC: Output circuit, OPR: Precharge circuit, ORD: Data signal, ORPH: Circuit, OSA: Sense amplifier, OSC: Circuit, OUTP: Output circuit, OWC: Write circuit, OWD: Data signal, OWLD: Circuit, PRPH: Circuit, PU: Arithmetic unit, rbl: Wiring, rwl: Wiring, RD: Data signal, RDATA: Data signal, RFBL: RF block circuit, SA: Sense amplifier, SCL1: Scribe line, SCL2: Scribe line, SRG: String, SSL: Wiring, STr: Transistor, SUB: Substrate, wbl: Wiring, wwl: Wiring, WC: Write circuit, WD: Data signal, Vdd: Potential, WDATA: Data signal, WL: Wiring, WLD: Circuit, 10: Layer, 10B: Layer, 20: Layer, 30: Layer, 30B: Layer, 40: Layer, 40A: Layer, 40B: Layer, 100: Memory device, 100A: Memory device, 110: Memory device, 111: Insulator, 112: Insulator, 113: Insulator, 114: Insulator, 115: Insulator, 116: Insulator, 117: Insulator, 121: Insulator, 122: Insulator, 131: Insulator, 132: Insulator, 133: Insulator, 141: Semiconductor, 142: Semiconductor, 143: Semiconductor, 150: Host, 151: Conductor, 152: Conductor, 153: Conductor, 154: Conductor, 155: Conductor, 156: Conductor, 200A: Central management unit, 211: Insulator, 212: Insulator, 213: Insulator, 214: Insulator, 215: Insulator, 216: Insulator, 221: Conductor, 222: Conductor, 223: Conductor, 231: Semiconductor, 232: Semiconductor, 240: Insulator, 241: Insulator, 242: Insulator, 250: Conductor, 251: Conductor, 252: Conductor,300: Transistor, 300A: Information processing system, 311: Substrate, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 402: Insulator, 404: Insulator, 410: Memory element, 411: Transistor, 412: Transistor, 413: Node, 421: Terminal, 422: Terminal, 423: Terminal, 425: Capacitance, 431: Transistor, 432: Transistor, 433: Terminal, 434: Terminal, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 505: Conductor, 505a: Conductor, 505b: Conductor, 510: Insulator, 510A: Transistor, 510B: Transistor, 510C: Transistor, 510D: Transistor, 511: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 521: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530c: Oxide, 530c1: Oxide, 530c2: Oxide, 532a: Conductor, 532b: Conductor, 540a: Conductor, 540b: Conductor, 542: Conductor, 542a: Conductor, 542b: Conductor, 543: Region, 543a: Region, 543b: Region, 544: Insulator, 545: Insulator, 546: Conductor, 546a: Conductor, 546b: Conductor, 548: Conductor, 550: Insulator, 550a: Insulator, 550b: Insulator, 551: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 572a: Conductor, 572b: Conductor, 574: Insulator, 576: Insulator, 576a: Insulator, 576b: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 584: Insulator, 586: Insulator, 600: Capacitor element, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator, 650: Insulator, 700: Transistor, 800: Transistor, 831: Master device, 832: M2M interface, 841: IoT terminal device, 842: Industrial robot, 881: Home, 882: Office, 883: Cloud, 884: Factory, 885: Factory, 886: Factory, 900: Transistor,901: Boundary region, 902: Boundary region, 4700: Electronic component, 4702: Printed circuit board, 4704: Mounting substrate, 4710: Memory device, 4711: Mold, 4712: Land, 4713: Electrode pad, 4714: Wire, 4730: Electronic component, 4731: Interposer, 4732: Package substrate, 4733: Electrode, 4735: Semiconductor device, 4800: Semiconductor wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit section, 4803: Spacing, 4803a: Spacing, 5110: SD card, 5111: Housing, 5112: Connector, 5113: Substrate, 5115: Controller chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Substrate, 5155: Memory chip, 5156: Controller chip, 5200: Portable game machine, 5201: Housing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main body, 5302: Display unit, 5303: Keyboard, 5400: ICD main body, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Housing, 5511: Display unit, 5600: Computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door, 5900: Information terminal, 5901: Housing, 5902: Display unit, 5903: Operation switch, 5904: Operation switch, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Substrate, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: Housing, 6302: Housing, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connection part, 7000: Computer system,7500: Standalone game console, 7520: Main body, 7522: Controller,

Claims

1. A first layer, a second layer, and a third layer, The first layer is provided with a circuit, a first memory cell unit is provided in the second layer; a second memory cell unit is provided in the third layer; the circuit has a function of driving or controlling the first memory cell unit and the second memory cell unit; the first memory cell unit has a function of retaining stored data for a longer period of time than the second memory cell unit when no power is supplied; the second memory cell unit has a function of writing data and reading data at a speed faster than that of the first memory cell unit; At least a portion of the second layer is laminated on the first layer, At least a portion of the third layer is laminated on the second layer, the circuit includes a first transistor having silicon in a channel forming region; the first memory cell portion has a second transistor; The second transistor is a first conductor having an opening; A first insulator provided in contact with an inner side surface of the opening; a second insulator provided in contact with the inner surface of the first insulator; a third insulator provided in contact with an inner surface of the second insulator; a semiconductor provided on an inner surface of the third insulator; the first conductor has a region that functions as a gate electrode; the semiconductor has silicon in a channel formation region; The second memory cell portion includes a third transistor having a metal oxide in a channel formation region.

2. A first layer, a second layer, and a third layer, The first layer is provided with a circuit, A memory cell unit is provided in the second layer, The third layer is provided with an RF blocking circuit; the circuit has a function of driving or controlling the memory cell unit and the RF block circuit, The memory cell unit has a function of retaining stored data in a state where power is not supplied, At least a portion of the second layer is laminated on the first layer, At least a portion of the third layer is laminated on the second layer, the circuit includes a first transistor having silicon in a channel forming region; the memory cell unit has a second transistor; The second transistor is a first conductor having an opening; A first insulator provided in contact with an inner side surface of the opening; a second insulator provided in contact with the inner surface of the first insulator; a third insulator provided in contact with an inner surface of the second insulator; a semiconductor provided on an inner surface of the third insulator; the first conductor has a region that functions as a gate electrode; the semiconductor has silicon in a channel formation region; The RF blocking circuit is a memory device having a third transistor having a metal oxide in a channel formation region.

3. In claim 1 or 2, The memory device, wherein the first transistor is provided on a single crystal silicon substrate.

4. In claim 1 or 2, The first transistor is formed on an SOI substrate.

Images