Differential amplifier

Abstract

To provide a differential amplifier capable of processing an analog signal with high accuracy.SOLUTION: A differential amplifier 10 includes: a first stage amplification circuit 20 having a first input terminal to which a first input signal INP1 is inputted, a second input terminal to which a second input signal INP2 is inputted, and first and second output terminals from which first and second output signals OP1, ON1 according to the first and the second input signals are respectively outputted; an RC filter 30 for filtering and outputting the first and second output signals outputted from the first and second output terminals; a second stage amplification circuit 40 having third and fourth input terminals to which filtered first and second output signals FOP1, FON1 are respectively inputted, and third output terminals from which third output signal OP2, ON2 according to the first and second output signals are outputted; and a third stage amplification circuit 50 having a fifth input terminal to which the third output signal is inputted, and fourth output terminals from which fourth output signals ON3 and OP3 according to the third output signals are outputted.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a differential amplifier.

Background Art

[0002] An amplifier that processes an analog signal in the audio band with high precision desirably has a high gain in the audio band. There are a two-pole compensated differential amplifier (see, for example, Patent Document 1) and a nested mirror compensated three-stage differential amplifier having an even higher gain (see, for example, Non-Patent Document 1). [Prior Art Documents] [Patent Documents] Patent Document 1 Japanese Patent Laid-Open No. 61-230414 [Non-Patent Documents] Non-Patent Document 1 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 2, FEBRUARY 2000

Summary of the Invention

[0003] In a first aspect of the present invention, there is provided a differential amplifier including: a first differential amplifier circuit having a first input terminal to which a first input signal is input, a second input terminal to which a second input signal is input, a first output terminal and a second output terminal that output a first output signal and a second output signal corresponding to the first input signal and the second input signal, respectively; an RC filter that filters and outputs the first output signal and the second output signal output from the first output terminal and the second output terminal of the first differential amplifier circuit; a third input terminal and a fourth input terminal to which the first output signal and the second output signal filtered by the RC filter are input, respectively; a second differential amplifier circuit having a third output terminal that outputs a third output signal corresponding to the first output signal and the second output signal; a third amplifier circuit having a fifth input terminal to which the third output signal output from the second differential amplifier circuit is input and a fourth output terminal that outputs a fourth output signal corresponding to the third output signal.

[0004] In the differential amplifier described above, a first feedback capacitor having one end connected to a node between the RC filter and the third input terminal of the second differential amplifier circuit and the other end connected to the fourth output terminal of the third amplifier circuit, and a second feedback capacitor having one end connected to a node between the third output terminal of the second differential amplifier circuit and the fifth input terminal of the third amplifier circuit and the other end connected to the fourth output terminal of the third amplifier circuit may be further provided.

[0005] In the differential amplifier described above, the RC filter has a filter section including a filter capacitor and a filter resistor connected in series, and the filter section may be connected between the first differential amplifier circuit and the second differential amplifier circuit so as not to be in a parallel connection relationship with the first feedback capacitor and the second feedback capacitor.

[0006] In the differential amplifier described above, the filter section may include a first filter section having one end connected to a node between the first output terminal of the first differential amplifier circuit and the third input terminal of the second differential amplifier circuit and the other end connected to a node between the second output terminal of the first differential amplifier circuit and the fourth input terminal of the second differential amplifier circuit, and a second filter section having one end connected between the second output terminal of the first differential amplifier circuit and the node to which the other end of the first filter section is connected and the other end connected between the node to which one end of the first filter section is connected and the third input terminal of the second differential amplifier circuit.

[0007] In any of the differential amplifiers described above, the filter section may include a first filter section having one end connected to a node between the first output terminal of the first differential amplifier circuit and the third input terminal of the second differential amplifier circuit and the other end connected to the reference potential, and a second filter section having one end connected to a node between the second output terminal of the first differential amplifier circuit and the fourth input terminal of the second differential amplifier circuit and the other end connected to the reference potential.

[0008] In any of the differential amplifiers described above, the filter section may include a first filter resistor having one end connected to a node between the first output terminal of the first differential amplification circuit and the third input terminal of the second differential amplification circuit, a second filter resistor having one end connected to a node between the second output terminal of the first differential amplification circuit and the fourth input terminal of the second differential amplification circuit, and a first filter capacitor and a second filter capacitor connected in parallel between the other end of the first filter resistor and the other end of the second filter resistor.

[0009] In any of the differential amplifiers described above, the filter section may include a first filter capacitor having one end connected to a node between the first output terminal of the first differential amplification circuit and the third input terminal of the second differential amplification circuit, a second filter capacitor having one end connected to a node between the second output terminal of the first differential amplification circuit and the fourth input terminal of the second differential amplification circuit, and a filter resistor connected between the other end of the first filter capacitor and the other end of the second filter capacitor.

[0010] In any of the differential amplifiers described above, the RC filter may further include a first buffer having an input connected to the first output terminal of the first differential amplification circuit and an output connected to the third input terminal of the second differential amplification circuit, and a second buffer having an input connected to the second output terminal of the first differential amplification circuit and an output connected to the fourth input terminal of the second differential amplification circuit.

[0011] In any of the differential amplifiers described above, the third output terminal of the second differential amplification circuit includes a positive third output terminal and a negative third output terminal that respectively output a third non-inverting output signal and a third inverting output signal corresponding to the first output signal and the second output signal. The fifth input terminal of the third amplification circuit includes a positive fifth input terminal to which the third non-inverting output signal is input and a negative fifth input terminal to which the third inverting output signal is input. The fourth output terminal of the third amplification circuit includes a negative fourth output terminal and a positive fourth output terminal that respectively output a fourth inverting output signal and a fourth non-inverting output signal corresponding to the third non-inverting output signal and the third inverting output signal. One end of the first feedback capacitor is connected to a node between the RC filter and the third input terminal of the second differential amplification circuit, and the other end is connected to the negative fourth output terminal of the third amplification circuit. One end of the second feedback capacitor is connected to a node between the positive third output terminal of the second differential amplification circuit and the positive fifth input terminal of the third amplification circuit, and the other end is connected to the negative fourth output terminal of the third amplification circuit. The differential amplifier may further include a third feedback capacitor having one end connected to a node between the RC filter and the fourth input terminal of the second differential amplification circuit and the other end connected to the positive fourth output terminal of the third amplification circuit, and a fourth feedback capacitor having one end connected to a node between the negative third output terminal of the second differential amplification circuit and the negative fifth input terminal of the third amplification circuit and the other end connected to the positive fourth output terminal of the third amplification circuit.

[0012] In any of the differential amplifiers described above, it may further include a third feedback capacitor having one end connected to a node between the RC filter and the fourth input terminal of the second differential amplification circuit and the other end connected to the reference potential.

[0013] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0014]

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Embodiments for Carrying Out the Invention

[0015] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0016] FIG. 1 shows a first configuration example of the differential amplifier 10 of the present embodiment. The differential amplifier 10 amplifies the signal level of a differentially input signal in, for example, the audio band and outputs it differentially. As an example, the differential amplifier 10 is a fully differential input / output type two-pole compensated circuit built-in nested mirror compensated type three-stage differential amplifier. The differential amplifier 10 includes a first-stage amplifier circuit 20, an RC filter 30, a second-stage amplifier circuit 40, a third-stage amplifier circuit 50, a first feedback capacitor 60, a first feedback resistor 62, a second feedback capacitor 64, a second feedback resistor 66, a third feedback capacitor 74, a third feedback resistor 76, a fourth feedback capacitor 70, and a fourth feedback resistor 72.

[0017] The first-stage amplifier circuit 20 performs the first-stage amplification operation in the differential amplifier 10. The first-stage amplifier circuit 20 includes a first differential amplifier circuit 100, a first output resistor 120, and a second output resistor 140.

[0018] The first differential amplifier circuit 100 receives a first input signal INP1 and a second input signal INN1 whose phases are inverted at the same signal level (voltage), amplifies the difference in the signal levels of the input first input signal INP1 and second input signal INN1, and outputs a first output signal OP1 and a second output signal ON1.

[0019] The first differential amplifier circuit 100 has a first input terminal to which a first input signal INP1 is input, a second input terminal to which a second input signal INN1 is input, and a first output terminal and a second output terminal that output a first output signal OP1 and a second output signal ON1 corresponding to the first input signal INP1 and the second input signal INN1, respectively. In the present embodiment shown in FIG. 1, the first input terminal is a positive input terminal (+), the second input terminal is a negative input terminal (-), the first output terminal is a positive output terminal (+), and the second output terminal is a negative output terminal (-). The first differential amplifier circuit 100 amplifies the difference in voltage applied to the first input terminal and the second input terminal by a predetermined gain (amplification factor) G1, and generates the amplified voltage difference between the first output terminal and the second output terminal.

[0020] One end of the first output resistor 120 is connected to the first output terminal of the first differential amplifier circuit 100. One end of the second output resistor 140 is connected to the second output terminal of the first differential amplifier circuit 100. The first output resistor 120 and the second output resistor 140 are the output impedances of the first-stage amplifier circuit 20. The first output resistor 120 and the second output resistor 140 may have the same resistance value.

[0021] The RC filter 30 has its positive input terminal connected to the other end of the first output resistor 120 and its negative input terminal connected to the other end of the second output resistor 140. The RC filter 30 is arranged between the first-stage amplifier circuit 20 and the second-stage amplifier circuit 40, filters the first output signal OP1 and the second output signal ON1 output from the first output terminal and the second output terminal of the first differential amplifier circuit 100, and outputs the filtered signals FOP1 and FON1. The RC filter 30 is, as an example, a low-pass filter. The attenuation amount of the first output signal OP1 and the second output signal ON1 changes according to the frequencies of the first output signal OP1 and the second output signal ON1 output by the first differential amplifier circuit 100. For example, in a predetermined frequency range, the higher the frequencies of the first output signal OP1 and the second output signal ON1, the greater the attenuation amount of the first output signal OP1 and the second output signal ON1.

[0022] The second-stage amplification circuit 40 performs the second-stage amplification operation in the differential amplifier 10. The second-stage amplification circuit 40 includes a second differential amplification circuit 200, a third output resistor 220, and a fourth output resistor 240.

[0023] The second differential amplification circuit 200 is connected to the positive output terminal (+) and the negative output terminal (-) of the RC filter 30. The second differential amplification circuit 200 has a third input terminal and a fourth input terminal to which the first output signal OP1 and the second output signal ON1 filtered by the RC filter 30 are respectively input, and a third output terminal that outputs third output signals OP2 and ON2 corresponding to the first output signal OP1 and the second output signal ON1. The third output terminal of the second differential amplification circuit 200 in this embodiment includes a positive third output terminal (+) and a negative third output terminal (-) that respectively output a third non-inverted output signal OP2 and a third inverted output signal ON2 corresponding to the first output signal OP1 and the second output signal ON1. The second differential amplification circuit 200 amplifies the voltage difference between the third input terminal and the fourth input terminal by the differentially input first output signal OP1 and second output signal ON1 with a predetermined gain G2, and generates the amplified voltage difference between the positive third output terminal and the negative third output terminal.

[0024] One end of the third output resistor 220 is connected to the positive third output terminal of the second differential amplification circuit 200. One end of the fourth output resistor 240 is connected to the negative third output terminal of the second differential amplification circuit 200. The third output resistor 220 and the fourth output resistor 240 are the output impedances of the second-stage amplification circuit 40. The third output resistor 220 and the fourth output resistor 240 may have the same resistance value.

[0025] The third-stage amplification circuit 50 performs the third-stage amplification operation in the differential amplifier 10. The third-stage amplification circuit 50 includes a third amplification circuit 300, a fifth output resistor 320, and a sixth output resistor 340.

[0026] The third amplification circuit 300 is connected to the positive third output terminal and the negative third output terminal of the second differential amplification circuit 200. The third amplification circuit 300 has a fifth input terminal to which the third output signals OP2 and ON2 output from the second differential amplification circuit 200 are input, and a fourth output terminal that outputs fourth output signals OP3 and ON3 corresponding to the third output signals OP2 and ON2. The third amplification circuit 300 of this embodiment performs differential amplification. The fifth input terminal of the third amplification circuit 300 includes a positive fifth input terminal (+) to which the third non-inverted output signal OP2 is input and a negative fifth input terminal (-) to which the third inverted output signal ON2 is input. The fourth output terminal of the third amplification circuit 300 includes a negative fourth output terminal (-) and a positive fourth output terminal (+) that respectively output a fourth inverted output signal ON3 and a fourth non-inverted output signal OP3 corresponding to the third non-inverted output signal OP2 and the third inverted output signal ON2. The third amplification circuit 300 amplifies the voltage difference between the positive fifth input terminal and the negative fifth input terminal by the input third non-inverted output signal OP2 and the third inverted output signal ON2 with a predetermined gain G3, and generates the amplified voltage difference between the negative fourth output terminal and the positive fourth output terminal.

[0027] The fifth output resistor 320 has one end connected to the negative fourth output terminal of the third amplification circuit 300 and the other end connected to the negative output terminal of the differential amplifier 10. The sixth output resistor 340 has one end connected to the positive fourth output terminal of the third amplification circuit 300 and the other end connected to the positive output terminal of the differential amplifier 10. The fifth output resistor 320 and the sixth output resistor 340 are the output impedances of the third-stage amplification circuit 50. The fifth output resistor 320 and the sixth output resistor 340 may have the same resistance value.

[0028] The first feedback capacitor 60 has one end connected to node 32 between the positive output terminal of the RC filter 30 and the third input terminal of the second differential amplifier circuit 200 via the first feedback resistor 62, and the other end connected to the negative fourth output terminal of the third amplifier circuit 300 at node 52. The first feedback capacitor 60 is a phase compensation capacitor. The first feedback resistor 62 has one end connected to node 32 between the positive output terminal of the RC filter 30 and the third input terminal of the second differential amplifier circuit 200, and the other end connected to one end of the first feedback capacitor 60. The first feedback resistor 62 adjusts the phase characteristics of the differential amplifier 10. The serially connected first feedback capacitor 60 and first feedback resistor 62 constitute a phase compensation circuit arranged in the feedback path from the negative output of the third amplifier circuit 300 to the positive input of the second differential amplifier circuit 200 in the differential amplifier 10.

[0029] The second feedback capacitor 64 has one end connected to node 42 between the positive third output terminal of the second differential amplifier circuit 200 and the positive fifth input terminal of the third amplifier circuit 300 via the second feedback resistor 66, and the other end connected to the negative fourth output terminal of the third amplifier circuit 300 at node 52. The second feedback capacitor 64 is a phase compensation capacitor. The second feedback resistor 66 has one end connected to node 42 between the positive third output terminal of the second differential amplifier circuit 200 and the positive fifth input terminal of the third amplifier circuit 300, and the other end connected to one end of the second feedback capacitor 64. The second feedback resistor 66 adjusts the phase characteristics of the differential amplifier 10. The serially connected second feedback capacitor 64 and second feedback resistor 66 constitute a phase compensation circuit arranged in the feedback path from the negative output of the third amplifier circuit 300 to the positive input of the third amplifier circuit 300 in the differential amplifier 10.

[0030] The third feedback capacitor 74 has one end connected to node 34 between the negative output terminal of the RC filter 30 and the fourth input terminal of the second differential amplifier circuit 200 via the third feedback resistor 76, and the other end connected to the positive fourth output terminal of the third amplifier circuit 300. The third feedback capacitor 74 is a phase compensation capacitor. The third feedback resistor 76 has one end connected to node 34 between the negative output terminal of the RC filter 30 and the fourth input terminal of the second differential amplifier circuit 200, and the other end connected to one end of the third feedback capacitor 74. The third feedback resistor 76 adjusts the phase characteristics of the differential amplifier 10. The serially connected third feedback capacitor 74 and third feedback resistor 76 constitute a phase compensation circuit arranged in the feedback path from the positive output of the third amplifier circuit 300 to the negative input of the second differential amplifier circuit 200 in the differential amplifier 10.

[0031] The fourth feedback capacitor 70 has one end connected to node 44 between the negative third output terminal of the second differential amplifier circuit 200 and the negative fifth input terminal of the third amplifier circuit 300 via the fourth feedback resistor 72, and the other end connected to the positive fourth output terminal of the third amplifier circuit 300. The fourth feedback capacitor 70 is a phase compensation capacitor. The fourth feedback resistor 72 has one end connected to node 44 between the negative third output terminal of the second differential amplifier circuit 200 and the negative fifth input terminal of the third amplifier circuit 300, and the other end connected to one end of the fourth feedback capacitor 70. The fourth feedback resistor 72 adjusts the phase characteristics of the differential amplifier 10. The serially connected fourth feedback capacitor 70 and fourth feedback resistor 72 constitute a phase compensation circuit arranged in the feedback path from the positive output of the third amplifier circuit 300 to the negative input of the third amplifier circuit 300 in the differential amplifier 10.

[0032] FIG. 2 shows a first circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 may have a filter section including a filter capacitor and a filter resistor connected in series. The filter section may be connected between the first differential amplifier circuit 100 and the second differential amplifier circuit 200 so as not to be in a parallel connection relationship with the first feedback capacitor 60 and the second feedback capacitor 64. The RC filter 30 of the first circuit example has a first filter section 400, a second filter section 403, a third filter resistor 405, and a fourth filter resistor 406.

[0033] One end of the first filter section 400 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200, and the other end is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200. The first filter section 400 has a first filter resistor 402 and a first filter capacitor 404 connected in series. One end of the first filter resistor 402 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200, and the other end is connected to one end of the first filter capacitor 404. The other end of the first filter capacitor 404 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200.

[0034] The second filter section 403 has one end connected between the second output terminal of the first differential amplifier circuit 100 and the node to which the other end of the first filter section 400 is connected, and the other end connected between the node to which one end of the first filter section 400 is connected and the third input terminal of the second differential amplifier circuit 200. The second filter section 403 has a second filter resistor 408 and a second filter capacitor 410 connected in series. One end of the second filter resistor 408 is connected between the second output terminal of the first differential amplifier circuit 100 and the node to which the other end of the first filter capacitor 404 is connected, and the other end is connected to one end of the second filter capacitor 410. The second filter resistor 408 may have the same resistance value as the first filter resistor 402. The other end of the second filter capacitor 410 is connected between the node to which one end of the first filter resistor 402 is connected and the third input terminal of the second differential amplifier circuit 200.

[0035] The third filter resistor 405 is connected between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200, and in this embodiment, is connected between the node to which one end of the first filter resistor 402 is connected and the node to which the other end of the second filter capacitor 410 is connected. The third filter resistor 405 may have a resistance value smaller than that of the first filter resistor 402. The fourth filter resistor 406 is connected between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200, and in this embodiment, is connected between the node to which one end of the second filter resistor 408 is connected and the node to which the other end of the first filter capacitor 404 is connected. The fourth filter resistor 406 may have a resistance value smaller than that of the second filter resistor 408 and may have the same resistance value as the third filter resistor 405.

[0036] By arranging the RC filter 30 between the output of the first-stage amplifier circuit 20 and the input of the second-stage amplifier circuit 40 in the differential amplifier 10 of this embodiment, a first pole, a second pole, and a zero point are generated in the open-loop characteristics of the gain, and the differential amplifier 10 can be stably operated.

[0037] FIG. 3 shows an equivalent circuit of a part of the differential amplifier 10 of the present embodiment. FIG. 3 shows, as an equivalent circuit, a transmission circuit until the signal amplified G1 times by the first-stage amplifier circuit 20 is input to the second-stage amplifier circuit 40 via the RC filter 30. The equivalent circuit shown in FIG. 3 equivalently omits some elements and changes the element sizes for the transmission circuit of the differential amplifier 10, and also equivalently changes the wiring. In FIG. 3, the first feedback resistor 62 and the third feedback resistor 76 are elements for adjusting the phase characteristics of the differential amplifier 10, and are omitted because they do not contribute to the first pole, the second pole, and the zero point.

[0038] One end of the first feedback capacitor 60 is connected to the output of the third-stage amplifier circuit 50, and the other end is connected to the input of the second-stage amplifier circuit 40 via the first feedback resistor 62. Therefore, the first feedback capacitor 60 can be regarded as a capacitor whose capacitance value C41 is amplified by the gain G2 of the second-stage amplifier circuit 40 and the gain G3 of the third-stage amplifier circuit 50, and one end of which is connected to the reference potential. Thus, the first feedback capacitor 60' in FIG. 3 can be equivalently represented as a capacitor having a capacitance of G1*G2*C41 with one end connected to the node 32 and the other end connected to the reference potential. Here, the reference potential is, for example, ground, and the same applies hereinafter.

[0039] One end of the third feedback capacitor 74 is connected to the output of the third-stage amplifier circuit 50, and the other end is connected to the input of the second-stage amplifier circuit 40 via the third feedback resistor 76. Therefore, the third feedback capacitor 74 can be regarded as a capacitor whose capacitance value C42 is amplified by the gain G2 of the second-stage amplifier circuit 40 and the gain G3 of the third-stage amplifier circuit 50, and one end of which is connected to the reference potential. Thus, the third feedback capacitor 74' in FIG. 3 can be equivalently represented as a capacitor having a capacitance of G1*G2*C42 with one end connected to the node 34 and the other end connected to the reference potential.

[0040] Assume that the voltage at the first output terminal of the first differential amplifier circuit 100 is +VO, the voltage at the second output terminal is -VO, the voltage at node 32 is +VIN2, and the voltage at node 34 is -VIN2. Then, VIN2 is represented by the transfer function of the following equation (1). Here, in equation (1), R111 represents the resistance value of the first filter resistor 402, R121 represents the resistance value of the third filter resistor 405, C111 represents the capacitance value of the first filter capacitor 404, R11 represents the resistance value of the first output resistor 120, G2 represents the gain of the second differential amplifier circuit 200, G3 represents the gain of the third amplifier circuit 300, C41 represents the capacitance value of the first feedback capacitor 60, and s represents the Laplace operator of Laplace transform.

[0041] VIN2=(1+s*(R111 - R121)*C111) / (1+s*(R111*C111+(R11+R121)*(C111+G2*G3*C41))+s 2 *R111*(R11+R121)*G2*G3*C41*C111)*VO···(1)

[0042] In equation (1), the magnitude of G2*G3*C41 is much larger than the capacitance value C111 because the magnitude of the capacitance value C41 is amplified by at least several hundred times by the gain G2 of the second differential amplifier circuit 200 and the gain G3 of the third amplifier circuit 300. Therefore, the following equation (2) holds. C111+G2*G3*C41≒G2*G3*C41···(2)

[0043] From equations (1) and (2), the following equation (3) is derived. VIN2≒(1+s*(R111 - R121)*C111) / (1+s*(R111*C111+(R11+R121)*(G2*G3*C41))+s 2 *R111*R121*G2*G3*C41*C111)*VO=(1+s*(R111 - R121)*C111) / ((1+s*(R11+R121)*G2*G3*C41)*(1+s*R111*C111))*VO···(3)

[0044] The (1 + s*(R11 + R121)*G2*G3*C41)*(1 + s*R111*C111) shown in the denominator of Equation (3) indicates that there are two poles in the open-loop characteristics of the differential amplifier 10. Also, since G2*G3*C41 is large compared to the capacitance value C111 as described above, the first pole is calculated from (1 + s*(R11 + R121)*G2*G3*C41), and the second pole is calculated from (1 + s*R111*C111). Further, the (1 + s*(R111 - R121)*C111) shown in the numerator of Equation (3) indicates that there is one zero point in the open-loop characteristics of the differential amplifier 10.

[0045] The first pole, the second pole, and the zero point in the open-loop characteristics of the differential amplifier 10 are calculated from Equation (3) and are represented by the following Equations (4), (5), and (6), respectively. First pole = 1 / (2π*(R11 + R121)*G2*G3*C41) ··· (4) Second pole = 1 / (2π*R111*C111) ··· (5) Zero point = 1 / (2π*(R111 - R121)*C111) ··· (6)

[0046] First, the configuration of the first pole shown in Equation (4) will be described. (R11 + R121) is the resistance through which the signal amplified G1 times by the first differential amplifier circuit 100 passes to the input of the second differential amplifier circuit 200. G2*G3*C41 is the capacitance value amplified by the gain G2 of the second differential amplifier circuit 200 and the gain G3 of the third amplifier circuit 300 in the first feedback capacitor 60.

[0047] Next, the configuration of the second pole represented by Equation (5) will be described. In the frequency range where the impedance of the capacitance value C111 of the first filter capacitor 404 is equal to or less than that of the resistance value R111 of the first filter resistor 402, the first output signal OP1 of the first differential amplifier circuit 100 is transmitted to the fourth input terminal of the second differential amplifier circuit 200 via the first filter resistor 402 and the first filter capacitor 404, and the differential signal transmitted from the first differential amplifier circuit 100 to the second differential amplifier circuit 200 is attenuated. Since the attenuation of the signal via the first filter resistor 402 and the first filter capacitor 404 is performed through a path different from the signal path via the resistance value R121 of the third filter resistor 405 forming the first pole, a second pole represented by Equation (5) is formed in relation to the resistance value R111 and the capacitance value C111, separately from the first pole represented by Equation (4).

[0048] Next, the configuration of the zero point represented by Equation (6) will be described. The zero point is related to the differential resistance between the resistance value R111 of the first filter resistor 402 connected between the first output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200, and the resistance value R121 of the third filter resistor 405 connected between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200. Although the attenuation by the signal path via the first filter resistor 402 and the first filter capacitor 404 becomes larger as the frequency increases, in a higher frequency range where the impedance of the first filter capacitor 404 can be regarded as a short circuit, the attenuation amount is limited based on the ratio of the resistance values R111 and R121. Also, in a higher frequency range where the impedance of the first filter capacitor 404 can be regarded as a short circuit, the phase delay caused by the first filter capacitor 404 disappears. Therefore, due to the second pole in Equation (5), the phase delay increased by the first filter capacitor 404 is canceled out by the phase advancing in a higher frequency range.

[0049] Note that, since it is preferable that the zero point has a positive value for the differential amplifier 10 to operate stably, the relationship between the resistance values R111 and R121 preferably satisfies the following Equation (7). R111 > R121 ··· (7)

[0050] In this embodiment, the first filter section 400 and the second filter section 403 are respectively connected to the node between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200, and the node between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200. Thus, as shown in the equivalent circuit, the first filter section 400 and the second filter section 403 are not in a parallel connection relationship with capacitances G2*G3*C41 and G2*G3*C42 which are sufficiently large, so that a second pole and a zero point can be generated.

[0051] FIG. 4 is a diagram for explaining the gain and phase characteristics in the open loop of the differential amplifier 10 of this embodiment. In FIG. 4, (a) shows the relationship between the gain of the differential amplifier 10 and the frequencies of the input signals INP1 and INN1, and (b) shows the relationship between the phases of the output signals ON3 and OP3 of the differential amplifier 10 and the frequencies of the input signals INP1 and INN1.

[0052] In FIGS. 4(a) and (b), the solid line indicates the gain and phase characteristics in an actual open loop in which the frequencies of the second pole and the zero point are adjusted so that the differential amplifier 10 operates stably. In FIG. 4, 1st Pole represents the frequency of the first pole, 2nd Pole represents the frequency of the second pole, and 1st Zero represents the frequency of the zero point. In FIGS. 4(a) and (b), the dotted line schematically represents the gain and phase characteristics in the open loop of a differential amplifier in a reference example without the RC filter 30. In FIG. 4, 1st Pole' represents the frequency of the first pole in the differential amplifier of the reference example.

[0053] As shown in Fig. 4, in the frequency range from frequency zero (DC) to the frequency of the first pole, the gain is equal to G1*G2*G3 which is the DC gain, and in the frequency range between the first pole and the second pole, it attenuates at 20 dB / dec. Also, in the frequency range between the second pole and the zero point, the gain attenuates at 40 dB / dec, and when the frequency exceeds the zero point, the gain attenuates again at 20 dB / dec.

[0054] Next, the phase characteristics in the open loop of the differential amplifier 10 of this embodiment will be described. When the frequency exceeds the second pole, the phase delay approaches 180 degrees but does not reach 180 degrees. Then, as the frequency approaches the zero point, the phase advances. Near the unity gain frequency f0 shown in Fig. 4, the phase delay due to the second pole and the phase advance due to the zero point are canceled out, and only the 90-degree phase delay due to the first pole remains.

[0055] Next, the adjustment of the unity gain frequency f0 of the differential amplifier 10 of this embodiment will be described. The poles generated due to the load capacitance etc. of the differential amplifier 10 cause a phase delay exceeding 180 degrees as shown in Fig. 4. In order to stably operate the differential amplifier 10 of this embodiment, it is preferable to set f0 at a frequency lower than the frequency of the poles generated due to the load capacitance etc. of the differential amplifier 10. However, as shown in Fig. 4, it is not always necessary to adjust the position of the first pole to a low frequency, and by adjusting the second pole and the zero point, the unity gain frequency f0 of the differential amplifier 10 can be designed to be equal to the unity gain frequency of the differential amplifier 10 in the reference example.

[0056] As shown in Fig. 4, the differential amplifier 10 of this embodiment can arrange the first pole at a relatively high frequency, so it can be seen that the gain in the audio band is high. Also, the RC filter 30 of the first circuit example has a small number of elements, so it can reduce the increase in cost and does not generate steady power consumption, thus having low power consumption.

[0057] FIG. 5 shows a second circuit example of the RC filter 30 of the differential amplifier 10 according to this embodiment. The RC filter 30 of the second circuit example may be the same as the RC filter 30 of the first circuit example, except that the connection relationship between the filter resistor and the filter capacitor is different. Hereinafter, the differences from the RC filter 30 of the first circuit example will be mainly described.

[0058] One end of the first filter resistor 402 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200, and the other end is connected to one end of the first filter capacitor 404. The other end of the first filter capacitor 404 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200. The first filter resistor 402 may have a resistance value larger than that of the third filter resistor 405.

[0059] One end of the second filter resistor 408 is connected between the node to which the other end of the first filter capacitor 404 is connected and the third input terminal of the second differential amplifier circuit 200, and the other end is connected to one end of the second filter capacitor 410. The other end of the second filter capacitor 410 is connected between the second output terminal of the first differential amplifier circuit 100 and the node to which one end of the first filter resistor 402 is connected. In the second circuit example, the second filter resistor 408 may have the same resistance value as the first filter resistor 402. The second filter capacitor 410 may have the same capacitance value as the first filter capacitor 404. The second filter resistor 408 may have a resistance value larger than that of the fourth filter resistor 406.

[0060] Even in the differential amplifier 10 provided with the RC filter 30 of such a second circuit example, as an equivalent circuit, it is equivalent to the first circuit example shown in FIG. 3, and the same gain and phase characteristics as those of the differential amplifier 10 provided with the first circuit example shown in FIG. 4 can be obtained. In addition, the RC filter 30 of the second circuit example has a small number of elements, so an increase in cost can be reduced, and since it does not generate steady power consumption, it has low power consumption.

[0061] FIG. 6 shows a third circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 of the third circuit example may be the same as the RC filter 30 of the first circuit example, except that it does not have the second filter section 403, and the difference is that the RC filter 30 has a first buffer 420 and a second buffer 422. Hereinafter, the differences from the RC filter 30 of the first circuit example will be mainly described.

[0062] One end of the first filter resistor 402 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200, and the other end is connected to one end of the first filter capacitor 404. The other end of the first filter capacitor 404 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200.

[0063] The first buffer 420 has an input connected to the first output terminal of the first differential amplifier circuit 100 and an output connected to the third input terminal of the second differential amplifier circuit 200. In the present embodiment, the first buffer 420 is connected between a node to which one end of the first filter resistor 402 is connected and one end of the third filter resistor 405. The first buffer 420 may have a gain of 1 times for input and output, and preferably has a small input and output delay. Therefore, the first buffer 420 may be, for example, a source follower using a MOS transistor or an emitter follower using a bipolar transistor, and may output the input signal OP1 after multiplying it by 1 times.

[0064] The second buffer 422 has an input connected to the second output terminal of the first differential amplifier circuit 100 and an output connected to the fourth input terminal of the second differential amplifier circuit 200. In the present embodiment, the second buffer 422 is connected between a node to which the other end of the first filter capacitor 404 is connected and one end of the fourth filter resistor 406. The second buffer 422 may have a gain of 1 times for input and output, and preferably has a small input and output delay. Therefore, the second buffer 422 may be, for example, a source follower using a MOS transistor or an emitter follower using a bipolar transistor, and may output the input signal ON1 after multiplying it by 1 times.

[0065] The third filter resistor 405 has the other end connected to the third input terminal of the second differential amplifier 10. The fourth filter resistor 406 has the other end connected to the fourth input terminal of the second differential amplifier 10. The fourth filter resistor 406 may have the same resistance value as the third filter resistor 405.

[0066] The RC filter 30 of the third circuit example has a configuration that separates the transmission circuit before and after the first buffer 420 and the second buffer 422. Thereby, a second pole and a zero point can be generated in the transmission circuit before the first buffer 420 and the second buffer 422, and a first pole can be generated in the transmission circuit after the first buffer 420 and the second buffer 422. Since the first buffer 420 and the second buffer 422 separate the first filter capacitor 404, the first feedback capacitor 60, and the second feedback capacitor 64, the first feedback capacitor 60 and the third feedback capacitor 74 do not affect the poles and zero points generated in relation to the first filter capacitor 404.

[0067] FIG. 7 shows an equivalent circuit of a part of the differential amplifier 10 including the RC filter 30 of the third circuit example. FIG. 7 shows, as an equivalent circuit, the transmission circuit until the signal amplified G1 times by the first-stage amplifier circuit 20 is input to the second-stage amplifier circuit 40 via the RC filter 30. The equivalent circuit shown in FIG. 7 equivalently performs omission of some elements and change of the element size with respect to the transmission circuit of the differential amplifier 10, and also equivalently performs change of the wiring. In FIG. 7, the first feedback resistor 62 and the third feedback resistor 76 are elements for adjusting the phase characteristics of the differential amplifier 10, and are omitted because they do not contribute to the first pole, the second pole, and the zero point.

[0068] The first feedback capacitor 60 can be equivalently represented as a capacitor 60' having a capacitance value of G1*G2*C41, with one end connected to node 32 and the other end connected to the reference potential. The third feedback capacitor 74 can be equivalently represented as a capacitor 74' having a capacitance value of G1*G2*C42, with one end connected to node 34 and the other end connected to the reference potential. Since the nodes to which the first filter resistor 402 and the first filter capacitor 404 are connected are differential nodes in the differential amplifier 10, the voltages appearing at these nodes are signals of the same magnitude but with inverted phases. Therefore, in FIG. 7, one end of a resistor 402' having a resistance value half that of the first filter resistor 402 is connected to the node to which the first filter resistor 402 is connected, the other end of the resistor 402' is connected to one end of a capacitor 404' having a capacitance value twice that of the first filter capacitor 404, and the other end of the capacitor 404' is connected to the reference potential, and it is equivalently represented as a circuit. Also, one end of a resistor 402'' having a resistance value half that of the first filter resistor 402 is connected to the node to which the first filter capacitor 404 is connected, the other end of the resistor 402'' is connected to one end of a capacitor 404'' having a capacitance value twice that of the first filter capacitor 404, and the other end of the capacitor 404'' is connected to the reference potential, and it is equivalently represented as a circuit.

[0069] Let the voltage at the first output terminal of the first differential amplifier circuit 100 be +VO, the voltage at the second output terminal be -VO, the voltage at node 32 be +VIN2, and the voltage at node 34 be -VIN2. Then, VIN2 is represented by the transfer function of the following equation (8). Here, in equation (8), R150 represents the resistance value of the first filter resistor 402, R161 represents the resistance value of the third filter resistor 405, C150 represents the capacitance value of the first filter capacitor 404, R11 represents the resistance value of the first output resistor 120, G2 represents the gain of the second differential amplifier circuit 200, G3 represents the gain of the third amplifier circuit 300, C41 represents the capacitance of the first feedback capacitor 60, and s represents the Laplace operator of the Laplace transform.

[0070] VIN2 = ((1 + s * R150 * C150) / (1 + s * (2 * R11 + R150) * C150)) * (1 / (1 + s * R161 * G2 * G3 * C41)) * VO = (1 + s * R150 * C150) / ((1 + s * R161 * G2 * G3 * C41) * (1 + s * (2 * R11 + R150) * C150)) * VO ··· (8)

[0071] (1 + s * R161 * G2 * G3 * C41) * (1 + s * (2 * R11 + R150) * C150) shown in the denominator of Equation (8) represents that there are two poles in the open-loop characteristics of the differential amplifier 10. Also, since G2 * G3 * C41 is larger than C150, the first pole is calculated from (1 + s * R161 * G2 * G3 * C41), and the second pole is calculated from (1 + s * (2 * R11 + R150) * C150). Also, (1 + s * R150 * C150) shown in the numerator of Equation (8) represents that there is one zero point in the open-loop characteristics of the differential amplifier 10.

[0072] The first pole, the second pole, and the zero point in the open-loop characteristics of the differential amplifier 10 are calculated from Equation (8) and are represented by the following Equation (9), Equation (10), and Equation (11), respectively. First pole = 1 / (2π * R161 * G2 * G3 * C41) ··· (9) Second pole = 1 / (2π * (2 * R11 + R150) * C150) ··· (10) Zero point = 1 / (2π * R150 * C150) ··· (11)

[0073] As shown by Equation (9) representing the frequency of the first pole, the first pole is not affected by R11 or R12, which is the output impedance of the first-stage amplifier circuit 20 that occurred when using the RC filter 30 of the first circuit example, due to the first buffer 420 and the second buffer 422 added inside the RC filter 30. Therefore, the deviation of the frequency of the first pole during mass production can be suppressed to be smaller when using the third circuit example of the RC filter 30 than when using the first circuit example of the RC filter 30.

[0074] Also, the first filter resistor 402 and the first filter capacitor 404 connected in series to the RC filter 30 are separated from G2*G3*C41 and G2*G3*C42, which have a sufficiently large capacitance, by the first buffer 420 and the second buffer 422, and are not in a parallel relationship. Therefore, the RC filter 30 can generate a second pole and a zero point.

[0075] In the RC filter 30 of the third circuit example, the impedance of the circuit connected to the first input terminal of the first differential amplifier circuit 100 is equal to the impedance of the circuit connected to the second input terminal. In a design situation where the parasitic capacitance at one end of the first filter capacitor 404 is different from the parasitic capacitance at the other end, the fourth to eighth circuit examples that can prevent deterioration of the performance of the differential amplifier 10 are shown below.

[0076] FIG. 8 shows a fourth circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 of the fourth circuit example may be the same as the RC filter 30 of the third circuit example, except that it has a second filter section 403. Hereinafter, the differences from the RC filter 30 of the third circuit example will be mainly described.

[0077] The second filter section 403 is connected in parallel to the first filter section 400. The second filter section 403 has a second filter resistor 408 and a second filter capacitor 410 connected in series. One end of the second filter resistor 408 is connected to a node between the node to which the first filter capacitor 404 is connected and the input of the second buffer 422, and the other end is connected to one end of the second filter capacitor 410. The other end of the second filter capacitor 410 is connected to a node between the node to which one end of the first filter resistor 402 is connected and the input of the first buffer 420. The second filter resistor 408 may have the same resistance value as the first filter resistor 402, and the second filter capacitor 410 may have the same capacitance value as the first filter capacitor 404.

[0078] Even in the differential amplifier 10 provided with the RC filter 30 of such a fourth circuit example, the equivalent circuit is equivalent to the third circuit example shown in FIG. 7, and the same gain and phase characteristics as those of the differential amplifier 10 provided with the third circuit example can be obtained.

[0079] FIG. 9 shows a fifth circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 of the fifth circuit example may be the same as the RC filter 30 of the fourth circuit example, provided that one end of the first filter section 400 and one end of the second filter section 403 are connected to the reference potential. Hereinafter, the differences from the RC filter 30 of the fourth circuit example will be mainly described.

[0080] One end of the first filter section 400 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200, and the other end is connected to the reference potential. The first filter section 400 includes a first filter resistor 402 and a first filter capacitor 404 connected in series. One end of the first filter resistor 402 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the input of the first buffer 420, and the other end is connected to one end of the first filter capacitor 404. The other end of the first filter capacitor 404 is connected to the reference potential.

[0081] One end of the second filter section 403 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200, and the other end is connected to the reference potential. The second filter section 403 includes a second filter resistor 408 and a second filter capacitor 410 connected in series. One end of the second filter resistor 408 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the input of the second buffer 422, and the other end is connected to one end of the second filter capacitor 410. The other end of the second filter capacitor 410 is connected to the reference potential. The second filter resistor 408 may have the same resistance value as the first filter resistor 402, and the second filter capacitor 410 may have the same capacitance value as the first filter capacitor 404.

[0082] Even in the differential amplifier 10 including the RC filter 30 of such a fifth circuit example, the equivalent circuit is equivalent to the third circuit example shown in FIG. 7, and the same gain and phase characteristics as those of the differential amplifier 10 including the third circuit example can be obtained.

[0083] FIG. 10 shows a sixth circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 of the sixth circuit example may be the same as the RC filter 30 of the fifth circuit example, provided that the first filter resistor 402 and the second filter resistor 408 are connected to the reference potential. Hereinafter, differences from the RC filter 30 of the fifth circuit example will be mainly described.

[0084] The first filter section 400 has a first filter resistor 402 and a first filter capacitor 404 connected in series. One end of the first filter resistor 402 is connected to the reference potential, and the other end is connected to one end of the first filter capacitor 404. The other end of the first filter capacitor 404 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the input of the first buffer 420.

[0085] The second filter section 403 has a second filter resistor 408 and a second filter capacitor 410 connected in series. One end of the second filter resistor 408 is connected to the reference potential, and the other end is connected to one end of the second filter capacitor 410. The other end of the second filter capacitor 410 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the input of the second buffer 422. The second filter resistor 408 may have the same resistance value as the first filter resistor 402, and the second filter capacitor 410 may have the same capacitance value as the first filter capacitor 404.

[0086] Even in the differential amplifier 10 including the RC filter 30 of such a sixth circuit example, the equivalent circuit is equivalent to the third circuit example shown in FIG. 7, and the same gain and phase characteristics as those of the differential amplifier 10 including the third circuit example can be obtained.

[0087] FIG. 11 shows a seventh circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 of the seventh circuit example may be the same as the RC filter 30 of the third circuit example, except that it has a filter section 1000 with a different configuration. Hereinafter, the differences from the RC filter 30 of the third circuit example will be mainly described.

[0088] The filter section 1000 includes a first filter resistor 402, a first filter capacitor 404, a second filter resistor 408, and a second filter capacitor 410. One end of the first filter resistor 402 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200. In the present embodiment, one end of the first filter resistor 402 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the input of the first buffer 420, and the other end is connected to one end of the first filter capacitor 404 and one end of the second filter capacitor 410.

[0089] The first filter capacitor 404 is connected in parallel with the second filter capacitor 410 between the other end of the first filter resistor 402 and the other end of the second filter resistor 408. The other ends of the first filter capacitor 404 and the second filter capacitor 410 are connected to the other end of the second filter resistor 408. One end of the second filter resistor 408 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200. In the present embodiment, the other end of the second filter resistor 408 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the input of the second buffer 422. The second filter resistor 408 may have the same resistance value as the first filter resistor 402, and the second filter capacitor 410 may have the same capacitance value as the first filter capacitor 404.

[0090] Even in the differential amplifier 10 provided with the RC filter 30 of such a seventh circuit example, as an equivalent circuit, it is equivalent to the third circuit example shown in FIG. 7, and the same gain and phase characteristics as those of the differential amplifier 10 provided with the third circuit example can be obtained.

[0091] FIG. 12 shows an eighth circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 of the eighth circuit example may be the same as the RC filter 30 of the third circuit example, except that it has a filter section 1000 with a different configuration. Hereinafter, the differences from the RC filter 30 of the third circuit example will be mainly described.

[0092] The filter section 1000 has a first filter capacitor 404, a second filter capacitor 410, and a first filter resistor 402. One end of the first filter capacitor 404 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the third input terminal of the second differential amplifier circuit 200. In the present embodiment, one end of the first filter capacitor 404 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and the input of the first buffer 420, and the other end is connected to one end of the first filter resistor 402. One end of the second filter capacitor 410 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the fourth input terminal of the second differential amplifier circuit 200. In the present embodiment, one end of the second filter capacitor 410 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the input of the second buffer 422, and the other end is connected to the other end of the first filter resistor 402. The first filter resistor 402 is connected between the other end of the first filter capacitor 404 and the other end of the second filter capacitor 410. The second filter capacitor 410 may have the same capacitance value as the first filter capacitor 404.

[0093] Even in the differential amplifier 10 provided with the RC filter 30 of such an eighth circuit example, the equivalent circuit is equivalent to the third circuit example shown in FIG. 7, and the same gain and phase characteristics as those of the differential amplifier 10 provided with the third circuit example can be obtained.

[0094] FIG. 13 shows a ninth circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 of the ninth circuit example may be the same as the RC filter 30 of the first circuit example, except that it further has the same first buffer 420 and second buffer 422 as the third circuit example. Hereinafter, the differences from the RC filter 30 of the first circuit example will be mainly described.

[0095] The RC filter 30 of the ninth circuit example includes a first filter section 400, a second filter section 403, a third filter resistor 405, a fourth filter resistor 406, a first buffer 420, a second buffer 422, a fifth filter resistor 411, and a sixth filter resistor 412.

[0096] The first filter section 400 includes a first filter resistor 402 and a first filter capacitor 404 connected in series. One end of the first filter resistor 402 is connected to a node between the first output terminal of the first differential amplifier circuit 100 and one end of the third filter resistor 405, and the other end is connected to one end of the first filter capacitor 404. The other end of the first filter capacitor 404 is connected to a node between one end of the fourth filter resistor 406 and the input of the second buffer 422.

[0097] The second filter section 403 includes a second filter resistor 408 and a second filter capacitor 410 connected in series. One end of the second filter resistor 408 is connected to a node between the second output terminal of the first differential amplifier circuit 100 and the other end of the fourth filter resistor 406, and the other end is connected to one end of the second filter capacitor 410. The other end of the second filter capacitor 410 is connected to a node between the other end of the third filter resistor 405 and the input of the first buffer 420.

[0098] The third filter resistor 405 is connected between the first output terminal of the first differential amplifier circuit 100 and the input of the first buffer 420. The fourth filter resistor 406 is connected between the second output terminal of the first differential amplifier circuit 100 and the input of the second buffer 422. The output of the first buffer 420 is connected to one end of the fifth filter resistor 411. The output of the second buffer 422 is connected to one end of the sixth filter resistor 412. The first buffer 420 and the second buffer 422 may be the same as those in the third circuit example. The other end of the fifth filter resistor 411 is connected to the third input terminal of the second differential amplifier circuit 200. The other end of the sixth filter resistor 412 is connected to the fourth input terminal of the second differential amplifier circuit 200.

[0099] In the ninth circuit example, the first filter resistor 402 may have the same resistance value as the second filter resistor 408 and a resistance value larger than that of the third filter resistor 405. The second filter resistor 408 may have a resistance value larger than that of the fourth filter resistor 406. The fourth filter resistor 406 may have the same resistance value as the third filter resistor 405. The sixth filter resistor 412 may have the same resistance value as the fifth filter resistor 411. The second filter capacitor 410 may have the same capacitance value as the first filter capacitor 404.

[0100] FIG. 14 shows an equivalent circuit of a part of the differential amplifier 10 included in the RC filter 30 of the ninth circuit example. FIG. 14 shows, as an equivalent circuit, the transmission circuit until the signal amplified G1 times by the first-stage amplifier circuit 20 is input to the second-stage amplifier circuit 40 via the RC filter 30. The equivalent circuit shown in FIG. 14 equivalently performs omission of some elements and change of the element size with respect to the transmission circuit of the differential amplifier 10, and also equivalently performs change of the wiring. Note that, in FIG. 14, the first feedback resistor 62 and the third feedback resistor 76 are elements for adjusting the phase characteristics of the differential amplifier 10, and are omitted because they do not contribute to the first pole, the second pole, and the zero point.

[0101] One end of the first feedback capacitor 60 is connected to the output of the third-stage amplifier circuit 50, and the other end is connected to the input of the second-stage amplifier circuit 40 via the first feedback resistor 62. Therefore, the first feedback capacitor 60 can be regarded as a capacitor having a capacitance value C41, which is amplified by the gain G2 of the second-stage amplifier circuit 40 and the gain G2 of the third-stage amplifier circuit 50, and one end of which is connected to the reference potential. Thus, the first feedback capacitor 60' in FIG. 14 can be equivalently represented as a capacitor having a capacitance of G1*G2*C41, one end of which is connected to the node 32 and the other end of which is connected to the reference potential.

[0102] One end of the third feedback capacitor 74 is connected to the output of the third-stage amplifier circuit 50, and the other end is connected to the input of the second-stage amplifier circuit 40 via the third feedback resistor 76. Therefore, the third feedback capacitor 74 can be regarded as a capacitor whose capacitance value C42 is amplified by the gain G2 of the second-stage amplifier circuit 40 and the gain G2 of the third-stage amplifier circuit 50, and one end is connected to the reference potential. Thus, the third feedback capacitor 74' in FIG. 14 can be equivalently represented as a capacitor having a capacitance of G1*G2*C42, with one end connected to node 34 and the other end connected to the reference potential.

[0103] Assuming that the voltage at the first output terminal of the first differential amplifier circuit 100 is +VO, the voltage at the second output terminal is -VO, the voltage at node 32 is +VIN2, and the voltage at node 34 is -VIN2, VIN2 is represented by the transfer function of the following equation (12). Here, in equation (12), R271 represents the resistance value of the first filter resistor 402, R281 represents the resistance value of the third filter resistor 405, R291 represents the resistance value of the fifth filter resistor 411, C271 represents the capacitance value of the first filter capacitor 404, R11 represents the resistance value of the first output resistor 120, G2 represents the gain of the second differential amplifier circuit 200, G3 represents the gain of the third amplifier circuit 300, C41 represents the capacitance value of the first feedback capacitor 60, and s represents the Laplace operator of the Laplace transform.

[0104] VIN2 = ((1 + s*(R271 - R281)*C271) / (1 + s*(4*R11 + R271 + R281)*C271))*(1 / (1 + s*R291*G2*G3*C41))*VO = (1 + s*(R271 - R281)*C271) / ((1 + s*R291*G2*G3*C41)*(1 + s*(4*R11 + R271 + R281)*C271))*VO ··· (12)

[0105] The (1 + s*R291*G2*G3*C41)*(1 + s*(4*R11 + R271 + R281)*C271) shown in the denominator of Equation (12) indicates that there are two poles in the open-loop characteristics of the differential amplifier 10. Also, since G2*G3*C41 is larger than C271, the first pole is calculated from (1 + s*R291*G2*G3*C41), and the second pole is calculated from (1 + s*(4*R11 + R271 + R281)*C271). Further, the (1 + s*(R271 - R281)*C271) shown in the numerator of Equation (12) indicates that there is one zero point in the open-loop characteristics of the differential amplifier 10.

[0106] The first pole, the second pole, and the zero point in the open-loop characteristics of the differential amplifier 10 are calculated from Equation (12) and are shown by the following Equation (13), Equation (14), and Equation (15), respectively. First pole = 1 / (2π*R291*G2*G3*C41) ··· (13) Second pole = 1 / (2π*(4*R11 + R271 + R281)*C271) ··· (14) Zero point = 1 / (2π*(R271 - R281)*C271) ··· (15)

[0107] As shown by Equation (13), the first pole is not affected by the first output resistance 120 and the second output resistance 140, which are the output impedances of the first-stage amplifier circuit 20 that may occur when using the RC filter 30 of the first circuit example, due to the first buffer 420 and the second buffer 422 added to the RC filter 30. Therefore, the deviation of the frequency of the first pole during mass production can be suppressed to be smaller when using the ninth circuit example than when using the first circuit example of the RC filter 30.

[0108] FIG. 15 shows a tenth circuit example of the RC filter 30 of the differential amplifier 10 of the present embodiment. The RC filter 30 of the tenth circuit example may be the same as the RC filter 30 of the ninth circuit example, except that the connection relationship between the filter resistor and the filter capacitor is different. Hereinafter, the differences from the RC filter 30 of the ninth circuit example will be mainly described.

[0109] The first filter resistor 402 has one end connected to the node between one end of the fourth filter resistor 406 and the input of the second buffer 422, and the other end connected to one end of the first filter capacitor 404. The first filter capacitor 404 has the other end connected to the node between the first output terminal of the first differential amplifier circuit 100 and one end of the third filter resistor 405.

[0110] The second filter resistor 408 has one end connected to the node between the other end of the third filter resistor 405 and the input of the first buffer 420, and the other end connected to one end of the second filter capacitor 410. The second filter capacitor 410 has the other end connected to the node between the second output terminal of the first differential amplifier circuit 100 and the other end of the fourth filter resistor 406. In the tenth circuit example, the second filter resistor 408 may have the same resistance value as the first filter resistor 402. The second filter capacitor 410 may have the same capacitance value as the first filter capacitor 404. The first filter resistor 402 may have a resistance value larger than that of the third filter resistor 405. The second filter resistor 408 may have a resistance value larger than that of the fourth filter resistor 406.

[0111] Even in the differential amplifier 10 provided with the RC filter 30 of such a tenth circuit example, as an equivalent circuit, it is equivalent to the ninth circuit example shown in FIG. 14, and the same gain and phase characteristics as those of the differential amplifier 10 provided with the ninth circuit example can be obtained.

[0112] FIG. 16 shows a second configuration example of the differential amplifier 10 of the present embodiment. The differential amplifier 10 of the second configuration example may be the same as the first configuration example, provided that the second-stage amplifier circuit 40 and the third-stage amplifier circuit 50 have single outputs. Similar to the first configuration example, the differential amplifier 10 of the second configuration example includes at least one RC filter 30 of the first circuit example to the tenth circuit example.

[0113] The second-stage amplifier circuit 40 differentially inputs the signals OP and ON output from the first differential amplifier circuit 100 via the RC filter 30, and singly outputs the amplified signal OP2. The second-stage amplifier circuit 40 includes a second differential amplifier circuit 600 and a seventh output resistor 610.

[0114] The second differential amplifier circuit 600 is connected to the positive output terminal (+) and the negative output terminal (-) of the RC filter 30. The second differential amplifier circuit 600 has a third input terminal (+) and a fourth input terminal (-) to which the first output signal and the second output signal filtered by the RC filter 30 are respectively input, and a third output terminal (+) that outputs a third output signal OP2 corresponding to the first output signal and the second output signal. The second differential amplifier circuit 600 amplifies (by a factor of G2) the voltage difference between the third input terminal and the fourth input terminal due to the differentially input first output signal and second output signal by a predetermined gain G2, and singly outputs from the third output terminal a third output signal OP2 with a signal level corresponding to the amplified voltage difference.

[0115] One end of the seventh output resistor 610 is connected to the third output terminal of the second differential amplifier circuit 600, and the other end is connected to the fifth input terminal of the third amplifier circuit 620.

[0116] The third-stage amplifier circuit 50 amplifies the signal output from the second differential amplifier circuit 600 and singly outputs it. The third-stage amplifier circuit 50 includes a third amplifier circuit 620 and an eighth output resistor 630.

[0117] The third amplifier circuit 620 is connected to the third output terminal of the second differential amplifier circuit 600. The third amplifier circuit 620 has a fifth input terminal (+) to which a third output signal OP2 output from the second differential amplifier circuit 600 is input, and a fourth output terminal (-) that outputs a fourth output signal ON3 corresponding to the third output signal OP2. The third amplifier circuit 620 amplifies (by a factor of G3) the signal level of the input third output signal OP2 by a predetermined gain G3 and outputs the amplified fourth output signal ON3. The eighth output resistor 630 has one end connected to the fourth output terminal of the third amplifier circuit 620 and the other end connected to the output terminal of the differential amplifier 10.

[0118] One end of the third feedback resistor 640 is connected to a node 34 between the negative output terminal of the RC filter 30 and the fourth input terminal of the second differential amplifier circuit 600, and the other end is connected to one end of the third feedback capacitor 642. One end of the third feedback capacitor 642 is connected to the node 34 between the RC filter 30 and the fourth input terminal of the second differential amplifier circuit 600 via the third feedback resistor 640, and the other end is connected to the reference potential. The differential amplifier 10 of the present embodiment connects the negative fourth input terminal of the second differential amplifier circuit 600 to the reference potential via the third feedback resistor 640 and the third feedback capacitor 642.

[0119] By arranging the RC filter 30 between the output of the first-stage amplifier circuit 20 and the input of the second-stage amplifier circuit 40, the differential amplifier 10 of the present embodiment can generate a first pole, a second pole, and a zero point in the open-loop characteristics, enabling the differential amplifier 10 to operate stably.

[0120] Next, a method for reducing the increase in die cost when the differential amplifier 10 of the first configuration example or the second configuration example of the present embodiment is mounted on a large-scale integrated circuit will be described.

[0121] As an example, when the differential amplifier 10 includes the RC filter 30 of the ninth circuit example, the first filter capacitor 404 forms the second pole shown in Equation (14). Here, comparing Equation (13) with Equation (14), in Equation (13), the capacitance value C41 of the first feedback capacitor 60 is amplified by the gain G2 of the second differential amplifier circuit 200 and the gain G3 of the third amplifier circuit 300, while in Equation (14), it can be seen that the capacitance value C271 itself of the first filter capacitor 404 forms the second pole. Therefore, in order to adjust the second pole to a desired frequency, the capacitance value C271 of the first filter capacitor 404 may be larger than the capacitance value C41, and when the differential amplifier 10 is implemented in a large-scale integrated circuit, the die size may increase. Therefore, in order to reduce the increase in die cost, it is preferable to reduce the die size of the filter capacitors constituting the RC filter 30.

[0122] The breakdown voltage of the capacitor and the capacitance value per unit area are in an inverse relationship. That is, if the breakdown voltage of the capacitor is not required, the die size of the capacitor can be reduced even with the same capacitance value. Here, let the minimum required breakdown voltage of the first filter capacitor 404 of the RC filter 30 of the differential amplifier 10 be Vcmax. Since the RC filter 30 is arranged between the output of the first-stage amplifier circuit 20 and the input of the second-stage amplifier circuit 40, Vcmax may be equal to the amplitude of the signal output from the first-stage amplifier circuit 20. Also, assuming that the required output amplitude at the output terminal of the differential amplifier 10 is Vout, the signal output from the first-stage amplifier circuit 20 is amplified by the gains of the second-stage amplifier circuit 40 and the third-stage amplifier circuit 50 and then output from the output terminal of the differential amplifier 10, so the following Equation (16) holds. Vcmax = Vout / (G2 * G3) ··· (16)

[0123] The breakdown voltage required for each capacitor that constitutes the differential amplifier 10 of the first configuration example and the differential amplifier 10 of the second configuration example will be described. For feedback capacitors such as the first feedback capacitor 60 and the third feedback capacitor 74 in the differential amplifier 10, where one end is connected to the output terminal of the differential amplifier 10, a breakdown voltage of at least Vout or higher is preferable. However, from Equation (16), since the breakdown voltage required for the filter capacitor that constitutes the RC filter 30 is such that G2*G3 is at least several hundred times, it can be seen that a lower breakdown voltage may be sufficient compared to the first feedback capacitor 60 and the third feedback capacitor 74. Therefore, the filter capacitor of the RC filter 30 is preferably of a lower breakdown voltage than the first feedback capacitor 60 and the third feedback capacitor 74 connected to the output terminal of the differential amplifier 10. As a result, it is possible to reduce the mounting size, and when the differential amplifier 10 is mounted on a large-scale integrated circuit, an increase in die cost can be reduced.

[0124] FIG. 17 shows the differential amplifier 110 of the reference example. The differential amplifier 110 of the reference example has the same configuration as the differential amplifier 10 of the first configuration example, except that the first output terminal and the second output terminal of the first differential amplifier circuit 100 are directly connected to the second differential amplifier circuit 200 via the first output resistor 120 and the second output resistor 140, and does not include the RC filter 30 between the first differential amplifier circuit 100 and the second differential amplifier circuit 200.

[0125] FIG. 18 shows a partial equivalent circuit of the differential amplifier 110 of the reference example. FIG. 18 shows an equivalent circuit of the transmission circuit until the signal amplified G1 times by the first-stage amplifier circuit 20 is directly input to the second-stage amplifier circuit 40. The equivalent circuit shown in FIG. 18 equivalently performs omission of some elements and change of the element size for the transmission circuit of the differential amplifier 110 of the reference example, and also equivalently performs change of the wiring. In FIG. 18, the first feedback resistor 62 and the third feedback resistor 76 are elements for adjusting the phase characteristics of the differential amplifier 110, and since they do not contribute to the first pole, the second pole, and the zero point, they are omitted.

[0126] The first feedback capacitor 60 has one end connected to the output of the third-stage amplifier circuit 50 and the other end connected to the input of the second-stage amplifier circuit 40 via the first feedback resistor 62. Therefore, the first feedback capacitor 60 can be regarded as a capacitor with a capacitance value C41 amplified by the gain G2 of the second-stage amplifier circuit 40 and the gain G3 of the third-stage amplifier circuit 50, and one end connected to the reference potential. Thus, the first feedback capacitor 60' in FIG. 18 can be equivalently represented as a capacitor having a capacitance of G1*G2*C41 with one end connected to node 32 and the other end connected to the reference potential.

[0127] The third feedback capacitor 74 has one end connected to the output of the third-stage amplifier circuit 50 and the other end connected to the input of the second-stage amplifier circuit 40 via the third feedback resistor 76. Therefore, the third feedback capacitor 74 can be regarded as a capacitor with a capacitance value C42 amplified by the gain G2 of the second-stage amplifier circuit 40 and the gain G3 of the third-stage amplifier circuit 50, and one end connected to the reference potential. Thus, the third feedback capacitor 74' in FIG. 18 can be equivalently represented as a capacitor having a capacitance of G1*G2*C42 with one end connected to node 34 and the other end connected to the reference potential.

[0128] Assuming that the voltage at the first output terminal of the first differential amplifier circuit 100 is +VO, the voltage at the second output terminal is -VO, the voltage at node 32 is +VIN2, and the voltage at node 34 is -VIN2, VIN2 is represented by the transfer function of the following equation (16). Here, in equation (16), R11 represents the resistance value of the first output resistor 120, G2 represents the gain of the second differential amplifier circuit 200, G3 represents the gain of the third amplifier circuit 300, C41 represents the capacitance value of the first feedback capacitor 60, and s represents the Laplace operator of Laplace transform.

[0129] VIN2 = 1 / (1 + s*R11*G2*G3*C41)*VO ··· (16)

[0130] (1 + s*R11*G2*G3*C41) shown in the denominator of Equation (16) indicates that there is one pole in the open-loop characteristics of the differential amplifier 110, and this pole becomes the first pole of the differential amplifier 110 in the reference example. The first pole of the differential amplifier 110 in the reference example is calculated from Equation (16) and is shown by the following Equation (17). First pole = 1 / (2π*R11*G2*G3*C41) ··· (17)

[0131] FIG. 19 is a diagram for explaining the gain and phase characteristics in the open loop of the differential amplifier 110 in the reference example. In FIG. 19, (a) shows the relationship between the gain of the differential amplifier 110 in the reference example and the frequency of the input signal, and (b) shows the relationship between the phase of the output signal of the differential amplifier 110 in the reference example and the frequency of the input signal.

[0132] In FIGS. 19(a) and (b), the solid line shows the gain and phase characteristics in an actual open loop in which the frequency of the first pole is adjusted so that the differential amplifier 110 in the reference example operates stably. In FIG. 19, 1st Pole represents the frequency of the first pole, and f0 represents the unity gain frequency. In FIGS. 19(a) and (b), the dotted line shows the gain and phase characteristics when the capacitance value C41 of the first feedback capacitor 60 is hypothetically set small, and 1st Pole' and f0' represent the frequency of the first pole and the unity gain frequency in the hypothetical state, respectively.

[0133] In the frequency range from frequency zero (DC) to the frequency of the first pole, the gain is equal to G1*G2*G3 which is the DC gain. When the frequency exceeds the first pole, the gain attenuates at 20 dB / dec, and then reaches the unity gain frequency at which the gain becomes 0 dB. Since the pole generated due to the load capacitance connected to the output terminal of the differential amplifier 110 generally causes a phase delay exceeding 180 degrees, in order to operate the differential amplifier 110 stably, it is necessary to set f0 to a frequency lower than the frequency of the pole generated due to the load capacitance connected to the output terminal of the differential amplifier 110.

[0134] In the open loop of the differential amplifier 110 of the reference example, the frequency of the first pole is arranged near the left end of the audio band as shown by the solid line in FIG. 19. Therefore, it can be seen that the gain in most of the frequency range of the audio band is lower than the DC gain. Thus, it can be understood that if the frequency of the first pole can be moved to a higher frequency, the gain in the audio band can be improved. Since the frequency of the first pole is represented by Equation (17), for example, if the capacitance value C41 is set smaller, the frequency of the first pole can be moved to a higher frequency.

[0135] Comparing the gain characteristics of the solid line and the dotted line in FIG. 19, the gain in the audio band is higher for the dotted line than for the solid line, so high-precision audio signal processing can be expected. However, in order to improve the gain in the audio band, if the frequency of the first pole is moved from the frequency indicated by 1st Pole to the higher frequency indicated by 1st Pole', the frequency of f0 also moves in conjunction to the higher frequency indicated by f0'. As a result, in the state shown by the dotted line, a phase delay exceeding 180 degrees occurs in the frequency range lower than f0' as shown in FIG. 19(b). Therefore, the differential amplifier 110 of the reference example enters an oscillation state and cannot operate stably, and high-precision audio signal processing cannot be performed.

[0136] In the actual design situation where the differential amplifier 110 of the reference example has a sharp phase delay due to a pole formed by a load capacitance or the like, the frequency of the first pole is also generally automatically determined in order to operate the differential amplifier 110 stably. Therefore, it can be seen that it is difficult to further improve the gain in the audio band.

[0137] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0138] In the claims, the specification, and the drawings, the execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown is not explicitly indicated as "earlier" or "preceding" etc. in particular. It should be noted that, unless the output of the previous process is used in the subsequent process, it can be realized in any order. Regarding the operation flow in the claims, the specification, and the drawings, even if it is described using "first," "next," etc. for convenience, it does not mean that it is essential to implement in this order.

Explanation of Reference Signs

[0139] 10 Differential amplifier 20 First-stage amplification circuit 30 RC filter 40 Second-stage amplification circuit 50 Third-stage amplification circuit 60 First feedback capacitor 62 First feedback resistor 64 Second feedback capacitor 66 Second feedback resistor 70 Fourth feedback capacitor 72 Fourth feedback resistor 74 Third feedback capacitor 76 Third feedback resistor 100 First differential amplification circuit 110 Differential amplifier 120 First output resistor 140 Second output resistor 200 Second differential amplification circuit 220 Third output resistor 240 Fourth output resistor 300 Third amplification circuit 320 Fifth output resistor 340 Sixth output resistor 400 First filter section 402 First filter resistor 404 First filter capacitor 403 Second filter section 405 Third filter resistor 406 Fourth filter resistor 408 Second Filter Resistance 410 Second Filter Capacitor 411 Fifth Filter Resistance 412 Sixth Filter Resistance 420 First Buffer 422 Second Buffer 600 Second Differential Amplifier Circuit 610 Seventh Output Resistance 620 Third Amplifier Circuit 630 Eighth Output Resistance 640 Third Feedback Resistance 642 Third Feedback Capacitor 1000 Filter Section

Claims

1. A first differential amplifier circuit having a first input terminal to which a first input signal is input, a second input terminal to which a second input signal is input, a first output terminal and a second output terminal that respectively output a first output signal and a second output signal corresponding to the first input signal and the second input signal; An RC filter that filters and outputs the first output signal and the second output signal output from the first output terminal and the second output terminal of the first differential amplifier circuit; A second differential amplifier circuit having a third input terminal and a fourth input terminal to which the first output signal and the second output signal filtered by the RC filter are respectively input, and a third output terminal that outputs a third output signal corresponding to the first output signal and the second output signal; A third amplifier circuit having a fifth input terminal to which the third output signal output from the second differential amplifier circuit is input, and a fourth output terminal that outputs a fourth output signal corresponding to the third output signal. A differential amplifier.

2. A first feedback capacitor having one end connected to a node between the RC filter and the third input terminal of the second differential amplifier circuit, and the other end connected to the fourth output terminal of the third amplifier circuit; The differential amplifier according to claim 1, further comprising a second feedback capacitor having one end connected to a node between the third output terminal of the second differential amplifier circuit and the fifth input terminal of the third amplifier circuit, and the other end connected to the fourth output terminal of the third amplifier circuit. The differential amplifier according to claim 1.

3. The RC filter has a filter section including a filter capacitor and a filter resistor connected in series, The filter section is connected between the first differential amplifier circuit and the second differential amplifier circuit so as not to be in a parallel connection relationship with the first feedback capacitor and the second feedback capacitor. The differential amplifier according to claim 2.

4. The filter section includes a first filter section having one end connected to a node between the first output terminal of the first differential amplifier circuit and the third input terminal of the second differential amplifier circuit, and the other end connected to a node between the second output terminal of the first differential amplifier circuit and the fourth input terminal of the second differential amplifier circuit; and a second filter section having one end connected between the second output terminal of the first differential amplifier circuit and the node to which the other end of the first filter section is connected, and the other end connected between the node to which the one end of the first filter section is connected and the third input terminal of the second differential amplifier circuit. The differential amplifier according to claim 3.

5. The filter unit is a first filter unit having one end connected to a node between the first output terminal of the first differential amplification circuit and the third input terminal of the second differential amplification circuit and the other end connected to a reference potential; a second filter unit having one end connected to a node between the second output terminal of the first differential amplification circuit and the fourth input terminal of the second differential amplification circuit and the other end connected to a reference potential, and includes The differential amplifier according to claim 3.

6. The filter unit is a first filter resistor having one end connected to a node between the first output terminal of the first differential amplification circuit and the third input terminal of the second differential amplification circuit; a second filter resistor having one end connected to a node between the second output terminal of the first differential amplification circuit and the fourth input terminal of the second differential amplification circuit; and a first filter capacitor and a second filter capacitor connected in parallel between the other end of the first filter resistor and the other end of the second filter resistor. The differential amplifier according to claim 3.

7. The filter unit is a first filter capacitor having one end connected to a node between the first output terminal of the first differential amplification circuit and the third input terminal of the second differential amplification circuit; a second filter capacitor having one end connected to a node between the second output terminal of the first differential amplification circuit and the fourth input terminal of the second differential amplification circuit; and a filter resistor connected between the other end of the first filter capacitor and the other end of the second filter capacitor. The differential amplifier according to claim 3.

8. The RC filter further includes a first buffer having an input connected to the first output terminal of the first differential amplification circuit and an output connected to the third input terminal of the second differential amplification circuit; and a second buffer having an input connected to the second output terminal of the first differential amplification circuit and an output connected to the fourth input terminal of the second differential amplification circuit. The differential amplifier according to any one of claims 3 to 7.

9. The third output terminal of the second differential amplification circuit includes a positive third output terminal and a negative third output terminal that respectively output a third non-inverted output signal and a third inverted output signal corresponding to the first output signal and the second output signal; the fifth input terminal of the third amplification circuit includes a positive fifth input terminal to which the third non-inverted output signal is input; and a negative fifth input terminal to which the third inverted output signal is input; the fourth output terminal of the third amplification circuit A negative fourth output terminal and a positive fourth output terminal that respectively output a fourth inverted output signal and a fourth non-inverted output signal according to the third non-inverted output signal and the third inverted output signal are included. One end of the first feedback capacitor is connected to a node between the RC filter and the third input terminal of the second differential amplifier circuit, and the other end is connected to the negative fourth output terminal of the third amplifier circuit. One end of the second feedback capacitor is connected to a node between the positive third output terminal of the second differential amplifier circuit and the positive fifth input terminal of the third amplifier circuit, and the other end is connected to the negative fourth output terminal of the third amplifier circuit. The differential amplifier further includes a third feedback capacitor having one end connected to a node between the RC filter and the fourth input terminal of the second differential amplifier circuit and the other end connected to the positive fourth output terminal of the third amplifier circuit; and a fourth feedback capacitor having one end connected to a node between the negative third output terminal of the second differential amplifier circuit and the negative fifth input terminal of the third amplifier circuit and the other end connected to the positive fourth output terminal of the third amplifier circuit. The differential amplifier according to claim 2.

10. further includes a third feedback capacitor having one end connected to a node between the RC filter and the fourth input terminal of the second differential amplifier circuit and the other end connected to a reference potential. The differential amplifier according to claim 1.

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