Electro-optical device and electronic apparatus

Abstract

To prevent occurrence of display failure due to an increase in diffusion of ion components during manufacture of an electro-optical device.SOLUTION: An electro-optical device comprises: a substrate; a first insulating layer provided on one side of the substrate; a first electrode and a second electrode provided on the substrate on the opposite side of the first insulating layer; a second insulating layer covering the first electrode; and a third insulating layer covering the second electrode. The height of the second insulating layer from the substrate is higher than the height of the third insulating layer from the substrate. A step is provided between the first electrode and the second electrode.SELECTED DRAWING: Figure 5B

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] In display devices such as projectors and electronic devices, liquid crystal devices such as liquid crystal panels are used as light modulation devices that modulate incident light according to image information and emit image light. For example, in a transmissive liquid crystal device, a liquid crystal layer is provided between a first substrate having a light-transmissive pixel electrode and a second substrate having a light-transmissive counter electrode. The light incident from the second substrate is modulated by the liquid crystal layer and emitted from the first substrate.

[0003] The pixel electrode is electrically connected to a transistor formed between the pixel electrode and the element substrate on the first substrate. The transistor on the first substrate functions as a switching element for modulating the color light incident on the pixel and converting it into image light.

[0004] For example, in Patent Document 1 below, in order to reduce the contact resistance between the pixel electrode and the transistor and the sheet resistance of the pixel electrode, there is disclosed an electro-optical device having a metal layer provided on one surface side of the element substrate and a pixel electrode in contact with the metal layer on the side opposite to the element substrate. The pixel electrode disclosed in Patent Document 1 includes a light-transmissive first metal oxide layer in contact with the metal layer and a light-transmissive second metal oxide layer laminated on the side opposite to the metal layer with respect to the first metal oxide layer. The oxygen content of the second metal oxide layer is larger than that of the first metal oxide layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the electro-optical device disclosed in Patent Document 1 above, ionic impurities may diffuse from the outside of the display region including the region where dummy pixels are arranged toward the display region during manufacturing or the like. In that case, in the electro-optical device, display defects such as corner shading, display unevenness, and image sticking due to the diffusion of ionic impurities may occur.

[0007] In the electro-optical device disclosed in Patent Document 1 above, no particular countermeasure is taken against the diffusion of ionic impurities into the display region, and there was a possibility that display defects caused by the diffusion of ionic impurities would occur. That is, there has been a demand for a countermeasure to prevent the occurrence of display defects caused by the diffusion of ionic impurities from the outside of the display region into the display region in a plan view.

Means for Solving the Problems

[0008] In order to solve the above problems, an electro-optical device according to one aspect of the present invention includes a substrate, a first insulating layer provided on one side of the substrate, a first electrode and a second electrode provided on the side of the first insulating layer opposite to the substrate, a second insulating layer covering the first electrode, and a third insulating layer covering the second electrode, and the height of the second insulating layer from the substrate is higher than the height of the third insulating layer from the substrate.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 5A

Figure 5B

Figure 5C

Figure 6

Figure 7A

Figure 7B

Figure 8

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, in order to make each component easy to see, the scale of the dimensions may be different depending on the component.

[0011] In the drawings, as necessary, the X-axis, the Y-axis, and the Z-axis are shown as three mutually orthogonal axes. Also, one direction along the X-axis is described as the +X direction, and the direction opposite to the +X direction is denoted as the -X direction. Similarly, one direction along the Y-axis is denoted as the +Y direction, and the direction opposite to the +Y direction is described as the -Y direction. One direction along the Z-axis is denoted as the +Z direction, and the direction opposite to the +Z direction is described as the -Z direction. Also, the plane including the X-axis and the Y-axis may be described as the "XY plane", and viewing the XY plane along the Z-axis may be described as "planar view".

[0012] In the following description, for example, with respect to a substrate, the description "on the substrate" means any of the following cases: when it is disposed in contact with the upper surface of the substrate, when it is disposed on the upper surface of the substrate via a component such as a structure other than the substrate, and when a part of it is disposed in contact with the upper surface of the substrate and the other part is disposed via a component other than the substrate. Further, the material and film thickness of each component of the electro-optical device are not limited to the exemplified materials and film thicknesses, unless otherwise described for suitable reasons or the like.

[0013] In one embodiment of the present invention, as an electro-optical device, an active driving type liquid crystal device including a thin film transistor (TFT) as a switching element for each pixel will be described as an example. Hereinafter, the thin film transistor may be abbreviated as TFT. The liquid crystal device is suitably used, for example, as a light modulation device in a projector as an electronic device described later.

[0014] (Outline of the physical structure of the liquid crystal device) FIG. 1 is a plan view of a liquid crystal device 100 of the present embodiment. FIG. 2 is a cross-sectional view of the liquid crystal device 100, which is a cross-sectional view when viewed in the direction of the line H-H' shown in FIG. 1. As shown in FIGS. 1 and 2, the liquid crystal device 100 includes a first substrate 10, a second substrate 20, and a liquid crystal layer 5. The second substrate 20 is disposed so as to face the first substrate 10. The liquid crystal layer 5 is sandwiched between the first substrate 10 and the second substrate 20 along the Z-axis and functions as an electro-optical layer of the liquid crystal device 100. The liquid crystal layer 5 contains a plurality of liquid crystals (not shown).

[0015] For the element substrate 111 of the first substrate 10 and the counter substrate 112 of the second substrate 20, a substrate formed of a material capable of transmitting the color light incident on the liquid crystal device 100 is used. For example, a substrate such as a glass substrate or a quartz substrate is used.

[0016] When viewed in plan view, the width of the first substrate 10 on the X-axis and the width on the Y-axis are larger than those of the second substrate 20. The first substrate 10 and the second substrate 20 are joined in the Z-axis direction via a sealing material 6 disposed along the outer edge of the second substrate 20. Liquid crystal having positive or negative dielectric anisotropy is encapsulated in the space surrounded by the first substrate 10, the second substrate 20, and the sealing material 6, and a liquid crystal layer 5 is provided.

[0017] When viewed in plan view, a display area E including a plurality of pixels P is provided inside the sealing material 6. The plurality of pixels P are arranged in a matrix along the X-axis and the Y-axis. When viewed in plan view, the area outside the display area E is a peripheral area F. When viewed in plan view, a dummy pixel DP is provided in a first peripheral area F1 between the sealing material 6 and the display area E in the peripheral area F. The first peripheral area F1 surrounds the display area E in the XY plane. The dummy pixel DP is arranged in the area closest to the display area E in the first peripheral area F1. The area where the dummy pixel DP is arranged is a dummy pixel area DF that does not contribute to display.

[0018] When viewed in plan view, a partition material 23 surrounding the display area E is provided in the first peripheral area F1. For example, an inspection circuit 41 is provided in the area between the sealing material 6 on one side extending along the X-axis and disposed on the +Y direction side in the Y-axis and the display area E in the first peripheral area F1. A scanning line driving circuit 45 is provided in the area between each of the sealing materials 6 on two sides extending along the X-axis and the display area E in the first peripheral area F1. A plurality of wirings 49 connecting the two scanning line driving circuits 45 to each other are provided in the area between the sealing material 6 and the inspection circuit 41 in the first peripheral area F1.

[0019] In the second peripheral region F2 of the first substrate 10 outside the sealing material 6 in the peripheral region F, a plurality of external connection terminals 43 are provided. The plurality of external connection terminals 43 extend along the X-axis, for example, and are arranged at intervals along the X-axis in the second peripheral region F2 on the -Y direction side in the Y-axis. When viewed in plan, in the second peripheral region F2, a data line driving circuit 47 is provided between the region where the plurality of external connection terminals 43 are arranged and the sealing material 6 extending along the X-axis.

[0020] The wiring 49 is connected to the data line driving circuit 47 and the scanning line driving circuit 45 and is connected to the plurality of external connection terminals 43. Note that the inspection circuit 41 may be arranged in a region different from the above-described region, that is, the region between the sealing material 6 on one side extending along the X-axis and arranged on the +Y direction side in the Y-axis and the display region E.

[0021] As shown in FIG. 2, on the surface of the element substrate 111 as the base material of the first substrate 10 facing the liquid crystal layer 5, a thin film transistor 30, an inspection circuit 41, a wiring 49, and an alignment film 12 are provided. The thin film transistor 30 is a switching element provided for each pixel P. The alignment film 12 covers the pixel electrode 11, the thin film transistor 30, and the wiring 49.

[0022] The thin film transistor 30 and the pixel electrode 11 are components of the pixel P. The first substrate 10 includes the element substrate 111, the pixel electrode 11, the thin film transistor 30, the wiring 49, and the alignment film 12, and is constituted by these components and the inspection circuit 41.

[0023] On the surface of the counter substrate 112 as the base material of the second substrate 20 facing the liquid crystal layer 5, a partition material 23, an insulating layer 25, a counter electrode 21, and an alignment film 22 are provided. The insulating layer 25 covers the partition material 23. The counter electrode 21 is arranged as a common electrode provided to cover the insulating layer 25. The alignment film 22 covers the counter electrode 21. The second substrate 20 includes the partition material 23, the counter electrode 21, and the alignment film 22, and is composed of these components and the insulating layer 25. Note that the counter electrode 21, which is a common electrode, is provided on the second substrate 20 as an example, but it may be provided on the first substrate 10. For example, an insulating layer (not shown) that covers the thin film transistor 30, the inspection circuit 41, and the wiring 49 may be provided, and the counter electrode 21 may be provided between the aforementioned insulating layer (not shown) and the alignment film 12.

[0024] As shown in FIG. 1 in plan view, the scanning line driving circuit 45 and the inspection circuit 41 overlap the partition material 23. The partition material 23 functions as a light shielding portion. The light L is emitted from a light source device (not shown) and enters the liquid crystal device 100 from the second substrate 20 along the -Y direction. The partition material 23 shields light so that the light L does not enter peripheral circuits such as the scanning line driving circuit 45. By providing the partition material 23, malfunction of the peripheral circuits is prevented. The partition material 23 shields light so that unnecessary stray light does not enter the display region E. By providing the partition material 23, a decrease in contrast in the liquid crystal device 100 is suppressed.

[0025] The insulating layer 25 is formed of an inorganic material such as silicon oxide (SiO2) having translucency with respect to the light L, for example. The surface of the insulating layer 25 in contact with the liquid crystal layer 5 is a flat surface parallel to the XY plane.

[0026] The conduction member 7 is provided at the four corners of the sealant 6 in plan view and extends along the Z axis. The counter electrode 21 is electrically connected to the conduction member 7. The conduction member 7 is electrically connected to a common wiring 18 described later.

[0027] The pixel electrode 11 and the counter electrode 21 are formed of a transparent conductive film such as, for example, ITO (Indium Tin Oxide; ITO) or IZO (Indium Zinc Oxide; IZO). The materials of the alignment films 12 and 22 are selected based on the optical design of the liquid crystal device 100. Examples of the materials of the alignment films 12 and 22 include inorganic compounds such as silicon oxide, or organic compounds such as polyimide.

[0028] In the liquid crystal device 100, an optical design of a normally white mode or a normally black mode is adopted. In the normally white mode, the transmittance of the pixel P in a state where no voltage is applied is larger than the transmittance when a voltage is applied. In the normally black mode, the transmittance of the pixel P in a state where no voltage is applied is smaller than the transmittance when a voltage is applied. Hereinafter, in the liquid crystal device 100, a case where an optical design of the normally black mode is adopted will be assumed and described. Note that, depending on the optical design of the liquid crystal device 100, polarizing elements (not shown) are disposed in each of the space on the incident side of the light L and the space on the emission side with respect to the liquid crystal device 100.

[0029] (Outline of the electrical structure of the liquid crystal device) FIG. 3 is an equivalent circuit diagram of the liquid crystal device 100. As shown in FIG. 3, in the liquid crystal device 100, a plurality of scanning lines 13, a plurality of data lines 16, and a plurality of common wirings 18 are provided on the element substrate 111 of the first substrate 10. The plurality of scanning lines 13 extend in parallel with the X axis. The plurality of data lines 16 and the plurality of common wirings 18 extend in parallel with the Y axis. The plurality of data lines 16 intersect at least the plurality of scanning lines 13. That is, the direction in which the scanning lines 13 extend and the direction in which the data lines 16 extend are different from each other. Note that the plurality of common wirings 18 do not necessarily extend along the Y axis, and the direction in which the common wirings 18 extend is not limited to a specific direction.

[0030] The pixel P is partitioned by a scanning line 13 extending along the X axis and a data line 16 extending along the Y axis. The pixel P is provided with a pixel electrode 11, a thin film transistor 30, a sixth relay electrode 50, and a capacitive element 60.

[0031] The scanning line 13 is electrically connected to the gate of the thin film transistor 30. The data line 16 is electrically connected to the source of the thin film transistor 30. The scanning line 13 controls the on and off of the thin film transistors 30 provided in the same row all at once. The pixel electrode 11 is electrically connected to the drain of the thin film transistor 30.

[0032] The data line 16 is electrically connected to the data line driving circuit 47, and supplies the image signals D1, D2, ···, Dn supplied from the data line driving circuit 47 to the pixel P. The scanning line 13 is electrically connected to the scanning line driving circuit 45, and supplies the scanning signals SC1, SC2, ···, SCm supplied from the scanning line driving circuit 45 to each pixel P.

[0033] The image signals D1 to Dn supplied from the data line driving circuit 47 to the data line 16 may be sequentially supplied, or may be supplied collectively for each group of a plurality of adjacent data lines 16. The scanning line driving circuit 45 sequentially supplies the scanning signals SC1 to SCm to the scanning line 13 as pulses at a predetermined timing.

[0034] When the scanning signal SC1 is input to the thin film transistor 30, the TFT30 is turned on for a certain period. As a result, the image signal D1 supplied from the data line 16 is written to the pixel electrode 11 at a predetermined timing. The image signal D1 at a predetermined level written to the liquid crystal layer 5 via the pixel electrode 11 is held for a certain period between the pixel electrode 11 and the counter electrode 21 arranged opposite to each other via the liquid crystal layer 5.

[0035] A capacitance element 60 is connected in parallel and electrically to the liquid crystal capacitance provided between the pixel electrode 11 and the counter electrode 21. This prevents the leakage of the image signal D1 held in the liquid crystal layer 5. One end of the capacitance element 60 is electrically connected to the drain of the TFT30 and the pixel electrode 11. The other end of the capacitance element 60 is electrically connected to the common wiring 18 to which a fixed potential is applied.

[0036] Although omitted in FIG. 3, an inspection circuit 41 is connected to the data line 16. Therefore, in the manufacturing process of the liquid crystal device 100, by detecting the image signals D1, D2, ···, Dn, it is possible to confirm malfunctions and the like in the operation of the liquid crystal device 100.

[0037] (Outline of the electrical structure of the liquid crystal element) FIG. 4A is a plan view of the pixel P of the liquid crystal device 100. FIG. 4B is a cross-sectional view of the pixel P, which is a view taken in the direction of the arrow along the line C1-C1 shown in FIG. 4A. FIG. 4C is another cross-sectional view of the pixel P, which is a view taken in the direction of the arrow along the line C2-C2 shown in FIG. 4A. FIG. 4D is a cross-sectional view of the pixel P, which is a view taken in the direction of the arrow along the line C3-C3 shown in FIG. 4A. In each of the figures from FIG. 4B to FIG. 4D, the upper structure of the pixel P described later is omitted.

[0038] As shown in FIGS. 4A to 4D, on the element substrate 111, a first conductive layer 121, a second conductive layer 122, a third conductive layer 123, a semiconductor layer 31, a fourth conductive layer 124, a fifth conductive layer 125, a sixth conductive layer 126, a seventh conductive layer 127, and a pixel electrode 11 are sequentially stacked in the +Z direction.

[0039] The first conductive layer 121 includes the second capacitive electrode 62 of the capacitive element 60. The second conductive layer 122 includes the first capacitive electrode 61 of the capacitive element 60. The third conductive layer 123 includes the scanning line 13. The semiconductor layer 31 and the fourth conductive layer 124 constitute the thin film transistor 30. The thin film transistor 30 employs a top gate structure and an LDD (Lightly Doped Drain) structure. The semiconductor layer 31 has a semiconductor layer 31A in the first region RA, a semiconductor layer 31B in the second region RB, and a semiconductor layer 31C in the third region RC. The fourth conductive layer 124 includes the gate electrode 32 of the thin film transistor 30. An insulating film 133 as a gate insulating film 33 is provided between the semiconductor layer 31 and the gate electrode 32 of the fourth conductive layer 124.

[0040] The semiconductor layer 31A is provided adjacent to the gate electrode 32 of the fourth conductive layer 124 via the gate insulating film 33 on the Z axis. That is, the semiconductor layer 31A is disposed below the gate electrode 32 with the gate insulating film 33 interposed therebetween. The semiconductor layer 31B is adjacent to the semiconductor layer 31A on the Y axis among the semiconductor layers 31, and is provided on the +Y direction side and the -Y direction side of the semiconductor layer 31A. Impurities such as phosphorus (P) are implanted in the semiconductor layer 31B. The semiconductor layer 31C includes the remaining portions of the semiconductor layer 31 other than the semiconductor layers 31A and 31B, is adjacent to the semiconductor layer 31B on the Y axis, and is provided on the +Y direction side and the -Y direction side of the semiconductor layer 31B. Similar to the semiconductor layer 31B, impurities such as phosphorus are implanted in the semiconductor layer 31C. However, the impurity concentration of the semiconductor layer 31C in the third region RC is higher than the impurity concentration of the semiconductor layer 31B in the second region RB.

[0041] The semiconductor layers 31B and 31C provided on the +Y direction side of the gate electrode 32 on the Y axis constitute one of the drain region and the source region of the thin film transistor 30, and constitute the drain region 31d in the present embodiment. The semiconductor layers 31B and 31C provided on the -Y direction side of the gate on the Y axis constitute the other of the drain region and the source region of the thin film transistor 30, and constitute the source region 31s in the present embodiment.

[0042] That is, impurities are added to the semiconductor layer 31C in the third region RC at a predetermined concentration required for the drain region and the source region of the thin film transistor 30. Impurities are added to the semiconductor layer 31B in the second region RB at a concentration lower than the predetermined concentration as described above. The semiconductor layer 31B constitutes the LDD 31l. By disposing the semiconductor layer 31B, the impurity distribution and the electric field of the source-drain diffusion layer are relaxed during the operation of the thin film transistor 30, and the deterioration of the thin film transistor 30 is suppressed.

[0043] The fifth conductive layer 125 includes the sixth relay electrode 50. The sixth conductive layer 126 includes the data line 16. The seventh conductive layer 127 includes the common wiring 18.

[0044] A second dielectric film 63 is provided between the first conductive layer 121 which is the second capacitance electrode 62 and the second conductive layer 122 which is the first capacitance electrode 61. A first interlayer insulating layer 71 is provided between the second conductive layer 122 and the third conductive layer 123. A second interlayer insulating layer 72 is provided between the third conductive layer 123 and the semiconductor layer 31. A third interlayer insulating layer 73 as the second insulating layer is provided between the fourth conductive layer 124 and the fifth conductive layer 125. A fourth interlayer insulating layer 74 as the first insulating layer is provided between the fifth conductive layer 125 and the sixth conductive layer 126. A fifth interlayer insulating layer 75 is provided between the sixth conductive layer 126 and the seventh conductive layer 127.

[0045] As shown in FIG. 4B, the capacitor element 60 has a first capacitance electrode 61 disposed on the side closer to the scanning line 13 on the Z axis, that is, on the +Z direction side, and a second capacitance electrode 62 disposed on the side closer to the element substrate 111 than the first capacitance electrode 61 on the Z axis, that is, on the -Z direction side.

[0046] As shown in FIGS. 4C and 4D, the first capacitance electrode 61 of the capacitor element 60 is electrically connected to the common wiring 18 via a first relay electrode 81 included in the sixth conductive layer 126 and a second relay electrode 82 included in the fourth conductive layer 124.

[0047] As shown in FIG. 4C, the common wiring 18 and the second relay electrode 82 are electrically connected via the first relay electrode 81 disposed in the sixth conductive layer 126. As shown in FIG. 4C, the second relay electrode 82 is electrically connected to an extension portion 61t of the first capacitance electrode 61 of the capacitor element 60. The extension portion 61t is a part of the first capacitance electrode 61 as will be described later.

[0048] The sixth relay electrode 50 and the second capacitance electrode 62 of the capacitor element 60 are electrically connected to the pixel electrode 11 and the drain region 31d of the thin film transistor 30. As shown in FIG. 4D, the pixel electrode 11 is electrically connected to a third relay electrode 83 included in the seventh conductive layer 127.

[0049] As shown in FIG. 4C, the third relay electrode 83 is electrically connected to the fourth relay electrode 84 included in the sixth conductive layer 126. The fourth relay electrode 84 is electrically connected to the sixth relay electrode 50. As shown in FIG. 4B, the sixth relay electrode 50 is electrically connected to the fifth relay electrode 85 included in the fourth conductive layer 124. The fifth relay electrode 85 is electrically connected to the second capacitive electrode 62 of the capacitive element 60.

[0050] Signal wirings such as the scanning line 13 and the common wiring 18, the thin film transistor 30, and electrodes such as the first relay electrode 81 are provided in a light-shielding region SD that planar-ly partitions a plurality of pixels P. The light-shielding region SD includes a linear portion including the scanning line 13 extending along the X axis and a linear portion including the data line 16 extending along the Y axis, and is provided in a lattice pattern in plan view.

[0051] (Outline of the upper structure of the pixel and the dummy pixel) FIG. 5A is a plan view of the upper structure of the pixel P and the dummy pixel DP of the liquid crystal device 100. FIG. 5B is a cross-sectional view of the upper structure of the pixel P and the dummy pixel DP, and is a view taken in the arrow direction along the line C4-C4 shown in FIG. 5A. FIG. 5C is a cross-sectional view of a modified example of the upper structure of the pixel P and the dummy pixel DP. The upper structure means a structure formed on the +Z direction side of the fifth interlayer insulating layer 75 including the seventh conductive layer 127 on the Z axis.

[0052] As shown in FIGS. 5A and 5B, the sixth interlayer insulating layer 76 is formed on the seventh conductive layer 127 provided on the upper part of the first substrate 10 in the display region E, that is, on the +Z direction side portion of the first substrate 10. The sixth interlayer insulating layer 76 is also formed on the seventh conductive layer 127 provided on the upper part of the first substrate 10 in the dummy pixel region DF outside the display region E in plan view, that is, on the +Z direction side portion of the first substrate 10.

[0053] In the dummy pixel region DF, in order to prevent the occurrence of display defects such as color unevenness in the liquid crystal device 100, a structure similar to the structure of the pixel P on the -Z direction side from the upper structure is formed on the element substrate 111.

[0054] For each of a plurality of pixels P in the display area E, a pixel electrode 11 is provided. The pixel electrode 11 is provided on the sixth interlayer insulating layer 76 of the opening region AR11 partitioned as the pixel P in plan view. The pixel electrode 11 has a first electrode layer 311 and a second electrode layer 312.

[0055] The first electrode layer 311 is disposed in plan view only in a region corresponding to the end portion on the -Y direction side of the opening region AR11 and the central portion of the opening region AR11 on the X axis, and overlaps with the extending portion 83t of the third relay electrode 83 of the pixel P.

[0056] In FIG. 5B, illustration of the steps of the common wiring 18 and the third relay electrode 83 included in the seventh conductive layer 127 in the Z axis direction is omitted. The first electrode layer 311 is connected to the extending portion 83t of the third relay electrode 83 of the pixel P by a contact hole CNT11 formed at the end portion on the -Y direction side of the opening region AR11 and the central portion on the X axis in plan view, and is electrically connected to the third relay electrode 83 of the pixel P.

[0057] The first electrode layer 311 is formed on the sixth interlayer insulating layer 76 in the vicinity of the periphery of the end portion on the -Y direction side of the opening region AR11 and the central portion on the X axis in plan view. Therefore, the first electrode layer 311 is also provided on the sixth interlayer insulating layer 76 forming the wall surface and the bottom of the contact hole CNT11.

[0058] The thickness s1 of the first electrode layer 311 formed on the surface parallel to the XY plane of the sixth interlayer insulating layer 76, that is, the height in the Z axis direction, is larger than the thickness s2 of the first electrode layer 311 formed on the wall surface and the bottom of the contact hole CNT11, that is, the height in the XY plane or the Z axis direction. The first electrode layer 311 is made of a transparent conductor such as ITO, for example.

[0059] The second electrode layer 312 is formed in a region that overlaps with the first electrode layer 311 in plan view, and covers the entire surface of the first electrode layer 311 that is exposed from the sixth interlayer insulating layer 76. The second electrode layer 312 is provided over the entire opening region AR11 including the region that overlaps with the first electrode layer 311 in plan view. As described above, the second electrode layer 312 covers the first electrode layer 311 from the +Z direction side, and also covers the surface of the sixth interlayer insulating layer 76 in the region of the opening region AR11 where the first electrode layer 311 is not provided in plan view.

[0060] The second electrode layer 312 is provided in the opening region AR11 with a substantially constant thickness. The thickness of the second electrode layer 312 formed to cover the first electrode layer 311, that is, the height in the XY plane or the Z-axis, is equal to the thickness of the second electrode layer 312 on the sixth interlayer insulating layer 76 in the region of the opening region AR11 where the first electrode layer 311 is not provided in plan view, that is, the height in the Z-axis.

[0061] The thickness s3 of the second electrode layer 312 is smaller than the thickness s1 of the first electrode layer 311 and is equal to the thickness s2 of the first electrode layer 311. The second electrode layer 312 is made of a transparent conductor having a higher oxygen content than a transparent conductor such as ITO that constitutes the first electrode layer 311. The thickness s1 of the first electrode layer 311 is, for example, about 140 nm. In that case, the thickness s3 of the second electrode layer 312 is, for example, about 10 nm to 20 nm.

[0062] In the opening region AR11 of the pixel P in the display region E, in plan view, the area of the region corresponding to the -Y direction side end and the central portion in the X-axis where the first electrode layer 311 is provided is significantly smaller than the region where the first electrode layer 311 is not provided. That is, in most regions of the opening region AR11, the first electrode layer 311 is not provided, and only the second electrode layer 312 is provided thinner than the first electrode layer 311. Therefore, the transmittance of the light L incident from the +Z direction side of the first substrate 10, that is, from the alignment film 12 side (not shown in the figure) toward the element substrate 111, is improved compared to the case where the first electrode layer 311 is provided over the entire opening region AR11.

[0063] In order to increase the transmittance of the light L incident on the liquid crystal device 100 from the +Z direction side as described above, the thickness s3 of the second electrode layer 312 is 1 / 5 or less of the thickness s1 of the first electrode layer 311, preferably 1 / 8 or less, and more preferably 1 / 10 or less.

[0064] For each of the plurality of dummy pixels DP in the dummy pixel region DF, a first dummy pixel electrode 15A and a second dummy pixel electrode 15B are provided. The first dummy pixel electrode 15A is provided outside the dummy pixel region DF rather than the pixel electrode 11 in a plan view. The second dummy pixel electrode 15B is provided outside the dummy pixel region DF rather than the first dummy pixel electrode 15A in a plan view.

[0065] In addition, in the present embodiment, the first dummy pixel electrode 15A and the second dummy pixel electrode 15B are arranged side by side one by one toward the outside of the dummy pixel region DF, but two or more first dummy pixel electrodes 15A may be arranged side by side outside the pixel electrode 11. Also, two or more second dummy pixel electrodes 15B may be arranged side by side outside the first dummy pixel electrode 15A.

[0066] The first dummy pixel electrode 15A and the second dummy pixel electrode 15B are provided on the sixth interlayer insulating layer 76 of the opening region AR15 partitioned as the dummy pixel DP in a plan view. The shapes of the first dummy pixel electrode 15A and the second dummy pixel electrode 15B when viewed in a plan view are different from the shape of the pixel electrode 11 when viewed in a plan view. The first dummy pixel electrode 15A and the second dummy pixel electrode 15B have a first dummy pixel electrode layer 315 and a second dummy pixel electrode layer 316.

[0067] The first dummy pixel electrode layer 315 is arranged only in a region corresponding to the end on the -Y direction side of the opening region AR15 and the central portion of the opening region AR15 on the X axis in a plan view, and overlaps with the extending portion 83t of the third relay electrode 83 of the dummy pixel DP.

[0068] The first dummy pixel electrode layer 315 that constitutes the first dummy pixel electrode 15A is connected to the extending portion 83t of the third relay electrode 83 of the dummy pixel DP by a contact hole CNT15 formed at the end on the -Y direction side of the opening region AR15 and at the central portion on the X axis in a plan view, and is electrically connected to the third relay electrode 83 of the dummy pixel DP. Note that the contact hole CNT15 is formed simultaneously with the contact hole CNT11 in the process of forming the contact hole CNT11 in the sixth interlayer insulating layer 76.

[0069] The first dummy pixel electrode layer 315 is formed substantially over the entire opening region AR15 in a plan view. The first dummy pixel electrode layer 315 is also provided on the sixth interlayer insulating layer 76 that forms the wall surface and the bottom of the contact hole CNT15. The shape and area of the opening region AR15 forming the dummy pixel DP in a plan view are substantially the same as the shape and area of the opening region AR11 forming the pixel P in a plan view. In a plan view, the first dummy pixel electrode layer 315 is larger than the first electrode layer 311.

[0070] The thickness s4 of the first dummy pixel electrode layer 315 formed on the surface parallel to the XY plane of the sixth interlayer insulating layer 76, that is, the height on the Z axis, is equivalent to the thickness s1 of the first electrode layer 311, and the thickness s5 of the first dummy pixel electrode layer 315 formed on the wall surface and the bottom of the contact hole CNT15, that is, the height on the XY plane or the Z axis, is larger. The first dummy pixel electrode layer 315 is formed of a transparent conductor such as ITO, for example, and is formed of the same material as the first electrode layer 311.

[0071] The first dummy pixel electrode layer 315 that constitutes the second dummy pixel electrode 15B has basically the same configuration as the first dummy pixel electrode layer 315 that constitutes the first dummy pixel electrode 15A, except that the contact hole CNT15 is omitted. That is, the first dummy pixel electrode layer 315 that constitutes the second dummy pixel electrode 15B is formed on the sixth interlayer insulating layer 76 without being electrically connected to the third relay electrode 83 of the dummy pixel DP.

[0072] The second dummy pixel electrode layer 316 is formed over the entire opening region AR15 in plan view, covering all the surfaces exposed from the sixth interlayer insulating layer 76 in the first dummy pixel electrode layer 315.

[0073] The second dummy pixel electrode layer 316 is provided with a substantially constant thickness in the opening region AR15. The thickness s6 of the second dummy pixel electrode layer 316 formed to cover the first dummy pixel electrode layer 315, that is, the height in the XY plane or the Z axis, is smaller than the thickness s4 of the first dummy pixel electrode layer 315 and is equivalent to the thickness s5 of the first dummy pixel electrode layer 315 and the thickness s3 of the second electrode layer 312.

[0074] The second dummy pixel electrode layer 316 is made of a transparent conductor having a higher oxygen content than a transparent conductor such as ITO constituting the first dummy pixel electrode layer 315, and is made of the same material as the second electrode layer 312. The thickness s4 of the first dummy pixel electrode layer 315 is, for example, about 140 nm. In that case, the thickness s6 of the second dummy pixel electrode layer 316 is, for example, about 10 nm.

[0075] As shown in FIG. 5B, the alignment film 12 is provided on the sixth interlayer insulating layer 76 so as to cover each of the pixel electrode 11, the first dummy pixel electrode 15A, and the second dummy pixel electrode 15B. The alignment film 12 has a vertical deposition layer 317 provided on the pixel electrode 11 and the first dummy pixel electrode 15A, and an oblique deposition layer 318 provided on the vertical deposition layer 317 and the second dummy pixel electrode 15B.

[0076] The vertical deposition layer 317 is a layer for planarizing the pixel electrode 11, and is formed, for example, by depositing an inorganic compound such as silicon oxide from a direction perpendicular to the first substrate 10. The vertical deposition layer 317 is provided with a thickness sufficient to planarize the pixel electrode 11 and the first dummy pixel electrode 15A.

[0077] The oblique vapor deposition layer 318 is a layer for controlling the alignment of the liquid crystal in the liquid crystal layer 5, and is formed by vapor depositing an inorganic compound such as silicon oxide on the first substrate 10 from an oblique direction. The thickness of the oblique vapor deposition layer 318 is smaller than the thickness of the vertical vapor deposition layer 317.

[0078] On the first dummy pixel electrode 15A, the vertical vapor deposition layer 317 and the oblique vapor deposition layer 318 are sequentially laminated and provided. On the second dummy pixel electrode 15B, the oblique vapor deposition layer 318 is provided. As a result, the height of the alignment film 12 provided on the first dummy pixel electrode 15A is higher than the height of the alignment film 12 provided on the second dummy pixel electrode 15B by the thickness of the vertical vapor deposition layer 317. The "height of the alignment film 12" is the shortest distance from the surface of the element substrate 111 on the alignment film 12 side to the surface of the alignment film 12 on the liquid crystal layer 5 side in the direction along the Z axis. The direction along the Z axis is the normal direction of the substrate surface of the element substrate 111.

[0079] A step ST is provided between the first dummy pixel electrode 15A and the second dummy pixel electrode 15B. The step ST forms a concave space TR between the first dummy pixel electrode 15A and the second dummy pixel electrode 15B.

[0080] Since the oblique vapor deposition layer 318 is obliquely vapor deposited toward the outside of the dummy pixel region DF, it is formed so as to cover the bottom surface of the step ST and the side surface of the second dummy pixel electrode 15B facing the step ST. On the side surface of the vertical vapor deposition layer 317 facing the step ST, the side surface of the vertical vapor deposition layer 317 is exposed without the oblique vapor deposition layer 318 being formed. As a result, the oblique vapor deposition layer 318 provided on the step ST is separated from the oblique vapor deposition layer 318 provided on the vertical vapor deposition layer 317 and is connected to the oblique vapor deposition layer 318 provided on the second dummy pixel electrode.

[0081] In the manufacturing process of the liquid crystal device, ionic impurities IO may diffuse from the sealing material 6 or the like through the first peripheral region F1 and the dummy pixel region DF toward the liquid crystal layer 5 in the display region E.

[0082] In the liquid crystal device 100 of the present embodiment, as described above, a step ST is provided between the first dummy pixel electrode 15A and the second dummy pixel electrode 15B, and this step ST forms a concave space TR. Further, across the step ST, the height of the alignment film 12 provided on the first dummy pixel electrode 15A is higher than the height of the alignment film 12 provided on the second dummy pixel electrode 15B by the thickness of the vertical deposition layer 317. The "height of the alignment film 12" is the shortest distance from the surface of the alignment film 12 on the side of the element substrate 111 to the surface of the alignment film 12 on the liquid crystal layer 5 side in the direction along the Z-axis. The direction along the Z-axis is the normal direction of the substrate surface of the element substrate 111.

[0083] As a result, for example, ionic impurities IO that pass through the dummy pixel region DF from the sealant 6 or the like and head toward the display region E are likely to be trapped in the space TR of the step ST. Further, when the ionic impurities IO are trapped in the space TR, the ionic impurities IO reaching the display region E can be reduced, and the diffusion of the ionic impurities IO into the display region E can be suppressed.

[0084] Therefore, according to the liquid crystal device 100 of the present embodiment, it is possible to prevent the occurrence of display defects such as corner stains, display unevenness, and image sticking caused by the diffusion of the ionic impurities IO.

[0085] Regarding the step ST, as shown in FIG. 5C, it may be configured such that a recess 319 is provided by recessing the sixth interlayer insulating layer 76 in the thickness direction. The recess 319 is formed by etching the sixth interlayer insulating layer 76 in the thickness direction between the second dummy pixel electrode 15B facing the step ST and the vertical deposition layer 317. The oblique deposition layer 318 provided on the second dummy pixel electrode 15B is continuously provided from the side surfaces of the second dummy pixel electrode 15B and the recess 319 to the bottom surface of the recess 319.

[0086] As a result, in the step ST, the space TR can be expanded in the depth direction by the depth of the recess 319. Therefore, in the recess 319, the ionic impurities IO can be efficiently trapped.

[0087] (Outline of the manufacturing method of the liquid crystal device) Next, a method for manufacturing the liquid crystal device 100 will be described. Hereinafter, among the manufacturing methods of the liquid crystal device 100, the manufacturing process of the first substrate 10 including the characteristic configuration will be described. FIGS. 6 and 7A are cross-sectional views for explaining the manufacturing process of the first substrate 10. FIG. 7B is a cross-sectional view of a modification for explaining the manufacturing process of the first substrate 10.

[0088] The first substrate 10 can basically be manufactured by a known semiconductor process including a reduced-pressure CVD (Chemical Vapor Deposition: CVD) method, an atmospheric-pressure CVD method, a plasma CVD method, a photolithography method, a sputtering method, an etching method, and a CMP (Chemical Mechanical Planarization) method, etc., or by combining these methods. Hereinafter, a manufacturing method suitable for manufacturing the structure of the first substrate 10 of the liquid crystal device 100 described above will be described. However, as long as an equivalent structure can be formed and the functions and characteristics required for the configuration are satisfied, other manufacturing methods may be used.

[0089] As shown in FIGS. 6 and 7A, after forming a pixel electrode 11 (not shown), a first dummy pixel electrode 15A, and a second dummy pixel electrode 15B (not shown) on the sixth interlayer insulating layer 76 of the first substrate 10, an alignment film 12 is formed.

[0090] Specifically, first, as shown in FIG. 6, a vertical evaporation layer 317 is formed over the entire surface on the sixth interlayer insulating layer 76 of the first substrate 10. The vertical evaporation layer 317 is formed by depositing an inorganic compound such as silicon oxide from a direction perpendicular to the first substrate 10. The vertical evaporation layer 317 is formed to have a thickness sufficient to planarize the pixel electrode 11 and the first dummy pixel electrode 15A.

[0091] Next, as shown in FIG. 7A, after forming a resist 330 so as to cover a region overlapping the pixel electrode 11 (not shown) and the first dummy pixel electrode 15A in plan view, a chemical solution that acts on the vertical vapor deposition layer 317 and to which the resist 330 is resistant is used to remove the exposed portion of the vertical vapor deposition layer 317 from the resist 330 by wet etching.

[0092] Next, after removing the resist 330, an oblique vapor deposition layer 318 is formed over the entire surface on the sixth interlayer insulating layer 76 of the first substrate 10. The oblique vapor deposition layer 318 is formed by vapor depositing an inorganic compound such as silicon oxide on the first substrate 10 from an oblique direction. The oblique vapor deposition layer 318 is formed to have a thickness smaller than that of the vertical vapor deposition layer 317.

[0093] Thereby, an alignment film 12 as shown in FIG. 5B can be formed. A step ST is formed between the first dummy pixel electrode 15A and the second dummy pixel electrode 15B. The step ST forms a concave space TR between the first dummy pixel electrode 15A and the second dummy pixel electrode 15B. Also, across the step ST, the height of the alignment film 12 provided on the first dummy pixel electrode 15A from the first substrate 10 is higher by the thickness of the vertical vapor deposition layer 317 than the height of the alignment film 12 provided on the second dummy pixel electrode 15B from the first substrate 10.

[0094] Since the oblique vapor deposition layer 318 is obliquely vapor deposited toward the outside of the dummy pixel region DF, it is formed so as to cover the bottom surface of the step ST and the side surface of the second dummy pixel electrode 15B facing the step ST. On the side surface of the vertical vapor deposition layer 317 facing the step ST, the side surface of the vertical vapor deposition layer 317 is exposed without the oblique vapor deposition layer 318 being formed. Thereby, the oblique vapor deposition layer 318 formed on the step ST is separated from the oblique vapor deposition layer 318 formed on the vertical vapor deposition layer 317 and is connected to the oblique vapor deposition layer 318 formed on the second dummy pixel electrode.

[0095] Further, as shown in FIG. 7B, the vertical vapor deposition layer 317 and the sixth interlayer insulating layer 76 of the exposed portion from the resist 330 may be removed by wet etching to form a recess 319 in the sixth interlayer insulating layer 76. The recess 319 is formed by adjusting the time for which the chemical solution acts during wet etching and the like.

[0096] (Electronic device) In this embodiment, as an electronic device including the liquid crystal device 100, the projector 1000 will be described as an example. FIG. 8 is a schematic diagram of the projector 1000. As shown in FIG. 8, the projector 1000 includes a light source device 1001, dichroic mirrors 1011 and 1012, liquid crystal devices 100B, 100G, and 100R, reflection mirrors 1111, 1112, and 1113, relay lenses 1121, 1122, and 1123, a cross dichroic prism 1130, and a projection lens 1140.

[0097] The light source device 1001 emits white light W. The light source device 1001 is, for example, a discharge-type lamp unit, but may be a light-emitting diode, a laser, or the like, or may be a device combining a light emitter that emits blue light and a phosphor that converts a part of the blue light emitted from the light emitter into yellow light and emits it, and is not limited to a specific light source device.

[0098] The white light W emitted from the light source device 1001 is separated into three-color light of different wavelength ranges by two dichroic mirrors 1011 and 1012. The three-color light includes red light R, green light G, and blue light B. The dichroic mirror 1011 transmits the red light R and reflects the green light G and the blue light B having wavelengths shorter than the red light R. The red light R transmitted through the dichroic mirror 1011 is reflected by the reflection mirror 1111 and enters the liquid crystal device 100R. The green light G reflected by the dichroic mirror 1011 is reflected by the dichroic mirror 1012 and then enters the liquid crystal device 100G. The blue light B reflected by the dichroic mirror 1011 passes through the dichroic mirror 1012 and is emitted to the relay lens system 1120.

[0099] The relay lens system 1120 includes relay lenses 1121, 1122, 1123 and reflection mirrors 1112, 1113. The optical path of the blue light B from the dichroic mirror 1011 to the liquid crystal device 100B is longer than the optical path of the green light G from the dichroic mirror 1011 to the liquid crystal device 100G and the optical path of the red light R from the dichroic mirror 1011 to the liquid crystal device 100R. Therefore, the light beam of the blue light B is more likely to be larger than the light beams of the green light G and the red light R. By using the relay lens 1122, the expansion of the light beam of the blue light B is suppressed. The blue light B incident on the relay lens system 1120 is reflected by the reflection mirror 1112 and converges near the relay lens 1122 by the relay lens 1121. The blue light B is incident on the liquid crystal device 100B through the reflection mirror 1113 and the relay lens 1123.

[0100] The liquid crystal devices 100R, 100G, 100B are light modulation devices in the projector 1000. The liquid crystal device 100 described above as the electro-optical device is applied to the liquid crystal devices 100R, 100G, 100B.

[0101] Each of the liquid crystal devices 100R, 100G, 100B is electrically connected to an external control device of the projector 1000. Image signals specifying the gradation levels of the red light R, the green light G, and the blue light B are supplied from the external control devices of the respective color lights and processed by the integrated circuits attached to the liquid crystal devices 100R, 100G, 100B. The liquid crystal devices 100R, 100G, 100B are driven according to the image signals received from the respective integrated circuits. The liquid crystal device 100R modulates the incident red light R. The liquid crystal device 100G modulates the incident green light G. The liquid crystal device 100B modulates the incident blue light B.

[0102] The red light R, green light G, and blue light B modulated by the liquid crystal devices 100R, 100G, and 100B are incident on the cross-dichroic prism 1130 from three directions. The cross-dichroic prism 1130 is a color-combining optical system in the projector 1000 and combines the incident red light R, green light G, and blue light B. In the cross-dichroic prism 1130, the red light R and the blue light B are reflected by 90 degrees with respect to their respective incident directions, and the green light G is transmitted. As a result, the red light R, green light G, and blue light B that are combined with each other are emitted in the same direction. The red light R, green light G, and blue light B are combined as display light for displaying a color image and are emitted from the cross-dichroic prism 1130 toward the projection lens 1140.

[0103] The projection lens 1140 is disposed facing the outside of the projector 1000. The display light is enlarged and emitted through the projection lens 1140 and projected onto the screen SCR that is the projection target.

[0104] (Operation and Effect of the Present Invention) The liquid crystal device 100 of the present embodiment described above includes the element substrate 111, a sixth interlayer insulating layer 76 provided on one side of the element substrate 111, a first dummy pixel electrode 15A and a second dummy pixel electrode 15B provided on the side of the sixth interlayer insulating layer 76 opposite to the element substrate 111, an alignment film 12 covering the first dummy pixel electrode 15A, and an alignment film 12 covering the second dummy pixel electrode 15B. The height of the alignment film 12 covering the first dummy pixel electrode 15A from the element substrate 111 is higher than the height of the alignment film 12 covering the second dummy pixel electrode 15B from the element substrate 111.

[0105] The element substrate 111 corresponds to the "substrate" of the present invention. The sixth interlayer insulating layer 76 corresponds to the "first insulating layer" of the present invention. The first dummy pixel electrode 15A corresponds to the "first electrode" of the present invention. The second dummy pixel electrode 15B corresponds to the "second electrode" of the present invention. The alignment film 12 covering the first dummy pixel electrode 15A corresponds to the "second insulating layer" of the present invention. The alignment film 12 covering the second dummy pixel electrode 15B corresponds to the "third insulating layer" of the present invention.

[0106] Therefore, the second insulating layer includes a vertically deposited layer 317 provided on the first dummy pixel electrode 15A and an obliquely deposited layer 318 provided on the vertically deposited layer 317. The third insulating layer includes the obliquely deposited layer 318 provided on the second dummy pixel electrode 15B. Accordingly, the height of the second insulating layer from the substrate is higher than the height of the third insulating layer from the substrate by the thickness of the vertically deposited layer 317.

[0107] A step ST is provided between the first dummy pixel electrode 15A and the second dummy pixel electrode 15B. Further, the step ST may be provided with a recess 319 in which the first insulating layer is recessed in the thickness direction. The step ST is provided with the obliquely deposited layer 318. The obliquely deposited layer 318 provided on the step ST is separated from the obliquely deposited layer 318 provided on the vertically deposited layer 317 and is connected to the obliquely deposited layer 318 provided on the second dummy pixel electrode 15B. The second dummy pixel electrode 15B is provided in a dummy pixel region DF outside the display region E.

[0108] As described above, in the liquid crystal device 100 of the present embodiment, for example, ionic impurities IO that pass from the sealing material 6 or the like through the dummy pixel region DF toward the display region E are likely to be captured in the space TR of the step ST. Further, when the ionic impurities IO are captured in the space TR, the ionic impurities IO reaching the display region E can be reduced, and the diffusion of the ionic impurities IO into the display region E can be suppressed. Therefore, according to the liquid crystal device 100 of the present embodiment, it is possible to prevent the occurrence of display defects such as corner shading, display unevenness, and image sticking caused by the diffusion of the ionic impurities IO.

[0109] Note that the technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

[0110] For example, in the above-described embodiment, a transmissive liquid crystal device is exemplified as the liquid crystal device. However, the liquid crystal device may be a reflective liquid crystal device or an LCOS (Liquid crystal on silicon) type liquid crystal device. Further, the electro-optical device may be an organic EL device having a layer made of an organic compound as the electro-optical layer in addition to the above-described liquid crystal device, or may be a device having an electro-optical layer other than the liquid crystal device and the organic EL device.

[0111] For example, in the above-described embodiment, a projector is exemplified as the electronic device. However, the electronic device is not limited to a projector. The electronic device including the above-described liquid crystal device may be, for example, a stereolithography apparatus, or may be a device that utilizes image light converted by the liquid crystal device other than a projector and a stereolithography apparatus.

[0112] [Summary of the Present Disclosure] Hereinafter, a summary of the present disclosure will be appended. (Appendix 1) An electro-optical device including a substrate, a first insulating layer provided on one side of the substrate, a first electrode and a second electrode provided on the side of the first insulating layer opposite to the substrate, a second insulating layer covering the first electrode, and a third insulating layer covering the second electrode, wherein a height of the second insulating layer from the substrate is higher than a height of the third insulating layer from the substrate.

[0113] According to the configuration of Appendix 1, during the manufacture of the electro-optical device, ionic impurities can be efficiently captured in the space between the first insulating layer and the second insulating layer while suppressing the diffusion of ionic impurities from the second electrode side to the first electrode side. Therefore, according to the configuration of Appendix 1, the occurrence of bright spots and display defects due to the diffusion of ionic impurities can be prevented.

[0114] (Appendix 2) The electro-optical device according to Appendix 1, wherein a step is provided between the first electrode and the second electrode.

[0115] According to the configuration of Appendix 2, ionic impurities can be efficiently captured at the step.

[0116] (Supplementary Note 3) The electro-optical device according to Supplementary Note 2, wherein the step has a recess formed by recessing the first insulating layer in the thickness direction.

[0117] According to the configuration of Supplementary Note 3, ionic impurities can be efficiently trapped in the recess.

[0118] (Supplementary Note 4) The second insulating layer includes a vertically deposited layer provided on the first electrode and an obliquely deposited layer provided on the vertically deposited layer, the third insulating layer includes the obliquely deposited layer provided on the second electrode, and the step has the obliquely deposited layer. The electro-optical device according to Supplementary Note 2.

[0119] According to the configuration of Supplementary Note 4, a step can be provided between the first electrode and the second electrode.

[0120] (Supplementary Note 5) The obliquely deposited layer provided on the step is separated from the obliquely deposited layer provided on the vertically deposited layer and is connected to the obliquely deposited layer provided on the second electrode. The electro-optical device according to Supplementary Note 4.

[0121] According to the configuration of Supplementary Note 5, diffusion of ionic impurities from the second electrode side to the first electrode side can be suppressed.

[0122] (Supplementary Note 6) The electro-optical device according to any one of Supplementary Notes 1 to 5, wherein the second electrode is provided in a dummy pixel region outside the display region.

[0123] According to the configuration of Supplementary Note 6, diffusion of ionic impurities into the display region can be suppressed.

[0124] (Supplementary Note 7) An electronic device including the electro-optical device according to any one of Supplementary Notes 1 to 6.

[0125] According to the configuration of Supplementary Note 7, occurrence of display defects in the electro-optical device can be prevented.

Description of Reference Numerals

[0126] 11… Pixel electrode, 12… Alignment film, 15A… First dummy pixel electrode (first electrode), 15B… Second dummy pixel electrode (second electrode), 100… Liquid crystal device (electro-optical device), 111… Element substrate (substrate), 317… Vertical evaporation layer, 318… Rhombic evaporation layer, 319… Concave portion, 1000… Projector (electronic device), P… Pixel, DP… Dummy pixel, E… Display area, DF… Dummy pixel area, ST… Step, TR… Space.

Claims

1. A substrate, a first insulating layer provided on one side of the substrate, a first electrode and a second electrode provided on the side of the first insulating layer opposite to the substrate, a second insulating layer covering the first electrode, a third insulating layer covering the second electrode, comprising: wherein the height of the second insulating layer from the substrate is higher than the height of the third insulating layer from the substrate, an electro-optical device.

2. A step is provided between the first electrode and the second electrode. The electro-optical device according to Claim 1.

3. A recess in which the first insulating layer is recessed in the thickness direction is provided in the step. The electro-optical device according to Claim 2.

4. The second insulating layer includes a vertically deposited layer provided on the first electrode and an obliquely deposited layer provided on the vertically deposited layer. The third insulating layer includes the obliquely deposited layer provided on the second electrode. The obliquely deposited layer is provided in the step. The electro-optical device according to Claim 2.

5. The obliquely deposited layer provided in the step is separated from the obliquely deposited layer provided on the vertically deposited layer and is connected to the obliquely deposited layer provided on the second electrode. The electro-optical device according to Claim 4.

6. The second electrode is provided in a dummy pixel region outside the display region. The electro-optical device according to Claim 1.

7. An electronic device comprising the electro-optical device according to any one of Claims 1 to 6. An electronic device.

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