Nitride semiconductor device and manufacturing method thereof

Abstract

To improve switching response in a normally-off type HEMT.SOLUTION: A nitride semiconductor device 10 includes an electron transit layer 22, an electron supply layer 24 provided on the electron transit layer 22, a gate layer 28 provided on the electron supply layer 24 and made of a nitride semiconductor containing acceptor-type impurities, a first gate electrode 30 in contact with an upper surface 28A of the gate layer 28, and a second gate electrode 31 located above the first gate electrode 30. A second density which is the density of second gate electrode 31 is higher than a first density which is the density of first gate electrode 30.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

Background Art

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes simply referred to as "nitride semiconductors") is progressing. A HEMT uses a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conduction path (channel). Power devices using HEMTs are recognized as devices that enable low on-resistance and high-frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron traveling layer composed of a gallium nitride (GaN) layer, and an electron supply layer composed of an aluminum gallium nitride (AlGaN) layer. In the electron traveling layer, a 2DEG is formed near the interface of the heterojunction between the electron traveling layer and the electron supply layer. Further, in the nitride semiconductor device of Patent Document 1, a GaN layer (p-type GaN layer) doped with acceptor-type impurities is provided on the electron supply layer and directly under the gate electrode. In this configuration, the p-type GaN layer raises the energy level of the conduction band near the heterojunction interface between the electron traveling layer and the electron supply layer in the region directly below it, so that the channel directly below the p-type GaN layer can be eliminated. Thereby, the normally-off operation of the nitride semiconductor device is realized.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In a normally-off type HEMT, a technique for improving the switching responsiveness is desired.

[0006] A semiconductor device according to an aspect of the present disclosure includes an electron traveling layer composed of a nitride semiconductor, an electron supply layer provided on the electron traveling layer and composed of a nitride semiconductor, a gate layer provided on the electron supply layer and composed of a nitride semiconductor containing acceptor-type impurities, a first gate electrode in contact with the upper surface of the gate layer, and a second gate electrode positioned above the first gate electrode, wherein a second density that is the density of the second gate electrode is higher than a first density that is the density of the first gate electrode.

Brief Description of the Drawings

[0007]

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[0008] [Detailed Description] Hereinafter, embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, in order to make the illustration and description concise and clear, the components shown in the drawings are not necessarily drawn at a constant scale. Further, in order to make the illustration concise and clear, hatching may be omitted in the cross-sectional view. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0009] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0010] [Schematic Structure of Nitride Semiconductor Device] With reference to FIGS. 1 to 4, an exemplary nitride semiconductor device 10 according to an embodiment will be described. In this embodiment, the nitride semiconductor device 10 may be configured as a semiconductor chip on which a high electron mobility transistor (HEMT) is formed. FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to an embodiment. FIG. 2 is an enlarged plan view of the nitride semiconductor device 10. FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F3-F3 of FIG. 2. FIG. 4 is an enlarged view of a part of FIG. 3.

[0011] The Z-axis direction of the XYZ axes orthogonal to each other shown in FIGS. 1 to 4 is a direction orthogonal to the surface of the semiconductor substrate 18 (see FIG. 3). Note that the term "plan view" used in this specification means viewing the nitride semiconductor device 10 from above along the Z-axis direction unless otherwise explicitly specified.

[0012] As shown in FIG. 1, the nitride semiconductor device 10 may include a gate pad 12, a source pad 14, and a drain pad 16 formed on the rectangular upper surface 10A in plan view. The gate pad 12, the source pad 14, and the drain pad 16 may be electrically connected to the gate electrode, the source electrode, and the drain electrode (for example, the second gate electrode 31, the source electrode 34, and the drain electrode 36 shown in FIG. 2) of the HEMT formed in the semiconductor chip, respectively. The gate pad 12, the source pad 14, and the drain pad 16 can constitute external connection terminals of the nitride semiconductor device 10.

[0013] In the example of FIG. 1, the nitride semiconductor device 10 includes a plurality of source pads 14 and a plurality of drain pads 16. The plurality of source pads 14 and the plurality of drain pads 16 may be alternately arranged in the X-axis direction. The number of pads 12, 14, 16 arranged on the upper surface 10A can be arbitrarily determined according to the needs of a specific application.

[0014] The layout of the gate pad 12, the source pad 14, and the drain pad 16 is not limited to the example shown in FIG. 1. The gate pad 12, the source pad 14, and the drain pad 16 can be arranged in any other layout.

[0015] FIG. 3 shows a schematic cross-sectional view of the active region of the HEMT located below the source pad 14 or the drain pad 16 shown in FIG. 1. As shown in FIG. 3, the nitride semiconductor device 10 may include a semiconductor substrate 18 and a buffer layer 20 formed on the semiconductor substrate 18.

[0016] The semiconductor substrate 18 can be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In one example, the semiconductor substrate 18 may be a Si substrate. The thickness of the semiconductor substrate 18 can be, for example, 200 μm or more and 1500 μm or less.

[0017] The buffer layer 20 may include one or more nitride semiconductor layers. The buffer layer 20 can be composed of any material that can suppress the occurrence of warping or cracking of the nitride semiconductor device 10 due to the difference in the coefficient of thermal expansion between the semiconductor substrate 18 and the layer formed on the buffer layer 20 (such as the electron traveling layer 22 described later). For example, the buffer layer 20 can include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 20 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0018] In one example, the buffer layer 20 can include a first buffer layer that is an AlN layer formed on the semiconductor substrate 18 and a second buffer layer that is an AlGaN layer formed on the AlN layer. The first buffer layer may be, for example, an AlN layer having a thickness of 100 nm to 300 nm, while the second buffer layer may include a plurality of AlGaN layers having different compositions and each having a thickness of 100 nm to 300 nm. In addition, in order to suppress the leakage current in the buffer layer 20, impurities may be introduced into a part of the buffer layer 20 to make the buffer layer 20 semi-insulating. In that case, the impurities are, for example, carbon (C) or iron (Fe), and the concentration of the impurities can be, for example, 4×10 16 cm -3 or more.

[0019] The nitride semiconductor device 10 further includes an electron traveling layer 22 and an electron supply layer 24 formed on the electron traveling layer 22. The electron transport layer 22 may be formed on the buffer layer 20. The electron transport layer 22 is composed of a first nitride semiconductor. The first nitride semiconductor may contain GaN. In one example, the thickness of the electron transport layer 22 may be 0.5 μm or more and 2 μm or less. In addition, in order to suppress the leakage current in the electron transport layer 22, by introducing impurities into a part of the electron transport layer 22, the region other than the surface layer region of the electron transport layer 22 may be made semi-insulating. In this case, the impurity may be, for example, C. The impurity concentration in the electron transport layer 22 is, for example, 4×10 16 cm -3 or more.

[0020] That is, the electron transport layer 22 may include a plurality of GaN layers with different impurity concentrations, for example, a C-doped GaN layer and an undoped GaN layer. In this case, the C-doped GaN layer may be formed on the buffer layer 20. The C-doped GaN layer may have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer is 5×10 17 cm -3 or more and 9×10 19 cm -3 or less. The undoped GaN layer is formed on the C-doped GaN layer and may have a thickness of 0.05 μm or more and 0.4 μm or less. The undoped GaN layer is in contact with the electron supply layer 24. In one example, the electron transport layer 22 may include a C-doped GaN layer with a thickness of 0.4 μm and an undoped GaN layer with a thickness of 0.4 μm. Also, the C concentration in the C-doped GaN layer may be about 2×10 19 cm -3 or so.

[0021] The electron supply layer 24 is composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The second nitride semiconductor may contain AlGaN. In one example, the electron supply layer 24 is Al x Ga 1-xIt is composed of N, where 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The electron supply layer 24 may have a thickness of 5 nm or more and 20 nm or less. In one example, the electron supply layer 24 may have a thickness of 8 nm or more.

[0022] The first nitride semiconductor (e.g., GaN) constituting the electron transport layer 22 and the second nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 24 have different lattice constants from each other. Therefore, the electron transport layer 22 and the electron supply layer 24 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 22 and the electron supply layer 24 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 22 near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 26 spreads in the electron transport layer 22 at a position close to the hetero-junction interface between the electron transport layer 22 and the electron supply layer 24 (e.g., within a range of about several nm from the interface). The 2DEG 26 in the electron transport layer 22 functions as a channel of the nitride semiconductor device 10. The sheet carrier density of the 2DEG 26 generated in the electron transport layer 22 can be increased by increasing at least one of the Al composition and the thickness of the electron supply layer 24.

[0023] (Gate layer) The nitride semiconductor device 10 further includes a gate layer 28 formed on the electron supply layer 24. The gate layer 28 may be formed on a part of the electron supply layer 24. The gate layer 28 includes a lower surface 28B in contact with the electron supply layer 24 and an upper surface 28A opposite to the lower surface 28B.

[0024] The gate layer 28 is composed of a third nitride semiconductor containing acceptor-type impurities. The third nitride semiconductor may include GaN. In the present embodiment, the gate layer 28 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 28 is 7×1018 cm -3 1×10 or more 20 cm -3 It can be set to the following.

[0025] (First gate electrode and second gate electrode) As shown in FIGS. 3 and 4, the nitride semiconductor device 10 further includes a first gate electrode 30 in contact with the upper surface 28A of the gate layer 28. The first gate electrode 30 has an upper surface 30A and a lower surface 30B facing the opposite side of the upper surface 30A. The lower surface 30B of the first gate electrode 30 is in contact with the upper surface 28A of the gate layer 28. The first gate electrode 30 is composed of a metal layer. The first gate electrode 30 forms a Schottky junction with the gate layer 28. Details of the metal layer constituting the first gate electrode 30 will be described later.

[0026] The first gate electrode 30 may be formed on a part of the upper surface 28A of the gate layer 28 or may be formed on the entire upper surface 28A of the gate layer 28. The drawing illustrates, as an example, a case where the first gate electrode 30 is formed on a part of the upper surface 28A of the gate layer 28. In this case, the first gate electrode 30 has an area smaller than the upper surface 28A of the gate layer 28 in plan view. Therefore, the side surface 30C of the first gate electrode 30 is not flush with the side surface 28C of the gate layer 28.

[0027] The nitride semiconductor device 10 further includes a second gate electrode 31 in contact with the upper surface 30A of the first gate electrode 30. The second gate electrode 31 has an upper surface 31A and a lower surface 31B facing the opposite side of the upper surface 31A. The lower surface 31B of the second gate electrode 31 is in contact with the upper surface 30A of the first gate electrode 30. The second gate electrode 31 is composed of a metal layer. Details of the metal layer constituting the second gate electrode 31 will be described later.

[0028] The second gate electrode 31 may be formed on a part of the upper surface 28A of the gate layer 28, or may be formed on the entire upper surface 28A of the gate layer 28. As an example, the drawing illustrates the case where the second gate electrode 31 is formed on the entire upper surface 30A of the first gate electrode 30. In this case, the second gate electrode 31 has the same area as the upper surface 30A of the first gate electrode 30 in plan view. Therefore, the side surface 31C of the second gate electrode 31 is flush with the side surface 31C of the second gate electrode 31.

[0029] The first gate electrode 30 and the second gate electrode 31 constitute the gate electrode of the HEMT. The gate electrode is electrically connected to the gate layer 28 by the first gate electrode 30 located on the lower side, and is electrically connected to the gate pad 12 by the second gate electrode 31 located on the upper side. In other words, the second gate electrode 31 is the main body portion constituting the gate electrode of the HEMT, and the first gate electrode 30 is a connecting portion interposed between the second gate electrode 31 and the gate layer 28 to electrically connect the second gate electrode 31 and the gate layer 28.

[0030] Next, the thicknesses of the first gate electrode 30 and the second gate electrode 31 will be described. The thickness T1 of the first gate electrode 30 is, for example, 10 nm or more, 20 nm or more, or 30 nm or more. The thickness T1 of the first gate electrode 30 is, for example, 190 nm or less, 180 nm or less, or 170 nm or less. The thickness T2 of the second gate electrode 31 is, for example, 10 nm or more, 20 nm or more, or 30 nm or more. The thickness T2 of the second gate electrode 31 is, for example, 60 nm or less, 50 nm or less, or 40 nm or less. The total thickness (T1 + T2) of the first gate electrode 30 and the second gate electrode 31 is, for example, 70 nm or more and 200 nm or less.

[0031] In one example, the thickness T2 of the second gate electrode 31 is greater than the thickness T1 of the first gate electrode 30. In this case, the ratio (T2 / T1) of the thickness T2 of the second gate electrode 31 to the thickness T1 of the first gate electrode 30 is, for example, 1.3 or more and 6 or less. Also, the thickness T2 of the second gate electrode 31 may be the same as the thickness T1 of the first gate electrode 30, or may be less than the thickness T1.

[0032] Next, the materials constituting the first gate electrode 30 and the second gate electrode 31 will be described. The first gate electrode 30 is a metal layer containing at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten silicide (WSi), zirconium nitride (ZrN), hafnium nitride (HfN), and molybdenum nitride (MoN). An example of the first gate electrode 30 is composed of a metal nitride. Examples of the metal nitride include TiN, TaN, WN, TiSiN, TaSiN, and WSiN.

[0033] The second gate electrode 31 is a metal layer containing at least one of TiN, TaN, WN, TiSiN, TaSiN, WSiN, WSi, ZrN, HfN, and MoN. An example of the second gate electrode 31 is composed of a metal nitride. Examples of the metal nitride include TiN, TaN, WN, TiSiN, TaSiN, and WSiN.

[0034] The first gate electrode 30 and the second gate electrode 31 may be made of the same material or different materials. Also, when the first gate electrode 30 and the second gate electrode 31 are made of the same material, the composition ratio of the first gate electrode 30 and the composition ratio of the second gate electrode may be the same or different. An example of the first gate electrode 30 and the second gate electrode 31 is made of the same material. Also, another example of the first gate electrode 30 and the second gate electrode 31 is made of the same material and has the same composition ratio of the material. A specific example of the first gate electrode 30 and the second gate electrode 31 is both made of TiN, and the molar ratio of Ti to N in the TiN constituting the first gate electrode 30 is the same as the molar ratio of Ti to N in the TiN constituting the second gate electrode 31.

[0035] Note that the fact that the composition ratio of the first gate electrode 30 and the composition ratio of the second gate electrode are the same is not limited to only the case where the composition ratios exactly match. For example, for all components constituting the first gate electrode 30 and the second gate electrode 31, the molar ratio in the first gate electrode 30 is compared with the molar ratio in the second gate electrode 31, and if the difference between them is within 5% of the molar ratio in the first gate electrode 30, it can be said that the composition ratios are the same.

[0036] Next, the densities of the first gate electrode 30 and the second gate electrode 31 will be described. The second density D2, which is the density of the second gate electrode 31, is lower than the first density D1, which is the density of the first gate electrode 30. The ratio (D2 / D1) of the second density D2 to the first density D1 is, for example, 1.18 or more, 1.25 or more, or 1.35 or more. Also, the ratio (D2 / D1) is, for example, 1.69 or less, 1.56 or less, or 1.47 or less.

[0037] Even when the first gate electrode 30 and the second gate electrode 31 are made of the same material and have the same composition ratio of the material, the first density D1 and the second density D2 can be made different. As a method, for example, manufacturing conditions when forming the first gate electrode 30 and the second gate electrode 31, specifically, sputtering conditions can be made different. Details of sputtering will be described later.

[0038] The first gate electrode 30 and the second gate electrode 31 have different resistivities based on the difference between the first density D1 and the second density D2. Specifically, the first resistivity R1, which is the resistivity of the first gate electrode 30, is higher than the second resistivity R2, which is the resistivity of the second gate electrode 31. The ratio (R2 / R1) of the first resistivity R1 to the second resistivity R2 is, for example, 0.14 or more, 0.15 or more, or 0.16 or more. Also, the ratio (R2 / R1) is, for example, 0.89 or less, 0.80 or less, or 0.73 or less.

[0039] When the first gate electrode 30 and the second gate electrode 31 are made of the same material and have the same composition ratio of the material, for example, the first gate electrode 30 and the second gate electrode 31 have different crystal perfection in the crystals constituting each electrode. More specifically, the first gate electrode 30 is composed of crystals with lower perfection compared to the second gate electrode 31, resulting in a rough metal layer, that is, a metal layer with a low density. On the other hand, the second gate electrode 31 is composed of crystals with higher perfection compared to the first gate electrode 30, resulting in a dense metal layer, that is, a metal layer with a low density. Note that a low crystal perfection means containing many lattice defects such as vacant lattice points and dislocations.

[0040] Hereinafter, an example of each density and each resistivity when both the first gate electrode 30 and the second gate electrode 31 are made of TiN with a stoichiometric composition (Ti:N = 1:1) will be described. The first density D1 of the first gate electrode 30 is, for example, 3.2 g / cm 3 or more, 3.4 g / cm 3 or more, or 3.6 g / cm 3The above is the case. Also, the first density D1 of the first gate electrode 30 is, for example, 3.8 g / cm 3 or less, 4.0 g / cm 3 or less, or 4.2 g / cm 3 or less.

[0041] The second density D2 of the second gate electrode 31 is, for example, 4.7 g / cm 3 or more, 4.8 g / cm 3 or more, or 5.0 g / cm 3 or more. Also, the second density D2 of the second gate electrode 31 is, for example, 5.2 g / cm 3 or less, 5.3 g / cm 3 or less, or 5.4 g / cm 3 or less.

[0042] The first resistivity R1 of the first gate electrode 30 is, for example, 90 μΩcm or more, 100 μΩcm or more, or 110 μΩcm or more. Also, the first resistivity R1 of the first gate electrode 30 is, for example, 140 μΩcm or less, 150 μΩcm or less, or 160 μΩcm or less.

[0043] The second resistivity R2 of the second gate electrode 31 is, for example, 22 μΩcm or more, 26 μΩcm or more, or 30 μΩcm or more. Also, the second resistivity R2 of the second gate electrode 31 is, for example, 40 μΩcm or less, 60 μΩcm or less, or 80 μΩcm or less.

[0044] (Passivation layer) As shown in FIG. 3, the nitride semiconductor device 10 may further include a passivation layer 32 that covers the electron supply layer 24, the gate layer 28, the first gate electrode 30, and the second gate electrode 31. As shown in FIG. 4, the passivation layer 32 covers the side surface 30C of the first gate electrode 30 and the upper surface 31A and the side surface 31C of the second gate electrode 31.

[0045] As shown in FIG. 3, the passivation layer 32 has a first opening 32A and a second opening 32B. The first opening 32A and the second opening 32B are spaced apart in the X-axis direction. The gate layer 28 is located between the first opening 32A and the second opening 32B. Specifically, the gate layer 28 may be disposed between the first opening 32A and the second opening 32B and closer to the first opening 32A than the second opening 32B.

[0046] The passivation layer 32 may be formed of, for example, at least one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 32 may be, for example, 80 nm or more and 150 nm or less.

[0047] (Source electrode and drain electrode) The nitride semiconductor device 10 further includes a source electrode 34 in contact with the electron supply layer 24 through the first opening 32A and a drain electrode 36 in contact with the electron supply layer 24 through the second opening 32B. The source electrode 34 and the drain electrode 36 can be formed of one or a plurality of metal layers (for example, any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer).

[0048] An example of the source electrode 34 and the drain electrode 36 is formed of the same material as the second gate electrode 31, and the density of the source electrode 34 and the drain electrode 36 is the same as the second density. In this case, the source electrode 34 and the drain electrode 36 have the same material and density as the second gate electrode 31 with a low resistivity.

[0049] Another example of the source electrode 34 and the drain electrode 36 is formed of the same material as the first gate electrode 30, and the density of the source electrode 34 and the drain electrode 36 is the same as the first density. In this case, the source electrode 34 and the drain electrode 36 have the same material and density as the first gate electrode 30 with a high resistivity.

[0050] Since at least a part of the source electrode 34 is filled in the first opening 32A, an ohmic contact can be made with the 2DEG 26 directly under the electron supply layer 24 through the first opening 32A. Similarly, since at least a part of the drain electrode 36 is filled in the second opening 32B, an ohmic contact can be made with the 2DEG 26 directly under the electron supply layer 24 through the second opening 32B.

[0051] (Field plate electrode) The nitride semiconductor device 10 may further include a field plate electrode 38 which is optionally formed on the passivation layer 32 and extends at least partially in a region between the gate layer 28 and the drain electrode 36 in a plan view. In the example shown in FIG. 3, the field plate electrode 38 is formed integrally with the source electrode 34. Among the integrally formed electrodes, the source electrode 34 may include at least a portion embedded in the first opening 32A of the passivation layer 32, and the field plate electrode 38 may include the remaining portion. Note that the field plate electrode 38 only needs to be electrically connected to the source electrode 34 and does not necessarily have to be continuous with the source electrode 34.

[0052] The field plate electrode 38 is separated from the drain electrode 36. The field plate electrode 38 may include an end portion 38A located between the drain electrode 36 (second opening 32B) and the gate layer 28 in a plan view.

[0053] When a drain voltage is applied to the drain electrode 36 in a zero-bias state where no gate voltage is applied to the first gate electrode 30 and the second gate electrode 31, the field plate electrode 38 can relieve the electric field concentration in the vicinity of the ends of the first gate electrode 30 and the second gate electrode 31.

[0054] (Cross-sectional shape of gate layer) As shown in FIG. 4, the gate layer 28 may include a ridge portion 40 that is in contact with the electron supply layer 24 and includes an upper surface 28A, and a first extending portion 42 and a second extending portion 44 that are in contact with the electron supply layer 24 and extend outward in a plan view from the ridge portion 40 and are thinner than the ridge portion 40. In the present disclosure, the first extending portion 42 and the second extending portion 44 may be collectively referred to as an “extending portion”. Since the first extending portion 42 and the second extending portion 44 are thinner than the ridge portion 40, the upper surface 42A of the first extending portion 42 and the upper surface 44A of the second extending portion 44 are located below the upper surface 28A of the gate layer 28 in the Z-axis direction. The side surface 28C of the gate layer 28 connects the upper surface 28A of the gate layer 28 to the upper surface 42A of the first extending portion 42 and the upper surface 44A of the second extending portion 44.

[0055] The first extending portion 42 extends from the ridge portion 40 toward the first opening 32A. The first extending portion 42 partially covers the surface of the electron supply layer 24 between the ridge portion 40 and the first opening 32A in a plan view. The first extending portion 42 does not reach the source electrode 34 embedded in the first opening 32A.

[0056] The second extending portion 44 extends from the ridge portion 40 toward the second opening 32B. The second extending portion 44 partially covers the surface of the electron supply layer 24 between the ridge portion 40 and the second opening 32B in a plan view. The second extending portion 44 does not reach the drain electrode 36 embedded in the second opening 32B.

[0057] The ridge portion 40 is between the first extending portion 42 and the second extending portion 44, and is integrally formed with the first extending portion 42 and the second extending portion 44. Due to the presence of the first extending portion 42 and the second extending portion 44, the lower surface 28B of the gate layer 28 has a larger area than the upper surface 28A. In the example shown in FIG. 3, the second extending portion 44 may extend longer toward the outside of the ridge portion 40 in plan view than the first extending portion 42. That is, the second extending portion 44 may have a dimension in the X-axis direction larger than that of the first extending portion 42. The first extending portion 42 may have a dimension in the X-axis direction, for example, of 0.2 μm or more and 0.3 μm or less. On the other hand, the second extending portion 44 may have a dimension in the X-axis direction, for example, of 0.2 μm or more and 0.6 μm or less.

[0058] The ridge portion 40 corresponds to a relatively thick portion of the gate layer 28. The ridge portion 40 may have a thickness, for example, of 80 nm or more and 150 nm or less. In one example, the ridge portion 40 may have a thickness greater than 110 nm. The first extending portion 42 and the second extending portion 44 have a thickness smaller than that of the ridge portion 40. In one example, the first extending portion 42 and the second extending portion 44 may have a thickness of half or less of the thickness of the ridge portion 40.

[0059] As shown in FIG. 4, the first extending portion 42 may include a first step portion 46 having a substantially constant thickness and a first intermediate portion 48 connecting the first step portion 46 to the ridge portion 40. Herein, "substantially constant thickness" means that the thickness is within the range of manufacturing variations (for example, 20%). In one example, the thickness of the first step portion 46 may be 5 nm or more and 25 nm or less. The thickness of the first intermediate portion 48 may be equal to or greater than the thickness of the first step portion 46 and less than the thickness of the ridge portion 40.

[0060] Similarly, the second extending portion 44 may include a second stepped portion 50 having a substantially constant thickness and a second intermediate portion 52 connecting the second stepped portion 50 to the ridge portion 40. In one example, the thickness of the second stepped portion 50 may be 5 nm or more and 25 nm or less. The thickness of the second intermediate portion 52 may be equal to or greater than the thickness of the second stepped portion 50 and less than the thickness of the ridge portion 40. The second stepped portion 50 may have the same thickness as the first stepped portion 46.

[0061] (Planar layout of nitride semiconductor device) Next, with reference to FIG. 2, an example of the planar layout of the nitride semiconductor device 10 will be described. FIG. 2 mainly shows the active region of the HEMT located below the source pad 14 or the drain pad 16 shown in FIG. 1. In FIG. 2, the second gate electrode 31, the source electrode 34, the drain electrode 36, and the field plate electrode 38 are drawn with broken lines. Further, for the passivation layer 32, the first opening 32A and the second opening 32B are drawn with solid lines, and the other portions are shown transparently. Also, in FIG. 2, the first extending portion 42 and the second extending portion 44 are omitted.

[0062] As shown in FIG. 2, the gate layer 28 may be formed so as to surround the drain electrode 36 in a plan view. The gate layer 28 may include a main body portion 54 extending in the Y-axis direction and a connecting portion 56 connecting two adjacent main body portions 54. The main body portion 54 of the gate layer 28 is disposed between the first opening 32A and the second opening 32B of the passivation layer 32.

[0063] The first gate electrode 30 and the second gate electrode 31 are arranged to overlap the gate layer 28 in a plan view. In an example shown in FIG. 2, the planar shape of the first gate electrode 30 and the planar shape of the second gate electrode 31 are the same. In FIG. 2, only the second gate electrode 31 located on the upper side is illustrated. The first gate electrode 30 and the second gate electrode 31 may be formed so as to surround the drain electrode 36 in a plan view, similar to the gate layer 28. The first gate electrode 30 and the second gate electrode 31 may include a main body portion 58 extending in the Y-axis direction and a connection portion 60 connecting two adjacent main body portions 58.

[0064] The nitride semiconductor device 10 may include a gate wiring 62, a source wiring 64, and a drain wiring 66. In FIG. 2, the gate wiring 62, the source wiring 64, and the drain wiring 66 are drawn with a dashed line. The gate wiring 62, the source wiring 64, and the drain wiring 66 are located above the source electrode 34 and the drain electrode 36 in the Z-axis direction. The gate wiring 62 may extend in the X-axis direction and may be disposed above the connection portion 60 of the first gate electrode 30. The source wiring 64 and the drain wiring 66 may extend in the X-axis direction and may be disposed so as to intersect the source electrode 34 and the drain electrode 36 in a plan view, respectively.

[0065] In an example, the first gate electrode 30 may be electrically connected to the gate wiring 62 via a via 68 disposed on the connection portion 60. The source electrode 34 may be electrically connected to the source wiring 64 via a via 70. The drain electrode 36 may be electrically connected to the drain wiring 66 via a via 72. The gate wiring 62, the source wiring 64, and the drain wiring 66 may be electrically connected to the gate pad 12, the source pad 14, and the drain pad 16 shown in FIG. 1, respectively.

[0066] The planar layout of the nitride semiconductor device 10 is not limited to the example shown in FIG. 2. Any other planar layout can be applied to the nitride semiconductor device 10. (Method for manufacturing a nitride semiconductor device) Next, with reference to FIGS. 5 to 11, an example of a method for manufacturing a nitride semiconductor device 10 will be described. FIGS. 5 to 11 are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device 10. For ease of understanding, in FIGS. 5 to 11, the same components as those in FIG. 3 are denoted by the same reference numerals.

[0067] The method for manufacturing the nitride semiconductor device 10 includes forming a first nitride semiconductor layer 78, forming a second nitride semiconductor layer 80 having a larger bandgap than the first nitride semiconductor layer 78 on the first nitride semiconductor layer 78, and forming a third nitride semiconductor layer 82 containing acceptor-type impurities on the second nitride semiconductor layer 80.

[0068] As shown in FIG. 5, for example, a buffer layer 20, a first nitride semiconductor layer 78, a second nitride semiconductor layer 80, and a third nitride semiconductor layer 82 are sequentially stacked on a semiconductor substrate 18 which is a Si substrate. The buffer layer 20, the first nitride semiconductor layer 78, the second nitride semiconductor layer 80, and the third nitride semiconductor layer 82 can be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method.

[0069] Although detailed illustration is omitted, in one example, the buffer layer 20 may be a multilayer buffer layer. The multilayer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 18 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer can be formed, for example, by stacking three AlGaN layers having Al compositions of 75%, 50%, and 25% in order from the side closer to the AlN layer.

[0070] The first nitride semiconductor layer 78 formed on the buffer layer 20 may be a GaN layer. Also, the second nitride semiconductor layer 80 formed on the first nitride semiconductor layer 78 may be an AlGaN layer. The second nitride semiconductor layer 80 has a larger bandgap than the first nitride semiconductor layer 78. The first nitride semiconductor layer 78 and the second nitride semiconductor layer 80 respectively correspond to the electron traveling layer 22 and the electron supply layer 24 shown in FIG. 3.

[0071] The third nitride semiconductor layer 82 may be a GaN layer containing acceptor-type impurities. In one example, the third nitride semiconductor layer 82 containing acceptor-type impurities can be formed by doping magnesium during the growth of the third nitride semiconductor layer 82. The amount of magnesium doped into the third nitride semiconductor layer 82 can be adjusted, for example, by controlling the flow rate of the doping gas (e.g., bis(cyclopentadienyl)magnesium (Cp2Mg)) introduced into the growth chamber, the growth temperature, etc. In one example, the third nitride semiconductor layer 82 may contain magnesium as an impurity at a concentration of 1×10 18 cm -3 or more and less than 1×10 20 cm -3

[0072] The method for manufacturing the nitride semiconductor device 10 further includes forming a first gate electrode 30 on the third nitride semiconductor layer 82 and forming a second gate electrode 31 on the first gate electrode 30.

[0073] As shown in FIG. 6, a first metal layer 83 is formed on the third nitride semiconductor layer 82. Next, a second metal layer 84 is formed on the first metal layer 83. The first metal layer 83 and the second metal layer 84 are formed by sputtering. Details of the sputtering for forming the first metal layer 83 and the second metal layer 84 will be described later. Next, a first hard mask layer 88 is formed on the second metal layer 84. The first hard mask layer 88 may be, for example, a SiN layer.

[0074] ​Next, as shown in FIG. 7, the first metal layer 83, the second metal layer 84, and the first hard mask layer 88 are selectively removed by lithography and etching. As a result, a portion of the first metal layer 83 corresponding to the first gate electrode 30, a portion of the second metal layer 84 corresponding to the second gate electrode 31, and the first hard mask layer 88 covering the upper surface of the above portion of the second metal layer 84 are left on the third nitride semiconductor layer 82.

[0075] Here, forming the first gate electrode 30 and forming the second gate electrode 31 may include performing chemical etching on the third nitride semiconductor layer 82. In the final stage of etching the first metal layer 83, the second metal layer 84, and the first hard mask layer 88, the surface of the third nitride semiconductor layer 82 is exposed. At this time, the surface of the third nitride semiconductor layer 82 may be damaged by etching (for example, physical etching such as plasma etching) used for removing the first metal layer 83 and the second metal layer 84. Therefore, in at least a part (for example, the final stage) of the etching process, by performing chemical etching on the exposed surface of the third nitride semiconductor layer 82, the damage layer formed on the surface of the third nitride semiconductor layer 82 can be removed.

[0076] Additionally or alternatively, forming the first gate electrode 30 and forming the second gate electrode 31 may include performing atomic layer etching (ALE) on the third nitride semiconductor layer 82. In ALE, a reactive gas is chemically reacted with the outermost atomic layer of the etching target (for example, the third nitride semiconductor layer 82), and the reacted layer (for example, a single atomic layer) can be selectively etched by ion irradiation. By performing ALE on the exposed surface of the third nitride semiconductor layer 82, the damage layer formed on the surface of the third nitride semiconductor layer 82 can be removed.

[0077] The method of manufacturing the nitride semiconductor device 10 further includes forming the gate layer 28 by selectively removing the third nitride semiconductor layer 82. As shown in FIG. 8, a second hard mask layer 90 is formed to cover the first gate electrode 30, the second gate electrode 31, the first hard mask layer 88, and the third nitride semiconductor layer 82. The second hard mask layer 90 may be, for example, a SiN layer.

[0078] Next, as shown in FIG. 9, the second hard mask layer 90 is selectively removed by anisotropic etching. The anisotropic etching mainly proceeds in the thickness direction of the second hard mask layer 90. As a result, portions of the second hard mask layer 90 that cover the side surfaces of each of the first gate electrode 30, the second gate electrode 31, and the first hard mask layer 88 remain.

[0079] As shown in FIG. 10, the third nitride semiconductor layer 82 is etched using the first hard mask layer 88 and the second hard mask layer 90. A portion of the third nitride semiconductor layer 82 that is located under the first hard mask layer 88 and the second hard mask layer 90 is not etched, and as a result, a first portion 92 corresponding to the ridge portion 40 of the gate layer 28 described with reference to FIG. 3 is formed. On the other hand, a portion of the third nitride semiconductor layer 82 that is not covered by the first hard mask layer 88 and the second hard mask layer 90 is etched, and as a result, a second portion 96 shown in FIG. 10 is formed. The thickness of the second portion 96 of the third nitride semiconductor layer 82 may be equal to or less than half of the thickness of the first portion 92.

[0080] Next, as shown in FIG. 11, the third nitride semiconductor layer 82 is selectively removed so that a part of the second portion 96 corresponding to the first extending portion 42 and the second extending portion 44 remains. As a result, the gate layer 28 including the ridge portion 40, the first extending portion 42, and the second extending portion 44 is formed.

[0081] Although illustration is omitted, the manufacturing method of the nitride semiconductor device 10 includes forming a passivation layer 32 covering the second nitride semiconductor layer 80 (electron supply layer 24), gate layer 28, first gate electrode 30, and second gate electrode 31, forming a first opening 32A and a second opening 32B in the passivation layer 32, and forming a source electrode 34 in contact with the second nitride semiconductor layer 80 through the first opening 32A and a drain electrode 36 in contact with the second nitride semiconductor layer 80 through the second opening 32B. Thereby, the nitride semiconductor device 10 shown in FIG. 3 can be obtained.

[0082] (Details of sputtering) Regarding the details of sputtering used for forming the first gate electrode 30 and the second gate electrode 31, a case where the first metal layer 83 and the second metal layer 84 are TiN layers composed of the same material and having the same composition ratio of the material will be described as an example. Hereinafter, the sputtering used for forming the first gate electrode 30 will be described as the first sputtering, and the sputtering used for forming the second gate electrode 31 will be described as the second sputtering.

[0083] The first sputtering and the second sputtering are sputterings in which a voltage is applied to the target in an atmosphere of an inert gas. Examples of the first sputtering and the second sputtering include DC sputtering using a DC power source for the power supply and RF sputtering using a high-frequency power source for the power supply. Examples of the inert gas include argon gas.

[0084] Referring to FIG. 12, an example of a DC sputtering apparatus 100 used for the first sputtering and the second sputtering will be described. FIG. 12 is a schematic diagram of the DC sputtering apparatus 100 used for the above sputtering.

[0085] The DC sputtering apparatus 100 includes a vacuum chamber 101, a substrate stage 102, a target 103, and a power supply 104. When it is a DC magnetron sputtering apparatus, the DC sputtering apparatus 100 may have a magnet (not shown) that generates a magnetic force.

[0086] The substrate stage 102 is disposed inside the vacuum chamber 101. A semiconductor substrate 18 is placed on the substrate stage 102. The semiconductor substrate 18 is the semiconductor substrate 18 shown in FIG. 5, that is, a semiconductor substrate in which a buffer layer 20, a first nitride semiconductor layer 78, a second nitride semiconductor layer 80, and a third nitride semiconductor layer 82 are laminated, and the uppermost surface is formed by the third nitride semiconductor layer 82. In FIG. 12, the illustration of the buffer layer 20, the first nitride semiconductor layer 78, the second nitride semiconductor layer 80, and the third nitride semiconductor layer 82 is omitted.

[0087] The target 103 is a film-forming material used for sputtering. An example of the target 103 for forming a TiN layer is composed of pure Ti. Further, the target 103 may be composed of TiN. Note that the TiN layer 103a shown in FIG. 12 is a layer formed during sputtering. Details thereof will be described later.

[0088] The power supply 104 is a DC power supply that applies a DC voltage. For example, the power supply 104 has its anode grounded and its cathode connected to the target 103 to apply a DC voltage. The substrate stage 102 is, for example, at a floating potential. Hereinafter, the DC voltage applied by the power supply 104 is referred to as DC power.

[0089] Next, an example of a method for forming a first metal layer 83 corresponding to the first gate electrode 30 and a second metal layer 84 corresponding to the second gate electrode 31 using the DC sputtering apparatus 100 will be described.

[0090] First, first sputtering for forming the first metal layer 83 on the third nitride semiconductor layer 82 is performed on the semiconductor substrate 18 placed on the substrate stage 102. When performing the first sputtering, the inside of the vacuum chamber 101 is evacuated, for example, using a vacuum pump. Then, a first sputtering gas is introduced into the vacuum chamber 101. An example of the first sputtering gas is a mixed gas containing an inert gas, argon (Ar) gas, and a reactive gas, nitrogen (N2) gas. The mixing ratio (volume ratio) of argon gas and nitrogen gas in the first sputtering gas is, for example, in the range of 1:3 to 1:10. The above range of the mixing ratio includes the upper limit value and the lower limit value. The flow rate of the first sputtering gas into the vacuum chamber 101 is, in terms of nitrogen gas conversion, for example, 30 sccm or more and 100 sccm or less.

[0091] Next, a DC voltage of the first DC power is applied from the power supply 104, and the temperature of the substrate stage 102 is adjusted to the first temperature. Details of the first DC power and the first temperature will be described later. When the DC voltage of the first DC power is applied, the plasmaized nitrogen gas ions (N * ) form a TiN layer 103a on the surface of the target 103. Also, the inert gas, argon gas, discharges to generate cations (Ar + ). The generated cations (Ar + ) collide with the target 103, which is the cathode, to release target particles 105 from the TiN layer 103a on the surface of the target 103. The target particles 105 released at this time are TiN particles. When the released target particles 105 adhere to and deposit on the upper surface of the semiconductor substrate 18, a first metal layer 83 composed of a TiN layer is formed. Then, the application of the DC voltage from the power supply 104 is stopped.

[0092] Next, second sputtering for forming a second metal layer 84 is performed on the semiconductor substrate 18 on the first metal layer 83 formed by the first sputtering. From the end of the first sputtering to the start of the second sputtering, the reduced pressure state inside the vacuum chamber 101 is maintained. Then, a second sputtering gas is introduced into the vacuum chamber 101. An example of the second sputtering gas is a mixed gas containing argon gas, which is an inert gas, and nitrogen gas, which is a reactive gas. The mixing ratio (volume ratio) of argon gas and nitrogen gas in the second sputtering gas is, for example, in the range of 1:3 to 1:10. The above range of the mixing ratio includes the upper limit value and the lower limit value. The flow rate of the second sputtering gas into the vacuum chamber 101 is, in terms of nitrogen gas conversion, for example, 30 sccm or more and 100 sccm or less. One or both of the composition and flow rate of the second sputtering gas may be the same as or different from those of the first sputtering. An example of the composition and flow rate of the second sputtering gas is the same as that of the first sputtering. Also, the target 103 used for the second sputtering is the same as that for the first sputtering. In the second sputtering, the target 103 used in the first sputtering is used as it is.

[0093] Next, a DC voltage of the second DC power is applied from the power supply 104, and the temperature of the substrate stage 102 is adjusted to the second temperature. Details of the second DC power and the second temperature will be described later. By applying a DC voltage from the power supply 104, a second metal layer 84 composed of a TiN layer is formed in the same manner as in the first sputtering. Then, the application of the DC voltage from the power supply 104 is stopped.

[0094] Here, the energies imparted to the inert gas in the first sputtering and the second sputtering are different. That is, the energy imparted to the inert gas in the second sputtering (hereinafter referred to as the second energy) is greater than the energy imparted to the inert gas in the first sputtering (hereinafter referred to as the first energy).

[0095] The energy imparted to the inert gas can be adjusted by changing the DC power. That is, in order to make the second energy greater than the first energy, the second DC power applied in the second sputtering may be made greater than the first DC power applied in the first sputtering.

[0096] In this case, the first DC power applied in the first sputtering is, for example, 2 kW or less, 1.5 kW or less, or 1 kW or less. Also, the first DC power is, for example, 0.5 kW or more. The second DC power applied in the second sputtering is, for example, 20 kW or more, 30 kW or more, or 40 kW or more. Also, the second DC power is, for example, 50 kW or less. The ratio (P2 / P1) of the second DC power (P2) to the first DC power (P1) is, for example, 10 or more and 100 or less.

[0097] Also, the energy imparted to the inert gas can be adjusted by changing the temperature of the inert gas during sputtering. The temperature of the inert gas during sputtering is equal to the first temperature and the second temperature described above. Therefore, in order to make the second energy greater than the first energy, the second temperature used in the second sputtering may be made greater than the first temperature used in the first sputtering.

[0098] In this case, the first temperature used in the first sputtering is, for example, 30 °C or less, 25 °C or less, or 20 °C or less. Also, the first temperature is 15 °C or more. The second temperature used in the second sputtering is, for example, 100 °C or more, 200 °C or more, or 300 °C or more. Also, the second temperature is 350 °C or less. The ratio (Tem2 / Tem1) of the second temperature (Tem2) to the first temperature (Tem1) is, for example, 5 or more and 20 or less.

[0099] As a method of varying the energy applied to the inert gas in the first sputtering and the second sputtering, either increasing the second DC power to be greater than the first DC power and / or increasing the second temperature to be greater than the first temperature may be employed, or both may be employed.

[0100] As an example when the first temperature and the second temperature are the same, the first temperature and the second temperature are both the same at room temperature (for example, in the range of 20°C or more and 30°C or less), the first DC power is 0.8 kW or more and 1.2 kW or less, and the second DC power is 20 kW or more and 30 kW or less. As an example when the first DC power and the second DC power are the same, the first DC power and the second DC power are both the same in the range of 1.2 kW or more and 2 kW or less, the first temperature is 20°C or more and 30°C or less, and the second temperature is 250°C or more and 300°C or less.

[0101] Since the first energy applied to the inert gas in the first sputtering is small, the first metal layer 83 formed by the first sputtering becomes a layer with relatively low density. Therefore, the first density D1 of the first gate electrode 30 formed from the first metal layer 83 becomes relatively low. Similarly, since the second energy applied to the inert gas in the second sputtering is small, the second metal layer 84 formed by the second sputtering becomes a layer with relatively low density. Therefore, the second density D2 of the second gate electrode 31 formed from the second metal layer 84 becomes relatively high.

[0102] Specifically, in sputtering, the target particles 105 emitted from the target 103 adhere to and deposit on the upper surface of the semiconductor substrate 18. At this time, after the target particles 105 reach the upper surface of the semiconductor substrate 18, they move on the upper surface and are arranged at a predetermined position to form crystals. Also, as the target particles 105 moving on the upper surface of the semiconductor substrate 18 enter a place where the crystal state is incomplete, a highly perfect crystal is formed.

[0103] Here, in the first sputtering, since the first energy applied to the inert gas is small, the kinetic energy of the target particles 105 emitted from the target 103 becomes small. The target particles 105 with small kinetic energy have a short movement distance on the upper surface of the semiconductor substrate 18 after reaching the upper surface. In this case, since the movement distance of the target particles 105 is limited, the target particles 105 cannot move sufficiently to the places where the crystal state is incomplete, and the crystal grows in an incomplete state. As a result, a low-density first metal layer 83 composed of a crystal with low perfection is formed.

[0104] On the other hand, in the second sputtering, since the second energy applied to the inert gas is large, the kinetic energy of the target particles 105 emitted from the target 103 becomes large. The target particles 105 with large kinetic energy have a long movement distance on the upper surface of the semiconductor substrate 18 after reaching the upper surface. In this case, since the movement distance of the target particles 105 becomes long, the target particles 105 can move to the places where the crystal state is incomplete, and the crystal grows in a complete or nearly complete state. As a result, a high-density second metal layer 84 composed of a crystal with high perfection is formed.

[0105] As a reference test, the temperature of the semiconductor substrate 18 was set to 25°C, the DC power was set to 0.8 kW or 1.2 kW, and the flow rate of the sputtering gas in terms of nitrogen gas (hereinafter referred to as the nitrogen gas flow rate) was changed to form a TiN layer, and the resistivity of the formed TiN layer was measured. The results are shown in FIG. 13.

[0106] FIG. 13 is a graph showing the relationship between the DC power of DC sputtering and the resistivity of the formed TiN layer. The horizontal axis of the graph shown in FIG. 13 indicates the nitrogen gas flow rate, and the vertical axis indicates the resistivity of the formed TiN layer. As shown in FIG. 13, the resistivity of the TiN layer formed at a low DC power (0.8 kW) is higher than that of the TiN layer formed at a high DC power (1.2 kW) at any nitrogen gas flow rate. From this result, it can be seen that by using a relatively low DC power, a TiN layer with a high resistivity is formed, and by using a relatively high DC power, a TiN layer with a low resistivity is formed.

[0107] (Actions and Effects) According to the nitride semiconductor device 10 and the method of manufacturing the nitride semiconductor device 10, the following actions and effects can be obtained.

[0108] (1) The nitride semiconductor device 10 includes an electron traveling layer 22, an electron supply layer 24 provided on the electron traveling layer 22, a gate layer 28 provided on the electron supply layer 24 and composed of a nitride semiconductor containing acceptor-type impurities, a first gate electrode 30 in contact with the upper surface 28A of the gate layer 28, and a second gate electrode 31 located above the first gate electrode 30. A second density D2, which is the density of the second gate electrode 31, is higher than a first density D1, which is the density of the first gate electrode 30.

[0109] According to this configuration, a second gate electrode 31 having a higher density than the first gate electrode 30 is formed on the first gate electrode 30. Based on its high density, the second gate electrode 31 has a lower resistivity than the first gate electrode 30. Since the second gate electrode 31 having a low resistivity is formed on the first gate electrode 30, the resistance of the entire gate electrode including the first gate electrode 30 and the second gate electrode 31 can be reduced. As a result, the switching responsiveness of the nitride semiconductor device 10 can be improved.

[0110] (2) The thickness T2 of the second gate electrode 31 is greater than the thickness T1 of the first gate electrode 30. According to this configuration, among the first gate electrode 30 and the second gate electrode 31, the ratio of the second gate electrode 31 occupying in the Z-axis direction becomes larger. Therefore, the resistance of the entire gate electrode including the first gate electrode 30 and the second gate electrode 31 can be further reduced. Accordingly, the effect of improving the switching responsiveness can be obtained more remarkably.

[0111] (3) The manufacturing method of the nitride semiconductor device 10 includes forming a first nitride semiconductor layer 78 that constitutes the electron traveling layer 22, forming a second nitride semiconductor layer 80 that constitutes the electron supply layer 24 on the first nitride semiconductor layer 78, forming a third nitride semiconductor layer 82 containing acceptor-type impurities on the second nitride semiconductor layer 80, forming a first gate electrode 30 on the third nitride semiconductor layer 82 using first sputtering, and forming a second gate electrode 31 on the first gate electrode 30 using second sputtering. The energy imparted to the inert gas in the sputtering when forming the second gate electrode 31 is greater than the energy imparted to the inert gas in the sputtering when forming the first gate electrode 30.

[0112] As the first sputtering for forming the first gate electrode 30 on the third nitride semiconductor layer 82, sputtering with reduced energy imparted to the inert gas is adopted. In this case, in the first sputtering, the injection of atoms derived from the inert gas (for example, argon atoms) and target particles 105 (for example, Ti) into the third nitride semiconductor layer 82 is suppressed. As a result, the amorphization in the third nitride semiconductor layer 82 and the generation of interstitial atoms are suppressed. Thereby, the leakage current in the Schottky junction formed between the gate layer 28 constituted by the third nitride semiconductor layer 82 and the first gate electrode 30 which is a metal layer formed on the third nitride semiconductor layer 82 can be suppressed. However, the first gate electrode 30 formed by sputtering with reduced energy imparted to the inert gas becomes a layer with a high resistivity due to its low density.

[0113] Therefore, in the above configuration, while forming the second gate electrode 31 on the first gate electrode 30 (first metal layer 83), as the second sputtering for forming the second gate electrode 31, sputtering with increased energy applied to the inert gas is adopted. In this case, a second gate electrode 31 (second metal layer 84) with high density, that is, low resistivity, is formed on the first gate electrode 30. By forming the second gate electrode 31 with low resistivity, the resistance of the entire gate electrode including the first gate electrode 30 and the second gate electrode 31 can be reduced. As a result, the switching responsiveness of the manufactured nitride semiconductor device 10 can be improved. Therefore, according to this configuration, it is possible to achieve both the effect of suppressing the leakage current in the Schottky junction formed between the gate layer 28 and the first gate electrode 30 and the effect of improving the switching responsiveness.

[0114] (4) The sputtering for forming the second gate electrode 31 is continuously performed while maintaining a reduced pressure state from the sputtering for forming the first gate electrode 30. According to this configuration, the first gate electrode 30 and the second gate electrode 31 can be efficiently formed.

[0115] (Modified Example) The above embodiment can be implemented with the following modifications. · The gate layer 28 may not include the extending portions 42 and 44. That is, the gate layer 28 may be formed to have a substantially uniform thickness.

[0116] · Regarding the first sputtering and the second sputtering, other conditions other than the DC power and the temperature of the inert gas may be made different. Examples of other conditions include the type of the target 103, the composition and flow rate of the sputtering gas.

[0117] · The first sputtering and the second sputtering may be performed discontinuously. For example, when the target 103 used for the first sputtering is different from the target 103 used for the second sputtering, after the first sputtering, the reduced pressure state in the vacuum chamber 101 is released. Then, after replacing the target 103, the inside of the vacuum chamber 101 is depressurized again to perform the second sputtering.

[0118] One or more of the various examples described in this specification can be combined within a technically non - conflicting range. In this specification, the description "at least one of A and B" should be understood to mean "only A, or only B, or both A and B".

[0119] As used in this specification, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the expression "the first layer is formed on the second layer" is intended that in some embodiments, the first layer can be directly disposed on the second layer in contact with the second layer, while in other embodiments, the first layer can be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which other layers are formed between the first layer and the second layer.

[0120] Terms indicating directions such as "vertical", "horizontal", "above", "below", "up", "down", "front", "rear", "longitudinal", "lateral", "left", "right", "forward", "backward" used in this specification depend on the specific orientation of the device being described and illustrated. In the present disclosure, various alternative orientations can be assumed, and thus these terms indicating directions should not be construed narrowly.

[0121] For example, the Z - axis direction used in this specification does not necessarily have to be the vertical direction and does not have to exactly coincide with the vertical direction. For example, the X - axis direction may be the vertical direction, or the Y - axis direction may be the vertical direction.

[0122] (Supplementary Note) The technical idea that can be grasped from the present disclosure is described below. Note that, for the purpose of assisting understanding rather than limitation, the components described in the supplementary note are assigned the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples for assisting understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0123] [Supplementary Note 1] An electron transport layer (22) composed of a nitride semiconductor, An electron supply layer (24) provided on the electron transport layer (22) and composed of a nitride semiconductor, A gate layer (28) provided on the electron supply layer (24) and composed of a nitride semiconductor containing acceptor-type impurities, A first gate electrode (30) in contact with the upper surface (28A) of the gate layer (28), A second gate electrode (31) located above the first gate electrode (30), and A nitride semiconductor device (10) in which a second density (D2) that is the density of the second gate electrode (31) is higher than a first density (D1) that is the density of the first gate electrode (30).

[0124] [Supplementary Note 2] The nitride semiconductor device (10) according to Supplementary Note 1, wherein the first gate electrode (30) and the second gate electrode (31) are made of the same material.

[0125] [Supplementary Note 3] The nitride semiconductor device (10) according to Supplementary Note 2, wherein the composition ratio of the first gate electrode (30) and the composition ratio of the second gate electrode (31) are the same.

[0126] [Supplementary Note 4] The nitride semiconductor device (10) according to any one of Supplementary Notes 1 to 3, wherein the first gate electrode (30) is configured to form a Schottky junction with the gate layer (28).

[0127] [Appendix 5] The nitride semiconductor device (10) according to any one of Appendices 1 to 4, wherein the first gate electrode (30) and the second gate electrode (31) are made of a metal nitride.

[0128] [Appendix 6] The nitride semiconductor device (10) according to any one of Appendices 1 to 4, wherein the first gate electrode (30) and the second gate electrode (31) contain at least one of TiN, TaN, WN, TiSiN, TaSiN, WSiN, WSi, ZrN, HfN, and MoN.

[0129] [Appendix 7] The nitride semiconductor device (10) according to any one of Appendices 1 to 6, wherein the thickness (T2) of the second gate electrode (31) is thicker than the thickness (T1) of the first gate electrode (30).

[0130] [Appendix 8] Including a source electrode (34) and a drain electrode (36) disposed so as to sandwich the gate layer (28) and in contact with the upper surface of the electron supply layer (24), The source electrode (34) and the drain electrode (36) are made of the same material as the second gate electrode (31), The nitride semiconductor device (10) according to claim 1, wherein the density of the source electrode (34) and the drain electrode (36) is the same as the second density (D2).

[0131] [Appendix 9] Forming a first nitride semiconductor layer (78) constituting the electron traveling layer (22); Forming a second nitride semiconductor layer (80) constituting the electron supply layer (24) on the first nitride semiconductor layer (78); Forming a third nitride semiconductor layer (82) containing acceptor-type impurities on the second nitride semiconductor layer (80); Forming a first gate electrode (30) on the third nitride semiconductor layer (82) by using sputtering in which a voltage is applied to a target in an atmosphere of an inert gas; Forming a second gate electrode (31) on the first gate electrode (30) by using the sputtering, and including: A method for manufacturing a nitride semiconductor device, wherein energy imparted to the inert gas in the sputtering when forming the second gate electrode (31) is greater than energy imparted to the inert gas in the sputtering when forming the first gate electrode (30).

[0132] [Appendix 10] The sputtering is DC sputtering in which a DC voltage is applied as the voltage, A method for manufacturing a nitride semiconductor device according to Appendix 9, wherein a DC voltage applied in the DC sputtering when forming the second gate electrode (31) is greater than a DC voltage applied in the DC sputtering when forming the first gate electrode (30).

[0133] [Appendix 11] A method for manufacturing a nitride semiconductor device according to Appendix 9 or Appendix 10, wherein the temperature of the inert gas in the sputtering when forming the second gate electrode (31) is greater than the temperature of the inert gas in the sputtering when forming the first gate electrode (30).

[0134] [Appendix 12] A method for manufacturing a nitride semiconductor device according to any one of Appendices 9 to 11, wherein the target used in the sputtering when forming the first gate electrode (30) is the same as the target used in the sputtering when forming the second gate electrode (31).

[0135] [Appendix 13] The sputtering for forming the second gate electrode (31) is continuously performed while maintaining a reduced pressure state from the sputtering for forming the first gate electrode (30), and the method for manufacturing a nitride semiconductor device according to any one of Appendices 9 to 12.

Explanation of Signs

[0136] T1, T2… Thickness 10… Nitride semiconductor device 10A… Upper surface 12… Gate pad 14… Source pad 16… Drain pad 18… Semiconductor substrate 20… Buffer layer 22… Electron traveling layer 24… Electron supply layer 26… Two-dimensional electron gas (2DEG) 28… Gate layer 28A… Upper surface 28B… Lower surface 28C… Side surface 30… First gate electrode 30A… Upper surface 30B… Lower surface 30C… Side surface 31… Second gate electrode 31A… Upper surface 31B… Lower surface 31C… Side surface 32… Passivation layer 32A… First opening 32B… Second opening 34… Source electrode 36… Drain electrode 38… Field plate electrode 40… Ridge portion 42… First extending portion 44… Second extending portion 46… First step portion 48… First intermediate portion 50… Second step portion 52… Second intermediate portion 54, 58… Body portion 56, 60… Connection portion 62… Gate wiring 64…Source wiring 66…Drain wiring 68, 70, 72…Via 78…First nitride semiconductor layer 80…Second nitride semiconductor layer 82…Third nitride semiconductor layer 83…First metal layer 84…Second metal layer 88…First hard mask layer 90…Second hard mask layer 92…First part 96…Second part 100…DC sputtering apparatus 101…Vacuum chamber 102…Substrate stage 103…Target 103a…TiN layer 104…Power supply 105…Target particles

Claims

1. An electron transport layer composed of a nitride semiconductor, an electron supply layer provided on the electron transport layer and composed of a nitride semiconductor, a gate layer provided on the electron supply layer and composed of a nitride semiconductor containing an acceptor-type impurity, a first gate electrode in contact with the upper surface of the gate layer, a second gate electrode located above the first gate electrode, and a nitride semiconductor device, wherein a second density which is the density of the second gate electrode is higher than a first density which is the density of the first gate electrode.

2. The nitride semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are made of the same material.

3. The nitride semiconductor device according to claim 2, wherein a composition ratio of the first gate electrode is the same as a composition ratio of the second gate electrode.

4. The nitride semiconductor device according to claim 1, wherein the first gate electrode is configured to form a Schottky junction with the gate layer.

5. The nitride semiconductor device according to claim 2, wherein the first gate electrode and the second gate electrode are made of a metal nitride.

6. The nitride semiconductor device according to claim 2, wherein the first gate electrode and the second gate electrode contain at least one of TiN, TaN, WN, TiSiN, TaSiN, WSiN, WSi, ZrN, HfN, and MoN.

7. The nitride semiconductor device according to claim 1, wherein a thickness of the second gate electrode is thicker than a thickness of the first gate electrode.

8. Forming a first nitride semiconductor layer constituting an electron transport layer, forming a second nitride semiconductor layer constituting an electron supply layer on the first nitride semiconductor layer, forming a third nitride semiconductor layer containing an acceptor-type impurity on the second nitride semiconductor layer, forming a first gate electrode on the third nitride semiconductor layer by using sputtering in which a voltage is applied to a target in an atmosphere of an inert gas, forming a second gate electrode on the first gate electrode by using the sputtering, and a method for manufacturing a nitride semiconductor device, wherein energy imparted to the inert gas in the sputtering when forming the second gate electrode is greater than energy imparted to the inert gas in the sputtering when forming the first gate electrode.

9. The sputtering is DC sputtering in which a DC voltage is applied as the voltage, The DC voltage applied in the DC sputtering when forming the second gate electrode is greater than the DC voltage applied in the DC sputtering when forming the first gate electrode. A method for manufacturing a nitride semiconductor device according to claim 8.

10. The temperature of the inert gas when forming the second gate electrode is greater than the temperature of the inert gas when forming the first gate electrode. A method for manufacturing a nitride semiconductor device according to claim 8 or claim 9.

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