Control device and control method

Abstract

To provide a control device and a control method for suppressing harmonics in an output voltage of an inverter power supply device.SOLUTION: A control device 100 includes: an adding unit 117 that writes a value obtained by multiplying a value stored in the Pth first register by (1-K1) and a value obtained by multiplying a capacitor current error value by 2πfL×K1 to the Pth first register; an adding unit 121 that writes a value obtained by multiplying a value stored in the Pth second register by (1-K2) and a value obtained by multiplying a load current differential value by 2πfL×K2 to the Pth second register; an adding unit 122 that adds a value stored in the P+1th first register to a value stored in the P+2th second register; and an adding unit 108 that adds the output voltage command value of an inverter voltage power supply device to the value added by the adding unit 122 and generates the inverter voltage command value.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a control device and a control method for an inverter power supply device that outputs an alternating voltage.

Background Art

[0002] An inverter power supply device is generally required to output a stable alternating voltage with little fluctuation to a load. In the control of a conventional inverter power supply device, feedforward control for controlling the inverter current and the output voltage based on the output target voltage value and the load current value, and feedback control for correcting the error between the output voltage value and the inverter current value by proportional-integral control are combined for control (see, for example, Patent Document 1). Further, when handling an alternating voltage, the voltage and current are handled as complex numbers and expressed in a rotating coordinate form or a polar coordinate form by a mathematical coordinate conversion operation, enabling integral control.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] FIG. 4 is a diagram showing a configuration example of an inverter power supply device 10. As shown in FIG. 4, the inverter power supply device 10 includes a three-phase inverter circuit section 11 and a three-phase LC filter circuit section 12. The three-phase inverter circuit section 11 supplies an alternating voltage (three-phase alternating voltage) corresponding to an inverter voltage command value output from a control device 100a described later to a load 20 via the three-phase LC filter circuit section 12.

[0005] The three-phase LC circuit filter section 12 includes an LC filter in which an inductor and a capacitor are connected in an L shape, provided corresponding to each phase, and removes harmonic components included in the output voltage of the three-phase inverter circuit section 11 and supplies it to the load 20.

[0006] The control device 100a generates an inverter voltage command value based on the current value of the current flowing through the inverter power supply device 10 (inverter current value), the output voltage value of the inverter power supply device 10, and the current value of the current flowing through the load 20 (load current value), and outputs it to the three-phase inverter circuit section 11.

[0007] FIG. 5 is a diagram showing a configuration example of a conventional control device 100a.

[0008] As shown in FIG. 5, the control device 100a includes a proportional-integral control section 101, a multiplication section 102, an addition section 103, a proportional-integral control section 104, an addition section 105, a multiplication section 106, an addition section 107, and an addition section 108a.

[0009] The proportional-integral control section 101 receives the output voltage value of the inverter power supply device 10 and the output voltage target value which is the target value of the output voltage of the inverter power supply device 10. The proportional-integral control section 101 generates a voltage error correction amount for correcting the error between the output voltage value and the output voltage target value by proportional-integral control, and outputs it to the addition section 108a.

[0010] The multiplication section 102 receives the output voltage target value. The multiplication section 102 multiplies the input output voltage target value by 1 / 2πfC. Here, f is the output frequency of the inverter power supply device 10. Also, C is the capacitance value of the capacitor that constitutes the three-phase LC filter circuit section 12. The multiplication value of the multiplication section 102 corresponds to the target value of the current flowing through the capacitor (capacitor current target value). The multiplication section 102 outputs the calculated capacitor current target value to the addition section 103.

[0011] The adder 103 receives the capacitor current target value and the load current value. The adder 103 adds the input capacitor current target value and the load current value. The added value of the adder 103 corresponds to the target value of the current flowing through the inverter power supply device 10 (inverter current target value). The adder 103 outputs the calculated inverter current target value to the proportional integral control unit 104 and the adder 105.

[0012] The proportional integral control unit 104 receives the inverter current target value and the inverter current value. The proportional integral control unit 104 generates a current error correction amount for correcting the error between the inverter current value and the inverter current target value by proportional integral control, and outputs it to the adder 105.

[0013] The adder 105 receives the inverter current target value and the current error correction amount. The adder 105 adds the input inverter current target value and the current error correction amount. The added value of the adder 105 corresponds to the inverter current command value for instructing the inverter current. The adder 105 outputs the calculated inverter current command value to the multiplier 106.

[0014] The multiplier 106 receives the inverter current command value. The multiplier 106 multiplies the input inverter current command value by 2πfL. Here, L is the inductance value of the inductor constituting the three-phase LC filter circuit section 12. The multiplied value of the multiplier 106 corresponds to the target value of the voltage applied to the inductor (inductor voltage target value). The multiplier 106 outputs the calculated inductor voltage target value to the adder 107.

[0015] The adder 107 receives the output voltage target value and the inductor voltage target value. The adder 107 adds the input output voltage target value and the inductor voltage target value. The added value of the adder 107 corresponds to the target value of the voltage of the inverter power supply device 10 (inverter voltage target value). The adder 107 outputs the calculated inverter voltage target value to the adder 108a.

[0016] The adder 108a receives the voltage error correction amount and the target inverter voltage. The adder 108a adds the input voltage error correction amount and the target inverter voltage. The added value of the adder 108a corresponds to the command value of the output voltage of the inverter power supply 10 (output voltage command value). The adder 108a outputs an inverter voltage command corresponding to the calculated output voltage command value to the three-phase inverter circuit section 11.

[0017] When the inverter power supply 10 that outputs a three-phase AC voltage is connected to a DC load having a rectifier, there is a problem that harmonics are generated in the output voltage of the inverter power supply 10 due to distortion of the load current. In the general proportional-integral control by the control device 100a shown in FIG. 5, it is difficult to suppress such harmonics.

[0018] In view of the above problems, an object of the present invention is to provide a control device and a control method capable of suppressing harmonics in the output voltage that occur when an inverter power supply is connected to a DC load having a rectifier.

Means for Solving the Problems

[0019] To solve the above problems, a control device according to the present invention is a control device for an inverter power supply device that supplies an AC voltage to a load via an LC filter circuit composed of an inductor and a capacitor. When the output frequency of the inverter power supply device is f and the control period of the inverter power supply device is Tc, it satisfies N=(1 / fTc)×1 / 6. It includes a first storage area composed of N first registers numbered from 0 to N-1, a second storage area composed of N second registers numbered from 0 to N-1, a first update unit for updating the values of the first registers, a third update unit for updating the values of the second registers, a first addition unit for calculating an addition value obtained by adding the value stored in the first register and the value stored in the second register, and a second addition unit for adding the addition value to the output voltage command value of the inverter power supply device to generate an inverter voltage command value for instructing the output voltage of the inverter power supply device. Each of the N first registers numbered from 0 to N-1 is associated with each phase θs(=2π / 6÷N), and each of the N second registers numbered from 0 to N-1 is associated with each phase θs. When the integer part obtained by dividing the remainder of dividing the current phase of the output voltage target value of the inverter power supply device by π / 3 by the phase θs is P, the first update unit multiplies the value stored in the P-th first register by (1-K1) (K1 is a predetermined first constant), and adds the value obtained by multiplying the capacitor current error value, which is the error between the capacitor current target value and the current flowing through the capacitor, by 2πfL×K1 (L is the inductance value of the capacitor), and writes the obtained value into the P-th first register. The third update unit multiplies the value stored in the P-th second register by (1-K2) (K2 is a predetermined second constant), and adds the value obtained by multiplying the load current derivative value obtained by differentiating the load current value of the load by 2πfL×K2, and writes the obtained value into the P-th second register. The first addition unit adds the value stored in the (P+1)-th first register and the value stored in the (P+2)-th second register.

[0020] Also, in the control device according to the present invention, it further includes a second update unit that updates the values of the N first registers, and a fourth update unit that updates the values of the N second registers. When the fractional part obtained by dividing the remainder obtained by dividing the current phase of the output voltage target value of the inverter power supply device by π / 3 by θs is defined as Wg, the first update unit multiplies the value stored in the P-th first register by (1 - K1), adds the value obtained by multiplying the capacitor current error value by 2πfL×K1 and (1 - Wg), and writes the resulting value into the P-th first register. The second update unit multiplies the value stored in the (P + 1)-th first register by (1 - K1), adds the value obtained by multiplying the capacitor current error value by 2πfL×K1 and Wg, and writes the resulting value into the (P + 1)-th first register. The third update unit multiplies the value stored in the P-th second register by (1 - K2), adds the value obtained by multiplying the load current derivative value by 2πfL×K2 and (1 - Wg), and writes the resulting value into the P-th second register. The fourth update unit multiplies the value stored in the (P + 1)-th second register by (1 - K2), adds the value obtained by multiplying the load current derivative value by 2πfL×K2 and Wg, and writes the resulting value into the (P + 1)-th second register. The first addition unit adds the value obtained by multiplying the value stored in the (P + 1)-th first register by (1 - Wg), the value obtained by multiplying the value stored in the (P + 2)-th first register by Wg, the value obtained by multiplying the value stored in the (P + 2)-th second register by (1 - Wg), and the value obtained by multiplying the value stored in the (P + 3)-th second register by Wg.

[0021] Also, to solve the above problems, a control method according to the present invention is a control method executed by a control device of an inverter power supply device that supplies an AC voltage to a load via an LC filter circuit composed of an inductor and a capacitor. When the output frequency of the inverter power supply device is f and the control period of the inverter power supply device is Tc, the control device includes a first storage area composed of N first registers numbered from 0 to N - 1 that satisfies N=(1 / fTc)×1 / 6, and a second storage area composed of N second registers numbered from 0 to N - 1. The N first registers numbered from 0 to N - 1 are each associated with a phase θs(=2π / 6÷N)°, and the N second registers numbered from 0 to N - 1 are each associated with a phase θs. When the integer part obtained by dividing the remainder of dividing the current phase of the output voltage target value of the inverter power supply device by π / 3 by the phase θs is P, a value obtained by multiplying the value stored in the P-th first register by (1 - K1) (K1 is a predetermined first constant) and a value obtained by multiplying the capacitor current error value, which is the error between the capacitor current target value and the current flowing through the capacitor, by 2πfL×K1 (L is the inductance value of the capacitor) are added, and the added value is written into the P-th first register. A value obtained by multiplying the value stored in the P-th second register by (1 - K2) (K2 is a predetermined second constant) and a value obtained by multiplying the load current derivative value obtained by differentiating the load current value of the load by 2πfL×K2 are added, and the added value is written into the P-th second register. A step of calculating an added value obtained by adding the value stored in the (P + 1)-th first register and the value stored in the (P + 2)-th second register. A step of adding the added value to the output voltage command value of the inverter power supply device to generate an inverter voltage command value for instructing the output voltage of the inverter power supply device.

Effect of the Invention

[0022] According to the control device and the control method of the present invention, it is possible to suppress the harmonics of the output voltage that occur when the inverter power supply device is connected to a DC load having a rectifier.

Brief Description of the Drawings

[0023]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0024] Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

[0025] (First Embodiment) FIG. 1 is a diagram showing the configuration of a control device 100 according to a first embodiment of the present disclosure. The control device 100 according to the present embodiment controls an inverter power supply device 10 that supplies an AC voltage to a load 20 via an LC filter circuit (three-phase LC filter circuit unit 12) composed of an inductor and a capacitor from the AC voltage output from a three-phase inverter unit 11 shown in FIG. 4. In FIG. 1, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted.

[0026] As shown in FIG. 1, the control device 100 according to the present embodiment includes a proportional-integral control unit 101, a multiplication unit 102, an addition unit 103, a proportional-integral control unit 104, an addition unit 105, a multiplication unit 106, an addition unit 107, an addition unit 108 as a second addition unit, a first storage area 110, a second storage area 111, a phase information extraction unit 112, a division unit 113, a subtraction unit 114, a multiplication unit 115, a multiplication unit 116, an addition unit 117 as a first update unit, a differentiation unit 118, a multiplication unit 119, a multiplication unit 120, an addition unit 121 as a third update unit, and an addition unit 122 as a first addition unit. The control device 100 according to the present embodiment is different from the conventional control device 100a shown in FIG. 5 in that the first storage area 110, the second storage area 111, the phase information extraction unit 112, the division unit 113, the subtraction unit 114, the multiplication unit 115, the multiplication unit 116, the addition unit 117, the differentiation unit 118, the multiplication unit 119, the multiplication unit 120, the addition unit 121, and the addition unit 122 are added, and the addition unit 108a is changed to the addition unit 108.

[0027] Let the output frequency of the inverter power supply device 10 be f and the control period of the inverter power supply device 10 be Tc. Then, the first storage area 110 includes N first registers that satisfy N = (1 / fTc) × 1 / 6. In the present embodiment, it is assumed that the output frequency f and the control period Tc are fixed, that is, the ratio of the output frequency f to the control period Tc is fixed.

[0028] The N first registers are assigned numbers from 0 to N - 1. Each of the N first registers from 0 to N - 1 is associated with a phase θs(=2π / 6÷N). Specifically, the 0th first register is associated with 0 (rad), the 1st first register is associated with θs (rad), the Pth first register is associated with P×θs (rad), and the (N - 1)th first register is associated with 2π / 6 - θs. For phases greater than 2π / 6, starting from the 0th first register in order, they are associated with a phase θs(=2π / 6÷N). Therefore, six phases of 0 + n×θs, 2π / 6 + n×θs, 4π / 6 + n×θs, 6π / 6 + n×θs, 8π / 6 + n×θs, 10π / 6 + n×θs are assigned to the nth (n is an integer from 0, 1 ··· N - 1) first register.

[0029] The second storage area 111 also includes N second registers numbered from 0 to N - 1, similar to the first storage area 110. The N second registers are assigned numbers from 0 to N - 1. Similar to the first register, six phases of 0 + n×θs, 2π / 6 + n×θs, 4π / 6 + n×θs, 6π / 6 + n×θs, 8π / 6 + n×θs, 10π / 6 + n×θs are assigned to the nth (n is an integer from 0, 1 ··· N - 1) second register.

[0030] The phase information extraction unit 112, division unit 113, subtraction unit 114, multiplication unit 115, multiplication unit 116, addition unit 117, differentiation unit 118, multiplication unit 119, multiplication unit 120, addition unit 121, addition unit 122, and addition unit 108a perform the following processing at each control timing of the inverter power supply device 10.

[0031] The phase information extraction unit 112 receives the output voltage target value. The phase information extraction unit 112 outputs the phase information indicating the current phase θ of the input output voltage target value to the division unit 113.

[0032] The division unit 113 receives the phase information and the phase θs (= 2π / 6÷N). The division unit 113 divides the remainder obtained by dividing the current phase θ of the output voltage target value indicated by the phase information by π / 3 by the phase θs, and outputs the quotient (integer part P) to the multiplication unit 116, the addition unit 117, the multiplication unit 120, and the addition unit 121.

[0033] The subtraction unit 114 receives the load current value, the inverter current value, and the capacitor current target value. The subtraction unit 114 subtracts the inverter current value and the capacitor current target value from the load current value. The subtraction value of the subtraction unit 114 corresponds to the error (capacitor current error value) between the current flowing through the capacitor constituting the three-phase LC filter circuit unit 12 and the capacitor current target value. The subtraction unit 114 outputs the calculated capacitor current error value to the multiplication unit 115.

[0034] The multiplication unit 115 receives the capacitor current error value. The multiplication unit 115 multiplies the input capacitor current error value by 2πfL×K1 (the first constant). Here, K1 is a predetermined constant and has a value of about 0 to 0.5. The multiplication unit 115 outputs the multiplication value to the addition unit 117.

[0035] The multiplication unit 116 reads out the value stored in the P-th first register of the first storage area 110, multiplies the read value by (1 - K1), and outputs the multiplication value to the addition unit 117.

[0036] The addition unit 117 receives the multiplication value of the multiplication unit 115 and the multiplication value of the multiplication unit 116. The addition unit 117 adds the input multiplication value of the multiplication unit 115 and the multiplication value of the multiplication unit 116, and writes the addition value into the P-th first register. That is, the addition unit 117 updates the value of the first register. Specifically, the addition unit 117 adds the value obtained by multiplying the value stored in the P-th first register by (1 - K1) and the value obtained by multiplying the capacitor current error value, which is the error between the capacitor current target value and the current flowing through the capacitor, by 2πfL×K1, and writes the added value into the P-th first register.

[0037] The differentiator 118 receives the load current value. The differentiator 118 differentiates the input load current and outputs the differentiated value (load current differentiated value) to the multiplier 119.

[0038] The multiplier 119 receives the load current differentiated value. The multiplier 119 multiplies the input load current differentiated value by 2πfL×K2 (the second constant). Here, K2 is a predetermined constant and has a value of about 0 to 0.5. The multiplier 119 outputs the multiplied value to the adder 121.

[0039] The multiplier 120 reads out the value stored in the P-th second register of the second storage area 111, multiplies the read value by (1 - K2), and outputs the multiplied value to the adder 121.

[0040] The adder 121 receives the multiplied value of the multiplier 119 and the multiplied value of the multiplier 120. The adder 117 adds the input multiplied value of the multiplier 119 and the multiplied value of the multiplier 120, and writes the added value to the P-th second register. That is, the adder 121 updates the value of the second register. Specifically, the adder 121 adds the value obtained by multiplying the value stored in the P-th second register by (1 - K2) and the value obtained by multiplying the load current differentiated value obtained by differentiating the load current value by 2πfL×K2, and writes the added value to the P-th second register.

[0041] The adder 122 adds the value stored in the first register and the value stored in the second register, and outputs the added value to the adder 108. Specifically, the adder 122 adds the value stored in the (P + 1)-th first register and the value stored in the (P + 2)-th second register, and outputs the added value to the adder 108.

[0042] The adder 108 adds the added value of the adder 122 to the output voltage command value of the inverter power supply device 10 to generate an inverter voltage command value. Specifically, the adder 108 calculates the output voltage command value by adding the voltage error correction amount and the inverter voltage target value, and adds the added value of the adder 122 to the calculated output voltage command value to generate an inverter voltage command value.

[0043] Note that the output voltage value, output voltage target value, inverter current value, capacitor current value, etc. are complex numbers. A complex number is represented as a combination of a real part x and an imaginary part y in the rectangular form (x + iy), and as a combination of a magnitude r and a phase θ in the polar coordinate form (r∠θ). In the first storage area 110 and the second storage area 111, these combinations are stored to store complex numbers. Also, the calculated values in the multiplication units 116, 120 and the addition units 117, 121 are treated as complex numbers.

[0044] When values are stored in the first storage area 110 and the second storage area 111 in the rectangular form, coordinate conversion processing is performed as necessary to calculate the phase value in the polar coordinate form. The conversion formulas are, for example, x = rcosθ, y = rsinθ, r = √(x 2 + y 2 ), θ = {Tan -1 (-y / -(y / x))} (when x > 0 and y ≥ 0), θ = {π + Tan -1 (-y / -x)} (when x < 0 and y ≤ 0), θ = {3π / 4 + Tan -1 (x / -y)} (when x ≥ 0 and y < 0).

[0045] The theoretical value of the capacitor current is a complex number whose real part is 0 and whose imaginary part is calculated as the output voltage target value × 2π × output frequency × capacitor capacitance.

[0046] FIG. 2 is a flowchart showing an example of the operation of the control device 100 according to the present embodiment, and is a diagram for explaining the control method executed by the control device 100.

[0047] The addition unit 117 updates the value of the first register of P (step S11). Specifically, the addition unit 117 writes, to the first register of P, a value obtained by adding a value obtained by multiplying the value stored in the first register of P by (1 - K1) and a value obtained by multiplying the capacitor current error value by 2πfL × K1.

[0048] The adder 121 updates the value of the second register of the P-th. Specifically, the adder 121 stores, in the second register of the P-th, a value obtained by adding a value obtained by multiplying the value stored in the second register of the P-th by (1 - K2) and a value obtained by multiplying the load current derivative value by 2πfL×K2.

[0049] The adder 122 calculates an addition value obtained by adding the value stored in the first register of the (P + 1)-th and the value stored in the second register of the (P + 2)-th (step S13).

[0050] The adder 108 adds the addition value of the adder 122 to the output voltage command value of the inverter power supply device 10 to generate an inverter voltage command value (step S14).

[0051] The capacitor current error value and the load current derivative value are caused by the harmonics of the output voltage that occur when the inverter power supply device 10 is connected to a load 20 having a rectifier. In the present embodiment, the values (Y[P]) stored in the first register and the second register assigned to the current phase θ (= P×(60° / N)) are updated in a first-order lag form (Y[P]) = (1 - K)Y[P]+KX (K is a constant from 0 to 0.5). Then, by adding the values (Y[P + a], a is an integer of 1 or more) stored in the first register and the second register assigned to the next phase to the output voltage command value, the harmonics of the output voltage of the inverter power supply device 10 can be suppressed.

[0052] (Second Embodiment) FIG. 3 is a diagram showing a configuration example of a control device 100A according to the second embodiment of the present disclosure. The control device 100A according to the present embodiment is applicable when the control cycle Tc and the output frequency of the inverter power supply device 10 are variable.

[0053] The control device 100A according to this embodiment includes a proportional-integral control unit 101, a multiplication unit 102, an addition unit 103, a proportional-integral control unit 104, an addition unit 105, a multiplication unit 106, an addition unit 107, an addition unit 108 as a second addition unit, a first storage area 110, a second storage area 111, a phase information extraction unit 112, a division unit 113A, a subtraction unit 114, a multiplication unit 115, a multiplication unit 116, an addition unit 117A as a first update unit, a differentiation unit 118, a multiplication unit 119, a multiplication unit 120, an addition unit 121A as a third update unit, an addition unit 122A as a first addition unit, a multiplication unit 123, a multiplication unit 124, a multiplication unit 125, an addition unit 126 as a second update unit, a multiplication unit 127, a multiplication unit 128, a multiplication unit 129, an addition unit 130 as a fourth update unit, a multiplication unit 131, a multiplication unit 132, a multiplication unit 133, and a multiplication unit 134. The control device 100A according to this embodiment is different from the control device 100 shown in FIG. 1 in that the multiplication unit 123, the multiplication unit 124, the multiplication unit 125, the addition unit 126, the multiplication unit 127, the multiplication unit 128, the multiplication unit 129, the addition unit 130, the multiplication unit 131, the multiplication unit 132, the multiplication unit 133, and the multiplication unit 134 are added, and the division unit 113, the addition unit 117, the addition unit 121, and the addition unit 122 are changed to a division unit 113A, an addition unit 117A, an addition unit 121A, and an addition unit 122A, respectively.

[0054] As described above, in the first embodiment, the ratio of the output frequency f to the control period Tc is fixed. In this case, since the phase at each control timing is an integer multiple of 2π×6÷N (rad), the first register and the second register corresponding to the current phase θ are determined uniquely. On the other hand, when the output frequency f and the control period Tc are variable, the phase at the control timing may not be an integer multiple of 2π×6÷N (rad). The following units described below perform the following processing when the phase at the control timing is not an integer multiple of 2π×6÷N (rad).

[0055] The division unit 113A receives the phase information and the phase θs (= 2π / 6÷N). The division unit 113 divides the remainder obtained by dividing the current phase θ of the output voltage target value indicated by the phase information by π / 3 by the phase θs, and outputs the quotient (integer part P) to the multiplication unit 116, addition unit 117A, multiplication unit 120, addition unit 121A, multiplication unit 125, addition unit 126, multiplication unit 129, and addition unit 130. Further, the division unit 113A divides the remainder obtained by dividing the current phase θ of the output voltage target value indicated by the phase information by π / 3 by the phase θs, and outputs the fractional part (weighting coefficient wg) to the multiplication units 123, 124, 127, 128, 131, 132, 133, and 134.

[0056] The multiplication unit 123 multiplies the multiplication value of the multiplication unit 115 (capacitor current error value × 2πfL × K1) by (1 - wg), and outputs the multiplication value to the addition unit 117A.

[0057] The multiplication unit 124 multiplies the multiplication value of the multiplication unit 115 (capacitor current error value × 2πfL × K1) by wg, and outputs the multiplication value to the addition unit 126.

[0058] The multiplication unit 125 reads the value stored in the (P + 1)-th first register of the first storage area 110, multiplies the read value by (1 - K1), and outputs the multiplication value to the addition unit 126.

[0059] The addition unit 117A receives the multiplication value of the multiplication unit 116 and the multiplication value of the multiplication unit 123. The addition unit 117A adds the input multiplication value of the multiplication unit 116 and the multiplication value of the multiplication unit 123, and writes the added value to the P-th first register. That is, the addition unit 117A updates the value of the first register. Specifically, the addition unit 117A writes, to the P-th first register, the value obtained by adding the value obtained by multiplying the value stored in the P-th first register by (1 - K1) and the value obtained by multiplying the capacitor current error value by 2πfL × K1 and (1 - Wg).

[0060] The addition unit 126 receives the multiplication value of the multiplication unit 124 and the multiplication value of the multiplication unit 125. The addition unit 126A adds the received multiplication value of the multiplication unit 124 and the multiplication value of the multiplication unit 125, and writes the added value into the (P + 1)-th first register. That is, the addition unit 126 updates the value of the first register. Specifically, the addition unit 126 multiplies the value stored in the (P + 1)-th first register by (1 - K1), adds the result to the value obtained by multiplying the capacitor current error value by 2πfL×K1 and Wg, and writes the sum into the (P + 1)-th first register.

[0061] The multiplication unit 127 multiplies the multiplication value of the multiplication unit 119 (load current derivative value × 2πfL×K2) by (1 - wg), and outputs the multiplication value to the addition unit 121A.

[0062] The multiplication unit 128 multiplies the multiplication value of the multiplication unit 119 (load current derivative value × 2πfL×K2) by wg, and outputs the multiplication value to the addition unit 130.

[0063] The multiplication unit 129 reads the value stored in the (P + 1)-th second register of the second storage area 111, multiplies the read value by (1 - K2), and outputs the multiplication value to the addition unit 130.

[0064] The addition unit 121A receives the multiplication value of the multiplication unit 120 and the multiplication value of the multiplication unit 127. The addition unit 121A adds the received multiplication value of the multiplication unit 120 and the multiplication value of the multiplication unit 127, and writes the added value into the P-th second register. That is, the addition unit 121A updates the value of the second register. Specifically, the addition unit 121A multiplies the value stored in the P-th second register by (1 - K2), adds the result to the value obtained by multiplying the load current derivative value by 2πfL×K2 and (1 - Wg), and writes the sum into the P-th second register.

[0065] The adder 130 receives the multiplication value from the multiplier 128 and the multiplication value from the multiplier 129. The adder 130 adds the input multiplication value from the multiplier 128 and the multiplication value from the multiplier 129, and writes the added value into the (P + 1)-th second register. That is, the adder 130 updates the value of the second register. Specifically, the adder 130 multiplies the value stored in the (P + 1)-th second register by (1 - K2), adds the result to the value obtained by multiplying the load current derivative value by 2πfL×K2 and Wg, and writes the sum into the (P + 1)-th second register.

[0066] The multiplier 131 reads the value stored in the (P + 1)-th first register of the first storage area 110, multiplies the read value by (1 - wg), and outputs the multiplication value to the adder 122A.

[0067] The multiplier 132 reads the value stored in the (P + 2)-th first register of the first storage area 110, multiplies the read value by wg, and outputs the multiplication value to the adder 122A.

[0068] The multiplier 133 reads the value stored in the (P + 2)-th second register of the second storage area 111, multiplies the read value by (1 - wg), and outputs the multiplication value to the adder 122A.

[0069] The multiplier 134 reads the value stored in the (P + 3)-th second register of the second storage area 111, multiplies the read value by wg, and outputs the multiplication value to the adder 122A.

[0070] The adder 122A receives the multiplication value of the multiplier 131, the multiplication value of the multiplier 132, the multiplication value of the multiplier 133, and the multiplication value of the multiplier 134. The adder 122A adds the input multiplication value of the multiplier 131, the multiplication value of the multiplier 132, the multiplication value of the multiplier 133, and the multiplication value of the multiplier 134. That is, the adder 122A adds the value obtained by multiplying the value stored in the first register of P + 1 by (1 - Wg), the value obtained by multiplying the value stored in the first register of P + 2 by Wg, the value obtained by multiplying the value stored in the second register of P + 2 by (1 - Wg), and the value obtained by multiplying the value stored in the second register of P + 3 by Wg. The adder 122A outputs the added value to the adder 108.

[0071] In addition, when P + 1, P + 2, or P + 3 is N or more, the calculation may be performed by reading them as P + 1 - N, P + 2 - N, and P + 3 - N.

[0072] In the present embodiment, the values stored in the first register and the second register corresponding to the phases before and after the current phase θ are updated in a one - time delay format with the values corrected by the weighting variable Wg, and the register values of the next phase are updated in a one - time delay format with the values corrected by the weighting variable, and the value corrected by the weighting variable Wg ((1 - Wg)Y[P + a]+WgY[P + 1 + a]) is added to the output voltage command value, so that the harmonics of the output voltage of the inverter power supply device 10 can be suppressed.

[0073] Although the above - described embodiments have been described as representative examples, it is obvious to those skilled in the art that many changes and substitutions are possible within the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited by the above - described embodiments, and various modifications and changes are possible without departing from the scope of the claims.

Explanation of Signs

[0074] 10 Inverter power supply device 11 Three - phase inverter circuit section 11 Three - phase LC filter circuit section 100, 100A Control device 101 Proportional Component Control Unit 102 Multiplication Unit 103 Addition Unit 104 Proportional-Integral Control Unit 105 Addition Unit 106 Multiplication Unit 107 Multiplication Unit 108 Addition Unit (Second Addition Unit) 110 First Memory Area 111 Second Memory Area 112 Phase Information Extraction Unit 113, 113A Division Unit 114 Subtraction Unit 115 Multiplication Unit 116 Multiplication Unit 117, 117A Addition Unit (First Update Unit) 118 Differentiation Unit 119 Multiplication Unit 120 Multiplication Unit 121, 121A Addition Unit (Third Update Unit) 122, 122A Addition Unit (First Addition Unit) 123 Multiplication Unit 124 Multiplication Unit 125 Multiplication Unit 126 Addition Unit (Second Update Unit) 127 Multiplication Unit 128 Multiplication Unit 129 Multiplication Unit 130 Addition Unit (Fourth Update Unit) 131 Multiplication Unit 132 Multiplication Unit 133 Multiplication Unit 134 Multiplication Unit

Claims

1. A control device for an inverter power supply device that supplies an alternating voltage to a load via an LC filter circuit composed of an inductor and a capacitor, wherein, when the output frequency of the inverter power supply device is f and the control period of the inverter power supply device is Tc, N = (1 / fTc) × 1 / 6 is satisfied, a first storage area composed of N first registers numbered from 0 to N - 1, a second storage area composed of N second registers numbered from 0 to N - 1, a first update unit that updates the value of the first register, a third update unit that updates the value of the second register, a first addition unit that calculates an addition value obtained by adding the value stored in the first register and the value stored in the second register, and a second addition unit that adds the addition value to the output voltage command value of the inverter power supply device to generate an inverter voltage command value for instructing the output voltage of the inverter power supply device, each of the N first registers numbered from 0 to N - 1 is associated with each phase θs (= 2π / 6 ÷ N), each of the N second registers numbered from 0 to N - 1 is associated with each phase θs, when the integer part obtained by dividing the remainder of dividing the current phase of the output voltage target value of the inverter power supply device by π / 3 by the phase θs is P, the first update unit multiplies the value stored in the P-th first register by (1 - K1) (K1 is a predetermined first constant), and adds the value obtained by multiplying the capacitor current error value, which is the error between the capacitor current target value and the current flowing through the capacitor, by 2πfL × K1 (L is the inductance value of the capacitor), and writes the added value into the P-th first register, the third update unit multiplies the value stored in the P-th second register by (1 - K2) (K2 is a predetermined second constant), and adds the value obtained by multiplying the load current derivative value obtained by differentiating the load current value of the load by 2πfL × K2, and writes the added value into the P-th second register, the first addition unit adds the value stored in the (P + 1)-th first register and the value stored in the (P + 2)-th second register, the control device.

2. In the control device according to claim 1, a second update unit that updates the values of the N first registers, and a fourth update unit that updates the values of the N second registers, further comprising. When the fractional part obtained by dividing the remainder of dividing the current phase of the output voltage target value of the inverter power supply device by π / 3 by θs is defined as Wg, the first update unit writes, to the P-th first register, a value obtained by adding a value obtained by multiplying the value stored in the P-th first register by (1 - K1) and a value obtained by multiplying the capacitor current error value by 2πfL×K1 and (1 - Wg); the second update unit writes, to the (P + 1)-th first register, a value obtained by adding a value obtained by multiplying the value stored in the (P + 1)-th first register by (1 - K1) and a value obtained by multiplying the capacitor current error value by 2πfL×K1 and Wg; the third update unit writes, to the P-th second register, a value obtained by adding a value obtained by multiplying the value stored in the P-th second register by (1 - K2) and a value obtained by multiplying the load current derivative value by 2πfL×K2 and (1 - Wg); the fourth update unit writes, to the (P + 1)-th second register, a value obtained by adding a value obtained by multiplying the value stored in the (P + 1)-th second register by (1 - K2) and a value obtained by multiplying the load current derivative value by 2πfL×K2 and Wg; the first addition unit adds a value obtained by multiplying the value stored in the (P + 1)-th first register by (1 - Wg), a value obtained by multiplying the value stored in the (P + 2)-th first register by Wg, a value obtained by multiplying the value stored in the (P + 2)-th second register by (1 - Wg), and a value obtained by multiplying the value stored in the (P + 3)-th second register by Wg, a control device.

3. A control method executed by a control device of an inverter power supply device that supplies an AC voltage to a load via an LC filter circuit including an inductor and a capacitor, wherein the control device sets a first storage area including N first registers numbered from 0 to N - 1 that satisfy N=(1 / fTc)×1 / 6, where f is the output frequency of the inverter power supply device and Tc is the control period of the inverter power supply device, and a second storage area including N second registers numbered from 0 to N - 1, wherein each of the N first registers numbered from 0 to N - 1 is associated with each phase θs(=2π / 6÷N)°, and each of the N second registers numbered from 0 to N - 1 is associated with each phase θs. When the integer part obtained by dividing the remainder of dividing the current phase of the output voltage target value of the inverter power supply device by π / 3 by the phase θs is defined as P, a step of writing, into the P-th first register, a value obtained by multiplying a value stored in the P-th first register by (1 - K1) (K1 is a predetermined first constant), and a value obtained by multiplying a capacitor current error value, which is an error between the target current value of the capacitor and the current flowing through the capacitor, by 2πfL×K1 (L is the inductance value of the capacitor); a step of writing, into the P-th second register, a value obtained by multiplying a value stored in the P-th second register by (1 - K2) (K2 is a predetermined second constant), and a value obtained by multiplying a load current derivative value obtained by differentiating the load current value of the load by 2πfL×K2; a step of calculating an addition value obtained by adding a value stored in the (P + 1)-th first register and a value stored in the (P + 2)-th second register; a control method including a step of generating an inverter voltage command value for instructing the output voltage of the inverter power supply device by adding the addition value to the output voltage command value of the inverter power supply device.

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