Trench gate type IGBT and driving method of them

Abstract

To provide an appropriate short circuit tolerance dose, and reduce a turn-off power loss and a conduction loss.SOLUTION: A trench gate type insulated gate bipolar transistor (IGBT) includes: a semiconductor substrate; and a plurality of trench type gates that are extended toward a back surface side from a front surface of the semiconductor substrate, and controls a current flowing in a channel region to be formed at a circumference by applying a voltage, and controls the current between an emitter and a collector by the voltage applied to the trench type gate. The plurality of trench type gates include: one or more main gates which have a relatively long ON time; and one or more control gates which have a relatively short ON time, are turned on after the main gates are turned on, and are turned off before the main gates are turned off.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Conventionally, an IGBT (Insulated Gate Bipolar Transistor) has been widely used as a switching element in a circuit for driving a high-power motor.

[0002] For example, Patent Document 1 shows that in a trench gate type IGBT, a carrier store (CS: Carrier Store) layer for accumulating carriers (for example, holes) is provided below the channel of the IGBT.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Here, when a carrier store layer is provided, the voltage drop (collector-emitter voltage Vce) when the IGBT is on can be reduced. That is, the voltage drop due to the on-resistance of the IGBT can be reduced, and the energy loss during on-state can be made small. However, if carriers are excessively accumulated in the carrier store layer, the saturation current increases and the short-circuit withstand capacity deteriorates. Also, when the IGBT turns off (switches from on to off), due to the influence of the remaining carriers, the time required for turn-off becomes long, and the energy consumption (turn-off loss) increases.

Means for Solving the Problems

[0005] The trench gate type IGBT according to the present disclosure is a semiconductor substrate, A trench gate type IGBT including a plurality of trench type gates that extend from the surface of the semiconductor substrate toward the back side and control the current flowing through the channel region formed in the periphery when a voltage is applied, and controlling the current between the emitter and the collector by the voltage applied to the trench type gate. The plurality of trench type gates include one or more main gates having a relatively long on-time, and one or more control gates having a relatively short on-time, turning on after the main gate turns on and turning off before the main gate turns off. [Effect of the Invention]

[0006] According to the trench gate type IGBT according to the present disclosure, since the control gate is turned on after the main gate is turned on, there is a time when only the main gate is on. Since the saturation current during the time when only the main gate is on can be reduced, the short-circuit withstand can be maintained at a predetermined level even if the concentration of the carrier storage layer is increased. Further, by turning off the main gate after the control gate is turned off, carriers can be reduced during the time when only the main gate is on, and the turn-off loss can be reduced. Further, by increasing the concentration of the carrier storage layer, the voltage drop during the on-state of the IGBT can also be reduced. However, from the viewpoints of short-circuit withstand and breakdown voltage, the impurity concentration of the carrier storage layer is 3E 17 ~2E 18 (atoms / cm 2 ) is desirable. [Brief Description of the Drawings]

[0007]

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Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present disclosure will be described below with reference to the drawings. Note that the following embodiments do not limit the present disclosure, and configurations formed by selectively combining a plurality of examples are also included in the present disclosure.

[0009] "Configuration of IGBT" FIG. 1 is a cross-sectional view schematically showing the configuration of a trench gate type IGBT according to an embodiment.

[0010] An interlayer insulating film 102 is formed on the surface of the semiconductor substrate 100. A metal wiring layer is provided on this interlayer insulating film 102 to make necessary electrical connections. In FIG. 1, an emitter pad 104 is shown as the metal wiring.

[0011] For the semiconductor substrate 100, a silicon (Si) wafer such as an FZ (Floating Zone) wafer is used, but a wafer of silicon carbide (SiC) or the like may also be used. As the interlayer insulating film 102, an insulating material such as silicon oxide is used. For the metal wiring, a metal material such as aluminum is usually used.

[0012] A collector pad 106 is formed on the back surface of the semiconductor substrate 100. A metal material such as aluminum is usually used for the collector pad 106.

[0013] On the back surface portion of the semiconductor substrate above the collector pad 106, a P+ P collector layer 110 with a high impurity concentration is formed, and on top of that, an N+ field stop layer 112 with a higher impurity concentration than the N drift layer 114 described later is formed. These N-type and P-type regions in the semiconductor substrate 100 are formed by doping impurities of their respective types. The P collector layer 110 functions as a collector region, and the field stop layer 112 prevents the expansion of the depletion layer during the off state.

[0014] Note that the impurity doping may be performed when forming the carrier storage layer 116 by epitaxial growth or the like, but it may also be doped into the semiconductor substrate 100 later.

[0015] An N drift layer 114 composed of an N-type semiconductor substrate 100 is located on the field stop layer 112. This N drift layer 114 is the body of the semiconductor substrate 100 and has a function as the base of the PNP bipolar transistor of the IGBT.

[0016] An N+-type carrier storage layer 116 having a higher impurity concentration than the N drift layer 114 is provided on the N drift layer 114. This carrier storage layer 116 has a function of reducing the on-resistance by accumulating holes and reducing the collector-emitter voltage (Vce), which is the voltage drop during conduction.

[0017] A P- type P body layer 118 having a relatively low impurity concentration is provided on the carrier storage layer 116. This P body layer 118 functions as the emitter of the PNP bipolar transistor.

[0018] In addition, a plurality of trenches 120 are formed downward from the surface of the semiconductor substrate 100. The trench 120 extends downward from the surface of the semiconductor substrate 100 (the lower side of the interlayer insulating film 102), penetrates the P body layer 118 and the carrier storage layer 116, and reaches the N drift layer 114.

[0019] The trench 120 is formed of an insulating film whose peripheral wall is made of, for example, silicon oxide and is insulated from the surroundings, and the inside thereof is filled with a conductive material, for example, polysilicon or the like. In this example, it includes a trench-type main gate 120MG whose inside is connected to a main gate pad (not shown), and a trench-type control gate 120CG whose inside is connected to a control gate pad (not shown). In FIG. 1, the main gate 120MG, the control gate CG120CG, a control unit 140 that controls these voltages, and wirings connecting them are schematically shown. The control unit 140 individually controls the voltages of the main gate 120MG and the control gate 120CG. That is, the control unit 140 turns on the control gate 120CG after turning on the main gate 120MG, and turns off the main gate 120MG after turning off the control gate 120CG.

[0020] The control unit 140 may be formed on the semiconductor substrate 100 or may be provided separately. Also, the control unit 140 may be configured by hardware or software as long as it creates and outputs signals for turning on and off the main gate 120MG and the control gate 120CG from signals regarding the on / off of the IGBT supplied from the outside. For example, control signals for the main gate 120MG and the control gate 120CG can be generated based on control signals for the on / off of the IGBT.

[0021] In this embodiment, the IGBT turns on when the gate voltage is a positive voltage equal to or higher than the threshold voltage. For example, when turning on the IGBT, the main gate 120MG and the control gate 120CG are set to +15V, and when turning off, the main gate 120MG and the control gate 120CG are set to -15V.

[0022] It is sufficient to be able to switch and supply +15V (on) or -15V (off) from the control unit 140 to the main gate 120MG and the control gate 120CG.

[0023] Also, on the surface side of the P-body layer 118, in the area adjacent to the main gate 120MG and the control gate 120CG, an N+ emitter region 122 with a high impurity concentration is formed. This emitter region 122 is electrically connected to the emitter pad 104. For example, in a portion not shown, the interlayer insulating film 102 is removed, and the emitter pad 104 and the emitter region 122 are directly connected.

[0024] As a result, the region between the emitter region 122 and the carrier storage layer 116 functions as the channel of the FET. When the FET is on, electrons, which are carriers, flow from the emitter region through the carrier storage layer 116 into the N-drift layer 114.

[0025] Also, the contact 132 from the emitter pad 104 is arranged to extend to the P-body layer 118 of each mesa section formed between the plurality of trenches 120. And this contact 132 is connected to a (P+) contact region 134 with a high impurity concentration formed inside (the middle part) of the P-body layer 118 of the mesa section. Therefore, the emitter pad 104 is electrically connected to the contact 132 and the contact region 134, and holes accumulated in the N-drift layer 114 during turn-off can be drawn out to the emitter pad 104 through the P-body layer 118.

[0026] In this way, in the present embodiment, an emitter region 122 with a high impurity concentration is formed on the surface portion of the semiconductor substrate 100, and the P-body layer 118 below it functions as a channel.

[0027] Note that the gate regions inside the main gate 120MG and the control gate 120CG are respectively connected to a separately provided main gate pad and control gate pad, and the insulating film on the peripheral wall of the trench 120 functions as a gate insulating film.

[0028] "Operation of IGBT" With a voltage applied between the collector pad 106 and the emitter pad 104 (for example, 400V applied to the collector pad 106 and 0V applied to the emitter pad 104), a positive voltage (for example, +15V) is applied to the main gate 120MG, and after a predetermined time has elapsed, a positive voltage (for example, +15V) is applied to the control gate 120CG. Note that the applied voltage of 400V to the collector pad 106 mentioned above is merely an example, and in some applications, it may be a low voltage such as 10V. In this example, when the IGBT is off, it is set to -15V together with the main gate 120MG and the control gate 120CG.

[0029] When both the main gate 120MG and the control gate 120CG are turned on, an inversion layer is generated in the channel around these gates, turning on the FET, and an electron current flows from the emitter region 122 toward the N-drift layer 114. That is, when the P regions of the P-body layer 118 set the main gate 120MG and the control gate 120CG to a positive voltage, negative carriers (electrons) are accumulated on the sidewalls of the main gate 120MG and the control gate 120CG, and this channel region is inverted from P-type to N-type, allowing current to flow through it. As a result, the PNP bipolar transistor is turned on, holes are supplied to the N-drift layer 114 from the collector side, and electrons are supplied from the emitter side, turning on the IGBT. That is, by the movement of both holes and electrons, a current flows from the collector pad 106 toward the emitter pad 104.

[0030] Also, since the field stop layer 112 can suppress the spread of the depletion layer, the overall thickness can be reduced.

[0031] Here, in the IGBT of this embodiment, the on-periods of the main gate 120MG and the control gate 120CG are made different.

[0032] Figure 2 is a timing chart showing the states of the collector-emitter voltage Vce, collector current Ic, voltage Vmg of main gate 120MG, and voltage Vcg of control gate 120CG of the IGBT when the IGBT is turned on for a predetermined time.

[0033] The voltage Vmg of main gate 120MG is raised from the off state of the IGBT. As a result, the FET with main gate 120MG as the gate turns on, and the corresponding PNP bipolar transistor gradually turns on, allowing the corresponding collector current Ic to flow. Also, as the PNP bipolar transistor turns on, the collector-emitter voltage Vce gradually decreases.

[0034] Since only the main gate 120MG is raised, even if sufficient carriers (holes) are retained in the carrier storage layer 116, the saturation current is not large. Therefore, by making the period during which only the main gate 120MG is on correspond to the short-circuit withstand period, the desired short-circuit withstand can be satisfied. For example, when the short-circuit withstand is 8 μsec, the short-circuit withstand can be satisfied by setting the period during which only the main gate 120MG is on to 8 μsec or more.

[0035] Next, the voltage Vcg of control gate 120CG is raised. As a result, the FET with control gate 120CG as the gate also turns on, allowing more electron current to flow. That is, by turning on the control gate 120CG, the number of channels increases, and as the electron current increases, the base current of the PNP transistor increases. This reduces the on-resistance and further decreases the Vce of the IGBT. Therefore, the energy loss during turn-on can be reduced.

[0036] After a predetermined on-time, the voltage Vcg of the control gate 120CG is lowered, turning off the FET having the control gate 120CG as its gate. Since the corresponding FET is on by the main gate 120MG, the current Ic continues to flow. Here, since the control gate 120CG is off, the amount of carrier injection decreases, and the amount of internal carriers decreases. For this reason, the voltage Vcg gradually rises and becomes equal to the voltage when only the main gate 120MG is on.

[0037] Next, the voltage Vmg of the main gate 120MG is lowered. As a result, the FET having the main gate 120MG as its gate also turns off, the corresponding PNP bipolar transistor gradually turns off, and the corresponding collector current Ic decreases. Also, as the PNP bipolar transistor turns off, the collector-emitter voltage Vce gradually rises.

[0038] As described above, according to this embodiment, when turning on the IGBT, first only the main gate 120MG is turned on, and after a predetermined time has elapsed, the control gate 120CG is also turned on. Therefore, during the period when only the main gate 120MG is on, a desired short-circuit withstand capacity can be obtained. Also, when turning off the IGBT, first only the control gate 120CG is turned off. As a result, carriers in the FET corresponding to the control gate 120CG are removed, and the carriers remaining in the N drift layer 114 and the P body layer 118 can be drawn out to the emitter pad 104.

[0039] When the main gate 120MG turns off, the amount of carriers in the N drift layer 114, the carrier storage layer 116, and the P body layer 118 decreases. Therefore, when the main gate 120MG is set to a negative voltage (for example, -15V) and the IGBT is turned off, the carriers can be eliminated in a relatively short time. Therefore, the turn-off loss can be reduced.

[0040] Next, the comparison results between the IGBT of the embodiment in FIG. 1 and the IGBT of the comparative example will be described. Here, in the embodiment of FIG. 1, five control gates 120CG are arranged for one main gate 120MG, but in the comparative example, three control gates 120CG are arranged for two main gates 120MG. Also, the control gate 120CG of the embodiment is set to +15V when on and -15V when off, while the control gate 120CG of the comparative example is always set to 0V, that is, 0V when on and 0V when off. Therefore, in the comparative example, no FET is formed in the region where the control gate 120CG is arranged, and the emitter region is also omitted.

[0041] Also, the amount of carrier addition is the doping amount by implantation of impurities into the carrier storage layer 116, and is in units of (atoms / cm 2 ).

[0042] FIG. 3 is a diagram showing the relationship between the amount of carrier addition (atoms / cm 2 ) of the carrier storage (CS) layer and the saturation current Isat (A / cm 2 ). The embodiment of FIG. 1 and the comparative example are shown.

[0043] Thus, in the IGBT of the comparative example, by increasing the carrier concentration in the carrier storage layer 116, the saturation current increases. On the other hand, in the IGBT of the embodiment, by providing a period during which only the main gate 120MG is turned on, the area to be turned on can be limited, and an increase in the saturation current can be suppressed.

[0044] FIG. 4 shows the amount of carrier addition (atoms / cm 2) It is a diagram showing the relationship with the collector-emitter saturation voltage Vce(sat) (V). Thus, in the IGBT of the embodiment, it can be seen that the saturation voltage is low. That is, in the present embodiment, by turning on both the main gate 120MG and the control gate 120CG, the base current of the PNP bipolar transistor can be increased, so the on-resistance of the IGBT is small, and thus the loss during turn-on can be reduced.

[0045] FIG. 5 is a diagram showing the relationship between the amount of carriers added (atoms / cm 2 ) and the turn-off loss (mJ). Thus, in the comparative example, in order to increase the saturation current and achieve the desired short-circuit withstand capacity, the amount of carrier addition cannot be increased. Also, since the control gate 120CG is not turned on, the amount of carriers (holes) remaining at turn-off is relatively small, and the turn-off loss is relatively small. On the other hand, in the IGBT of the embodiment, since both the main gate 120MG and the control gate 120CG are turned on, the turn-off loss at the same carrier concentration as in the comparative example is relatively high. This is because by turning off the control gate 120CG before the main gate 120MG, the carriers in the drift layer decrease earlier than in the comparative example, the conductivity modulation weakens, and the collector-emitter saturation voltage (Vce(sat)) increases. However, by further increasing the carrier concentration, the collector-emitter saturation voltage (Vce(sat)) during turn-on can be reduced, and although more carriers are accumulated in the carrier storage layer than in the comparative example, by turning off the control gate 120CG first, the carriers in that area can be consumed, so the loss during turn-on can be reduced.

[0046] FIG. 6 is a diagram showing the relationship between the collector-emitter saturation voltage (Vce(sat)) and the collector current Ic. Thus, in this embodiment, the collector current Ic can be made larger than in the comparative example. When the collector-emitter saturation voltage Vce(sat) is 1.2 V, the current can be increased by 228% in this embodiment. Therefore, according to this embodiment, it is possible to reduce the chip size by about 70%.

[0047] "Planar and Cross-sectional Configurations" FIG. 7 is a plan view showing an example of the metal wiring layer (single layer) of the IGBT. In this example, the IGBT has a square planar shape.

[0048] Emitter pads 104 divided into three parts in the vertical direction in the figure are provided on the surface of the square. The three emitter pads 104 are spaced apart at the peripheral portion, and a predetermined gap is provided between the three emitter pads 104.

[0049] The left emitter pad 104 in the figure has a concave upper left corner, and a control gate pad 142 is disposed at this upper left corner. Further, a rectangular control gate wiring 142a is provided along the outer periphery of the surface of the IGBT connected to the control gate pad 142. The control gate wiring 142a is disposed inside the scribe pitch from the outer periphery. The control gate pad 142 functions as a control fixed terminal for controlling the voltage of the control gate 120CG.

[0050] Also, the left center of the left emitter pad 104 is concave, and a main gate pad 108 is disposed here. A main gate wiring 108a is connected to the main gate pad 108, and the main gate wiring 108a extends to both the left and right sides, the lower side, and the vertical gap between the three emitter pads 104.

[0051] FIG. 8A is an enlarged schematic view of part A in FIG. 7, and also shows the structure within the semiconductor substrate 100. FIG. 8B is a cross-sectional view taken along line A-A' of FIG. 8A, and FIG. 8C is a cross-sectional view taken along line B-B' of FIG. 7A.

[0052] In this way, the main gate 120MG and the control gate 120CG extend horizontally and are located below the emitter pad 104, the main gate wiring 108a, and the control gate wiring 142a that extend vertically.

[0053] The main gate 120MG and the main gate wiring 108a are connected by a contact 108b that extends downward, and the control gate 120CG and the control gate wiring 142a are connected by a contact 142b that extends downward.

[0054] FIG. 9 is a plan view showing another example of the metal wiring layer (single layer) of the IGBT. Also, FIG. 10 is an enlarged view of part B in FIG. 8.

[0055] In this example, the control gate wiring 142a also extends into the gap of the divided emitter pad 104. Therefore, the number of contacts 142b between the control gate wiring 142a and the control gate 120CG can be increased, and the electric field by the control gate 120CG can be set earlier.

[0056] Note that the cross-sectional views taken along line A-A' and line B-B' in FIG. 10 are the same as FIG. 8B and FIG. 8C, respectively. Also, as long as the main gate wiring 108a and the control gate wiring 142a are arranged so as not to interfere with each other, various arrangements different from the above example can also be made.

[0057] FIG. 11 is a plan view showing an example of the metal wiring layer (two layers) of the IGBT. Also, FIG. 12A is an enlarged view of part C in FIG. 11, and FIG. 12B is a cross-sectional view taken along line A-A' in FIG. 11A.

[0058] As shown in FIG. 11, on the surface of the semiconductor substrate 100, there are an emitter pad 104, a main gate pad 108, a control gate pad 142, and a control gate wiring 142a, but there is no main gate wiring 108a. As shown in FIG. 12B, the main gate wiring 108a is disposed in the interlayer insulating film 102 below the control gate wiring 142a. In FIG. 11, the position of the main gate wiring 108a is schematically shown with a dashed line shifted slightly. Since the control gate wiring 142a and the main gate wiring 108a are different in the position in the thickness direction, there is no problem even if they overlap in the plan view. Also, the main gate wiring 108a must not be in contact with the contact 142b, and in FIG. 12A, the main gate wiring 108a is removed in the area where the contact 142b is disposed. In this way, by adopting a two-layer structure for the wiring layer, it becomes possible to reduce the area for arranging a plurality of wirings.

[0059] <Other Configuration Examples of IGBT> FIG. 13 is a cross-sectional view schematically showing another configuration example of a trench gate type IGBT. In this example, the main gates 120MG and the control gates 120CG are alternately arranged. Even with such a configuration, first the main gate 120MG is turned on, then the control gate 120CG is turned on, and after the control gate 120CG is turned off, the main gate 120MG is turned off, whereby the same operational effects as those of the above-described embodiment can be obtained.

[0060] <Configuration Example of Control Unit> FIG. 14 is a diagram showing a configuration example of the control unit 140. A control signal Vg1 for controlling the on / off of the IGBT is provided from the outside. The control signal Vg1 becomes a signal Vg2 delayed by a predetermined time by the first delay circuit 150. This signal vg2 is supplied to the control gate 120CG and becomes the voltage Vcg of the control gate 120CG.

[0061] The signal Vg1 is directly input to the first input terminal of the OR gate 154. Also, the signal Vg1 is delayed by the second delay circuit 152 to become the signal Vg3. The delay time of the second delay circuit 152 is longer than that of the first delay circuit 150. Vg3, which is the output of the second delay circuit 152, is input to the second input terminal of the OR gate 154. The output of the OR gate 154 is supplied to the main gate 120MG and becomes the voltage Vmg of the main gate 120MG. FIG. 15 is a timing chart for explaining the operation of the control unit 140. As such, the signal vg2 is delayed from the signal vg1 by a predetermined time, and the signal vg3 is more delayed from the signal vg1 than the signal vg2.

[0062] The signal that is the output of the OR gate 154 (= the voltage Vmg of the main gate 120MG) rises at the rising edge of the signal vg1 and falls at the falling edge of the signal Vg3. For this reason, the voltage Vmg of the main gate 120MG first rises, then the voltage Vcg of the control gate 120CG rises, after a predetermined time has elapsed, the voltage Vcg of the control gate 120CG falls, and then the voltage Vmg of the main gate 120MG falls.

[0063] <Manufacturing Process> FIG. 16 is a diagram showing the manufacturing process of the IGBT according to the embodiment. First, a semiconductor substrate 100 is prepared and introduced into the manufacturing process (S11). As the semiconductor substrate 100, for example, an FZ (Floating Zone) wafer of N-type is used.

[0064] First, the surface side is oxidized to form an interlayer insulating film 102 (S12). Note that since a plurality of elements (in this case, IGBTs) are formed on one wafer, the element isolation process may be performed at this stage.

[0065] Next, a P+ P-body layer 118 is formed by P-type impurity doping from the surface side (S13). A trench is formed by etching from the surface side (S14), and an oxide film is formed on the wall surface of the formed trench (S15). In the case of a gate trench, this oxide film becomes the gate insulating film. Then, polysilicon is deposited inside the trench (S16). This polysilicon is conductive, and the inside of the trench becomes the gate region.

[0066] Next, a carrier storage layer (CS layer) 116 is formed by implanting N-type impurities (S17). Then, an emitter region is formed by implanting N-type impurities from the surface side (S18).

[0067] A contact hole is formed by etching from the surface side, and a contact region 134 is formed by implanting P-type impurities. Next, after forming the interlayer insulating film 102, necessary contact holes are formed. Then, by depositing metal, an emitter pad 104, a main gate pad 108, a control gate pad 142, and a contact extending into the contact hole are formed (S20). Then, the surface side is covered with a passivation film (S21).

[0068] Next, the back side is polished (S22), and a field stop layer 112 and a P collector layer 110 are sequentially formed from the back side (S22, S24). Then, a collector pad 106 is formed by depositing metal (S24).

[0069] In this way, an IGBT is formed. Next, various inspections are performed on this (S25), and the manufacturing process is completed.

Explanation of Reference Numerals

[0070] 100 Semiconductor substrate, 102 Interlayer insulating film, 104 Emitter pad, 106 Collector pad, 108 Main gate pad, 108a Main gate wiring, 110 P collector layer, 112 Field stop layer, 114 N drift layer, 116 Carrier storage layer, 118 P body layer, 120 Trench, 120MG Main gate, 120CG: Control gate, 122 Emitter region, 132 Contact, 134 Contact region, 140 Control unit, 142 Control gate pad, 142a Control gate wiring, 142b Contact.

Claims

1. A semiconductor substrate, including a plurality of trench-type gates that extend from the surface of the semiconductor substrate toward the back side and control the current flowing through a channel region formed in the periphery when a voltage is applied, and the trench gate type IGBT controls the current between the emitter and the collector by the voltage applied to the trench-type gate, wherein the plurality of trench-type gates include one or more main gates having a relatively long on-time, and one or more control gates having a relatively short on-time, turning on after the main gate turns on and turning off before the main gate turns off, and is a trench gate type IGBT.

2. The trench gate type IGBT according to Claim 1, wherein the one or more main gates are two or more, and the one or more control gates are disposed between two of the main gates, is a trench gate type IGBT.

3. The trench gate type IGBT according to Claim 1, wherein the one or more control gates are two or more, and two or more control gates are disposed between two main gates, is a trench gate type IGBT.

4. A semiconductor substrate, an emitter pad formed on the surface of the semiconductor substrate, a collector pad formed on the back surface of the semiconductor substrate, a P-type P collector layer formed on the back surface side of the semiconductor substrate above the collector pad, an N-type N drift layer located above the P collector layer in the semiconductor substrate, an N-type carrier storage layer formed above the N drift layer and having a higher impurity concentration than the N drift layer, a P-type P body layer formed on the surface side of the carrier storage layer of the semiconductor substrate, a plurality of trench-type main gates formed discretely from the surface side of the semiconductor substrate with a mesa section interposed therebetween and extending to the N drift layer toward the back side, the plurality of main gates having a gate region formed therein via an insulating film, a trench-type control gate formed discretely from the surface side of the semiconductor substrate with a mesa section interposed therebetween and extending to the N drift layer toward the back side, the control gate having a gate region formed therein via an insulating film, a main gate pad formed on the surface of the semiconductor substrate and connected to the main gate, A control gate pad formed on the surface of the semiconductor substrate and connected to the control gate, including, the on-time of the main gate is longer than that of the control gate, the control gate turns on after the main gate turns on, and turns off after the main gate turns off, a trench gate type IGBT.

5. The trench gate type IGBT according to claim 4, wherein the one or more main gates are two or more, and the one or more control gates are arranged between the two main gates. A trench gate type IGBT.

6. The trench gate type IGBT according to claim 4, wherein the one or more control gates are two or more, and two or more control gates are arranged between the two main gates. A trench gate type IGBT.

7. The trench gate type IGBT according to claim 4, The impurity concentration of the carrier storage layer is 3E １７ to 2E １８ (atoms / cm ２ ). A trench gate type IGBT.

8. A semiconductor substrate, a driving method of a trench gate type IGBT including a plurality of trench type gates extending from the surface of the semiconductor substrate toward the back side and allowing current to flow through a channel region formed around them when a voltage is applied, wherein at least one of the plurality of trench type gates is a main gate, and the main gate is turned on for a relatively long time wherein at least one of the plurality of trench type gates is a control gate, and the control gate is turned on after the main gate is turned on and turned off before the main gate is turned off, A driving method of a trench gate type IGBT.

9. The driving method of the trench gate type IGBT according to claim 8, wherein the one or more main gates are two or more, and the one or more control gates are arranged between the two main gates. A driving method of a trench gate type IGBT.

10. The driving method of the trench gate type IGBT according to claim 8, wherein the one or more control gates are two or more, and two or more control gates are arranged between the two main gates. A driving method of a trench gate type IGBT.

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