Wiring board and manufacturing method thereof

Abstract

To improve adhesion between a pad of an electronic component and an insulating layer covering the pad in a wiring board that incorporates an electronic component.SOLUTION: A wiring board includes a first insulating layer, a cavity formed in the first insulating layer, an insulating base, and a pad provided on one side of the insulating base, and further includes an electronic component arranged in the cavity such that the pad faces the opening side of the cavity, and a second insulating layer arranged on the first insulating layer and in the cavity, an upper surface and a side surface of the pad have an area exposed from the insulating base, at least a portion of the upper surface and the side surface of the pad exposed from the insulating base are covered by the second insulating layer, and the roughness of the surface of the pad covered by the second insulating layer is greater than the roughness of the surface of the pad not covered by the second insulating layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the same.

Background Art

[0002] A wiring board incorporating electronic components is known. For example, a wiring board having a first insulating layer, a second insulating layer disposed under the first insulating layer and having a conductor layer formed on the upper surface, a cavity penetrating the first insulating layer and the conductor layer and exposing the second insulating layer on the bottom surface, and an electronic component housed in the cavity can be mentioned (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the wiring board as described above, it is preferable for improving the reliability of the wiring board to strengthen the adhesion between the pads of the electronic component and the insulating layer covering the pads.

[0005] The present invention has been made in view of the above points, and an object thereof is to improve the adhesion between the pads of an electronic component and the insulating layer covering the pads in a wiring board incorporating the electronic component.

Means for Solving the Problems

[0006] This wiring board includes a first insulating layer, a cavity formed in the first insulating layer, an insulating substrate, and a pad provided on one side of the insulating substrate, and an electronic component disposed in the cavity such that the pad faces the opening side of the cavity, and a second insulating layer disposed on the first insulating layer and in the cavity. The upper surface and side surface of the pad have regions exposed from the insulating substrate, and at least a part of the upper surface and side surface of the pad exposed from the insulating substrate is covered by the second insulating layer. The roughness of the surface of the pad covered by the second insulating layer is greater than the roughness of the surface of the pad not covered by the second insulating layer.

Advantages of the Invention

[0007] According to the disclosed technology, in a wiring board incorporating an electronic component, the adhesion between the pad of the electronic component and the insulating layer covering the pad can be improved.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Modes for Carrying Out the Invention

[0009] Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same components, and duplicate descriptions may be omitted.

[0010] <First Embodiment> [Structure of Wiring Substrate] FIG. 1 is a cross-sectional view illustrating a wiring substrate according to the first embodiment, FIG. 1(a) is an overall view, and FIG. 1(b) is a partially enlarged view of part A in FIG. 1(a).

[0011] Referring to FIG. 1, the wiring substrate 1 is a wiring substrate in which a wiring layer and an insulating layer are laminated on both surfaces of a core layer 10.

[0012] Specifically, in the wiring substrate 1, on one surface 10a of the core layer 10, a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, and a solder resist layer 17 are sequentially laminated. Also, on the other surface 10b of the core layer 10, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27 are sequentially laminated.

[0013] In the first embodiment, for convenience, the side of the solder resist layer 17 of the wiring substrate 1 is defined as the upper side or one side, and the side of the solder resist layer 27 is defined as the lower side or the other side. Also, the surface on the solder resist layer 17 side of each part is defined as one surface or the upper surface, and the surface on the solder resist layer 27 side is defined as the other surface or the lower surface. However, the wiring substrate 1 can be used in an upside-down state or arranged at an arbitrary angle. Also, a plan view refers to viewing an object from the normal direction of one surface 10a of the core layer 10, and a planar shape refers to the shape of an object viewed from the normal direction of one surface 10a of the core layer 10.

[0014] As the core layer 10, for example, a so-called glass epoxy substrate obtained by impregnating a glass cloth with an insulating resin such as an epoxy resin can be used. As the core layer 10, a substrate obtained by impregnating a woven fabric or non-woven fabric of glass fiber, carbon fiber, aramid fiber, etc. with an epoxy resin or the like may also be used. The thickness of the core layer 10 is, for example, about 60 to 1000 μm. A through hole 10x penetrating the core layer 10 in the thickness direction is provided in the core layer 10. The planar shape of the through hole 10x is, for example, circular.

[0015] The wiring layer 12 is formed on one surface 10a of the core layer 10. Also, the wiring layer 22 is formed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by a through wiring 11 formed in the through hole 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. As the material of the wiring layers 12 and 22 and the through wiring 11, for example, copper (Cu) or the like can be used. The thickness of the wiring layers 12 and 22 is, for example, about 10 to 40 μm. Note that the wiring layer 12, the wiring layer 22, and the through wiring 11 may be integrally formed.

[0016] The insulating layer 13 is formed so as to cover the wiring layer 12 on one surface 10a of the core layer 10. As the material of the insulating layer 13, for example, an insulating resin mainly composed of an epoxy resin or a polyimide resin can be used. The thickness of the insulating layer 13 can be, for example, about 30 to 40 μm. The insulating layer 13 can contain a filler such as silica (SiO2).

[0017] A via hole 13x penetrating the insulating layer 13 and exposing the upper surface of the wiring layer 12 is formed in the insulating layer 13. The via hole 13x can be a frustum of a cone-shaped recess in which the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 12.

[0018] The wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 is composed of via wirings filled in via holes 13x and wiring patterns formed on the upper surface of the insulating layer 13. The wiring patterns are electrically connected to the wiring layer 12 via the via wirings. The wiring patterns may include pads 14a for mounting electronic components formed on the upper surface of the insulating layer 13. The material of the wiring layer 14 and the thickness of the wiring patterns can be the same as those of the wiring layer 12, for example.

[0019] The insulating layer 15 includes a first insulating layer 15a and a second insulating layer 15b. The thickness of the insulating layer 15 can be the same as that of the insulating layer 13, for example. The first insulating layer 15a is formed so as to cover the upper surface and the side surfaces of the wiring layer 14. The material of the first insulating layer 15a can be the same as that of the insulating layer 13, for example. The first insulating layer 15a can contain fillers such as silica (SiO2).

[0020] A cavity 15z that exposes the upper surface of the pad 14a for mounting an electronic component is formed in the first insulating layer 15a. An electronic component 30 is disposed in the cavity 15z. The electronic component 30 includes an insulating substrate 31 and a pad 32 provided on one side of the insulating substrate 31. The electronic component 30 is disposed on the upper surface of the pad 14a for mounting an electronic component in the cavity 15z such that the pad 32 faces the opening side of the cavity 15z. An adhesive layer 40 may be provided between the lower surface of the insulating substrate 31 and the upper surface of the pad 14a for mounting an electronic component. The upper surface of the pad 32 and the upper surface of the first insulating layer 15a may be at the same height or at different heights. When they are at different heights, either the upper surface of the pad 32 or the upper surface of the first insulating layer 15a may be higher.

[0021] In the electronic component 30, the insulating substrate 31 can be made of, for example, silicon oxides or nitrides. Examples of silicon oxides include SiO2. Examples of silicon nitrides include SiN. The thickness of the insulating substrate 31 can be, for example, about 6 μm to 30 μm. The pads 32 are, for example, integrally formed from the same material. That is, the pads 32 referred to here were originally formed on the electronic component 30 and do not include metal layers or the like laminated on the pads 32 after obtaining the electronic component 30. Examples of the material of the pads 32 include copper, copper alloy, aluminum, and aluminum alloy. The thickness of the pads 32 can be, for example, about 5 μm to 15 μm.

[0022] The number of electronic components 30 incorporated in the wiring board 1 may be one or a plurality. The electronic component 30 may be a passive component or an active component. When there are a plurality of electronic components 30 incorporated in the wiring board 1, the electronic components 30 may be passive components or active components, or both may be mixed. The electronic component 30 is, for example, an IPD (Integrated Passive Device), a semiconductor chip, a capacitor, an inductor, a resistor, or the like. The planar shape of the cavity 15z is, for example, similar to the planar shape of the electronic component 30 and is larger in size than the electronic component 30.

[0023] The upper surface and side surfaces of the pads 32 of the electronic component 30 have regions exposed from the insulating substrate 31. In the example of FIG. 1(b), the upper surface of the pad 32 and the side close to the upper surface of the side surface are exposed from the insulating substrate 31. The side close to the lower surface of the side surface of the pad 32 is covered by the insulating substrate 31.

[0024] The second insulating layer 15b is an embedded insulating layer disposed on the first insulating layer 15a and within the cavity 15z. The second insulating layer 15b covers the electronic component 30 within the cavity 15z and extends upward from within the cavity 15z to cover the upper surface of the first insulating layer 15a. The material of the second insulating layer 15b can be the same as that of the first insulating layer 15a, for example. The second insulating layer 15b may be formed of a material different from that of the first insulating layer 15a. The thickness of the portion of the second insulating layer 15b laminated on the upper surface of the first insulating layer 15a can be, for example, about 10 to 20 μm. The second insulating layer 15b may contain a filler such as silica (SiO2).

[0025] At least a part of the upper surface and the side surface of the pad 32 exposed from the insulating substrate 31 is covered by the second insulating layer 15b. In the example of Fig. 1(b), among the upper surface of the pad 32 exposed from the insulating substrate 31, the portion other than the portion exposed within the via hole 15y is covered by the second insulating layer 15b. Also, all of the side surfaces of the pad 32 exposed from the insulating substrate 31 are covered by the second insulating layer 15b.

[0026] The surface of the pad 32 covered by the second insulating layer 15b is a roughened surface. That is, the roughness of the surface of the pad 32 covered by the second insulating layer 15b is greater than the roughness of the surface of the pad 32 not covered by the second insulating layer 15b. In Fig. 1(b), the surface indicated by the wavy line is the roughened surface. The roughness of the outer peripheral side of the via hole 15y on the upper surface of the pad 32 and the side closer to the upper surface of the side surface of the pad 32 is greater than the roughness of the upper surface of the pad 32 exposed within the via hole 15y not indicated by the wavy line, the side closer to the lower surface of the side surface of the pad 32, and the lower surface of the pad 32. In Fig. 1(b), all of the side surfaces of the pad 32 may be exposed from the insulating substrate 31 and covered by the second insulating layer 15b. In this case, all of the side surfaces of the pad 32 will be roughened surfaces. The roughness of the roughened surface of the pad 32 can be, for example, about 50 nm to 300 nm in terms of surface roughness Ra.

[0027] The insulating layer 15 is provided with via holes 15x that penetrate through the first insulating layer 15a and the second insulating layer 15b and expose the upper surface of the wiring layer 14. Further, the insulating layer 15 is provided with via holes 15y that penetrate through the second insulating layer 15b and expose a part of the upper surface of the pad 32 of the electronic component 30. The via holes 15x and 15y can be formed as inverted frustum-shaped recesses in which the diameter of the opening on the solder resist layer 17 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 14 or the upper surface of the pad 32. The roughness of the upper surface of the pad 32 exposed at the bottom of the via hole 15y can be, for example, about 300 nm or less in terms of surface roughness Ra.

[0028] The wiring layer 16 is formed on one side of the insulating layer 15. The wiring layer 16 is composed of via wirings filled in the via holes 15x and 15y and a wiring pattern formed on the upper surface of the insulating layer 15. The wiring pattern includes a portion that is electrically connected to the wiring layer 14 via the via wiring filling the via hole 15x. Further, the wiring pattern includes a portion that is electrically connected to the pad 32 of the electronic component 30 via the via wiring filling the via hole 15y. The material of the wiring layer 16 and the thickness of the wiring pattern can be, for example, the same as those of the wiring layer 12.

[0029] The solder resist layer 17 is a protective insulating layer located on the outermost side on one side of the wiring substrate 1, and is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The solder resist layer 17 can be formed from, for example, a photosensitive epoxy-based insulating resin or an acrylic-based insulating resin. The thickness of the solder resist layer 17 is, for example, about 15 to 35 μm.

[0030] The solder resist layer 17 has an opening 17x. The opening 17x penetrates through the solder resist layer 17 and exposes the upper surface of the wiring layer 16. The wiring layer 16 exposed in the opening 17x can be used, for example, as a pad for electrically connecting to an electronic component such as a semiconductor chip.

[0031] Note that a metal layer may be formed on the surface of the wiring layer 16 exposed inside the opening 17x, or an antioxidant treatment such as OSP (Organic Solderability Preservative) treatment may be performed to form an organic film. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), a Ni / Pd / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order), a Sn layer, and the like.

[0032] The insulating layer 23 is formed so as to cover the wiring layer 22 on the other surface 10b of the core layer 10. The material and thickness of the insulating layer 23 can be the same as those of the insulating layer 13, for example. The insulating layer 23 can contain a filler such as silica (SiO2).

[0033] A via hole 23x that penetrates the insulating layer 23 and exposes the lower surface of the wiring layer 22 is formed in the insulating layer 23. The via hole 23x can be a frustum-shaped recess in which the diameter of the opening on the insulating layer 25 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 22.

[0034] The wiring layer 24 is formed on the other side of the insulating layer 23. The wiring layer 24 includes via wirings filled in the via hole 23x and a wiring pattern formed on the lower surface of the insulating layer 23. The wiring pattern is electrically connected to the wiring layer 22 via the via wiring. The material and thickness of the wiring layer 24 can be the same as those of the wiring layer 12, for example.

[0035] The insulating layer 25 is formed so as to cover the wiring layer 24 on the lower surface of the insulating layer 23. The material and thickness of the insulating layer 25 can be the same as those of the insulating layer 13, for example. The insulating layer 25 can contain a filler such as silica (SiO2).

[0036] The insulating layer 25 is formed with via holes 25x that penetrate the insulating layer 25 and expose the lower surface of the wiring layer 24. The via holes 25x can be frustum-shaped recesses in which the diameter of the opening on the solder resist layer 27 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 24.

[0037] The wiring layer 26 is formed on the other side of the insulating layer 25. The wiring layer 26 includes via wirings filled in the via holes 25x and wiring patterns formed on the lower surface of the insulating layer 25. The wiring patterns are electrically connected to the wiring layer 24 via the via wirings. The material and thickness of the wiring layer 26 can be the same as those of the wiring layer 12, for example.

[0038] The solder resist layer 27 is a protective insulating layer located outermost on the other side of the wiring substrate 1, and is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The material and thickness of the solder resist layer 27 can be the same as those of the solder resist layer 17, for example. The solder resist layer 27 has an opening 27x, and a part of the lower surface of the wiring layer 26 is exposed in the opening 27x. The planar shape of the opening 27x can be circular, for example. The wiring layer 26 exposed in the opening 27x can be used as a pad for electrically connecting to a mounting substrate such as a motherboard. If necessary, a metal layer can be formed on the lower surface of the wiring layer 26 exposed in the opening 27x, or an antioxidant treatment such as OSP treatment can be performed.

[0039] [Method for manufacturing a wiring substrate] FIGS. 2 to 5 are diagrams illustrating the manufacturing process of the wiring substrate according to the first embodiment, and are cross-sectional views corresponding to FIG. 1. Note that FIG. 3(d) is an enlarged view of part A in FIG. 3(c), FIGS. 4(b) and 4(c) are enlarged views of part A in FIG. 4(a), and FIG. 5(b) is an enlarged view of part A in FIG. 5(a).

[0040] Since the processes on one surface 10a side and the other surface 10b side of the core layer 10 are substantially the same, only the one surface 10a side of the core layer 10 will be illustrated and described here. Also, here, an example of the process for manufacturing one wiring board is shown, but it may also be a process of manufacturing a plurality of parts that will become the wiring board and then separating them into individual wiring boards.

[0041] First, in the process shown in FIG. 2(a), a core layer 10 in which through-wiring 11 and wiring layer 12 are formed is prepared. Specifically, for example, a laminate in which a planar copper foil that has not been patterned is formed on one surface 10a of a core layer 10, which is a so-called glass epoxy substrate or the like, is prepared. Then, in the prepared laminate, after thinning the copper foil as necessary, a through-hole 10x that penetrates the core layer 10 and the copper foil is formed by a laser processing method using a CO2 laser or the like.

[0042] Next, if necessary, a desmear treatment is performed to remove the resin residue contained in the core layer 10 adhering to the inner surface of the through-hole 10x. Then, a seed layer (copper or the like) that coats the copper foil and the inner surface of the through-hole 10x is formed by, for example, electroless plating or sputtering, and an electrolytic plating layer (copper or the like) is formed on the seed layer by an electrolytic plating method using the seed layer as a power supply layer. As a result, the through-hole 10x is filled with the electrolytic plating layer formed on the seed layer, and a wiring layer 12 in which a copper foil, a seed layer, and an electrolytic plating layer are laminated is formed on one surface 10a of the core layer 10. Next, the wiring layer 12 is patterned into a predetermined planar shape by a subtractive method or the like.

[0043] Next, in the process shown in FIG. 2(b), a semi-cured film-like epoxy resin or the like is laminated so as to cover the wiring layer 12 on one surface 10a of the core layer 10 and cured to form an insulating layer 13. Alternatively, instead of laminating a film-like epoxy resin or the like, a liquid or paste-like epoxy resin or the like may be applied and then cured to form the insulating layer 13. The material and thickness of the insulating layer 13 are as described above.

[0044] Next, in the process shown in FIG. 2(c), a via hole 13x that penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12 is formed in the insulating layer 13. The via hole 13x can be formed, for example, by a laser processing method using a CO2 laser or the like. After forming the via hole 13x, it is preferable to perform a desmear treatment to remove the resin residue attached to the surface of the wiring layer 12 exposed at the bottom of the via hole 13x.

[0045] Next, in the process shown in FIG. 2(d), a wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 includes via wirings filled in the via holes 13x and wiring patterns formed on the upper surface of the insulating layer 13. The wiring pattern may include pads 14a for mounting electronic components. The material of the wiring layer 14 and the thickness of the wiring pattern can be, for example, the same as those of the wiring layer 12. The wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via hole 13x.

[0046] The wiring layer 14 can be formed using various wiring formation methods such as the semi-additive method and the subtractive method. For example, when the wiring layer 14 is formed by the semi-additive method, a seed layer by electroless copper plating is formed on the surface of the insulating layer 13 including the inner wall of the via hole 13x and the surface of the wiring layer 12 exposed in the via hole 13x. Next, a plating resist pattern having an opening conforming to the shape of the wiring layer 14 is formed on the seed layer, and an electrolytic plating layer is deposited on the seed layer exposed in the opening of the plating resist pattern by electrolytic copper plating that supplies power from the seed layer. Next, after removing the plating resist pattern, etching using the electrolytic plating layer as a mask is performed to remove the seed layer exposed from the electrolytic plating layer to obtain the wiring layer 14.

[0047] Next, in the process shown in FIG. 3(a), a first insulating layer 15a is formed on the insulating layer 13 so as to cover the wiring layer 14. The first insulating layer 15a can be formed, for example, by the same method as the insulating layer 13. The material of the first insulating layer 15a is as described above.

[0048] Next, in the process shown in FIG. 3(b), a cavity 15z that penetrates the first insulating layer 15a and exposes the upper surface of the electronic component mounting pad 14a is formed in the first insulating layer 15a. The cavity 15z can be formed, for example, by a laser processing method using a CO2 laser or the like.

[0049] Next, in the processes shown in FIGS. 3(c) and 3(d), an electronic component 30 including an insulating substrate 31 and a pad 32 provided on one side of the insulating substrate 31 is prepared. In the electronic component 30, the upper surface of the pad 32 is exposed from the insulating substrate 31, and all side surfaces of the pad 32 are covered with the insulating substrate 31. The upper surface of the pad 32 is flush with the upper surface of the insulating substrate 31, for example. Then, the electronic component 30 is disposed on the upper surface of the electronic component mounting pad 14a exposed in the cavity 15z such that the pad 32 faces the opening side of the cavity 15z. The electronic component 30 may be temporarily fixed to the upper surface of the electronic component mounting pad 14a via an adhesive layer 40. Alternatively, the electronic component 30 may be directly disposed on the upper surface of the electronic component mounting pad 14a.

[0050] Next, in the processes shown in FIGS. 4(a) and 4(b), the electronic component 30 disposed in the cavity 15z is dry-etched from the arrow side to expose at least a part of the side surface of the pad 32 from the insulating substrate 31. The dry etching is performed under conditions such that the etching rate of the insulating substrate 31 is sufficiently higher than that of the pad 32. For example, when the insulating substrate 31 is made of SiO2 or SiN and the pad 32 is made of copper, plasma etching using a fluorine-based etching gas such as carbon tetrafluoride (CF4) can be selected as the dry etching. As the etching gas, a mixed gas of a fluorine-based gas and an oxygen gas may be used. Instead of plasma etching, ion milling or the like may be used. The dry etching may use isotropic dry etching or anisotropic dry etching.

[0051] The insulating substrate 31 is made of a material with an etching rate in dry etching such as plasma etching higher than that of the pad 32. Therefore, by dry etching, the pad 32 is hardly etched, and the insulating substrate 31 is selectively etched. As a result, as shown in FIG. 4(b), the upper surface side of the insulating substrate 31 is scraped, and a part of the side surface of the pad 32 is exposed from the insulating substrate 31. All of the side surfaces of the pad 32 may be exposed from the insulating substrate 31. Note that the upper surface of the first insulating layer 15a is also etched together with the electronic component 30. A mask for preventing etching of the upper surface of the first insulating layer 15a may be disposed.

[0052] Next, in the process shown in FIG. 4(c), the upper surface and the side surface of the pad 32 exposed from the insulating substrate 31 are roughened. The roughening of the pad 32 can be performed, for example, by CZ treatment. In the CZ treatment, for example, the pad 32 is etched using a solution mainly composed of formic acid to form a roughened surface. By performing the CZ treatment, the roughness of the upper surface and the side surface of the pad 32 exposed from the insulating substrate 31 can be made larger than the roughness of the portion of the pad 32 covered by the insulating substrate 31. In this step, the roughness of the portion covered by the insulating substrate 31 is about several nm to 50 nm in surface roughness Ra, whereas the roughness of the upper surface and the side surface of the pad 32 exposed from the insulating substrate 31 is preferably roughened to be about 50 nm to 300 nm in surface roughness Ra. Instead of the CZ treatment, the pad 32 may be roughened by other means such as black oxidation treatment (black oxide). Note that in these methods, the upper surface of the insulating substrate 31 is not roughened.

[0053] Next, in the process shown in FIG. 4(d), a second insulating layer 15b is disposed on the first insulating layer 15a and within the cavity 15z, and the roughened regions on the upper and side surfaces of the pad 32 are covered with the second insulating layer 15b. Specifically, for example, a semi-cured film-like epoxy resin or the like is laminated so as to cover the electronic component 30 and then cured to form the second insulating layer 15b. Alternatively, instead of laminating a film-like epoxy resin or the like, a liquid or paste-like epoxy resin or the like may be applied and cured to form the second insulating layer 15b. The material of the second insulating layer 15b is as described above. The thicknesses of the first insulating layer 15a and the second insulating layer 15b can be, for example, the same as that of the insulating layer 13. In this process, the insulating layer 15 is formed by the first insulating layer 15a and the second insulating layer 15b.

[0054] Next, in the process shown in FIG. 5(a), via holes 15x that penetrate the first insulating layer 15a and the second insulating layer 15b of the insulating layer 15 and expose the upper surface of the wiring layer 14 are formed. Also, via holes 15y that penetrate the second insulating layer 15b of the insulating layer 15 and expose the upper surface of the pad 32 of the electronic component 30 are formed. The via holes 15x and 15y can be formed as inverted frustoconical recesses in which the diameter of the opening on the upper surface side of the insulating layer 15 is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 14 or the upper surface of the pad 32. The via holes 15x and 15y can be formed, for example, by a laser processing method using a CO2 laser, a UV laser, an Excimer laser, or the like. After forming the via holes 15x and 15y, it is preferable to perform a desmear treatment to remove the resin residues adhering to the upper surfaces of the wiring layer 14 and the pad 32 exposed at the bottoms of the via holes 15x and 15y, respectively.

[0055] Also, after the desmear treatment, it is preferable to perform soft etching on the upper surfaces of the wiring layer 14 and the pad 32 that are respectively exposed at the bottoms of the via holes 15x and 15y. By the soft etching, the upper surfaces of the wiring layer 14 and the pad 32 that are respectively exposed at the bottoms of the via holes 15x and 15y become chemically clean surfaces, and good electrical connection with the via wiring formed in the subsequent process can be achieved. Soft etching means uniformly etching the surface of the object by about several μm. When the pad 32 is made of copper, for example, soft etching can be performed using an aqueous solution of cupric chloride. By the soft etching, the upper surface of the pad 32 exposed at the bottom of the via hole 15y is flattened more than the upper surface of the pad 32 located on the outer peripheral side of the via hole 15y. Also, by the soft etching, the upper surface of the pad 32 exposed at the bottom of the via hole 15y is slightly recessed from the upper surface of the pad 32 on the outer peripheral side of the via hole 15y. In this step, it is preferable that the soft etching is performed so that the upper surface of the pad 32 exposed at the bottom of the via hole 15y has a surface roughness Ra of about several nm to 300 nm.

[0056] Next, in the process shown in FIG. 5(c), the wiring layer 16 is formed. The wiring layer 16 is configured to include via wirings filled in the via holes 15x and 15y and wiring patterns formed on the upper surface of the insulating layer 15. The wiring pattern includes a portion that is electrically connected to the wiring layer 14 through the via wiring filling the inside of the via hole 15x. Also, the wiring pattern includes a portion that is electrically connected to the pad 32 of the electronic component 30 through the via wiring filling the inside of the via hole 15y. The wiring layer 16 can be formed using various wiring formation methods such as the semi-additive method and the subtractive method.

[0057] Next, in the process shown in FIG. 5(d), a solder resist layer 17 is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy-based insulating resin or acrylic-based insulating resin onto the upper surface of the insulating layer 15 so as to cover the wiring layer 16 by screen printing, roll coating, spin coating, or the like. Alternatively, for example, a film-like photosensitive epoxy-based insulating resin or acrylic-based insulating resin may be laminated onto the upper surface of the insulating layer 15 so as to cover the wiring layer 16.

[0058] Next, by exposing and developing the solder resist layer 17, an opening 17x is formed in the solder resist layer 17 to expose a part of the upper surface of the wiring layer 16 (photolithography method). The planar shape of the opening 17x can be, for example, circular. In this case, the diameter of the opening 17x can be arbitrarily designed according to the connection target (such as a semiconductor chip, etc.).

[0059] Note that in this process, the above-mentioned metal layer may be formed on the upper surface of the wiring layer 16 exposed at the bottom of the opening 17x by, for example, electroless plating or the like. Alternatively, instead of forming the metal layer, an antioxidant treatment such as OSP treatment may be performed. Through the above processes, the wiring board 1 is completed.

[0060] FIG. 6 is a partial cross-sectional view illustrating a wiring board according to a comparative example, showing a cross-section corresponding to FIG. 1(b). In the wiring board 1X shown in FIG. 6, all of the side surfaces of the pad 32 are covered by the insulating substrate 31, and the upper surface of the pad 32 exposed from the insulating substrate 31 is a roughened surface. The upper surface of the insulating substrate 31 is located above the upper surface of the pad 32. In this case, good adhesion can be obtained between the upper surface of the pad 32 and the second insulating layer 15b.

[0061] In contrast, in the region B located between adjacent pads 32 on the upper surface of the insulating substrate 31, since it is not a roughened surface, good adhesion cannot be obtained with the second insulating layer 15b. Therefore, in the region B, a gap is likely to occur between the upper surface of the insulating substrate 31 and the second insulating layer 15b. For example, if the plating solution when forming the wiring layer 16 soaks into this gap, there is a risk of short - circuit between adjacent pads 32. If the pitch between adjacent pads 32 is relatively wide (for example, 50 μm or more), such a problem is less likely to occur. However, in recent years, there has been a tendency for the pitch between adjacent pads 32 to become narrower. In particular, when the pitch between adjacent pads 32 is 40 μm or less, the risk of short - circuit between adjacent pads 32 cannot be ignored.

[0062] On the other hand, in the wiring board 1 shown in Fig. 1(b), the side of the pad 32 closer to the upper surface is exposed from the insulating substrate 31 and is a roughened surface. As a result, the adhesion between the pad 32 and the second insulating layer 15b becomes stronger than in the case of Fig. 6. That is, since the bonding area between the roughened surface of the pad 32 and the second insulating layer 15b increases, the adhesion between the pad 32 and the second insulating layer 15b covering the pad 32 can be improved compared to the case of Fig. 6. As a result, a gap is less likely to occur between the upper surface of the insulating substrate 31 and the second insulating layer 15b, and the infiltration of the plating solution when forming the wiring layer 16 can be suppressed, so the reliability of the wiring board 1 is improved.

[0063] Also, in Fig. 1(b), the upper surface of the insulating substrate 31 located between adjacent pads 32 is located below the upper surface of the pad 32. Therefore, even if infiltration of the plating solution occurs, the distance until it reaches the adjacent pads 32 becomes longer, so the risk of short - circuit between adjacent pads 32 can be reduced.

[0064] In this way, since the wiring board 1 has a structure in which short - circuit is less likely to occur between adjacent pads 32 of the electronic component 30, it is possible to reduce the pitch between adjacent pads 32. For example, even when the pitch between adjacent pads 32 is 40 μm or less, a higher electrical short - circuit resistance can be obtained compared to the structure shown in Fig. 6.

[0065] <Example 1 of Modification of the First Embodiment> In Example 1 of the modification of the first embodiment, another example of the manufacturing process of the wiring board according to the first embodiment is shown. In Example 1 of the modification of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0066] FIG. 7 is a diagram showing another example of the manufacturing process of the wiring board according to the first embodiment. The processes shown in FIGS. 3(c) to 4(a) of the first embodiment may be replaced with the processes shown in FIGS. 7(a) to 7(c).

[0067] First, the same processes as those in FIGS. 2(a) to 3(b) of the first embodiment are performed. Next, in the processes shown in FIGS. 7(a) and 7(b), the electronic component 30 is dry-etched to expose at least a part of the side surface of the pad 32 from the insulating substrate 31. Specifically, a wafer 30W on which a plurality of electronic components 30 are arranged is prepared, and dry etching is performed from the arrow direction with respect to the side on which the pad 32 of the wafer 30W is formed. The upper side of the arrow in FIG. 7(b) shows the electronic component 30 before dry etching, and the lower side of the arrow in FIG. 7(b) shows the electronic component 30 after dry etching. In each of the electronic components 30 arranged on the wafer 30W, before dry etching, as shown on the upper side of the arrow in FIG. 7(b), the lower surface and the side surface of the pad 32 are covered with the insulating substrate 31, and the upper surface is exposed from the insulating substrate 31. The upper surface of the insulating substrate 31 and the upper surface of the pad 32 are, for example, flush.

[0068] In each of the electronic components 30 arranged on the wafer 30W, the insulating substrate 31 having a high etching rate with respect to the pad 32 is selectively removed by dry etching. Therefore, after dry etching, as shown in FIG. 7(b), at least a part of the side surface and the upper surface of the pad 32 are exposed from the insulating substrate 31.

[0069] Note that the processes same as those in FIGS. 2(a) to 3(b) of the first embodiment and the processes shown in FIGS. 7(a) and 7(b) may be performed either first or in parallel.

[0070] Next, in the process shown in FIG. 7(c), after the dry etching processes shown in FIGS. 7(a) and 7(b), the electronic component 30 is placed in the cavity 15z such that the pad 32 faces the opening side of the cavity 15z. Specifically, the wafer 30W is singulated to produce a plurality of electronic components 30, and the electronic component 30 is placed in the cavity 15z in the same manner as in the process of FIG. 3(c). Thereafter, by performing the processes from FIG. 4(c) onward of the first embodiment, the wiring board 1 can be obtained.

[0071] In the processes shown in FIGS. 4(a) and 4(b) of the first embodiment, the upper surface of the first insulating layer 15a is also dry-etched together with the pad 32 of the electronic component 30. In contrast, in the processes shown in FIGS. 7(a) and 7(b), only the insulating substrate 31 of the electronic component 30 is dry-etched, so the upper surface of the first insulating layer 15a is not dry-etched in the process shown in FIG. 7(c). Therefore, depending on the necessity of dry-etching the first insulating layer 15a, the processes shown in FIGS. 4(a) and 4(b) and the processes shown in FIGS. 7(a) and 7(b) can be selected.

[0072] Note that the process shown in FIG. 4(c) of the first embodiment may be performed between the processes of FIGS. 7(a) and 7(b) and the process of FIG. 7(c).

[0073] <Second Embodiment> The second embodiment shows an example in which a part of the lower surface of the pad of the electronic component is roughened. In the second embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0074] FIG. 8 is a partial cross-sectional view illustrating a wiring board according to the second embodiment, showing a cross-section corresponding to FIG. 1(b). In the wiring board 2 shown in FIG. 8, a recess 31x is provided in the insulating substrate 31 of the electronic component 30 to expose the outer peripheral portion of the lower surface of the adjacent pad 32. The outer peripheral portion of the lower surface of the pad 32 exposed in the recess 31x is roughened to the same extent as the upper surface and the side surface of the pad 32. All of the side surfaces and the outer peripheral portion of the lower surface of the adjacent pads 32 are covered with the second insulating layer 15b. In a cross-sectional view, the depth of the recess 31x is, for example, the deepest at the central portion between the adjacent pads 32, and becomes shallower as it moves away from the central portion.

[0075] The recess 31x can be formed by isotropic dry etching. The recess 31x can be formed, for example, by isotropic plasma etching using a fluorine-based etching gas such as carbon tetrafluoride.

[0076] Thus, in the wiring board 2, the outer peripheral portion of the lower surface of the pad 32 exposed in the recess 31x is roughened to the same extent as the upper surface and the side surface of the pad 32. Therefore, the bonding area between the roughened surface of the pad 32 and the second insulating layer 15b increases, and the adhesion between the pad 32 and the second insulating layer 15b can be further improved. In addition, since a part of the second insulating layer 15b wraps around to the lower surface side of the pad 32, an anchor effect occurs, and the adhesion between the pad 32 and the second insulating layer 15b can be further improved. Further, even if the plating solution infiltrates, the distance until it reaches the adjacent pad 32 becomes longer, so that the risk of short circuit between the adjacent pads 32 can be further reduced.

[0077] As described above, the preferred embodiments have been described in detail. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

Description of Reference Numerals

[0078] 1, 2 Wiring board 10 Core layer 10a One surface 10b The other side 10x Through-hole 11 Through-wiring 12, 14, 16, 22, 24, 26 Wiring layer 13, 15, 23, 25 Insulating layer 15a First insulating layer 15b Second insulating layer 13x, 15x, 15y, 23x, 25x Via hole 14a Pad for mounting electronic component 15z Cavity 17, 27 Solder resist layer 17x, 27x Opening 30 Electronic component 30W Wafer 31 Insulating substrate 31x Recess 32 Pad

Claims

1. a first insulating layer; a cavity formed in the first insulating layer; an insulating substrate, and a pad provided on one side of the insulating substrate, and an electronic component disposed in the cavity such that the pad faces an opening side of the cavity; a second insulating layer disposed on the first insulating layer and in the cavity; an upper surface and a side surface of the pad have regions exposed from the insulating substrate; at least a part of the upper surface and the side surface of the pad exposed from the insulating substrate is covered with the second insulating layer; a wiring board, wherein a roughness of a surface of the pad covered with the second insulating layer is greater than a roughness of a surface of the pad not covered with the second insulating layer.

2. The wiring board according to claim 1, wherein the pad is integrally formed from the same material.

3. a via hole is provided that penetrates the second insulating layer and exposes a part of an upper surface of the pad; The wiring board according to claim 1 or 2, wherein a roughness of a surface of the pad covered with the second insulating layer is greater than a roughness of an upper surface of the pad exposed in the via hole.

4. The wiring board according to claim 1 or 2, wherein all of side surfaces of the pad are exposed from the insulating substrate and covered with the second insulating layer.

5. a plurality of the pads are provided; a recess is provided in the insulating substrate to expose an outer peripheral portion of a lower surface of adjacent pads; The wiring board according to claim 4, wherein all of side surfaces and an outer peripheral portion of a lower surface of adjacent pads are covered with the second insulating layer.

6. The wiring board according to claim 5, wherein in a cross-sectional view, a depth of the recess is deepest at a central portion between adjacent pads and becomes shallower as it is farther from the central portion.

7. The wiring board according to claim 1 or 2, wherein the insulating substrate is made of a material having an etching rate in plasma etching using a fluorine-based etching gas higher than that of the pad.

8. a step of forming a cavity in a first insulating layer; a step of preparing an insulating substrate and a pad provided on one side of the insulating substrate, and an electronic component having an upper surface of the pad exposed from the insulating substrate and all side surfaces of the pad covered with the insulating substrate; a step of disposing the electronic component in the cavity such that the pad faces an opening side of the cavity; A step of dry-etching the electronic component disposed in the cavity to expose at least a part of the side surface of the pad from the insulating substrate; A step of roughening the upper surface and the side surface of the pad exposed from the insulating substrate; A method for manufacturing a wiring substrate, comprising: disposing a second insulating layer on the first insulating layer and in the cavity, and covering the roughened regions of the upper surface and the side surface of the pad with the second insulating layer.

9. A step of forming a cavity in the first insulating layer; A step of preparing an electronic component including an insulating substrate and a pad provided on one side of the insulating substrate, wherein the upper surface of the pad is exposed from the insulating substrate and all of the side surfaces of the pad are covered by the insulating substrate; A step of dry-etching the electronic component to expose at least a part of the side surface of the pad from the insulating substrate; A step of disposing the electronic component in the cavity after the dry-etching step so that the pad faces the opening side of the cavity; A step of roughening the upper surface and the side surface of the pad exposed from the insulating substrate; A method for manufacturing a wiring substrate, comprising: disposing a second insulating layer on the first insulating layer and in the cavity, and covering the roughened regions of the upper surface and the side surface of the pad with the second insulating layer.

10. The dry-etching is plasma etching using a fluorine-based etching gas, The method for manufacturing a wiring substrate according to claim 8 or 9, wherein the insulating substrate is made of a material having an etching rate higher than that of the pad in the plasma etching.

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