Semiconductor switch

Abstract

To provide a semiconductor switch that can shorten the start time while suppressing the increase in consumption power.SOLUTION: A power transistor 110 is connected between an input pin IN and an output pin OUT. A current detection circuit 120 generates a current detection signal VCS representing a current IOUT flowing in the power transistor 110. A controller circuit 130 switches on and off of the power transistor 110 in accordance with a control signal SCNT. The controller circuit 130 regulates a gate voltage VG of the power transistor 110 so that the current detection signal VCS does not exceed a current limiting level VILIM having a positive correlation with respect to a voltage VOUT of the output pin OUT when the power transistor 110 is on.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor switch.

Background Art

[0002] A semiconductor switch is used to switch the electrical conduction and interruption of a certain path. The semiconductor switch includes a power transistor connected between an input pin and an output pin, and a controller that controls the on and off of the power transistor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] The inventor has come to recognize the following problems in designing a semiconductor switch having a current limiting function for circuit protection. An input voltage V IN is input to the input pin of the semiconductor switch, and a load is connected to the output pin. When the semiconductor switch is in the off state, a voltage unrelated to the input voltage V IN is generated at the output pin of the semiconductor switch, for example, zero.

[0005] When the semiconductor switch is switched on, the voltage (output voltage) V OUT of the output pin rises with time and approaches the input voltage V IN . The limit current I LIM of the semiconductor switch needs to be designed in consideration of the rated power of the semiconductor switch. The power consumption P of the semiconductor switch is the product of the potential difference ΔV (= V IN -V OUT ) between the input pin and the output pin and the current I flowing through the semiconductor switch. P = (V IN -V OUT ) × I

[0006] The power consumption of the semiconductor switch is maximized immediately after the semiconductor switch is turned on, and the output voltage V OUT is minimum and 0V at this time. Therefore, the maximum power consumption is P MAX =V IN ×I LIM is represented by. Therefore, increasing the limit current I LIM will increase the power consumption.

[0007] On the contrary, if the limit current I LIM is set too low, the startup time until the output voltage V OUT rises to near the input voltage V IN will become long.

[0008] The present disclosure has been made in such a situation, and one of the exemplary purposes of a certain aspect thereof is to provide a semiconductor switch capable of shortening the startup time while suppressing an increase in power consumption.

[0009] A semiconductor switch according to an aspect of the present disclosure includes an input terminal, an output terminal, a power transistor connected between the input terminal and the output terminal, a current detection circuit that generates a current detection signal indicating a current flowing through the power transistor, and, in response to a control signal, turns on and off the power transistor, and adjusts the gate voltage of the power transistor so that, when the power transistor is in the on state, the current detection signal does not exceed a current limit level having a positive correlation with the output voltage generated at the output terminal.

[0010] In addition, combinations of the above components arbitrarily, and components and expressions mutually replaced between methods, devices, systems, etc. are also effective as aspects of the present invention or the present disclosure. Furthermore, the description of this item (means for solving the problem) does not explain all the essential features of the present invention, and therefore, sub-combinations of these described features can also be the present invention.

Brief Description of the Drawings

[0011]

Figure 1

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[0012] [Detailed Description] (Overview of the Embodiment) An overview of some exemplary embodiments of the present disclosure will be described. This overview is provided as a prelude to the detailed description that follows and is intended to provide a basic understanding of the embodiments by simplifying and explaining some concepts of one or more embodiments. It is not intended to limit the scope of the invention or disclosure. This overview is not an exhaustive overview of all possible embodiments, nor is it intended to identify the important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, "one embodiment" may be used herein to refer to one embodiment (example or modification) or a plurality of embodiments (examples or modifications) disclosed in this specification.

[0013] A semiconductor switch according to an embodiment includes an input terminal, an output terminal, a power transistor connected between the input terminal and the output terminal, a current detection circuit that generates a current detection signal indicating the current flowing through the power transistor, and a controller circuit that switches the power transistor between on and off according to a control signal and adjusts the gate voltage of the power transistor so that the current detection signal does not exceed a current limit level having a positive correlation with the output voltage generated at the output terminal when the power transistor is in the on state.

[0014] According to this configuration, the lower the output voltage, the smaller the current limit level, and the higher the output voltage, the larger the current limit level. Immediately after turning on the semiconductor switch, the output voltage is low, so the current control signal is small. However, as the output voltage rises over time, the current limit level increases accordingly, and the current flowing through the power transistor increases. This can suppress the increase in power consumption while shortening the startup time.

[0015] In one embodiment, the current limit level may change linearly with respect to the output voltage. In this case, the current limit level can be generated by a simple configuration such as a voltage dividing circuit.

[0016] In one embodiment, the current limit level may be the lower one of a voltage detection signal based on the output voltage and a reference signal having a predetermined voltage level. Thereby, the upper limit of the current limit level can be defined by the voltage level of the reference signal.

[0017] In one embodiment, the controller circuit may include a voltage dividing circuit that divides the output voltage to generate a voltage detection signal, a gate voltage generation circuit that applies a high-level or low-level gate voltage to the gate of the power transistor according to a control signal, and a current limit circuit that adjusts the high-level gate voltage so that the current detection signal does not exceed a current limit level based on the voltage detection signal.

[0018] In one embodiment, the gate voltage generation circuit may include a voltage source that generates a high-level voltage corresponding to a high level, and a driver that applies a gate voltage corresponding to the high-level voltage to the gate of the power transistor. The current limiting circuit may adjust the high-level voltage generated by the voltage source so that the current detection signal does not exceed the current limit level.

[0019] In one embodiment, the power transistor is N-type, and the current limiting circuit may be a shunt regulator that extracts a current corresponding to the error between the current detection signal and the current limit level from the output of the voltage source.

[0020] In one embodiment, the shunt regulator may include an operational amplifier having three input nodes that receive a shunt transistor, a voltage detection signal, a reference signal, and a current detection signal, and an output node connected to the gate of the shunt transistor.

[0021] In one embodiment, the operational amplifier may have an offset. When the output voltage is near zero, the current limit level becomes a non-zero value based on the offset of the operational amplifier, enabling reliable startup.

[0022] In one embodiment, the power transistor is N-type, and the voltage source may be a charge pump circuit.

[0023] In one embodiment, the current detection circuit includes a replica transistor of the same type as the power transistor, having a first end connected to the input terminal and a gate connected to the gate of the power transistor, a regulator that adjusts the voltage at the second end of the replica transistor to be equal to the voltage at the corresponding terminal of the power transistor, and a current sense resistor connected between the second end of the replica transistor and ground. The voltage drop across the current sense resistor may be the current detection signal.

[0024] In one embodiment, the power transistor and the replica transistor may each be configured by connecting two transistors of the same type in reverse series.

[0025] In one embodiment, the power transistor may be P-type.

[0026] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Also, the embodiments are illustrative rather than limiting the disclosure and the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and the invention.

[0027] In this specification, the phrase "member A is in a state of being connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members without substantially affecting their electrical connection states or impairing the functions and effects achieved by their connection.

[0028] Similarly, the phrase "member C is in a state of being connected (provided) between member A and member B" includes not only the case where member A and member C or member B and member C are directly connected, but also the case where they are indirectly connected via other members without substantially affecting their electrical connection states or impairing the functions and effects achieved by their connection.

[0029] (Embodiment) FIG. 1 is a circuit diagram of a semiconductor switch 100 according to an embodiment. The semiconductor switch 100 is an integrated circuit (IC) integrated on a single semiconductor substrate. In the present embodiment, the semiconductor switch 100 is a switch IC.

[0030] The semiconductor switch 100 includes an input pin IN, an output pin OUT, and a control pin CNT. An input voltage V is input to the input pin IN from the outside. INis applied. A load 2 is connected to the output pin OUT. A control signal S for instructing the on and off of the semiconductor switch 100 is input to the control pin CNT. CNT The control signal S CNT is a binary signal of a high level and a low level, and one is assigned to an on level for instructing the on of the semiconductor switch 100, and the other is assigned to an off level for instructing the off of the semiconductor switch 100.

[0031] The semiconductor switch 100 includes a power transistor 110, a current detection circuit 120, and a controller circuit 130.

[0032] The power transistor 110 is connected between the input pin IN and the output pin OUT. In this embodiment, the power transistor 110 is an NMOS transistor, that is, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0033] The current detection circuit 120 generates a current detection signal V indicating the current I flowing through the power transistor 110. OUT The current detection signal V CS is generated.

[0034] The controller circuit 130 switches the on and off of the power transistor 110 according to the control signal S. CNT Specifically, when the control signal S CNT is at the on level, the power transistor 110 is turned on, and when the control signal S CNT is at the off level, the power transistor 110 is turned off.

[0035] The semiconductor switch 100 has a current limiting function. The controller circuit 130 adjusts the gate voltage (voltage between gate and source) V of the power transistor 110 so that the current detection signal V does not exceed the current limit level V when the power transistor 110 is on. The current limit level V CS When the current detection signal V exceeds the current limit level V ILIM The gate voltage (voltage between gate and source) V of the power transistor 110 is adjusted so that it does not exceed the current limit level V G The current limit level V ILIMIt is based on the internal signal of the controller circuit 130 and is not shown in FIG. 1.

[0036] The controller circuit 130 changes the current limit level V OUT to have a positive correlation with the output voltage V ILIM generated at the output pin OUT.

[0037] FIG. 2 is a diagram for explaining the relationship between the output voltage V OUT generated at the output pin OUT and the current limit level V ILIM . The horizontal axis in the upper part of FIG. 2 is the output voltage V OUT of the output pin OUT, and the horizontal axis in the lower part is the potential difference ΔV between the voltage V IN of the input pin IN and the output voltage V OUT of the output pin OUT, that is, the voltage across both ends of the power transistor 110.

[0038] The current limit level V ILIM defines the upper limit (limit current) I OUT of the current I LIM flowing through the power transistor 110. As shown in the upper part of FIG. 2, the current limit level V ILIM has a positive correlation with the voltage V OUT of the output pin OUT, and the higher the voltage V OUT of the output pin OUT, the larger the current limit level V ILIM . The current limit level V ILIM changes linearly with the voltage V OUT of the output pin OUT. Note that when the output voltage V OUT is zero and the current limit level V ILIM is zero, it will cause startup failure. Therefore, the current limit level V ILIM changes in a range higher than the non-zero minimum voltage V MIN . Also, in an application where the upper limit of the input voltage V IN is large, the upper limit of the output voltage V OUT will also be high. In this case, in order to prevent the current limit level V ILIM from becoming too large, it is advisable to set a maximum value V ILIM for the current limit level V MAX .

[0039] The input voltage V of the input terminal IN IN is set as a constant. At this time, as shown in the lower part of FIG. 2, the current limit level V ILIM has a negative correlation with the potential difference ΔV between the input pin IN and the output pin OUT.

[0040] The dashed line indicates the maximum rating P of the power transistor 110 MAX and V = P MAX / ΔV holds. The current limit level V ILIM can be determined within a range not exceeding the maximum rating P MAX .

[0041] The above is the configuration of the semiconductor switch 100. The advantages of the semiconductor switch 100 become clear by comparison with the comparative technology. Therefore, the comparative technology will be described. In the comparative technology, the current limit level V ILIM is fixed at a predetermined value V0. That is, the upper limit (limit current) of the output current I OUT is fixed at the current amount I LIM0 corresponding to the predetermined value V0.

[0042] FIG. 3 is a diagram for explaining the operation of the semiconductor switch according to the comparative technology. Before time t0, the control signal S CNT is at a low level, and the controller circuit 130 applies 0 V to the gate of the power transistor 110 to turn it off. Here, a capacitor is considered as the load.

[0043] At time t0, the control signal S CNT becomes high level. The controller circuit 130 applies a gate voltage V IN higher than the input voltage V G to the gate of the power transistor 110 to turn on the power transistor 110.

[0044] When the power transistor 110 is turned on, the output voltage V OUTrises. The current I flowing through the power transistor 110 OUT is clamped to the limit current I LIM0 . When the load is a capacitor, the output voltage V OUT rises at a constant slope with respect to time, with a slope corresponding to the limit current I LIM0 . At time t1, when the output voltage V OUT rises to near the input voltage V IN , the current I OUT becomes zero, and the startup is completed.

[0045] The startup time τ = t1 - t0 is limited by the limit current I LIM0 . When fixing the limit current I LIM0 , it is necessary to determine the limit current I LIM0 so that the maximum rating of the power transistor 110 is not exceeded in a state where ΔV immediately after startup is large. Therefore, the limit current I LIM0 cannot be increased. For this reason, in the comparative technology, the startup time τ becomes long.

[0046] Subsequently, the operation of the semiconductor switch 100 according to the embodiment will be described.

[0047] FIG. 4 is a diagram for explaining the operation of the semiconductor switch 100 of FIG. 1. Before time t0, the control signal S CNT is at a low level, and the controller circuit 130 applies 0V to the gate of the power transistor 110 to turn it off.

[0048] At time t0, the control signal S CNT becomes high level. The controller circuit 130 applies a gate voltage V IN higher than the input voltage V G to the gate of the power transistor 110 to turn on the power transistor 110.

[0049] Immediately after the power transistor 110 is turned on, the limit current I LIM is the amount of current I MIN based on the lowest voltage V MINand the output voltage V generated at the output pin OUT OUT rises.

[0050] Then, as the output voltage V OUT rises, the limit current I LIM increases, and the output current I LIM limited by the limit current I OUT also increases as the output voltage V OUT rises. Therefore, a larger output current I OUT flows compared to the comparative technology, and the output voltage V OUT rises at a faster speed compared to the comparative technology.

[0051] The above is the operation of the semiconductor switch 100. According to this semiconductor switch 100, the startup time can be shortened while suppressing an increase in power consumption.

[0052] This disclosure is understood as the block diagram and circuit diagram of FIG. 1, or extends to various devices and methods derived from the above description, and is not limited to a specific configuration. Hereinafter, in order to assist in understanding the essence and operation of this disclosure and the present invention, and to clarify them, rather than narrowing the scope of this disclosure, more specific configuration examples and embodiments will be described.

[0053] FIG. 5 is a circuit diagram of the semiconductor switch 100 according to an embodiment. In this embodiment, the power transistor 110 includes NMOS transistors 112 and 114 of the same type connected in series. The back gates of the first transistor 112 and the second transistor 114 are connected such that the body diodes thereof are in opposite directions. Thereby, a reverse current from the output pin OUT to the input pin IN is prevented.

[0054] The controller circuit 130 includes a voltage dividing circuit 132, a gate voltage generating circuit 140, and a current limiting circuit 150.

[0055] The voltage dividing circuit 132 divides the voltage V OUT of the output pin OUT to generate a voltage detection signal V DETGenerate. The voltage dividing circuit 132 includes resistors R1 and R2.

[0056] The gate voltage generation circuit 140 applies a gate voltage V at a high level or a low level to the gate of the power transistor according to the control signal S. CNT In this embodiment, since the power transistor 110 is an NMOS transistor, the gate voltage generation circuit 140 generates a high-level gate voltage V when the control signal S is at the on level (high level) indicating the on state of the power transistor 110, and generates a low-level gate voltage V when the control signal S is at the off level (low level) indicating the off state of the power transistor 110. The high-level gate voltage V is a voltage higher than the input voltage V, and the low-level gate voltage V is the ground voltage (0V). The current limiting circuit 150 adjusts the voltage level of the high-level gate voltage V so that the current detection signal V does not exceed the current limit level V based on the voltage detection signal V. The current limit level V is based on an internal signal of the current limiting circuit 150 and is not shown in FIG. 5. G In this embodiment, since the power transistor 110 is an NMOS transistor, the gate voltage generation circuit 140 generates a high-level gate voltage V when the control signal S is at the on level (high level) indicating the on state of the power transistor 110, and generates a low-level gate voltage V when the control signal S is at the off level (low level) indicating the off state of the power transistor 110. The high-level gate voltage V is a voltage higher than the input voltage V, and the low-level gate voltage V is the ground voltage (0V). The current limiting circuit 150 adjusts the voltage level of the high-level gate voltage V so that the current detection signal V does not exceed the current limit level V based on the voltage detection signal V. The current limit level V is based on an internal signal of the current limiting circuit 150 and is not shown in FIG. 5. CNT is at the on level (high level) indicating the on state of the power transistor 110, and generates a high-level gate voltage V. G When the control signal S. CNT is at the off level (low level) indicating the off state of the power transistor 110, it generates a low-level gate voltage V. G The high-level gate voltage V. G is a voltage higher than the input voltage V. IN The low-level gate voltage V. G is the ground voltage (0V). The current limiting circuit 150 adjusts the voltage level of the high-level gate voltage V so that the current detection signal V does not exceed the current limit level V based on the voltage detection signal V. The current limit level V is based on an internal signal of the current limiting circuit 150 and is not shown in FIG. 5. CS When the current detection signal V. DET exceeds the current limit level V based on the voltage detection signal V. ILIM The high-level gate voltage V. G The current limiting circuit 150 adjusts the voltage level of the high-level gate voltage V so that the current detection signal V does not exceed the current limit level V based on the voltage detection signal V. The current limit level V is based on an internal signal of the current limiting circuit 150 and is not shown in FIG. 5. ILIM The current limit level V is based on an internal signal of the current limiting circuit 150 and is not shown in FIG. 5.

[0057] The gate voltage generation circuit 140 includes a voltage source 142 and a driver 144. The voltage source 142 generates a voltage V corresponding to the high level of the gate voltage V. The driver 144 receives the voltage V at the upper power supply node 146 and the ground voltage 0V at the lower power supply node 148. The driver 144 outputs a low-level (0V) gate voltage V when the control signal S at the input node is at the low level, and outputs a high-level (V) gate voltage V when the control signal S at the input node is at the high level. G The voltage dividing circuit 132 includes resistors R1 and R2. H The driver 144 receives the voltage V at the upper power supply node 146 and the ground voltage 0V at the lower power supply node 148. The driver 144 outputs a low-level (0V) gate voltage V when the control signal S at the input node is at the low level, and outputs a high-level (V) gate voltage V when the control signal S at the input node is at the high level. H The driver 144 receives the voltage V at the upper power supply node 146 and the ground voltage 0V at the lower power supply node 148. The driver 144 outputs a low-level (0V) gate voltage V when the control signal S at the input node is at the low level, and outputs a high-level (V) gate voltage V when the control signal S at the input node is at the high level. CNT When the control signal S at the input node is at the low level, it outputs a low-level (0V) gate voltage V. G When the control signal S at the input node is at the low level, it outputs a low-level (0V) gate voltage V. CNT When the control signal S at the input node is at the high level, it outputs a high-level (V). H The driver 144 receives the voltage V at the upper power supply node 146 and the ground voltage 0V at the lower power supply node 148. The driver 144 outputs a low-level (0V) gate voltage V when the control signal S at the input node is at the low level, and outputs a high-level (V) gate voltage V when the control signal S at the input node is at the high level. GOutput it. The voltage source 142 is, for example, the input voltage V IN or a power supply voltage V (not shown) DD It may be a charge pump circuit that boosts the voltage

[0058] The current limiting circuit 150 adjusts the voltage level of the output voltage V CS of the voltage source 142 so that the current detection signal V ILIM does not exceed the current limit level V H

[0059] Note that the configuration of the gate voltage generation circuit 140 is not limited to that in FIG. 5. For example, the on and off of the voltage source 142 may be controlled in conjunction with the control signal CNT. In this case, the driver 144 may be omitted, and the output voltage V H of the voltage source 142 may be directly supplied to the gate of the power transistor 110 as the gate voltage V G

[0060] Also, the output of the current limiting circuit 150 may be connected to the gate of the power transistor 110 to directly adjust the gate voltage V G

[0061] FIG. 6 is a circuit diagram showing a configuration example of the current limiting circuit 150. In this example, the current limiting circuit 150 is a shunt regulator that sinks the current I CS from the output of the voltage source 142 so that the current detection signal V ILIM approaches the current limit level V ADJ The current I ADJ is related to the current detection signal V CS and the current limit level V ILIM ​​​It depends on the error. The current limiting circuit 150 includes a shunt transistor 152, an error amplifier (operational amplifier) 154, and an enable switch 156. The source of the shunt transistor 152 is grounded, and the drain is connected to the output node of the voltage source 142 via the enable switch 156. The enable switch 156 is controlled according to the enable signal ILIM_EN. When the enable switch 156 is off, the current limiting function is disabled. If you want the current limiting function to operate constantly, the enable switch 156 may be omitted.

[0062] The error amplifier 154 receives the current detection signal V CS at the first input node (+), the voltage detection signal V DET at the second input node (-), and the reference signal V REF at the third input node (-). The reference signal V REF defines the maximum level I LIM of the limit current I MAX . The output node of the error amplifier 154 is connected to the gate of the shunt transistor 152.

[0063] With this shunt regulator, the error between the lower of the current detection signal V CS , the voltage detection signal V DET , and the reference signal V REF is amplified, and the shunt current I ADJ corresponding to the error flows through the shunt transistor 152. When the shunt current I ADJ flows, the output voltage V H of the voltage source 142, that is, the gate voltage V G decreases, and feedback is applied so that the output current I OUT , that is, the current detection signal V CS decreases. In this configuration, the lower of the voltage detection signal V DET and the reference signal V REF becomes the current limiting level V ILIM .

[0064] An intentional input offset voltage V OFS may also be introduced to the error amplifier 154. In this case, VCS and V DET and V REF Feedback is applied such that the following relational expression holds between the lower one of them. V CS = MIN(V DET , V REF ) + V OFS MIN() is a function that selects the smaller one of two arguments. By introducing the input offset voltage V OFS , at the moment immediately after startup when V DET ≈ 0V, feedback is applied such that V CS = V OFS holds. That is, the minimum current I OFS determined by the input offset voltage V MIN flows.

[0065] Note that instead of introducing the input offset voltage V OFS to the error amplifier 154, a clamp circuit may be further added to clamp the voltage detection signal V DET so that it does not fall below a predetermined minimum level V MIN .

[0066] FIG. 7 is a circuit diagram showing a configuration example of the current detection circuit 120. The current detection circuit 120 includes a replica transistor 122, a regulator 124, and a current sense resistor 128.

[0067] The replica transistor 122 has its first end connected to the input pin IN and its gate connected to the gate of the power transistor 110. The replica transistor 122 has the same configuration as the power transistor 110. The size of the replica transistor 122 may be smaller than the size of the power transistor 110.

[0068] The regulator 124 adjusts the voltage V S at the second end of the replica transistor 122 to the voltage V OUT at the corresponding terminal of the power transistor 110, that is, the output pin OUT.Adjust so as to be equal to. In the replica transistor 122, a detection current I OUT proportional to the current I DET flowing through the power transistor 110 flows. The regulator 124 includes a transistor 125 and an error amplifier 126. The error amplifier 126 receives the voltage V OUT of the output pin OUT at the first input node (+) and receives the voltage V S of the second end of the replica transistor 122 at the second input node (-). The output of the error amplifier 126 is connected to the gate of the transistor 125.

[0069] The current sense resistor 128 is connected between the drain of the replica transistor 122 and the ground. A detection current I DET flows through the current sense resistor 128, and a voltage drop proportional to the detection current I DET occurs. This voltage drop becomes the current detection signal V CS .

[0070] Next, a modified example will be described.

[0071] (Modified Example 1) FIG. 8 is a circuit diagram of a controller circuit 130A according to Modified Example 1. The controller circuit 130A includes a current limit value setting circuit 134, a current limit circuit 150A, a voltage source 142, and a driver 144.

[0072] The current limit value setting circuit 134 generates a current limit signal V OUT showing the input-output characteristics shown in FIG. 2 with respect to the voltage V ILIM of the output pin OUT. The current limit value setting circuit 134 includes a clamp circuit 136 in addition to a voltage dividing circuit 132 including resistors R1 and R2. The clamp circuit 136 clamps the voltage V DET after voltage division so as not to exceed a predetermined upper limit level V MAX .

[0073] The current limit circuit 150A is such that the current limit circuit 150, the current detection signal V CS is the current limit signal V ILIMso as to approach, from the output of the voltage source 142, a current I ADJ is a shunt regulator that sinks it.

[0074] The error amplifier 154 receives a current detection signal V CS at a first input node (+) and a voltage detection signal V DET at a second input node (-). The output node of the error amplifier 154 is connected to the gate of the shunt transistor 152.

[0075] By this shunt regulator, the error between the current detection signal V CS and the current limit signal V ILIM is amplified, and a shunt current I ADJ corresponding to the error flows through the shunt transistor 152. When the shunt current I ADJ flows, the output voltage V H of the voltage source 142, that is, the gate voltage V G decreases, and feedback is applied so that the output current I OUT , that is, the current detection signal V CS decreases.

[0076] Also in Modification 1, the error amplifier 154 may have an input offset voltage V OFS . Thereby, a minimum current I MIN can be defined. Instead of introducing the input offset voltage V OFS into the error amplifier 154, a clamp circuit that clamps the voltage V DET after voltage division so as not to fall below a predetermined minimum level V MIN may be further added.

[0077] (Modification 2) In the embodiment, the power transistor 110 is an N-channel MOSFET, but it may be a P-channel MOSFET. In this case, the controller circuit 130 (gate voltage generation circuit 140) supplies a low-level gate voltage V CNT to the gate of the power transistor 110 when the control signal S G is at the on level, and the control signal S CNTWhen it is at the off level, the gate voltage V IN ) of the high level (V G ) is supplied to the gate of the power transistor 110. The controller circuit 130 adjusts the gate voltage V CS of the low level so that the current detection signal V ILIM does not exceed the current limit level V G when the power transistor 110 is in the on state.

[0078] (Modification 3) In the embodiment, the semiconductor switch 100 was a switch IC, but the present disclosure is not limited thereto. The semiconductor switch 100 may be incorporated into a functional IC such as a controller IC of a DC / DC converter, a linear regulator IC, or a power management IC (PMIC). In this case, the input pin IN and the output pin OUT become internal nodes of the IC.

[0079] Although the embodiments according to the present disclosure have been described using specific terms, this description is merely an exemplification for facilitating understanding and does not limit the present disclosure or the scope of the claims. The scope of the present invention is defined by the scope of the claims. Also, not only the embodiments but also the embodiments, examples, and modifications not described here are included in the scope of the present invention.

[0080] (Supplementary Note) The technology disclosed in this specification is defined as follows in one aspect.

[0081] (Item 1) An input terminal, An output terminal, A power transistor connected between the input terminal and the output terminal, A current detection circuit that generates a current detection signal indicating the current flowing through the power transistor, According to the control signal, turn on and off the power transistor, and when the power transistor is in the on state, adjust the gate voltage of the power transistor so that the current detection signal does not exceed a current limit level that has a positive correlation with the output voltage generated at the output terminal, a controller circuit; A semiconductor switch comprising.

[0082] (Item 2) The semiconductor switch according to item 1, wherein the current limit level changes linearly with respect to the output voltage.

[0083] (Item 3) The semiconductor switch according to item 1 or 2, wherein the current limit level is the lower of a voltage detection signal based on the output voltage and a reference signal having a predetermined voltage level.

[0084] (Item 4) The controller circuit is A voltage dividing circuit that divides the output voltage and generates a voltage detection signal; A gate voltage generation circuit that applies the gate voltage of a high level or a low level to the gate of the power transistor according to the control signal; A current limit circuit that adjusts the gate voltage of the high level so that the current detection signal does not exceed the current limit level based on the voltage detection signal; The semiconductor switch according to any one of items 1 to 3, including.

[0085] (Item 5) The gate voltage generation circuit is A voltage source that generates a high level voltage corresponding to the high level; A driver that applies the gate voltage corresponding to the high level voltage to the gate of the power transistor; Including The semiconductor switch according to item 4, wherein the current limit circuit adjusts the high level voltage generated by the voltage source so that the current detection signal does not exceed the current limit level.

[0086] (Item 6) The power transistor is of N-type, The current limiting circuit is a shunt regulator that extracts a current corresponding to the error between the current detection signal and the current limit level from the output of the voltage source, the semiconductor switch according to Item 5.

[0087] (Item 7) The shunt regulator, a shunt transistor, an operational amplifier having three input nodes that receive the voltage detection signal, the reference signal, and the current detection signal, and an output node connected to the gate of the shunt transistor, comprising the semiconductor switch according to Item 6.

[0088] (Item 8) The operational amplifier has an offset, the semiconductor switch according to Item 7.

[0089] (Item 9) The power transistor is of N-type, The voltage source is a charge pump circuit, the semiconductor switch according to Item 5.

[0090] (Item 10) The current detection circuit, a replica transistor of the same type as the power transistor having a first end connected to the input terminal and a gate connected to the gate of the power transistor, a regulator that adjusts the voltage at the second end of the replica transistor to be equal to the voltage at the corresponding terminal of the power transistor, a current sense resistor connected between the second end of the replica transistor and ground, comprising, the voltage drop across the current sense resistor being the current detection signal, the semiconductor switch according to any one of Items 1 to 9.

[0091] (Item 11) The power transistor and the replica transistor are each composed of two transistors of the same type connected in inverse series, as described in item 10 of the semiconductor switch.

[0092] (Item 12) The power transistor is P-type, as described in any one of items 1 to 8 of the semiconductor switch.

Explanation of symbols

[0093] 100 Semiconductor switch IN Input pin OUT Output pin CNT Control pin 110 Power transistor 112 First transistor 114 Second transistor V CS Current detection signal V ILIM Current limit level 120 Current detection circuit 122 Replica transistor 124 Regulator 125 Transistor 126 Error amplifier 128 Current sense resistor 130 Controller circuit 132 Voltage dividing circuit 140 Gate voltage generation circuit 142 Voltage source 144 Driver 150 Current limit circuit 152 Shunt transistor 154 Error amplifier 156 Enable switch

Claims

1. An input terminal, An output terminal, A power transistor connected between the input terminal and the output terminal, A current detection circuit that generates a current detection signal indicating the current flowing through the power transistor, A controller circuit that switches the power transistor on and off according to a control signal, and adjusts the gate voltage of the power transistor so that, when the power transistor is in the on state, the current detection signal does not exceed a current limit level having a positive correlation with the output voltage generated at the output terminal, A semiconductor switch comprising the above.

2. The semiconductor switch according to claim 1, wherein the current limit level changes linearly with respect to the output voltage.

3. The semiconductor switch according to claim 1 or 2, wherein the current limit level is the lower of a voltage detection signal based on the output voltage and a reference signal having a predetermined voltage level.

4. The controller circuit A voltage dividing circuit that divides the output voltage to generate a voltage detection signal, A gate voltage generation circuit that applies the gate voltage of a high level or a low level to the gate of the power transistor according to the control signal, A current limit circuit that adjusts the gate voltage of the high level so that the current detection signal does not exceed the current limit level based on the voltage detection signal, The semiconductor switch according to claim 1 or 2, including the above.

5. The gate voltage generation circuit A voltage source that generates a high level voltage corresponding to the high level, A driver that applies the gate voltage corresponding to the high level voltage to the gate of the power transistor, Including The semiconductor switch according to claim 4, wherein the current limit circuit adjusts the high level voltage generated by the voltage source so that the current detection signal does not exceed the current limit level.

6. The power transistor is of N type, The semiconductor switch according to claim 5, wherein the current limit circuit is a shunt regulator that extracts a current corresponding to the error between the current detection signal and the current limit level from the output of the voltage source.

7. The shunt regulator A shunt transistor, An operational amplifier having three input nodes that receive the voltage detection signal, a reference signal, and the current detection signal, and an output node connected to the gate of the shunt transistor, The semiconductor switch according to claim 6, including the above.

8. The operational amplifier has an offset, the semiconductor switch according to claim 7.

9. The power transistor is N-type, The voltage source is a charge pump circuit, the semiconductor switch according to claim 5.

10. The current detection circuit A replica transistor of the same type as the power transistor, having a first end connected to the input terminal and a gate connected to the gate of the power transistor, A regulator that adjusts the voltage at the second end of the replica transistor to be equal to the voltage at the corresponding terminal of the power transistor, A current sense resistor connected between the second end of the replica transistor and ground, The semiconductor switch according to claim 1 or 2, comprising a voltage drop across the current sense resistor being the current detection signal.

11. The semiconductor switch according to claim 10, wherein the power transistor and the replica transistor are each composed of two transistors of the same type connected in inverse series.

12. The power transistor is P-type, the semiconductor switch according to claim 1 or 2.

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