Power semiconductor element and power conversion device including the same

Abstract

To provide a power semiconductor element, a power conversion device including the element, and a method for manufacturing the power semiconductor element by which the electric field concentrated at the trench corner is dispersed, the breakdown voltage drop of the gate insulating layer is prevented, and the reliability of the gate dielectric layer is improved.SOLUTION: A power semiconductor element 105 includes a substrate, a first epitaxial layer 111 of first conductivity type arranged on the substrate, a second epitaxial layer 112 of first conductivity type arranged on the first epitaxial layer of first conductivity type, a first well 121 of second conductivity type spaced apart on the second epitaxial layer of first conductivity type, and an ion implantation coupling region 126 of second conductivity type that connects the third well 124b of the second conductivity arranged on the second epitaxial layer of first conductivity type provided below the first well of second conductivity type with the first well of second conductivity type and the third well of second conductivity type.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The embodiments relate to a power semiconductor device, a power semiconductor module, a power conversion device, and a method for manufacturing the same.

Background Art

[0002] Power semiconductors are one of the core elements that determine the efficiency, speed, durability, and reliability of power electronic systems.

[0003] Recently, with the development of the power electronics industry, the silicon (Si) power semiconductors used in the past have reached their physical limits, and research on wide-bandgap power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace them has been actively conducted.

[0004] Wide-bandgap power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, thereby having characteristics such as a low intrinsic carrier concentration, a high breakdown electric field (about 4 to 20 times), a high thermal conductivity (about 3 to 13 times), and a high electron saturation velocity (about 2 to 2.5 times).

[0005] Due to such characteristics, they can operate in high-temperature and high-voltage environments and have a high switching speed and low switching loss. Among them, gallium nitride (GaN) power semiconductor devices can be used in low-voltage systems, and silicon carbide (SiC) power semiconductor devices are suitable for high-voltage systems.

[0006] Conventional SiC MOSFET power semiconductors are generally denoted as VDMOSFET in a vertical diffused structure and can also be simply denoted as double-diffused structure DMOSFET. In addition, SiC MOSFETs can be classified into planar MOSFETs and trench MOSFETs according to the channel direction.

[0007] Among these, the trench MOSFET has a structure in which a channel is formed on the sidewall of the trench. For this purpose, a gate insulating film is formed on the sidewall of the trench, and a gate electrode is formed in the trench.

[0008] The SiC MOSFET has a high on-resistance (R on ) due to its low channel mobility and large channel resistance. Therefore, a trench MOSFET has been proposed to reduce this. The trench MOSFET has the advantage of increasing the channel density by forming a channel on the sidewall of the trench.

[0009] However, the trench MOSFET has a larger electric field in the trench gate oxide with a shorter drift distance than the P-base (P-well), and the electric field particularly concentrates at the end portion of the trench. Therefore, there is a problem that the breakdown of the gate oxide occurs early and the breakdown voltage (BV) decreases.

[0010] For example, in the case of a SiC trench MOSFET, since the breakdown electric field strength is 10 times that of silicon (Si), the SiC semiconductor device is used in a state where a voltage nearly 10 times that of the Si device is applied. For this reason, an electric field 10 times the strength of the silicon device is applied to the gate insulating film formed in the trench, and there is a problem that the gate insulating film is easily broken at the corner portion of the trench.

[0011] In internal technology, research has been conducted to place a bottom P-well under the trench in order to prevent electric field concentration at the trench corner portion of the SiC trench MOSFET.

[0012] However, even if the bottom P-well for preventing electric field concentration at the trench corner portion contributes to preventing the breakdown voltage drop, a technical contradiction occurs in that the on-resistance (R on ) increases due to the bottom P-well.

Summary of the Invention

Problems to be Solved by the Invention

[0013] One of the technical problems of the embodiment is to solve the technical contradiction between preventing the breakdown voltage drop by preventing the electric field concentration in the trench corner portion and increasing the on-resistance (R on ).

[0014] For example, the embodiment is to prevent the bottom P-well from increasing the on-resistance while preventing the electric field concentration in the trench corner portion.

[0015] The technical problems of the embodiment are not limited to those described in this item, and include those that can be grasped from the description of the invention.

Means for Solving the Problems

[0016] The power semiconductor device according to the embodiment may include a substrate, a first epitaxial layer of a first conductivity type disposed on the substrate, a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer of the first conductivity type, a first well of a second conductivity type disposed separately from the second epitaxial layer of the first conductivity type, a third well of the second conductivity type disposed in the second epitaxial layer of the first conductivity type provided under the separated first well of the second conductivity type, and an ion implantation connection region of the second conductivity type connecting the first well of the second conductivity type and the third well of the second conductivity type.

[0017] Further, the power semiconductor device according to the embodiment includes a substrate 111, a first epitaxial layer 111 of a first conductivity type disposed on the substrate 111, a second epitaxial layer 112 of the first conductivity type disposed on the first epitaxial layer 111 of the first conductivity type, a first well 121 of a second conductivity type spaced apart from the second epitaxial layer 112 of the first conductivity type, a source region 141 of the first conductivity type disposed on the first well 121 of the second conductivity type, a second gate insulating layer 131b disposed on the source region 141 of the first conductivity type, the first well 121 of the second conductivity type, and the second epitaxial layer 112 of the first conductivity type, a second gate 132b disposed on the second gate insulating layer 131b, a third well 124b of the second conductivity type disposed in the second epitaxial layer 112 of the first conductivity type below between the spaced-apart first wells 121 of the second conductivity type, and a second conductivity type ion implantation connection region 126 connecting the first well 121 of the second conductivity type and the third well 124b of the second conductivity type.

[0018] When a ground potential is applied to the first well 121 of the second conductivity type, the ground potential is also applied to the third well 124b of the second conductivity type by the second conductivity type ion implantation connection region 126.

[0019] The horizontal width of the third well 124b of the second conductivity type may be equal to or greater than the distance between the adjacent first wells 121 of the second conductivity type.

[0020] The third well 124b of the second conductivity type is disposed below a region provided between the spaced-apart first wells 121 of the second conductivity type, and the second gate is disposed in a continuous form along the region.

[0021] The third well 124b of the second conductivity type is disposed to extend in a first direction Y that is horizontal in a first direction Y which is the extending direction of the second gate 132b.

[0022] The second conductivity type ion implantation connection region 126 is disposed to extend in a second direction X that is perpendicular to a first direction Y which is the extending direction of the second gate 132b.

[0023] The second-conductivity-type ion implantation connection region 126 is arranged horizontally in the first direction Y while being separated in the first direction Y, and connects the third well 124b of the second conductivity type arranged horizontally in the first direction Y, and is arranged to extend in the second direction X perpendicular to the first direction Y.

[0024] The second-conductivity-type ion implantation connection region 126 can include a first ion implantation connection region 126a of the second conductivity type that connects the third well 124b of the second conductivity type arranged below the second gate 132b in the first cell region and the third well 124b of the second conductivity type arranged below the second gate 132b in the third cell region adjacent to the positive direction of the X axis in the first cell region.

[0025] The first ion implantation connection region 126a of the second conductivity type can connect the third well 124b of the second conductivity type in the first cell region and the third well 124b of the second conductivity type in the third cell region to the first well 121 of the second conductivity type on the upper side.

[0026] The second-conductivity-type ion implantation connection region 126 can include a second ion implantation connection region 126b of the second conductivity type that connects the third well 124b of the second conductivity type arranged below the second gate 132b in the second cell region and the third well 124b of the second conductivity type arranged below the second gate 132b in the fourth cell region adjacent to the negative (-) direction of the X axis in the second cell region.

[0027] The second ion implantation connection region 126b of the second conductivity type can connect the third well 124b of the second conductivity type in the second cell region and the third well 124b of the second conductivity type in the fourth cell region to the first well 121 of the second conductivity type on the upper side.

[0028] Also, the power conversion device according to the embodiment can include any one of the power semiconductor elements.

Advantages of the Invention

[0029] According to the power semiconductor device according to the embodiment, the power conversion device including the same, and the method of manufacturing the power semiconductor device, while preventing electric field concentration at the trench corner portion, the on-resistance (R on ) can be increased or there is a technical effect that can solve the problem of adversely affecting the electrical characteristics of the power semiconductor device.

[0030] For example, according to the embodiment, the second well 124 of the second conductivity type is disposed below the trench and is disposed in a continuous form along the trench region, thereby dispersing the electric field concentrated at the trench corner and preventing the breakdown voltage drop of the gate insulating layer, and having a technical effect of improving the reliability of the gate insulating layer.

[0031] Further, according to the embodiment, the ion implantation connection region 126 of the second conductivity type can connect the second well 124 of the second conductivity type and the first well 121 of the second conductivity type. Thereby, the first well 121 of the second conductivity type to which the ground potential is applied is connected to the second well 124 of the second conductivity type by the ion implantation connection region 126 of the second conductivity type, so that the ground potential is also applied to the second well 124 of the second conductivity type.

[0032] Further, according to the embodiment, since the second well 124 of the second conductivity type does not directly contact the bottom surface of the gate trench, when performing the thermal oxidation process for forming the gate insulating film, there is an advantage that the risk of forming an unexpectedly grown oxide in the thickness and characteristics of the gate insulating film is small.

[0033] Further, according to the embodiment, by applying a ground potential to the second well 124 of the second conductivity type that prevents electric field concentration at the trench corner, the generation of a depletion region in the second well 124 of the second conductivity type can be prevented, and there is a combined technical effect that an increase in the on-resistance (R on ) can also be prevented.

[0034] Also, according to the second embodiment, the first well 121 of the second conductivity type to which the ground potential is applied is connected to the third well 124b of the second conductivity type by the ion implantation connection region 126 of the second conductivity type, so that the third well 124b of the second conductivity type is also applied with the ground potential. As a result, there is a combined technical effect that an increase in the on-resistance (R on ) can also be prevented by applying the ground potential to the third well 124b of the second conductivity type that prevents electric field concentration.

[0035] Also, according to the third embodiment, there is a combined technical effect that the first ion implantation connection region 126a of the second conductivity type or the second ion implantation connection region 126b of the second conductivity type is arranged only on one side or a part of the other side below the second gate 132b of each cell, and the flow of current can be improved.

[0036] The technical effects of the embodiments are not limited to those described in this item, and include those that can be grasped from the description of the invention.

Brief Description of Drawings

[0037]

Figure 1

Figure 2

Figure 3

Figure 4a

Figure 4b

Figure 5

Figure 6a

Figure 6b

Figure 7a

Figure 7b

[0038] Hereinafter, with reference to the drawings, the invention according to the embodiment for solving the above problems will be described in more detail.

[0039] In the following description, the suffixes "module" and "section" for the components are merely given for facilitating the preparation of the specification, and do not give any particularly important meaning or role by themselves. Therefore, the "module" and "section" can be used interchangeably.

[0040] Terms including ordinal numbers such as first, second, etc. can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

[0041] The singular expressions include plural expressions unless the context clearly indicates otherwise.

[0042] In the present application, terms such as "including", "having" or "comprising" are intended to specify the presence of the features, numbers, steps, operations, components, parts or combinations thereof described in the specification, and should be understood not to preclude the presence or addition possibility of one or more other features, numbers, steps, operations, components, parts or combinations thereof in advance.

[0043] (Embodiment) FIG. 1 is a configuration example diagram of a power conversion device 1000 according to an embodiment.

[0044] The power conversion device 1000 according to the embodiment can receive a DC power supply from a battery or a fuel cell and convert it into an AC power supply, and can supply the AC power supply to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive a DC power supply from a battery, convert it into a three-phase AC power supply, and supply it to the motor M. The motor M can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0045] The power conversion device 1000 according to the embodiment can include a power semiconductor element 100. The power semiconductor element 100 is a MOSFET, but is not limited thereto, and can include an IGBT (Insulated Gate Bipolar Transistor).

[0046] For example, the power conversion device 1000 can include a plurality of power semiconductor elements 100a, 100b, 100c, 100d, 100e, 100f, and can include a plurality of diodes (not shown). Each of the plurality of diodes may be internally present in the form of an internal diode in the power semiconductor elements 100a, 100b, 100c, 100d, 100e, 100f respectively, but is not limited thereto, and may be separately arranged.

[0047] The embodiment can convert a DC power supply into an AC power supply by on / off control of a plurality of power semiconductor elements 100a to 100f. For example, the power conversion device 1000 according to the embodiment can turn on the first power semiconductor element 100a and turn off the second power semiconductor element 100b in the first period of one cycle to supply a positive-polarity power supply to the motor M, and turn off the first power semiconductor element 100a and turn on the second power semiconductor element 100b in the second period of one cycle to supply a negative-polarity power supply to the motor M.

[0048] In an embodiment, a group of power semiconductor devices arranged in series between a high-voltage line and a low-voltage line on the input side can be referred to as an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b form the first arm, the third power semiconductor device 100c and the fourth power semiconductor device 100d form the second arm, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f can form the third arm.

[0049] The upper and lower power semiconductor devices in the arm are controlled so as not to be turned on simultaneously. For example, in the first arm, the first power semiconductor device 100a and the second power semiconductor device 100b are not turned on simultaneously and can be turned on and off alternately.

[0050] Each of the power semiconductor devices 100a to 100f receives high power in the off state. For example, when the first power semiconductor device 100a is on and the second power semiconductor device 100b is off, the input voltage is directly applied to the second power semiconductor device 100b. The voltage input to the second power semiconductor device 100b is a relatively high voltage, and the breakdown voltages of the power semiconductor devices 100a to 100f are designed to a high level so as to withstand such a high voltage.

[0051] Each of the power semiconductor devices 100a to 100f can conduct a high current in the on state. The motor M is driven by a relatively high current, and such a high current is supplied to the motor M through the power semiconductor that is on.

[0052] The high voltage applied to each of the power semiconductor devices 100a to 100f can induce high switching losses. The high current flowing through the power semiconductor devices 100a to 100f can induce high conduction losses. In order to dissipate the heat generated by such losses, the power semiconductor devices 100a to 100f may be packaged in a power semiconductor module including a heat dissipation means.

[0053] The power semiconductor device 100 of the embodiment may be a silicon carbide (SiC) power semiconductor device, which can operate in a high-temperature and high-voltage environment and can have a high switching speed and low switching losses.

[0054] On the other hand, the power conversion device 1000 according to the embodiment may include a plurality of power semiconductor modules.

[0055] For example, a plurality of power semiconductor devices 100a to 100f illustrated in FIG. 1 may be packaged in one power semiconductor module, or the power semiconductor devices constituting each arm may be packaged in one power semiconductor module.

[0056] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, the fifth power semiconductor device 100e, and the sixth power semiconductor device 100f illustrated in FIG. 1 may be packaged in one power semiconductor module.

[0057] In addition, additional power semiconductor devices arranged in parallel with each of the power semiconductor devices 100a to 100f may further exist to increase the current capacity. In this case, the number of power semiconductor devices included in the power semiconductor module may be more than six.

[0058] The power conversion device 1000 according to the embodiment may also include power semiconductor devices in the form of diodes in addition to the power semiconductor devices 100a to 100f in the form of transistors. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor device 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor device 100b. And such diodes may also be packaged together in one power semiconductor module. Further, the diodes may be arranged in the form of internal diodes in each power semiconductor device.

[0059] Next, the power semiconductor elements constituting each arm may be packaged in one power semiconductor module.

[0060] For example, the first power semiconductor element 100a and the second power semiconductor element 100b constituting the first arm may be packaged in the first power semiconductor module, the third power semiconductor element 100c and the fourth power semiconductor element 100d constituting the second arm may be packaged in the second power semiconductor module, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f constituting the third arm may be packaged in the third power semiconductor module.

[0061] In addition, there may further be additional power semiconductor elements arranged in parallel with each of the power semiconductor elements 100a to 100f to increase the current capacity. In this case, the number of power semiconductor elements included in each power semiconductor module may be more than two. And each arm may further include a diode-type power semiconductor element (not shown) in addition to the transistor-type power semiconductor elements 100a to 100f, and such a diode may also be packaged together in one power semiconductor module. Also, the diode may be arranged in the form of an internal diode in each power semiconductor element.

[0062] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor elements 100 according to the embodiment.

[0063] The power semiconductor element 100 according to the embodiment may include a source electrode 140 spaced apart above a predetermined semiconductor epitaxial layer 110E, a gate electrode 130, and a drain electrode 160 disposed below the semiconductor epitaxial layer 110E.

[0064] In the form of a MOSFET, the source electrode 140 or the gate electrode 130 may include an Al-based metal and may include a Ni layer, a Ti layer, a Ni / Ti layer, or a TiN / Ti silicide layer.

[0065] The drain electrode 160 can contain a Ni-based metal and can include a Ti layer, a Ni layer, and an Ag layer. For example, the drain electrode 160 can include, but is not limited to, Ti / Ag, Ti / Ni / Ag, NiV / Ag, V (vanadium) / Ni / Ag, etc.

[0066] One of the technical problems of the embodiment is to solve the technical contradiction of preventing the breakdown voltage drop by preventing the electric field concentration at the trench corner and increasing the on-resistance (R on ).

[0067] Hereinafter, the technical features of the power semiconductor device according to the embodiment for solving the above technical problems will be described.

[0068] FIG. 3 is a three-dimensional cross-sectional view of a power semiconductor device 101 according to the first embodiment.

[0069] FIGS. 4A and 4B are cross-sectional views taken along lines A-A' and B-B' of the power semiconductor device 101 illustrated in FIG. 3, respectively. Hereinafter, the "first embodiment" may be described simply as the "embodiment".

[0070] Referring to FIGS. 3, 4A, and 4B, the power semiconductor device 101 according to the first embodiment can include one or more of a drain electrode 160 (see FIG. 4A), an epi layer 110E, a second-conductivity-type first well 121, a first-conductivity-type source region 141, a source contact region 142 (see FIG. 4A), a second-conductivity-type contact region 123 (see FIG. 4B), a source electrode 140 (see FIG. 4A), a gate insulating layer 131, a trench gate 132, and an interlayer insulating layer 150 (see FIG. 4A).

[0071] The epi layer 110E can include a first-conductivity-type first epi layer 111 and a first-conductivity-type second epi layer 112.

[0072] In addition, the embodiment can include a second-conductivity-type first well 121, a second-conductivity-type second well 124, and a second-conductivity-type ion implantation connection region 126.

[0073] The first conductivity type may be N-type, and the second conductivity type may be P-type, but is not limited thereto. For example, as the N-type dopant, N, P, etc. may be implanted, but is not limited thereto. Also, as the P-type dopant, Al, boron, etc. may be implanted, but is not limited thereto.

[0074] Specifically, referring to FIGS. 4a and 4b, the power semiconductor device 101 according to the first embodiment may include a first epi-layer 111 of the first conductivity type and a second epi-layer 112 of the first conductivity type disposed on the first epi-layer 111 of the first conductivity type.

[0075] The first epi-layer 112 of the first conductivity type and the second epi-layer 112 of the first conductivity type may contain SiC (Silicon Carbide) and may be doped with N-type, but is not limited thereto. For example, the first and second epi-layers 111 and 112 of the first conductivity type may contain a 4H-SiC material, but is not limited thereto. For example, the first and second epi-layers 111 and 112 of the first conductivity type may contain 3C-SiC or 6H-SiC.

[0076] The first epi-layer 111 of the first conductivity type may include a first conductivity type buffer layer (not shown) and a first conductivity type drift layer (not shown). By doping the first epi-layer 111 of the first conductivity type at a lower concentration than the second epi-layer 112 of the first conductivity type, the breakdown voltage (VB) drop can be prevented.

[0077] Also, by doping the second epi-layer 112 of the first conductivity type at a higher concentration than the first epi-layer 111 of the first conductivity type, the on-resistance can be reduced by functioning as a current spreading layer (CSL).

[0078] The first well 121 of the second conductivity type can be formed by ion implantation of dopants of the second conductivity type or growth of an epitaxial layer of the second conductivity type in the second epitaxial layer 112 of the first conductivity type. The first well 121 of the second conductivity type can be referred to as a second conductivity type base layer, but is not limited thereto.

[0079] Referring to FIG. 4b, the source region 141 of the first conductivity type and the contact region 123 of the second conductivity type can be formed in the first well 121 of the second conductivity type by ion implantation.

[0080] The doping concentrations of the source region 141 of the first conductivity type and the contact region 123 of the second conductivity type may be higher than those of the first well 121 of the second conductivity type. The contact region 123 of the second conductivity type may be partially formed as shown in FIG. 3. The contact region 123 of the second conductivity type can function to maintain the zero potential of the first well 121 of the second conductivity type.

[0081] Next, the gate insulating layer 131 can be formed on the bottom and sidewalls of the trench region where a part of the source region 141 of the first conductivity type, the first well 121 of the second conductivity type, and the second epitaxial layer 112 of the first conductivity type are removed by a thermal oxidation or vapor deposition process.

[0082] Next, the trench gate 132 can be formed in the trench on the gate insulating layer 131 by a polysilicon vapor deposition process and an etch-back process.

[0083] Next, the source contact region 142 may be formed with the source region 141 of the first conductivity type and / or the contact region 123 of the second conductivity type. For example, the source contact region 142 can be formed using Ti, Ni, etc., but is not limited thereto.

[0084] Next, the interlayer insulating layer 150 can be formed on the trench gate 132 by a vapor deposition process such as an oxide film.

[0085] Next, a source electrode 140, a gate electrode (not shown), and a drain electrode 160 are formed.

[0086] For example, the source electrode 140 or the gate electrode 130 can include an Al-based metal and can include a Ni layer, a Ti layer, a Ni / Ti layer, or a TiN / Ti silicide layer. Further, the drain electrode 160 can include a Ni-based metal and can include a Ti layer, a Ni layer, and an Ag layer. For example, the drain electrode 160 can include Ti / Ag, Ti / Ni / Ag, or NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.

[0087] Next, referring to FIG. 4B, the embodiment can include a second well 124 of a second conductivity type that is disposed on the second epitaxial layer 112 of the first conductivity type and is spaced apart from the gate insulating layer 131 and the first well 121 of the second conductivity type. Further, the embodiment may include a second conductivity type ion implantation connection region 126 that connects the first well 121 of the second conductivity type and the second well 124 of the second conductivity type.

[0088] The second well 124 of the second conductivity type is disposed below the trench and may be doped at a concentration below that of the second well 124 of the second conductivity type, but is not limited thereto.

[0089] The second conductivity type ion implantation connection region 126 may be doped at a concentration lower than that of the second well 124 of the second conductivity type, but is not limited thereto.

[0090] Referring to FIG. 3, the second well 124 of the second conductivity type is disposed below the trench and is disposed in a continuous form along the trench region.

[0091] The second well 124 of the second conductivity type can be formed by high-energy ion implantation or by utilizing a re-growth process. For example, after growing a second epitaxial layer 112 of the first conductivity type on the first epitaxial layer 111 of the first conductivity type, the second well 124 of the second conductivity type can be formed by high-energy ion implantation. Alternatively, after forming the first epitaxial layer 111 of the first conductivity type, the second well 124 of the second conductivity type can be formed by ion implantation, and then the second epitaxial layer 112 of the first conductivity type can be formed.

[0092] The second well 124 of the second conductivity type is arranged to extend in a first direction Y that is horizontal with respect to a first direction Y which is the extending direction of the trench gate 132.

[0093] On the contrary, the ion implantation connection region 126 of the second conductivity type is arranged to extend in a second direction X that is perpendicular to the first direction Y which is the extending direction of the trench gate 132.

[0094] The ion implantation connection region 126 of the second conductivity type connects the second well 124 of the second conductivity type that is horizontally arranged in the first direction Y while being spaced apart in the first direction Y, and is arranged to extend in a second direction X that is perpendicular to the first direction Y.

[0095] The upper end of the ion implantation connection region 126 of the second conductivity type is arranged higher than the lower end of the gate insulating layer 131, and the lower end of the ion implantation connection region 126 of the second conductivity type is arranged lower than the lower end of the gate insulating layer 131.

[0096] According to the power semiconductor device according to the embodiment, the power conversion device including the same, and the method for manufacturing the power semiconductor device, there is a technical effect of being able to solve the problem that the on-resistance (R on ) increases or the problem that it will have an adverse effect on the electrical characteristics of the power semiconductor device while preventing electric field concentration at the trench corner portion.

[0097] For example, according to the embodiment, a second well 124 of a second conductivity type is disposed below the trench and disposed in a continuous form along the trench region, thereby dispersing the electric field concentrated at the trench corner and preventing the breakdown voltage drop of the gate insulating layer, and having a technical effect of improving the reliability of the gate insulating layer.

[0098] Also, according to the embodiment, an ion implantation connection region 126 of a second conductivity type can connect the second well 124 of the second conductivity type and the first well 121 of the second conductivity type. As a result, the first well 121 of the second conductivity type to which the ground potential is applied is connected to the second well 124 of the second conductivity type by the ion implantation connection region 126 of the second conductivity type, so that the second well 124 of the second conductivity type is also applied with the ground potential.

[0099] Also, according to the embodiment, since the second well 124 of the second conductivity type does not directly contact the bottom surface of the gate trench, when performing a thermal oxidation process for forming a gate insulating film, there is an advantage that the risk of forming an unexpectedly grown oxide on the gate insulating film in terms of thickness and characteristics side is small.

[0100] On the other hand, in the internal technology, research has been conducted to dispose a bottom P-well below the trench in order to prevent electric field concentration at the trench corner portion.

[0101] First, using the first internal technology, a floating "floating bottom P-well" separated from the trench gate and the gate insulating layer was formed.

[0102] Such a "floating bottom P-well" has an effect of relaxing the electric field concentration at the trench corner portion and preventing the breakdown voltage drop, but it has been studied that charging and discharging continuously occur inside the floating bottom P-well, and the potential around the floating bottom P-well is affected.

[0103] That is, in addition to the externally applied potential applied to the floating lower P-well, a problem has been studied in which an unknown internal potential is generated, which affects the electrical characteristics of the power semiconductor device.

[0104] Also, the floating lower P-well has a problem that it obstructs the flow of current in the on state and increases the on-resistance (R on / RDS), which is the drain-source resistance.

[0105] Next, in the second internal technique, a "contact bottom P-well" was formed below the trench so as to be in contact with the trench gate insulating layer.

[0106] By the way, when forming a "contacted lower P-well" at the bottom of the trench so as to be in contact with the trench gate insulating layer, although there is an effect of alleviating the electric field concentration at the trench corner, a problem has been studied in which the forward current characteristics deteriorate due to an increase in the width of the depletion layer in the "contacted lower P-well" in contact with the gate insulating layer by the drain voltage.

[0107] Also, when forming a "contacted lower P-well" near the P-base (P-well) so as to be in contact with the trench gate insulating layer, a JFET resistance is generated between the P-base (P-well) and the contacted lower P-well, and the on-resistance (R on ) increases, and this problem has been studied.

[0108] On the contrary, referring to FIGS. 3 and 4b, in the embodiment, the ion implantation connection region 126 of the second conductivity type can connect the second well 124 of the second conductivity type and the first well 121 of the second conductivity type. Thereby, the first well 121 of the second conductivity type to which the ground potential is applied is connected to the second well 124 of the second conductivity type by the ion implantation connection region 126 of the second conductivity type, so that the ground potential is also applied to the second well 124 of the second conductivity type.

[0109] Therefore, according to the embodiment, by applying a ground potential to the second well 124 of the second conductivity type that prevents the electric field concentration at the trench corner, it is possible to prevent the generation of a depletion region in the second well 124 of the second conductivity type, and there is a composite technical effect that can also prevent the increase in the on-resistance (R on ).

[0110] Next, FIG. 5 is a three-dimensional cross-sectional view of the power semiconductor device 105 according to the second embodiment.

[0111] FIGS. 6A and 6B are cross-sectional views along the lines A-A' and B-B' of the power semiconductor device 105 illustrated in FIG. 5, respectively.

[0112] The second embodiment is a planar MOSFET structure, and the technical features of the first embodiment described above can be adopted. Hereinafter, the description will focus on the features of the second embodiment.

[0113] Referring to FIGS. 5, 6A, and 6B, the power semiconductor device 101 according to the second embodiment may include a drain electrode 160 (see FIG. 6A), a substrate 111, an epi layer 110E, a first well 121 of the second conductivity type, a source region 141 of the first conductivity type, a source contact region 142 (see FIG. 6A), a contact region 123 of the second conductivity type (see FIG. 6B), a source electrode 140 (see FIG. 6A), a gate insulating layer 131, a trench gate 132, and an interlayer insulating layer 150 (see FIG. 6A).

[0114] The epi layer 110E may include a first epi layer 111 of the first conductivity type and a second epi layer 112 of the first conductivity type.

[0115] In addition, the second embodiment may include a first well 121 of the second conductivity type, a second well 124 of the second conductivity type, and an ion implantation connection region 126 of the second conductivity type.

[0116] In the second embodiment, the second gate insulating layer 131b can be formed on the first conductivity type source region 141, the first well 121 of the second conductivity type, and the second epi-layer 112 of the first conductivity type by a thermal oxidation or vapor deposition process.

[0117] Also, the second gate 132b can be formed on the second gate insulating layer 131b by a polysilicon vapor deposition process.

[0118] Next, referring to FIGS. 5 and 6b, the second embodiment can include a third well 124b of the second conductivity type disposed in the second epi-layer 112 of the first conductivity type below the spaced-apart first wells 121 of the second conductivity type. Also, the second embodiment can include an ion implantation connection region 126 of the second conductivity type that connects the first well 121 of the second conductivity type and the third well 124b of the second conductivity type.

[0119] The third well 124b of the second conductivity type is disposed below the spaced-apart first wells 121 of the second conductivity type.

[0120] The horizontal width of the third well 124b of the second conductivity type may be formed to be equal to or greater than the distance between the first wells 121 of the second conductivity type, which is the width of the JFET.

[0121] Referring to FIG. 5, the third well 124b of the second conductivity type is disposed below the region between the spaced-apart first wells 121 of the second conductivity type, and the second gate is disposed in a continuous form along the region.

[0122] The third well 124b of the second conductivity type is extended and disposed in the first direction Y so as to be horizontal in the first direction Y, which is the extending direction of the second gate 132b.

[0123] On the contrary, the ion implantation connection region 126 of the second conductivity type is extended and disposed in the second direction X, which is perpendicular to the first direction Y, which is the extending direction of the second gate 132b.

[0124] The second-conductivity-type ion implantation connection region 126 connects the second-conductivity-type third well 124b that is horizontally arranged in the first direction Y while being spaced apart in the first direction Y, and is arranged to extend in the second direction X perpendicular to the first direction Y.

[0125] According to the second embodiment, by arranging the second-conductivity-type third well 124b, which is a JFET region, below the region between the second-conductivity-type first wells 121, there is a technical effect of dispersing the electric field concentrated at the corners of the second-conductivity-type first wells 121.

[0126] Also, according to the second embodiment, since the second-conductivity-type first well 121 to which the ground potential is applied is connected to the second-conductivity-type third well 124b by the second-conductivity-type ion implantation connection region 126, the ground potential is also applied to the second-conductivity-type third well 124b.

[0127] As a result, by applying the ground potential to the second-conductivity-type third well 124b that prevents electric field concentration, there is a combined technical effect that can also prevent an increase in the on-resistance (R on ).

[0128] Next, FIGS. 7a and 7b are cross-sectional views of the power semiconductor device 106 according to the third embodiment, respectively.

[0129] The third embodiment can adopt the technical features of the first embodiment or the second embodiment described above, and the following description will focus on the features of the third embodiment.

[0130] Different from the second embodiment, the third embodiment can include a second-conductivity-type first ion implantation connection region 126a and a second-conductivity-type second ion implantation connection region 126b.

[0131] For example, in the second embodiment, the second-conductivity-type ion implantation connection region 126 has a stripe structure and continuously connects the second-conductivity-type third wells 124b of adjacent cells (see FIG. 5).

[0132] On the other hand, in the third embodiment, a structure is formed in which the first ion implantation connection region 126a of the second conductivity type or the second ion implantation connection region 126b of the second conductivity type intersects in cell units and connects the third well 124b of the second conductivity type.

[0133] For example, FIGS. 7a and 7b are cross-sectional views of the first cell region and the second cell region of the power semiconductor device 106 according to the third embodiment.

[0134] For example, referring to FIG. 7a, in the first cell region, the first ion implantation connection region 126a of the second conductivity type can connect the third well 124b of the second conductivity type and the first well 121 of the second conductivity type while being disposed on one side, for example, the left side, of the second gate 132b.

[0135] For example, the first ion implantation connection region 126a of the second conductivity type is disposed below between the second gate 132b in the first cell region and the second gate 132b in the third cell region adjacent to the positive (+) direction of the X axis in the first cell region.

[0136] At this time, the first ion implantation connection region 126a of the second conductivity type can connect the third well 124b of the second conductivity type disposed below the second gate 132b in the first cell region and the third well 124b of the second conductivity type disposed below the second gate 132b in the third cell region adjacent to the positive direction of the X axis in the first cell region.

[0137] Further, the first ion implantation connection region 126a of the second conductivity type can connect the third well 124b of the second conductivity type in the first cell region and the third well 124b of the second conductivity type in the third cell region to the first well 121 of the second conductivity type on the upper side.

[0138] Also, referring to FIG. 7b, in the second cell region, the second ion implantation connection region 126b of the second conductivity type can connect the third well 124b of the second conductivity type and the first well 121 of the second conductivity type on the upper side while being disposed on the other side, for example, the right side, of the second gate 132b.

[0139] For example, the second ion implantation connection region 126b of the second conductivity type is disposed below between the second gate 132b of the second cell region and the second gate 132b of the fourth cell region adjacent to the second cell region in the negative (-) direction of the X axis.

[0140] At this time, the second ion implantation connection region 126b of the second conductivity type can connect the third well 124b of the second conductivity type disposed below the second gate 132b of the second cell region and the third well 124b of the second conductivity type disposed below the second gate 132b of the fourth cell region adjacent to the second cell region in the negative (-) direction of the X axis.

[0141] Further, the second ion implantation connection region 126b of the second conductivity type can connect the third well 124b of the second conductivity type of the second cell region and the third well 124b of the second conductivity type of the fourth cell region to the first well 121 of the second conductivity type on the upper side.

[0142] According to the third embodiment, by disposing the third well 124b of the second conductivity type below the region between the first well 121 of the second conductivity type which is the JFET region, there is a technical effect of dispersing the electric field concentrated at the corner of the first well 121 of the second conductivity type.

[0143] Further, according to the third embodiment, since the first well 121 of the second conductivity type to which the ground potential is applied is connected to the third well 124b of the second conductivity type by the ion implantation connection region 126 of the second conductivity type, the ground potential is also applied to the third well 124b of the second conductivity type.

[0144] Thereby, there is a combined technical effect that an increase in the on-resistance (R on ) can also be prevented by applying the ground potential to the third well 124b of the second conductivity type that prevents electric field concentration.

[0145] Also, according to the third embodiment, since the first ion implantation connection region 126a of the second conductivity type or the second ion implantation connection region 126b of the second conductivity type can be disposed only below one side or a part of the other side of the second gate 132b of each cell, there is a combined technical effect capable of improving the current flow.

[0146] Although the embodiments of the present invention have been described above with reference to the embodiments, those having ordinary knowledge in the art should easily understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the following claims.

Claims

1. A substrate; a first epitaxial layer of a first conductivity type disposed on the substrate; a second epitaxial layer of a first conductivity type disposed on the first epitaxial layer of the first conductivity type; a first well of a second conductivity type disposed on the second epitaxial layer of the first conductivity type in a spaced apart relationship; a third well of a second conductivity type disposed in the second epitaxial layer of the first conductivity type below the spaced apart first well of the second conductivity type; an ion-implanted connection region of a second conductivity type connecting the first well of the second conductivity type and the third well of the second conductivity type.

2. 2 . The power semiconductor device of claim 1 , wherein when a ground potential is applied to the first well of the second conductivity type, the ground potential is also applied to the third well of the second conductivity type by the ion-implanted connection region of the second conductivity type.

3. The power semiconductor device according to claim 2 , wherein a horizontal width of the third well of the second conductivity type is equal to or greater than a distance between adjacent first wells of the second conductivity type.

4. a first conductivity type source region disposed on the first well of the second conductivity type; a second gate insulating layer disposed on the first conductivity type source region, the first conductivity type first well, and the first conductivity type second epitaxial layer; a second gate disposed on the second gate insulating layer, The power semiconductor device according to claim 1 , wherein the third well of the second conductivity type is disposed below a region provided between the spaced apart first wells of the second conductivity type.

5. The power semiconductor device of claim 4 , wherein the third well of the second conductivity type is disposed in a continuous form along the second gate.

6. the third well of the second conductivity type is disposed so as to extend horizontally in a first direction in which the second gate extends; The power semiconductor device according to claim 4 , wherein the second conductive type ion implantation connection region is disposed to extend in a second direction perpendicular to the first direction.

7. a second gate insulating layer disposed on the first well of the second conductivity type and the second epitaxial layer of the first conductivity type; a second gate disposed on the second gate insulating layer, 2. The power semiconductor device according to claim 1, wherein the third well of the second conductivity type includes a 3-1 well of the second conductivity type arranged below the second gate of the first cell region, and a 3-2 well of the second conductivity type arranged below the second gate of a third cell region adjacent to the first cell region in the positive direction of the X-axis.

8. 8. The power semiconductor device of claim 7, wherein the second conductive type ion implantation connection region includes a second conductive type first ion implantation connection region connecting the second conductive type 3-1 well and the second conductive type 3-2 well.

9. 9. The power semiconductor device of claim 8, wherein when a ground potential is applied to the first well of the second conductivity type, the ground potential is also applied to the third well of the second conductivity type by the ion-implanted connection region of the second conductivity type.

10. A power conversion device comprising the power semiconductor element according to any one of claims 1 to 9.

Images