Semiconductor device and data storage system

Abstract

To provide a semiconductor device to increase the degree of integration, and a data storage system including the same.SOLUTION: A semiconductor device CH includes a first structure ST1 including a first memory block MAT1 and a second memory block MAT2 that are arranged in order in a first direction. A first gate electrode of the first memory block includes a first word line WL1 including a first word line pad P1a disposed in a second connection region R1b, and a first upper gate line UL1a including a first upper gate pad P1b disposed in a first connection region and disposed on the first word line. A second gate electrode of the second memory block includes a second word line WL2 including a second word line pad P2a disposed in a third connection region R2b, and a second upper gate line UL2a including a second upper gate pad P2b disposed in a fourth connection region R2b and disposed on the second word line.SELECTED DRAWING: Figure 3a

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a data system including the same.

Background Art

[0002] In an electronic system that requires data storage, there is a need for a semiconductor device that can store a large amount of data. Therefore, a solution for increasing the data storage capacity of the semiconductor device has been studied. For example, as one method of increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of memory cells arranged two-dimensionally has been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device in which a connection region where gate pads are arranged is arranged on both sides of a memory cell array region, and the integration degree can be improved.

[0004] One of the technical problems to be achieved by the technical idea of the present invention is to provide a data storage system including the above semiconductor device.

Means for Solving the Problems

[0005] Provided is a semiconductor device according to an embodiment of the technical idea of the present invention. This semiconductor device includes a first structure having first and second side surfaces facing each other, and including a first memory block and a second memory block arranged in order in a first direction from the first side surface toward the second side surface, and a second structure including a peripheral circuit and overlapping the first structure in the vertical direction. The first memory block has a first connection region, a first memory cell array region, and a second connection region arranged in order in the first direction, and the second memory block has a third connection region, a second memory cell array region, and a fourth connection region arranged in order in the first direction. The first memory block includes a first gate electrode spaced apart from each other in the vertical direction and extending from the first connection region to the second connection region, and the second memory block includes a second gate electrode spaced apart from each other in the vertical direction and extending from the third connection region to the fourth connection region. The first gate electrode of the first memory block has a first word line having a first word line pad disposed in the second connection region, and a first upper gate pad disposed in the first connection region, and includes a first upper gate line disposed on the first word line. The second gate electrode of the second memory block has a second word line having a second word line pad disposed in the third connection region, and a second upper gate pad disposed in the fourth connection region, and includes a second upper gate line disposed on the second word line. The first structure further includes a first word line contact plug connected to the first word line pad, a first upper gate contact plug connected to the first upper gate pad, a second word line contact plug connected to the second word line pad, and a second upper gate contact plug connected to the second upper gate pad.

[0006] Provided is a semiconductor device according to an embodiment of the technical idea of the present invention. This semiconductor device has a first side surface and a second side surface facing each other, and includes a first connection region, a first memory cell array region, a second connection region, a third connection region, a second memory cell array region, and a fourth connection region arranged in order in a first direction from the first side surface to the second side surface, and a first structure including a fourth connection region, and a second structure including a peripheral circuit and overlapping the first structure in the vertical direction. The first structure includes a first side conductive layer disposed in the first connection region, the first memory cell array region, and the second connection region, a first vertical memory structure penetrating the first side conductive layer in the first memory cell array region, a second side conductive layer disposed in the third connection region, the second memory cell array region, and the fourth connection region, and a second vertical memory structure penetrating the second side conductive layer in the second memory cell array region. The first side conductive layer includes a first lower conductive group having a first lower pad arranged in a stepped shape in the second connection region, and a first upper conductive group disposed at a level higher than the first lower conductive group and having a first upper pad arranged in a stepped shape in the first connection region. The second side conductive layer includes a second lower conductive group disposed at the same level as the first conductive group and having a second lower pad arranged in a stepped shape in the third connection region, and a second upper conductive group disposed at the same level as the second conductive group and having a second upper pad arranged in a stepped shape in the fourth connection region.

[0007] Provided is a data storage system according to an embodiment of the technical idea of the present invention. This data storage system includes a semiconductor device including input / output pads, and a controller electrically connected to the semiconductor device via the input / output pads and controlling the semiconductor device. The semiconductor device includes a first structure having first and second side surfaces facing each other and including a first memory block and a second memory block arranged in order in a first direction from the first side surface to the second side surface, and a second structure including a peripheral circuit and overlapping the first structure in a vertical direction. The first memory block has a first connection region, a first memory cell array region, and a second connection region arranged in order in the first direction, and the second memory block has a third connection region, a second memory cell array region, and a fourth connection region arranged in order in the first direction. The first memory block includes a first gate electrode spaced apart from each other in the vertical direction and extending from the first connection region to the second connection region, and the second memory block includes a second gate electrode spaced apart from each other in the vertical direction and extending from the third connection region to the fourth connection region. The first gate electrode of the first memory block includes a first word line having a first word line pad disposed in the second connection region, a first upper gate pad disposed in the first connection region, and a first upper gate line disposed on the first word line. The second gate electrode of the second memory block includes a second word line having a second word line pad disposed in the third connection region, a second upper gate pad disposed in the fourth connection region, and a second upper gate line disposed on the second word line. The first structure further includes a first word line contact plug connected to the first word line pad, a first upper gate contact plug connected to the first upper gate pad, a second word line contact plug connected to the second word line pad, and a second upper gate contact plug connected to the second upper gate pad.

Effects of the Invention

[0008] According to an embodiment of the technical idea of the present invention, it is possible to provide a semiconductor device including a connection region in which gate pads are arranged on both sides of a memory cell array region, and a data storage system including the same. By arranging the connection regions on both sides of the memory cell array region, it is possible to minimize and optimize the space for arranging the gate pads, and thus increase the integration degree of the semiconductor device.

[0009] In addition, by arranging a first connection region in which a gate pad of an upper gate electrode is arranged on one side of the memory cell array region and a second connection region in which a gate pad of a word line is arranged on the other side of the memory cell array region, it is possible to effectively arrange a peripheral circuit that is electrically connected to the upper gate electrode and the word line, and minimize the distance between the upper gate electrode and the word line and the peripheral circuit. Therefore, the signal transmission speed can be improved, and thus the performance of the semiconductor device can be improved.

[0010] The various beneficial advantages and effects of the present invention are not limited to the above-described content, and can be more easily understood in the process of describing specific embodiments of the present invention.

Brief Description of the Drawings

[0011]

Figure 1a

Figure 1b

Figure 1c

Figure 1d

Figure 2

Figure 3a

Figure 3b

Figure 4

Figure 5

Figure 6a

Figure 6b

Figure 6c

Figure 6d

Figure 7

Figure 8a

Figure 8b

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Mode for Carrying Out the Invention

[0012] Hereinafter, terms such as "upper", "middle", "lower", "inner", and "outer" may be replaced with other terms, for example, terms such as "first", "second", and "third", and may also be used to describe the components of the specification. Terms such as "first", "second", and "third" can be used when describing various components, but the above components are not limited by the above terms. "The first component" may be named "the second component" or may be named with other terms that can distinguish it from other components.

[0013] Referring to FIGS. 1a, 1b, 1c, and 1d, a semiconductor device according to an embodiment of the present invention will be described. In FIGS. 1a to 1d, FIG. 1a is a perspective view schematically showing a data storage system including a semiconductor device according to an embodiment of the present invention, FIG. 1b is a perspective view schematically showing a semiconductor device according to an embodiment of the present invention, FIG. 1c is a block diagram schematically showing a data storage system including a semiconductor device according to an embodiment of the present invention, and FIG. 1d is a block diagram schematically showing a semiconductor device according to an embodiment of the present invention.

[0014] First, referring to FIG. 1a, a data storage system 1 according to an embodiment may include a main board 5, controllers 10 mounted on the main board 5, one or more semiconductor packages 15, and DRAMs 20. The semiconductor packages 15 and the DRAMs 20 can be interconnected with the controller 10 by a wiring pattern 25 formed on the main board 5.

[0015] The main board 5 may include a connector 30 including a plurality of pins for coupling to an external host (HOST in FIG. 1c). The number and arrangement of the plurality of pins in the connector 30 may vary according to the communication interface between the data storage system 1 and the external host (HOST).

[0016] In an exemplary embodiment, the data storage system 1 can communicate with an external host by any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage).

[0017] In an exemplary embodiment, the data storage system 1 can operate by power supplied from the external host (HOST in FIG. 1c) via the connector 30.

[0018] The data storage system 1 may further include a PMIC (Power Management Integrated Circuit) that distributes the power supplied from the external host HOST to the controller 10 and the semiconductor package 15.

[0019] The controller 10 can record data on the semiconductor package 15 or read data from the semiconductor package 15, and can improve the operating speed of the data storage system 1.

[0020] The DRAM 20 may be a buffer memory for alleviating the speed difference between the semiconductor package 15, which is a data storage space, and an external host. The DRAM 20 included in the data storage system 1 can also operate as a kind of cache memory and can provide a space for temporarily storing data in the control operation for the semiconductor package 15. When the DRAM 20 is included in the data storage system 1, the controller 10 can further include a DRAM controller for controlling the DRAM 20 in addition to a NAND controller (1220 in FIG. 2) for controlling the semiconductor package 15.

[0021] The semiconductor package 15 can include first and second semiconductor packages 15a and 15b separated from each other. The first and second semiconductor packages 15a and 15b may each be a semiconductor package including a plurality of semiconductor devices CH. The semiconductor device CH can also be referred to as a semiconductor chip.

[0022] Each of the first and second semiconductor packages 15a and 15b can include a package substrate 50, the semiconductor device CH on the package substrate 50, an adhesive layer 60 disposed on the lower surface of each of the semiconductor devices CH, a connection structure 70 for electrically connecting the semiconductor device CH and the package substrate 50, and a molding layer 80 covering the semiconductor device CH and the connection structure 70 on the package substrate 50.

[0023] The package substrate 50 may be a printed circuit board including package upper pads 55. Each of the semiconductor devices CH can include input / output pads IOP.

[0024] In an exemplary embodiment, the connecting structure 70 may be a bonding wire that electrically connects the input / output pad IOP and the package upper pad 55. Therefore, in each of the first and second semiconductor packages 15a and 15b, the semiconductor devices CH can be electrically connected to each other in a bonding wire manner and can be electrically connected to the package upper pad 55 of the package substrate 50. Depending on the embodiment, in each of the first and second semiconductor packages 15a and 15b, instead of the connecting structure 70 of the bonding wire manner, the semiconductor devices CH can also be electrically connected to each other by a connecting structure including a Through Silicon Via (TSV).

[0025] In an exemplary embodiment, the controller 10 and the semiconductor device CH may be included in one package. For example, the controller 10 and the semiconductor device CH may be mounted on a separate interposer substrate different from the main substrate 5, and the controller 10 and the semiconductor device CH can be connected to each other by wirings formed on the interposer substrate.

[0026] In an exemplary embodiment, in each of the semiconductor devices CH, the first structure ST1 may include an input / output pad IOP. Depending on the embodiment, the input / output pad IOP may be disposed on the second structure ST2.

[0027] Next, referring to FIGS. 1b, 1c, and 1d together with FIG. 1a, each of the semiconductor devices CH can include a first structure ST1 and a second structure ST2 that vertically overlap the first structure ST1 in the vertical direction Z.

[0028] In each of the semiconductor devices CH, the first structure ST1 can include a plurality of memory mats MAT1, MAT2 spaced apart from each other.

[0029] Hereinafter, one semiconductor device CH will be mainly described.

[0030] The first structure ST1 can have a first side surface S1 and a second side surface S2 that face each other. In the first structure ST1, the plurality of memory mats MAT1, MAT2 can be arranged between the first side surface S1 and the second side surface S2.

[0031] The plurality of memory mats MAT1, MAT2 can include a first memory mat MAT1 adjacent to the first side surface S1 and a second memory mat MAT2 adjacent to the second side surface S2.

[0032] In an embodiment, the direction from the first side surface S1 to the second side surface S2 can be defined as the +X direction, and the direction from the second side surface S2 to the first side surface S1 can be defined as the -X direction. The +X direction can be referred to as the first horizontal direction or the first direction, and the -X direction can also be referred to as the second horizontal direction or the second direction.

[0033] The +X direction and the -X direction can be perpendicular to the vertical direction Z.

[0034] The first memory mat MAT1 and the second memory mat MAT2 can be arranged in order in the +X direction.

[0035] The first memory mat MAT1 and the second memory mat MAT2 may have a mirror-symmetric structure.

[0036] The first memory mat MAT1 can include a plurality of first memory blocks BLK1, and the second memory mat MAT2 can include a plurality of second memory blocks BLK2.

[0037] Each of the plurality of first memory blocks BLK1 may be in a line shape or a bar shape extending in the +X direction. Each of the plurality of second memory blocks BLK2 may be in a line shape or a bar shape extending in the +X direction.

[0038] The plurality of first memory blocks BLK1 can be spaced apart from each other in the Y direction. The plurality of second memory blocks BLK2 can be spaced apart from each other in the Y direction.

[0039] The Y direction can be perpendicular to the +X direction, the -X direction, and the vertical direction Z. The Y direction can also be referred to as the third horizontal direction or the third direction.

[0040] Each of the plurality of first memory blocks BLK1 can include a first connection region R1a, a first memory cell array region M1, and a second connection region R1b that are arranged in order in the +X direction. Each of the plurality of second memory blocks BLK2 can include a third connection region R2b, a second memory cell array region M2, and a fourth connection region R2a that are arranged in order in the +X direction. The second connection region R1b of the first memory blocks BLK1 that are adjacent to each other among the plurality of first memory blocks BLK1 can be adjacent to the third connection region R2b of the second memory blocks BLK2 that are adjacent to each other among the plurality of second memory blocks BLK2.

[0041] Since the first structure ST1 can include the first and second memory blocks BLK1, BLK2, the first structure ST1 can include the first connection region R1a, the first memory cell array region M1, the second connection region R1b, the third connection region R2b, the second memory cell array region M2, and the fourth connection region R2a that are arranged in order in the +X direction.

[0042] The first connection region R1a can be referred to as a first outer connection region, and the fourth connection region R2a can be referred to as a second outer connection region.

[0043] The second and third connection regions R1b, R2b can be referred to as a first and a second intermediate connection region, respectively.

[0044] In an embodiment, in the +X direction, the first and second memory cell array regions M1, M2 can have the same length as each other.

[0045] In an embodiment, in the +X direction, each of the first and second memory cell array regions M1 and M2 can have a length greater than the length of each of the first to fourth connection regions R1a, R1b, R2a, and R2b.

[0046] In an embodiment, in the +X direction, the first and fourth connection regions R1a and R2a can have the same length as each other.

[0047] In an embodiment, in the +X direction, the second and third connection regions R1b and R2b can be adjacent to each other and can have the same length as each other.

[0048] In an embodiment, in the +X direction, the length of each of the second and third connection regions R1b and R2b may be greater than the length of each of the first and fourth connection regions R1a and R2a.

[0049] In an embodiment, in the Y direction, the first to fourth connection regions R1a, R1b, R2a, and R2b can have substantially the same width.

[0050] In an embodiment, in the Y direction, the width of each of the first to fourth connection regions R1a, R1b, R2a, and R2b can be substantially the same as the width of each of the first and second memory cell array regions M1 and M2.

[0051] In an embodiment, the "length" in the +X direction can also be referred to as the "width" in the +X direction.

[0052] The controller 10 can write data DATA to the semiconductor device CH and read the data DATA stored in the semiconductor device CH. The controller 10 can transmit a command CMD, an address ADDR, a control signal CTRL, and data DATA to the semiconductor device CH in order to write the data DATA to the semiconductor device CH. The controller 10 can transmit a command CMD, an address ADDR, and a control signal CTRL to the semiconductor device CH in order to read the data DATA stored in the semiconductor device CH.

[0053] The semiconductor device CH can include a non-volatile memory device such as a NAND flash memory, a phase change memory (PRAM), a resistive memory (ReRAM), a magnetoresistive memory (MRAM), or a ferroelectric memory (FRAM). The semiconductor device CH can perform operations such as writing, reading, and erasing of data DATA in response to signals received from the controller 10.

[0054] Each of the first and second memory mats MAT1 and MAT2 can include a memory cell array MCA including memory cells arranged three-dimensionally. For example, in the first structure ST1, the first memory cell array region M1 of the first memory block BLK1 and the second memory cell array region M2 of the second memory block BLK2 are arranged three-dimensionally and can include memory cells capable of storing data.

[0055] The first memory cell array region M1 of the first memory mat MAT1 may be a region where memory cells are arranged three-dimensionally, and the second memory cell array region M2 of the second memory mat MAT2 may be a region where memory cells are arranged three-dimensionally.

[0056] The second structure ST2 can include a peripheral circuit PC. The peripheral circuit PC can include an address decoder 93, a control logic 94, a page buffer 95, an input / output circuit 96, and a voltage generation circuit 97. Therefore, in the semiconductor device CH, the first structure ST1 can include the memory cell array MCA, and the second structure ST2 can include the peripheral circuit PC.

[0057] The first structure ST1 can further include a word line WL, a string selection line SSL, a ground selection line GSL, a bit line BL, an erase control line ECL, and a common source CSL.

[0058] The memory cell arrays MCA of the first and second memory mats MAT1 and MAT2 can be electrically connected to the address decoder 93 of the peripheral circuit PC via the word line WL, the string selection line SSL, the ground selection line GSL, and the common source CSL, and can be electrically connected to the page buffer 95 of the peripheral circuit PC via the bit line BL.

[0059] The address decoder 93 can select any one of the first and second memory blocks BLK1 and BLK2. The address decoder 93 can select any one of the word lines WL of the selected memory block. The address decoder 93 can transmit the voltage provided from the voltage generation circuit 97 to the word line WL, the selection lines SSL and GSL of the selected memory block. During the program operation, the address decoder 93 can transmit a positive (+) high voltage program voltage to the selected word line, and during the erase operation, can transmit a positive (+) high voltage erase voltage to the bulk of the selected memory block.

[0060] The control logic 94 receives the command CMD and the control signal CTRL from the controller 10, and can control the address decoder 93, the page buffer 95, and the input / output circuit 96 in response to the received signals. The control logic 94 can control the voltage generation circuit 97 that generates various voltages required for the operation of the semiconductor device CH. For example, the control logic 94 can adjust the voltage levels provided to the word line WL and the bit line BL when executing a memory operation such as a program operation or an erase operation.

[0061] The voltage generation circuit 97 can generate various levels of voltages such as a plurality of selected read voltages, a plurality of non-selected read voltages, a plurality of program pulses, a plurality of pass voltages, and a plurality of erase pulses according to the control of the control logic 94, and provide them to the address decoder 93 and the first and second memory blocks BLK1, BLK2. For example, the voltage generation circuit 97 can generate a positive (+) high voltage corresponding to a plurality of program pulses or a plurality of erase pulses. The voltage generation circuit 97 can include a charge pump including at least one pumping capacitor to generate various levels of voltages as described above.

[0062] The page buffer 95 can operate as a write driver or a sense amplifier according to the operation mode. During a read operation, the page buffer 95 can sense the bit line BL of the selected memory cell among the memory cells three-dimensionally arranged in the first and second memory blocks BLK1, BLK2 according to the control of the control logic 94. The sensed data can be stored in a latch provided inside the page buffer 95. The page buffer 95 can dump the data stored in the latch to the input / output circuit 96 according to the control of the control logic 94.

[0063] The input / output circuit 96 can temporarily store a command word CMD, an address ADDR, a control signal CTRL, and data DATA provided from the outside of the semiconductor device CH via the input / output pad IOP. The input / output circuit 96 can temporarily store the read data of the semiconductor device CH and output it to the outside via the input / output pad IOP at a specified time point.

[0064] With reference to FIG. 2 together with FIGS. 1a to 1d described above, an exemplary example of the data storage system 1 described above will be described. FIG. 2 is a diagram schematically showing a data system including a semiconductor device according to an exemplary embodiment of the present invention.

[0065] Referring to FIG. 2 together with FIGS. 1a to 1d, the data storage system 1 may be a storage device including the semiconductor device CH or an electronic device including a storage device. For example, the data storage system 1 may be a solid state drive device (SSD device) including one or more semiconductor devices CH, a USB (Universal Serial Bus), a computing system, a medical device, or a communication device.

[0066] The second structure ST2 may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130.

[0067] The first structure ST1 can include bit lines BL, a common source CSL, word lines WL, first and second upper gate lines ULa, ULb, first and second lower gate lines LLa, LLb, and a memory cell string CSTR between the bit line BL and the common source CSL.

[0068] In the first chip structure ST1 shown in FIG. 2, the bit line BL, the common source CSL, the word line WL, the first and second upper gate lines ULa and ULb, the first and second lower gate lines LLa and LLb, and the memory cell string CSTR can be included in any one of the memory blocks in one of the plurality of memory mats MAT1 and MAT2. For example, the bit line BL, the common source CSL, the word line WL, the first and second upper gate lines ULa and ULb, the first and second lower gate lines LLa and LLb, and the memory cell string CSTR shown in FIG. 2 can be understood as being included in one of the second memory blocks in the second memory mat MAT2. Since the first and second memory mats MAT1 and MAT2 can have a mirror structure, the bit line BL, the common source CSL, the word line WL, the first and second upper gate lines ULa and ULb, the first and second lower gate lines LLa and LLb, and the memory cell string CSTR shown in FIG. 2 can be understood as being included in either one of the first memory block BLK1 and the second memory block BLK2.

[0069] The first lower gate line LLa can be arranged at a level higher than the common source CSL. The second lower gate line LLb can be arranged at a level higher than the first lower gate line LLa. The word line WL can be arranged at a level higher than the second lower gate line LLb. The first gate upper line ULa can be arranged at a level higher than the word line WL. The second gate upper line ULb can be arranged at a level higher than the first gate upper line ULa.

[0070] In the first structure ST1, each memory cell string CSTR can include lower transistors LTa and LTb adjacent to the common source CSL, upper transistors UTa and UTb adjacent to the bit line BL, and a plurality of memory cell transistors MCT arranged between the lower transistors LTa and LTb and the upper transistors UTa and UTb.

[0071] The number of the lower transistors LTa and LTb and the number of the upper transistors UTa and UTb can be variously modified according to embodiments. The plurality of memory cell transistors MCT can include an information storage region capable of storing information (data).

[0072] In an exemplary embodiment, the upper transistors UTa and UTb can include string selection transistors, and the lower transistors LTa and LTb can include ground selection transistors. The lower gate lines LLa and LLb may be gate electrodes of the lower transistors LTa and LTb, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines ULa and ULb may be gate electrodes of the upper transistors UTa and UTb, respectively.

[0073] In an exemplary embodiment, the lower transistors LTa and LTb can include a first lower transistor LTa and a second lower transistor LTb on the first lower transistor LTa. The first and second lower transistors LTa and LTb can be connected in series. The first lower transistor LTa may be a lower erase control transistor, and the second lower transistor LTb may be a lower selection transistor, for example, a ground selection transistor. The first lower gate line LLa may be a lower erase control gate electrode of the lower erase control transistor LTa, and the second lower gate line LLb may be a lower selection gate electrode of the lower selection transistor LTb.

[0074] The above-described first and second lower gate lines LLa, LLb, the word line WL, and the first and second upper gate lines ULa, ULb may be gate electrodes.

[0075] In an exemplary embodiment, the upper transistors UTa, UTb may include a first upper transistor UTa and a second upper transistor UTb on the first upper transistor UTa. The first and second upper transistors UTa, UTb may be connected in series.

[0076] In one example, the first upper transistor UTa may be an upper erase control transistor, and the second upper transistor UTb may be an upper selection transistor, for example, a string selection transistor. In this case, the first upper gate line ULa may be the upper erase control gate electrode of the upper erase control transistor UTa, and the second upper gate line ULb may be the string selection gate electrode of the string selection transistor UTb. At least one of the lower erase control transistor LTa and the upper erase control transistor UTa can be used for an erase operation to erase data stored in the memory cell transistor MCT by utilizing a Gate Induce Drain Leakage (GIDL) phenomenon.

[0077] In other embodiments, the first upper transistor UTa may be an upper selection transistor, for example, a string selection transistor, and the second upper transistor UTb may be an upper erase control transistor. In this case, the first upper gate line ULa may be the string selection gate electrode of the string selection transistor UTa, and the second upper gate line ULb may be the upper erase control gate electrode of the upper erase control transistor UTb.

[0078] In an embodiment, the common source CSL, the first and second lower gate lines LLa and LLb, the word line WL, and the first and second upper gate lines ULa and ULb can be electrically connected to the decoder circuit 1110 via routing wiring structures 1115a and 1115b extending from the first structure ST1 to the second structure ST2.

[0079] In an embodiment, the routing wiring structures 1115a and 1115b can be connected to the pad regions of the first and second lower gate lines LLa and LLb, the pad region of the word line WL, and the pad regions of the first and second upper gate lines ULa and ULb.

[0080] The decoder circuit 1110 can include a first circuit 1110a electrically connected to the second upper gate line ULb, a second circuit 1110b electrically connected to the first upper gate line ULa, a third circuit 1110c electrically connected to the word line WL, a fourth circuit 1110d electrically connected to the second lower gate line LLb, a fifth circuit 1110e electrically connected to the first lower gate line LLa, and a sixth circuit 1110f electrically connected to the common source CSL.

[0081] In one example, the routing wiring structures 1115a and 1115b can include a first routing wiring structure 1115a electrically connected to the common source CSL, the first and second lower gate lines LLa and LLb, and the word line WL, and a second routing wiring structure 1115b electrically connected to the first and second upper gate lines ULa and ULb.

[0082] In one embodiment, the common source CSL, the first and second lower gate lines LLa, LLb, and the word line WL can be electrically connected to the decoder circuit 1110 via the first routing wiring structure 1115a, and the first and second upper gate lines ULa, ULb can be electrically connected to the decoder circuit 1110 via the second routing wiring structure 1115b.

[0083] In other embodiments, the second upper gate line ULb can also be electrically connected to the first circuit 1110a of the decoder circuit 1110 via the first routing wiring structure 1115a.

[0084] In other embodiments, the second upper gate line ULb can also be electrically connected to the first circuit 1110a of the decoder circuit 1110 via the first and second routing wiring structures 1115a, 1115b.

[0085] In other embodiments, the first upper gate line ULa can also be electrically connected to the second circuit 1110b of the decoder circuit 1110 via the first and second routing wiring structures 1115a, 1115b.

[0086] In other embodiments, the word line WL can include a lower word line and an upper word line disposed at a level higher than the lower word line. The lower word line can be electrically connected to the third circuit 1110c of the decoder circuit 1110 via the first routing wiring structure 1115a, and the upper word line can be electrically connected to the third circuit 1110c of the decoder circuit 1110 via the second routing wiring structure 1115b.

[0087] The bit line BL can be electrically connected to the page buffer 1120 via a second routing wiring structure 1125 that extends from within the second structure ST2 to the first structure ST1.

[0088] In the second structure ST2, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors. The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130.

[0089] The semiconductor device 1100 can communicate with the controller 1200 via the input / output pad IOP that is electrically connected to the logic circuit 1130. The input / output pad IOP can be electrically connected to the logic circuit 1130 via an input / output connection wiring 1135 that extends from within the first chip structure 1100F to the second chip structure 1100S.

[0090] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230.

[0091] The above-mentioned processor 1210 can control the operation of the entire data storage system 1 including the above-mentioned controller 1200. The above-mentioned processor 1210 can operate according to a predetermined firmware, and can control the NAND controller 1220 to access the semiconductor device CH. The above-mentioned NAND controller 1220 can include a NAND interface 1221 that processes communication with the semiconductor device CH. Through the above-mentioned NAND interface 1221, control commands for controlling the semiconductor device CH, data to be recorded in the memory cell transistor MCT of the semiconductor device CH, data to be read from the memory cell transistor MCT of the semiconductor device CH, etc. can be transmitted. The above-mentioned host interface 1230 can provide a communication function between the data storage system 1 and the external host (HOST in FIG. 1c). When a control command is received from the external host (HOST in FIG. 1c) through the above-mentioned host interface 1230, the above-mentioned processor 1210 can control the semiconductor device CH in response to the control command.

[0092] As described above, each of the plurality of first memory blocks (BLK1 in FIG. 1b) of the first memory mat MAT1 can include the first connection region R1a, the first memory cell array region M1, and the second connection region R1b that are arranged in order in the +X direction, and each of the plurality of second memory blocks (BLK2 in FIG. b) of the second memory mat MAT2 can include the third connection region R2b, the second memory cell array region M2, and the fourth connection region R2a that are arranged in order in the +X direction. The peripheral circuit PC of the second structure ST2 described above can include a first peripheral circuit (PC1 in FIG. 3a) that can be configured to be electrically connected to the first memory mat MAT1 and a second peripheral circuit (PC2 in FIG. 3a) that can be configured to be electrically connected to the second memory mat MAT2.

[0093] Hereinafter, with reference to FIGS. 3A and 3B, one first memory block BLK1 among the plurality of first memory blocks (BLK1 in FIG. 1B) and the electrical connection relationship between the first memory block BLK1 and the first peripheral circuit (PC1 in FIG. 3A) will be described, and one second memory block BLK2 among the plurality of second memory blocks (BLK2 in FIG. 1B) and the electrical connection relationship between the second memory block BLK2 and the second peripheral circuit (PC2 in FIG. 3A) will be described. FIG. 3A is a diagram for explaining an example of the semiconductor device CH including the above-described first structure ST1 and second structure ST2, and FIG. 3B is a diagram showing circuits in the first memory cell array region M1 of the first memory mat MAT1 in FIG. 3A and circuits in the second memory cell array region M2 of the second memory mat MAT2.

[0094] Referring to FIGS. 3A and 3B together with FIGS. 1A to 1D and FIG. 2, as described above, the first connection region R1a, the first memory cell array region M1, the second connection region R1b, the third connection region R2b, the second memory cell array region M2, and the fourth connection region R2a can be arranged in this order in the +X direction.

[0095] The first memory mat MAT1 of the first structure ST1 can include a first common source CSL1 that can correspond to the common source CSL described in FIG. 2, a first lower gate line LL1a and a second lower gate line LL1b that can respectively correspond to the first and second lower gate lines LLa and LLb described in FIG. 2A, a first word line WL1 that can correspond to the word line WL described in FIG. 2A, a first upper gate line UL1a and a second upper gate line UL1b that can respectively correspond to the first and second upper gate lines ULa and ULb described in FIG. 2A, and a first bit line BL1 that can correspond to the bit line BL described in FIG. 2A.

[0096] The first gate electrode of the first memory mat MAT1 of the first structure ST1 can include the first and second lower gate lines LL1a, LL1b, the first word line WL1, and the first and second upper gate lines UL1a, UL1b.

[0097] The second memory mat MAT2 of the first structure ST1 can include a second common source CSL2 that can correspond to the common source CSL described in FIG. 2, third and fourth lower gate lines LL2a, LL2b that can respectively correspond to the first and second lower gate lines LLa, LLb described in FIG. 2a, a second word line WL2 that can correspond to the word line WL described in FIG. 2a, third and fourth upper gate lines UL2a, UL2b that can respectively correspond to the first and second upper gate lines ULa, ULb described in FIG. 2a, and a second bit line BL2 that can correspond to the bit line BL described in FIG. 2a.

[0098] The second gate electrode of the second memory mat MAT2 of the first structure ST1 can include the third and fourth lower gate lines LL2a, LL2b, the second word line WL2, and the third and fourth upper gate lines UL2a, UL2b.

[0099] The first memory mat MAT1 can include a first memory cell string CSTR1 that corresponds to the memory cell string CSTR described in FIG. 2, and the second memory mat MAT2 can include a second memory cell string CSTR2 that corresponds to the memory cell string CSTR described in FIG. 2.

[0100] The first memory cell string CSTR1 can be arranged within the first memory cell array region M1, and the second memory cell string CSTR2 can be arranged within the second memory cell array region M2.

[0101] Hereinafter, one of the first memory cell strings CSTR1 of the above first memory cell string CSTR1 and one of the second memory cell strings CSTR2 of the above second memory cell string CSTR2 will be described as the center.

[0102] Each of the above first memory cell string CSTR1 and the above second memory cell string CSTR2 can be substantially the same as the above memory cell string CSTR described in FIG. 2.

[0103] The above first memory cell string CSTR1 can include first and second lower transistors LT1a and LT1b corresponding to the above first and second lower transistors (LTa, LTb in FIG. 2), a first memory cell transistor MCT1 corresponding to the plurality of memory cell transistors (MCT in FIG. 2), and first and second upper transistors UT1a and UT1b corresponding to the above first and second upper transistors (UTa, UTb in FIG. 2).

[0104] The above second memory cell string CSTR2 can include third and fourth lower transistors LT2a and LT2b corresponding to the above first and second lower transistors (LTa, LTb in FIG. 2), a second memory cell transistor MCT2 corresponding to the plurality of memory cell transistors (MCT in FIG. 2), and third and fourth upper transistors UT2a and UT2b corresponding to the above first and second upper transistors (UTa, UTb in FIG. 2).

[0105] The above second structure ST2 can include a first peripheral circuit PC1 electrically connected to the above first memory mat MAT1 and a second peripheral circuit PC2 electrically connected to the above second memory mat MAT2.

[0106] For example, each of the above-described first and second peripheral circuits PC1 and PC2 can include the above-described first circuit 1110a, the above-described second circuit 1110b, the above-described third circuit 1110c, the above-described fourth circuit 1110d, and the above-described fifth circuit 1110e as described in FIG. 2.

[0107] In the above-described first peripheral circuit PC1, the above-described first circuit 1110a can be electrically connected to the above-described second upper gate line UL1b, the above-described second circuit 1110b can be electrically connected to the above-described first upper gate line UL1a, the above-described third circuit 1110c can be electrically connected to the above-described first word line WL1, the above-described fourth circuit 1110d can be electrically connected to the above-described second lower gate line LL1b, and the above-described fifth circuit 1110e can be electrically connected to the above-described first lower gate line LL1a.

[0108] In the above-described second peripheral circuit PC2, the above-described first circuit 1110a can be electrically connected to the above-described fourth upper gate line UL2b, the above-described second circuit 1110b can be electrically connected to the above-described third upper gate line UL2a, the above-described third circuit 1110c can be electrically connected to the above-described second word line WL2, the above-described fourth circuit 1110d can be electrically connected to the above-described fourth lower gate line LL2b, and the above-described fifth circuit 1110e can be electrically connected to the above-described third lower gate line LL2a.

[0109] The above-described semiconductor device CH can include routing wiring structures 1115a1, 1115a2, 1115b1, and 1115b2 that can correspond to the above-described routing wiring structures 1115a and 1115b described in FIG. 2. For example, the above-described routing wiring structures 1115a1, 1115a2, 1115b1, and 1115b2 can include a first routing wiring structure 1115a1, a second routing wiring structure 1115b1, a third routing wiring structure 1115a2, and a fourth routing wiring structure 1115b2.

[0110] The first and second routing wiring structures 1115a1 and 1115b1 may be configured to electrically connect the first memory mat MAT1 and the first peripheral circuit PC1. The third and fourth routing wiring structures 1115a2 and 1115b2 may be configured to electrically connect the second memory mat MAT2 and the second peripheral circuit PC2.

[0111] The first routing wiring structure 1115a1 can be electrically connected in contact with the first and second lower gate lines LL1a and LL1b and the gate pad P1a of the first word line WL1. The second routing wiring structure 1115b1 can be electrically connected in contact with the gate pads P1b of the first and second upper gate lines UL1a and UL1b. The third routing wiring structure 1115a2 can be electrically connected in contact with the third and fourth lower gate lines LL2a and LL2b and the gate pad P2a of the second word line WL2. The fourth routing wiring structure 1115b2 can be electrically connected in contact with the gate pads P2b of the third and fourth upper gate lines UL2a and UL2b.

[0112] The gate pad P1a of the first and second lower gate lines LL1a and LL1b and the first word line WL1 can be disposed within the second connection region R1b. The gate pad P1b of the first and second upper gate lines UL1a and UL1b can be disposed within the first connection region R1a. The gate pad P2a of the third and fourth lower gate lines LL2a and LL2b and the second word line WL2 can be disposed within the third connection region R2b. The gate pad P2b of the third and fourth upper gate lines UL2a and UL2b can be disposed within the fourth connection region R2a.

[0113] For the program operation, read operation, and erase operation of the first and second memory cell transistors MCT1 and MCT2 in the first and second memory cell strings CSTR1 and CSTR2, voltages of various conditions can be applied to the first and second bit lines BL1 and BL2, the first and second common sources CSL1 and CSL2, the first gate lines LL1a, LL1b, WL1, UL1a, UL1b, and the second gate lines LL2a, LL2b, WL2, UL2a, UL2b.

[0114] For example, when programming data into a selected memory cell among the memory cells of the first memory cell transistor MCT1 or reading data stored in the selected memory cell, in order to turn on the second upper transistor UT1b that can be a string selection transistor and the second lower transistor LT1b that can be a ground selection transistor, a first operating voltage can be applied to the second upper gate line UL1b, and a second operating voltage can be applied to the second lower gate line LL1b. Accordingly, a current flow can occur between the first bit line BL1 and the first common source CSL1.

[0115] The first memory cell transistor MCT1 can be controlled by the first word line WL1 respectively. For example, a program voltage can be applied to a selected word line among the first word lines WL1, and a pass voltage can be applied to non-selected word lines.

[0116] During the erase operation for erasing data stored in the memory cell of the first memory cell transistor MCT1, an erase voltage can be applied to the first upper gate line UL1a and / or the first lower gate line LL1a of the first upper transistor UT1a and / or the first lower transistor LT1a that can be an erase control transistor.

[0117] For the operation of the first lower transistor LT1a of the first memory cell string CSTR1, for example, for turning on the first lower transistor LT1a, a first voltage V is applied to the first lower gate line LL1a via the gate pad P1a of the first lower gate line LL1a in the -X direction. LT1a It may be applied.

[0118] For the operation of the second lower transistor LT1b of the first memory cell string CSTR1, a second voltage V is applied to the second lower gate line LL1b via the gate pad P1a of the second lower gate line LL1b in the -X direction. LT1b It can be applied.

[0119] For the operation of the first memory cell transistor MCT1 of the first memory cell string CSTR1, a third voltage V is applied to the first word line WL1 via the gate pad P1a of the first word line WL1 in the -X direction. WL1 It can be applied. For example, applying the third voltage V WL1 can include applying a program voltage to the selected word line among the first word lines WL1 and applying a pass voltage to the non - selected word lines.

[0120] For the operation of the first upper transistor UT1a of the first memory cell string CSTR1, a fourth voltage V is applied to the first upper gate line UL1a via the gate pad P1b of the first upper gate line UL1a in the +X direction. UL1a It can be applied.

[0121] For the operation of the second upper transistor UT1b of the first memory cell string CSTR1, a fifth voltage V is applied to the second upper gate line UL1b via the gate pad P1b of the second upper gate line UL1b in the +X direction. UL1b It can be applied.

[0122] For the operation of the third lower transistor LT2a of the second memory cell string CSTR2, a sixth voltage V is applied to the third lower gate line LL2a via the gate pad P2a of the third lower gate line LL2a in the +X direction. LT2a can be applied. The magnitude of the sixth voltage V LT2a can be substantially the same as the magnitude of the first voltage V LT1a .

[0123] For the operation of the fourth lower transistor LT2b of the second memory cell string CSTR2, a seventh voltage V is applied to the fourth lower gate line LL2b via the gate pad P2a of the fourth lower gate line LL2b in the +X direction. LT2b can be applied. The magnitude of the seventh voltage V LT2b can be substantially the same as the magnitude of the second voltage V LT1b .

[0124] For the operation of the second memory cell transistor MCT2 of the second memory cell string CSTR2, an eighth voltage V is applied to the second word line WL2 via the gate pad P2a of the second word line WL2 in the +X direction. WL2 can be applied. The magnitude of the eighth voltage V WL2 can be substantially the same as the magnitude of the third voltage V WL1 .

[0125] For the operation of the third upper transistor UT2a of the second memory cell string CSTR2, a ninth voltage V is applied to the third upper gate line UL2a via the gate pad P2b of the third upper gate line UL2a in the -X direction. UL2a can be applied. The magnitude of the ninth voltage V UL2a can be substantially the same as the magnitude of the fourth voltage V UL1a .

[0126] For the operation of the fourth upper transistor UT2b of the second memory cell string CSTR2, a tenth voltage V is applied to the fourth upper gate line UL2b via the gate pad P2b of the fourth upper gate line UL2b in the -X direction. UL2b can be applied. The magnitude of the tenth voltage V UL2b can be substantially the same as the magnitude of the fifth voltage V UL1b .

[0127] In the first memory mat MAT1, an erase voltage is applied in the +X direction to the first upper gate line UL1a so that gate-induced leakage current can occur in the first upper transistor UT1a, which can be an upper erase transistor, and an erase voltage is applied in the -X direction to the first lower gate line LL1a so that gate-induced leakage current can occur in the first lower transistor LT1a, which can be a lower erase transistor.

[0128] In the second memory mat MAT2, an erase voltage is applied in the -X direction to the third upper gate line UL2a so that gate-induced leakage current can occur in the third upper transistor UT2a, which can be an upper erase transistor, and an erase voltage is applied in the +X direction to the third lower gate line LL2a so that gate-induced leakage current can occur in the third lower transistor LT2a, which can be a lower erase transistor.

[0129] Hereinafter, a component referred to as a "gate contact plug" can be electrically connected while contacting the gate pads P1a, P1b, P2a, P2b as part of the routing wiring structures 1115a1, 1115a2, 1115b1, 1115b2. Therefore, a voltage can be applied to the gate pads P1a, P1b, P2a, P2b through the component referred to as the "gate contact plug".

[0130] The above-described first and second lower gate lines LL1a, LL1b, the first word line WL1, and the first and second upper gate lines UL1a, UL1b may be the first side conductive layers LL1a, LL1b, WL1, UL1a, UL1b disposed in the first connection region R1a, the first memory cell array region M1, and the second connection region R1b. The third and fourth lower gate lines LL2a, LL2b, the second word line WL2, and the third and fourth upper gate lines UL2a, UL2b may be the second side conductive layers LL2a, LL2b, WL2, UL2a, UL2b disposed in the third connection region R2a, the second memory cell array region M2, and the fourth connection region R2b.

[0131] The first side conductive layers LL1a, LL1b, WL1, UL1a, UL1b can extend from the first connection region R1a to the second connection region R1b. The first side conductive layers LL1a, LL1b, WL1, UL1a, UL1b include a first lower conductive group LL1a, LL1b, WL1 having a first lower pad P1a arranged in a stepped shape within the second connection region R1b, and a first upper conductive group UL1a, UL1b having a first upper pad P1b arranged in a stepped shape within the first connection region R1a and disposed at a level higher than that of the first lower conductive group LL1a, LL1b, WL1.

[0132] Among the first side conductive layers LL1a, LL1b, WL1, UL1a, UL1b, the number of the first side conductive layers of the first lower conductive group LL1a, LL1b, WL1 may be larger than the number of the first side conductive layers of the first upper conductive group UL1a, UL1b.

[0133] The second side conductive layers LL2a, LL2b, WL2, UL2a, and UL2b can extend from the third connection region R2a to the fourth connection region R2b. The second side conductive layers LL2a, LL2b, WL2, UL2a, and UL2b are arranged at the same level as the first lower conductive groups LL1a, LL1b, WL1 within the third connection region R2b, and include a second lower conductive group LL2a, LL2b, WL2 having second lower pads P2a arranged in a stepped shape, and a second upper conductive group UL2a, UL2b arranged at the same level as the first upper conductive groups UL1a, UL1b and having second upper pads P2b arranged in a stepped shape within the fourth connection region R2a.

[0134] Next, with reference to FIGS. 4, 5, 6a, 6b, 6c, and 6d together with FIGS. 1a to 3b described above, an exemplary example of the semiconductor device CH will be described. In FIGS. 4, 5, 6a, 6b, 6c, and 6d, FIG. 4 is a top view showing an exemplary example of the semiconductor device CH, FIG. 5 is a cross-sectional view showing a region taken along line I-I' of FIG. 4, FIG. 6a is a partial enlarged view showing the region represented by "A" in FIG. 5, FIG. 6b is a partial enlarged view showing the region represented by "B" in FIG. 5, FIG. 6c is a partial enlarged view showing the region represented by "C" in FIG. 5, and FIG. 6d is a partial enlarged view showing the region represented by "D" in FIG. 5.

[0135] In an embodiment, since the first memory mat MAT1 and the second memory mat MAT2 can have a mirror-symmetric structure, hereinafter, the structure of the second memory mat MAT2 can be understood from the description of the structure of the first memory mat MAT1. Therefore, hereinafter, the description will focus on the structure of the first memory mat MAT1.

[0136] Referring to FIGS. 1a to 3b and FIGS. 4 to 6d, the width in the +X direction of each of the second and third connection regions R1b and R2b described above may be larger than the width in the +X direction of each of the first and fourth connection regions R1a and R2a.

[0137] The semiconductor device CH can further include a separation structure SP that separates the first memory blocks BLK1 from each other in the Y direction and separates the second memory blocks BLK2 from each other in the Y direction. Each of the separation structures SP can be disposed between the first memory blocks BLK1 adjacent to each other in the Y direction and between the second memory blocks BLK2 adjacent to each other in the Y direction.

[0138] The separation structure SP can extend from a portion located between the first memory blocks BLK1 to between the second memory blocks BLK2.

[0139] The first structure ST1 can further include a base 103, a plate pattern 106 on the base 103, and an insulating pattern 109 on a side surface of the plate pattern 106.

[0140] The base 103 can include an insulating material. The plate pattern 106 can include at least one of a semiconductor material and a conductive material. For example, at least a part of the plate pattern 106 can include a conductive material such as doped silicon. For example, at least a part of the plate pattern 106 can include polysilicon having an N-type conductivity type. Depending on the embodiment, the plate pattern 106 may include a doped polysilicon layer and a metal layer overlapping the doped silicon layer vertically. The insulating pattern 109 can include an insulating material such as silicon oxide. At least a part of the plate pattern 106 may be the aforementioned first common source (CS1 in FIGS. 3A and 3B).

[0141] In an embodiment, the plate pattern 106 can be referred to as a source structure or a common source.

[0142] Each of the first memory mat MAT1 and the second memory mat MAT2 can include a gate electrode GE. For example, in each of the first and second memory mats MAT1 and MAT2, the first structure ST1 can include gate electrodes GE spaced apart from each other in the vertical direction Z. Each of the gate electrodes GE can be made of W, Ru, Mo, Nb, Ni, Co, Ti, Ta, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but is not limited thereto. For example, each of the gate electrodes GE can include a single layer or multiple layers of the above-described substances.

[0143] In one example, the gate electrode GE can include a gate electrode formed of a first material and one or more gate electrodes formed of a second material different from the first material.

[0144] In other examples, the gate electrodes GE may be formed of the same material as each other.

[0145] The gate electrode GE can include a lower gate electrode GE_L, an intermediate gate electrode GE_M on the lower gate electrode GE_L, and an upper gate electrode GE_U on the intermediate gate electrode GE_M.

[0146] The lower gate electrode GE_L can include a first lower gate electrode GE_La and a second lower gate electrode GE_Lb on the first lower gate electrode GE_La.

[0147] The first lower gate electrode GE_La may be the first lower gate line (LL1a in FIGS. 3a and 3b) described above, and the second lower gate electrode GE_Lb may be the second lower gate line (LL1b in FIGS. 3a and 3b) described above.

[0148] The above-mentioned intermediate gate electrode GE_M may include a first intermediate gate electrode GE_Ma and a second intermediate gate electrode GE_Mb on the first intermediate gate electrode GE_Ma. The intermediate gate electrode GE_M may include the above-mentioned first word line (WL1 in FIGS. 3a and 3b).

[0149] The upper gate electrode GE_U may include a first upper gate electrode GE_Ua and a second upper gate electrode GE_Ub on the first upper gate electrode GE_Ua. At least one of the first upper gate electrodes GE_Ua may be the above-mentioned first upper gate line (UL1a in FIGS. 3a and 3b). For example, among the first upper gate electrodes GE_Ua, the gate electrode located relatively above may be the above-mentioned first upper gate line (UL1a in FIGS. 3a and 3b), and the gate electrode located relatively below may be a dummy gate electrode. The second upper gate electrode GE_Ub may be the above-mentioned second upper gate line (UL1b in FIGS. 3a and 3b).

[0150] In one example, the second upper gate electrode GE_Ub may be the string selection gate line of the above-mentioned string selection transistor, and at least one of the first upper gate electrodes GE_Ua may be the erase control gate line of the above-mentioned erase control transistor.

[0151] The first structure ST1 may include a stacked structure GS. The stacked structure GS may include a first stacked structure GS1 and a second stacked structure GS2 on the first stacked structure GS1.

[0152] The first stacked structure GS1 may include the lower gate electrode GE_L and the first intermediate gate electrode GE_Ma. The second stacked structure GS2 may include the second intermediate gate electrode GE_Mb and the upper gate electrode GE_U.

[0153] The first structure ST1 may further include interlayer insulating layers ILDa and ILDb. The interlayer insulating layers ILDa and ILDb may include a first interlayer insulating layer ILDa and a second interlayer insulating layer ILDb. The first interlayer insulating layer ILDa may be alternately laminated with a gate electrode including the lower gate electrode GE_L and the first intermediate gate electrode GE_Ma. The second interlayer insulating layer ILDb may be alternately laminated with a gate electrode including the second intermediate gate electrode GE_Mb and the first upper gate electrode GE_Ua.

[0154] The gate electrode GE can be laminated in the vertical direction Z spaced apart from each other within the first memory cell array region M1, and can extend from the first memory cell array region M1 to the first connection region R1a and the second connection region R1b.

[0155] Within the first memory cell array region M1, each of the lower gate electrodes GE_L can have a first thickness T1, each of the intermediate gate electrodes GE_M can have a second thickness T2, each of the first upper gate electrodes GE_Ua can have a third thickness T3, and the second upper gate electrode GE_Ub can have a fourth thickness T4.

[0156] The third thickness T3 may be greater than at least one of the first thickness T1 and the second thickness T2. For example, the third thickness T3 may be greater than each of the first and second thicknesses T1 and T2. The fourth thickness T4 may be greater than the third thickness T3. The fourth thickness T4 may be greater than each of the first, second, and third thicknesses T1, T2, and T3.

[0157] The lower gate electrode GE_L and the intermediate gate electrode GE_M may have gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c) disposed in the second connection region R1b. The respective thicknesses of the gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c) of the lower gate electrode GE_L and the intermediate gate electrode GE_M may be greater than the respective first and second thicknesses (T1, T2 in FIG. 6a).

[0158] The upper gate electrode GE_U may have gate pads (G_P1a in FIG. 6b, G_P1b in FIG. 5) disposed in the first connection region R1a. The respective thicknesses of the gate pads (G_P1a in FIG. 6b) of the first upper gate electrode GE_Ua may be greater than the third thickness (T3 in FIG. 6a). The gate pad (G_P1b in FIG. 5) of the second upper gate electrode GE_Ub may have the fourth thickness (T4 in FIG. 6a).

[0159] The gate pads (G_P1a in FIG. 6b, G_P1b in FIG. 5) of the upper gate electrode GE_U may be the gate pads P1b of the first and second upper gate lines UL1a, UL1b described in FIG. 3a.

[0160] The gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c) of the lower gate electrode GE_L and the intermediate gate electrode GE_M may be the gate pads P1a of the first and second lower gate lines LL1a, LL1b and the first word line WL1 described in FIG. 3a.

[0161] The gate pad of the gate electrode GE has a first lower gate pad (G_P2a1 in FIG. 6d) having a stepped structure that decreases in order in the +X direction, a second lower gate pad (G_P2a2 in FIG. 6c) having a stepped structure that decreases in order in the +X direction, a first upper gate pad (G_P2b1 in FIG. 6d) having a stepped structure that decreases in order in the +X direction, a second upper gate pad (G_P2b2 in FIG. 6c) having a stepped structure that decreases in order in the +X direction, and a third upper gate pad (G_P1a in FIG. 6b) having a stepped structure that decreases in order in the -X direction.

[0162] The first lower gate pad (G_P2a1 in FIG. 6d) can be composed of the gate pad of the first intermediate gate electrode located at the lower part of the first intermediate gate electrode GE_Ma and the gate pad of the lower gate electrode GE_L. The second lower gate pad (G_P2a2 in FIG. 6c) can be composed of the gate pad of the first intermediate gate electrode located at the upper part of the first intermediate gate electrode GE_Ma. The first upper gate pad (G_P2b1 in FIG. 6d) can be composed of the gate pad of the second intermediate gate electrode located at the lower part of the second intermediate gate electrode GE_Mb. The second upper gate pad (G_P2b2 in FIG. 6c) can be composed of the gate pad of the second intermediate gate electrode located at the upper part of the second intermediate gate electrode GE_Mb. The third upper gate pad (G_P1a in FIG. 6b) can be composed of the gate pad of the first upper gate electrode GE_Ua.

[0163] The above-described second lower gate pad (G_P2a2 in FIG. 6c) can be arranged at a level higher than that of the above-described first lower gate pad (G_P2a1 in FIG. 6d). The above-described first upper gate pad (G_P2b1 in FIG. 6d) can be arranged at a level higher than that of the above-described second lower gate pad (G_P2a2 in FIG. 6c). The above-described second upper gate pad (G_P2b2 in FIG. 6c) can be arranged at a level higher than that of the above-described first upper gate pad (G_P2b1 in FIG. 6d). The above-described third upper gate pad (G_P1a in FIG. 6b) can be arranged at a level higher than that of the above-described second upper gate pad (G_P2b2 in FIG. 6c).

[0164] The above-described first lower gate pad (G_P2a1 in FIG. 6d), the above-described second lower gate pad (G_P2a2 in FIG. 6c), the above-described first upper gate pad (G_P2b1 in FIG. 6d), and the above-described second upper gate pad (G_P2b2 in FIG. 6c) arranged in the above-described second connection region R1b may not overlap in the above-described vertical direction Z.

[0165] The above-described first lower gate pad (G_P2a1 in FIG. 6d) can be arranged at a position farther from the above-described first memory cell array region M1 than the above-described second lower gate pad (G_P2a2 in FIG. 6c). The above-described first upper gate pad (G_P2b1 in FIG. 6d) can be arranged at a position farther from the above-described first memory cell array region M1 than the above-described second upper gate pad (G_P2b2 in FIG. 6c).

[0166] In an embodiment, the positions where the above-described first lower gate pad (G_P2a1 in FIG. 6d), the above-described second lower gate pad (G_P2a2 in FIG. 6c), the above-described first upper gate pad (G_P2b1 in FIG. 6d), and the above-described second upper gate pad (G_P2b2 in FIG. 6c) are separated from the above-described first memory cell array region M1 are not limited to the form shown in FIG. 5 and can be deformed into various forms.

[0167] The first structure ST1 can further include an insulating capping structure (INS_C in FIG. 4). The insulating capping structure (INS_C in FIG. 4) can be disposed between the first memory mat MAT1 and the second memory mat MAT2.

[0168] The insulating capping structure (INS_C in FIG. 4) can include a first lower insulating capping pattern (INS_C1c in FIG. 6d), a second lower insulating capping pattern (INS_C1b in FIG. 6c), a first upper insulating capping pattern (INS_C2c in FIG. 6d), and a second upper insulating capping pattern (INS_C2b in FIG. 6c).

[0169] The first lower insulating capping pattern (INS_C1c in FIG. 6d) and the second lower insulating capping pattern (INS_C1b in FIG. 6c) can be disposed at a level lower than that of the second stacked structure GS2. For example, the first lower insulating capping pattern (INS_C1c in FIG. 6d) and the second lower insulating capping pattern (INS_C1b in FIG. 6c) may be disposed at a level lower than that of the lowermost second intermediate gate electrode among the second intermediate gate electrodes GE_Mb.

[0170] The first lower insulating capping pattern (INS_C1c in FIG. 6d) is disposed on the first lower gate pad (G_P2a1 in FIG. 6d), penetrates through a gate electrode and an interlayer insulating layer that are at a level higher than that of the first lower gate pad (G_P2a1 in FIG. 6d) in the vertical direction Z, and can penetrate through the first lower gate electrode GE_La. Therefore, end portions of the lower gate electrode GE_L and the first intermediate gate electrode GE_Ma located in the +X direction can be adjacent to the first lower insulating capping pattern (INS_C1c in FIG. 6d).

[0171] The above-described second lower insulating capping pattern (INS_C1b in FIG. 6c) is disposed on the above-described second lower gate pad (G_P2a2 in FIG. 6c) and can penetrate through the gate electrode and the interlayer insulating layer at a level higher than that of the above-described second lower gate pad (G_P2a2 in FIG. 6c) in the above-described vertical direction Z.

[0172] The above-described first upper insulating capping pattern (INS_C2c in FIG. 6d) and the above-described second upper insulating capping pattern (INS_C2b in FIG. 6c) can be disposed at a level higher than that of the uppermost first intermediate gate electrode among the above-described first intermediate gate electrodes GE_Ma.

[0173] The above-described first upper insulating capping pattern (INS_C2c in FIG. 6d) is disposed on the above-described first upper gate pad (G_P2b1 in FIG. 6d) and can penetrate through the second intermediate gate electrode GE_Mb and the above-described first upper gate electrode GE_Ua while covering the above-described first upper gate pad (G_P2b1 in FIG. 6d) in the above-described vertical direction Z.

[0174] The above-described second upper insulating capping pattern (INS_C2b in FIG. 6c) is disposed on the above-described second upper gate pad (G_P2b2 in FIG. 6c) and can penetrate through the gate electrode and the interlayer insulating layer at a level higher than that of the gate pad of the above-described second upper gate pad (G_P2b2 in FIG. 6c) in the above-described vertical direction Z.

[0175] The gate electrode GE in the above-described first memory mat MAT1 can be separated from the gate electrode GE in the above-described second memory mat MAT2.

[0176] The lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua in the first memory mat MAT1 can be separated from the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua in the second memory mat MAT2 by the first lower insulating capping pattern (INS_C1c in FIG. 6d), the second lower insulating capping pattern (INS_C1b in FIG. 6c), the first upper insulating capping pattern (INS_C2c in FIG. 6d), and the second upper insulating capping pattern (INS_C2b in FIG. 6c).

[0177] Among the gate electrodes GE, the gate electrode GE_F located between the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua in the first memory mat MAT1 and the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua in the second memory mat MAT2 may be an electrically isolated dummy gate electrode. For example, in FIGS. 6c and 6d, the dummy gate electrode GE_F may be a gate electrode GE located on the right side of the second lower insulating capping pattern (INS_C1b in FIG. 6c), a gate electrode GE located on the right side of the first upper insulating capping pattern (INS_C2c in FIG. 6d), and a gate electrode GE located on the right side of the second upper insulating capping pattern (INS_C2b in FIG. 6c).

[0178] The first structure ST1 may further include an outer capping insulating structure (INS_C1a, INS_C2a in FIG. 6b).

[0179] The above-described outer capping insulating structure (INS_C1a, INS_C2a in FIG. 6b) can be arranged to surround the outer surfaces of the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua of the first and second memory mats MAT1 and MAT2. For example, a part of the above-described outer capping insulating structure (INS_C1a, INS_C2a in FIG. 6b) can be arranged on the outer surfaces of the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua to cover the third upper gate pad (G_P1a in FIG. 6b) as shown in FIG. 6b.

[0180] The above-described insulating capping structure (INS_C in FIG. 4) can include a first lower insulating capping pattern (INS_C1c in FIG. 6d), a second lower insulating capping pattern (INS_C1b in FIG. 6c), a first upper insulating capping pattern (INS_C2c in FIG. 6d), and a second upper insulating capping pattern (INS_C2b in FIG. 6c).

[0181] The above-described outer capping insulating structure (INS_C1a, INS_C2a in FIG. 6b) can include a first outer capping insulating structure (INS_C1a in FIG. 6b) and a second outer capping insulating structure (INS_C2a in FIG. 6b).

[0182] The first outer capping insulating structure (INS_C1a in FIG. 6b) can be arranged on the insulating pattern 109 and on the outer surfaces of the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first interlayer insulating layer ILDa.

[0183] The second outer capping insulating structure (INS_C2a in FIG. 6b) can be arranged on the first outer capping insulating structure (INS_C1a in FIG. 6b) and on the outer surfaces of the first upper gate electrode GE_Ua and the second interlayer insulating layer ILDb to cover the third upper gate pad (G_P1a in FIG. 6b).

[0184] The upper surfaces of the outer capping insulating structure (INS_C1a, INS_C2a in FIG. 6b), the first upper insulating capping pattern (INS_C2c in FIG. 6d), and the second upper insulating capping pattern (INS_C2b in FIG. 6c) can be arranged at a level higher than that of the uppermost first upper gate electrode among the first upper gate electrodes GE_Ua.

[0185] The upper surfaces of the outer capping insulating structure (INS_C1a, INS_C2a in FIG. 6b), the first upper insulating capping pattern (INS_C2c in FIG. 6d), and the second upper insulating capping pattern (INS_C2b in FIG. 6c) can be coplanar with the upper surface of the uppermost second interlayer insulating layer among the second interlayer insulating layers ILDb.

[0186] The first structure ST1 can further include a buffer insulating layer 120 disposed on the upper surfaces of the outer capping insulating structure (INS_C1a, INS_C2a in FIG. 6b), the first upper insulating capping pattern (INS_C2c in FIG. 6d), and the second upper insulating capping pattern (INS_C2b in FIG. 6c) and on the upper surface of the uppermost second interlayer insulating layer among the second interlayer insulating layers ILDb. The buffer insulating layer 120 may be an etching stop layer. The buffer insulating layer 120 can include an insulating material such as SiN, SiCN, or SiBN. The second upper gate electrode GE_Ub can be arranged at a level higher than that of the buffer insulating layer 120.

[0187] The first structure ST1 can further include a vertical memory structure VS that penetrates the gate electrode GE. For example, the vertical memory structure VS may be arranged in the first and second memory cell array regions M1, M2.

[0188] Each of the vertical memory structures VS can include a first vertical memory structure VS_L, a second vertical memory structure VS_U, and a connecting structure VS_C.

[0189] The first vertical memory structure VS_L can penetrate the lower gate electrode GE_L, the intermediate gate electrode GE_M, the first upper gate electrode GE_Ua, the first interlayer insulating layer ILDa, and the second interlayer insulating layer ILDb, and can contact the plate pattern 106.

[0190] The first vertical memory structure VS_L can include the first insulating core region 116, a first channel layer 114 disposed on the side surface of the first insulating core region 116 and connected to the plate pattern 106, and an information storage structure 112 disposed on the outer side surface of the first channel layer 114.

[0191] The first vertical memory structure VS_L can further include a first pad pattern 118 disposed on the first insulating core region 116 and connected to the first channel layer 114.

[0192] The first insulating core region 116 can include an insulating material such as silicon oxide.

[0193] The first channel layer 114 can cover the side surface and the lower surface of the first insulating core region 116. The first channel layer 114 can include a semiconductor material such as polysilicon, single crystal silicon, or an oxide semiconductor. The portion of the plate pattern 106 in contact with the first channel layer 114 can include at least doped silicon. For example, the plate pattern 106 can include polysilicon having an N-type conductivity type. Depending on the embodiment, the plate pattern 106 can include polysilicon having an N-type conductivity type and polysilicon having a P-type conductivity type.

[0194] The information storage structure 112 can include a first dielectric layer 112a, a second dielectric layer 112c, and an information storage layer 112b between the first and second dielectric layers 112a, 112c. The second dielectric layer 112c can contact the first channel layer 114.

[0195] The above-described first dielectric layer 112a may be a blocking dielectric layer. The first dielectric layer 112a can include at least one of silicon oxide and a high dielectric material. The second dielectric layer 112c may be a tunnel dielectric layer. The second dielectric layer 112c can include silicon oxide or silicon oxide doped with impurities.

[0196] The above-described information storage layer 112b can include a material capable of trapping charge to store information, for example, silicon nitride. The information storage layer 112b can include a region capable of storing information in a semiconductor device such as a flash memory device.

[0197] In the embodiment, the above-described information storage structure 112 includes the above-described information storage layer 112b capable of trapping charge to store information, but the embodiment is not limited thereto. For example, the information storage structure 112 may be an information storage structure used in a ferroelectric memory capable of storing information using remanent polarization by dipoles.

[0198] The above-described first pad pattern 118 can be disposed at a level higher than the above-described first upper gate electrode GE_Ua. The first pad pattern 118 can include polysilicon. For example, the first pad pattern 118 may include doped polysilicon.

[0199] The above-described first vertical memory structure VS_L can include a lower vertical portion VS_La, an upper vertical portion VS_Lc on the lower vertical portion VS_La, and a junction portion VS_Lb between the lower vertical portion VS_La and the upper vertical portion VS_Lc.

[0200] In the first vertical memory structure VS_L, the joining portion VS_Lb can be arranged at a level higher than the uppermost first intermediate gate electrode among the first intermediate gate electrodes GE_Ma, and at a level lower than the lowermost second intermediate gate electrode among the second intermediate gate electrodes GE_Mb.

[0201] The joining portion VS_Lb can have a side surface that bends from the side surfaces of the lower vertical portion VS_La and the upper vertical portion VS_Lc.

[0202] The connecting structure VS_C can penetrate the buffer insulating layer 120 and be connected to the first pad pattern 118 and the first channel layer 114. The connecting structure VS_C can include polysilicon. The vertical central axis of the connecting structure VS_C and the vertical central axis of the first vertical memory structure VS_L do not have to be aligned.

[0203] The vertical central axis of the second vertical memory structure VS_U does not have to be aligned with the vertical central axis of the first vertical memory structure VS_L.

[0204] The second vertical memory structure VS_U can penetrate the second upper gate electrode GE_Ub and be connected to the connecting structure VS_C.

[0205] The second vertical memory structure VS_U can include a second insulating core region 126, a second channel layer 124 arranged on the side surface of the second insulating core region 126 and connected to the connecting structure VS_C, a gate dielectric layer 122 arranged on the outer side surface of the second channel layer 124, and a second pad pattern 128 arranged on the second insulating core region 126.

[0206] The second channel layer 124 can include at least one material layer. For example, the second channel layer 124 can include a first layer 124a and a second layer 124b. The second layer 124b can be connected to the connection structure VS_C by covering the side and bottom surfaces of the second insulating core region 126. The first layer 124a can be disposed between the second layer 124b and the gate dielectric layer 122.

[0207] The gate dielectric layer 122 can include at least one of silicon oxide and a high dielectric.

[0208] The first layer 124a and the second layer 124b of the second channel layer 124 can include a semiconductor material such as polysilicon, single crystal silicon, or an oxide semiconductor. The first layer 124a and the second layer 124b can be formed of the same semiconductor material as each other, but the embodiments are not limited thereto. For example, the first layer 124a and the second layer 124b may be formed of the same semiconductor material as each other.

[0209] In other embodiments, the second channel layer 124 may be formed of one layer.

[0210] The second pad pattern 128 can include polysilicon. For example, the second pad pattern 128 can include doped polysilicon having an N-type conductivity type.

[0211] The first structure ST1 can further include a gate contact plug 160 and an upper gate contact plug 163.

[0212] The gate contact plug 160 can include a first gate contact plug 160a and a second gate contact plug 160b. The first gate contact plug 160a can be electrically connected to the third upper gate pad (G_P1a in FIG. 6b) of the first upper gate electrode GE_Ua. The second gate contact plug 160b can be electrically connected to the gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c) of the lower gate electrode GE_L and the intermediate gate electrode GE_M.

[0213] The gate contact plug 160 can include a connection plug portion 160P that is connected while contacting the gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6C, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c), a lower plug portion 160_La below the connection plug portion 160P, and a first upper plug portion 160_Lb on the connection plug portion 160P.

[0214] Since the gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c) can be arranged at different levels from each other, the connection plug portion 160P that contacts and is connected to the gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c) can also be arranged at different levels from each other.

[0215] The side surface of the connection plug portion 160P can contact the side surfaces of the gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c).

[0216] The gate contact plug 160 can further include a second upper plug portion 160_U on the first upper plug portion 160_Lb.

[0217] For example, each of the gate contact plugs 160 may include the connection plug portion 160P, the lower plug portion 160_La extending downward from the connection plug portion 160P, and the first upper plug portion 160_Lb extending upward from the connection portion 160P. Each of the gate contact plugs 160 may include the second upper plug portion 160_U extending upward from the first upper plug portion 160_Lb.

[0218] In each of the gate contact plugs 160, the width of the connection plug portion 160P may be greater than the width of the lower plug portion 160_La adjacent to the connection plug portion 160P, and may also be greater than the width of the first upper plug portion 160_Lb adjacent to the connection plug portion 160P.

[0219] In each of the gate contact plugs 160, the width of the second upper plug portion 160_U and the width of the first upper plug portion 160_Lb may be different from each other. For example, the width of the second upper plug portion 160_U adjacent to the first upper plug portion 160_Lb may be greater than the width of the first upper plug portion 160_Lb adjacent to the second upper plug portion 160_U.

[0220] The connection plug portion 160P of the first gate contact plug 160a connected to the third upper gate pad (G_P1a in FIG. 6b) of the first upper gate electrode GE_Ua may be arranged at a higher level than the connection plug portion 160P of the second gate contact plug 160b connected to the gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c) of the lower gate electrode GE_L and the intermediate gate electrode GE_M.

[0221] Each of the gate contact plugs 160 can have a lower surface disposed at a level lower than the lowest gate electrode GE_La among the gate electrodes GE and an upper surface disposed at a level higher than the highest gate electrode GE_Ub among the gate electrodes GE.

[0222] Each of the gate contact plugs 160 can extend continuously from the lower surface to the upper surface. For example, each of the gate contact plugs 160 can include one conductive layer that extends continuously from a level lower than the lowest gate electrode GE_La among the gate electrodes GE to a level higher than the highest gate electrode GE_Ub among the gate electrodes GE.

[0223] The first structure ST1 can further include an isolation insulating layer 158. The isolation insulating layer 158 can be disposed between a gate electrode among the gate electrodes GE that is not electrically connected to the gate contact plug 160 and the gate contact plug 160. For example, the isolation insulating layer 158 can be disposed between the lower plug portion 160_La and the gate electrode GE, and between the first upper plug portion 160_Lb and the gate electrode GE. The isolation insulating layer 158 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0224] The upper gate contact plug 163 can be disposed on the gate pad G_P1b of the second upper gate electrode GE_Ub. The upper gate contact plug 163 can be in contact with the gate pad G_P1b of the second upper gate electrode GE_Ub to be electrically connected. The lower surface of the upper gate contact plug 163 can be in contact with the gate pad G_P1b of the second upper gate electrode GE_Ub and can be disposed at a level higher than the lower surface of the gate pad G_P1b.

[0225] The above-mentioned bit line BL can be arranged at a level higher than that of the second upper gate electrode UE_Ub and the gate contact plug 160.

[0226] The first structure ST1 is arranged between the bit line BL and the vertical memory structure VS, and can further include a bit line stud BLP that is electrically connected to the bit line BL and the vertical memory structure VS. Therefore, the bit line BL can be electrically connected to the second pad pattern 128 of the vertical memory structure VS by the bit line stud BLP.

[0227] The first structure ST1 is arranged on the gate contact plug 160 and can further include a gate stud 166 that is electrically connected to the gate contact plug 160.

[0228] The first structure ST1 can further include lower routing wiring structures 169, 172, 175. The lower routing wiring structures 169, 172, 175 can include a first horizontal wiring 169, a first via 172, and a first bonding pad 175. The first bonding pad 175 can be arranged at a level higher than that of the first horizontal wiring 169 and the first via 172.

[0229] The first structure ST1 can further include the first insulating structure INS_U. The first insulating structure INS_U can be arranged on the buffer insulating layer 120 and can have an upper surface that is coplanar with the upper surface of the first bonding pad 175.

[0230] The second structure ST2 can include a substrate 206, a peripheral active region 209a under the substrate 206, and a peripheral element isolation region 209s that limits the peripheral active region 209a under the substrate 206. The substrate 206 may be a semiconductor substrate.

[0231] The second structure ST2 can further include the peripheral element PTR below the substrate 206, the upper routing wiring structures 220, 225, and the second insulating structure 230.

[0232] The peripheral element PTR can constitute the peripheral circuit PC described above.

[0233] The peripheral element PTR can include peripheral transistors including peripheral source / drain regions PTR_SD spaced apart from each other within the peripheral active region 209a, a peripheral channel region PTR_CH between the peripheral source / drain regions PTR_SD, and a peripheral gate PTR_G below the peripheral active region 209a.

[0234] The upper routing wiring structures 220, 225 can be embedded in the upper insulating structure 230 and can be electrically connected to the peripheral element PTR. The upper routing wiring structures 220, 225 can include a wiring portion 220 including a horizontal portion and a vertical portion, and a second bonding pad 225 having a lower surface coplanar with the lower surface of the second insulating structure 230 below the wiring portion 220. The first bonding pad 175 and the second bonding pad 225 can be joined to each other by an intermetallic bonding process. The lower routing wiring structures 169, 172, 175, the upper routing wiring structures 220, 225, the gate contact plug 160, the gate stud 166, and the upper gate contact plug 163 can constitute the routing wiring structures (1115a, 1115b in FIG. 2) described above.

[0235] Hereinafter, with reference to FIGS. 9 to 22, various modifications of the above-described embodiments for increasing the integration degree and improving the reliability of the semiconductor device CH will be described. Various modifications of the components of the above-described embodiments to be described below will be described centering on the components to be modified, the components to be replaced, or the components to be added. Further, the components that can be modified or replaced in the various modifications to be described below can be combined with each other or combined with the above-described components to configure a semiconductor device according to an embodiment of the present invention.

[0236] FIG. 7 is a cross-sectional view showing a region cut along the line I-I' of FIG. 4 to explain a modification of a semiconductor device according to an embodiment of the present invention, FIG. 8a is a partial enlarged view of the region represented by "Aa" in FIG. 7, and FIG. 8b is a partial enlarged view of the region represented by "Ba" in FIG. 7.

[0237] Referring to FIGS. 4, 7, 8a, and 8b, in the above-described semiconductor device CH, the above-described second upper gate electrode (GE_Ub in FIGS. 5 and 6a) described with reference to FIGS. 5 to 6d can be omitted. Therefore, the above-described first upper gate electrode (GE_Ua in FIGS. 5 to 6d) can be described as an upper gate electrode GE_U'. Therefore, the upper gate electrode GE_U' can have a gate pad G_P1' that is substantially the same as the above-described gate pad (G_P1a in FIG. 6b).

[0238] In an embodiment, by omitting the second upper gate electrode (GE_Ub in FIGS. 5 and 6a), the upper gate electrode GE_U' can include a selection gate electrode that can be a string selection gate line of the above-described string selection transistor, and an erase control gate electrode that can be an erase control gate line of the above-described erase control transistor. For example, the topmost gate electrode and the second topmost gate electrode among the upper gate electrodes GE_U' may be erase control gate electrodes that can be the erase control gate lines of the above-described erase control transistors, and the gate electrode below the erase control gate electrode may be a selection gate electrode that can be the string selection gate line of the above-described string selection transistor.

[0239] The above-described vertical memory structure (VS in FIGS. 5 and 6a) can be replaced with a vertical memory structure VS' as shown in FIGS. 7 and 8a. For example, in the above-described vertical memory structure (VS in FIGS. 5 and 6a), the second vertical memory structure VS_U and the connection structure VS_C can be omitted. Therefore, the cross-sectional structure of the vertical memory structure VS' can be substantially the same as the cross-sectional structure of the first vertical memory structure VS_L in FIG. 6a. The above-described bit line stud BLP can be connected to the first pad pattern 118 of the vertical memory structure VS'.

[0240] FIG. 9 is a cross-sectional view showing a region cut along the line I-I' of FIG. 4 to explain a modification of the semiconductor device according to an embodiment of the present invention.

[0241] In the modification, referring to FIGS. 4 and 9, the gate pads (G_P2a1 in FIG. 6d, G_P2a2 in FIG. 6c, G_P2b1 in FIG. 6d, G_P2b2 in FIG. 6c) of the second intermediate gate electrode GE_Mb, the first intermediate gate electrode GE_Ma, and the lower gate electrode GE_L disposed in the above-described second connection region R1b can be deformed into gate pads GP_2b' and GP_2a' arranged in a stepped shape that decreases in order in the +X direction as shown in FIG. 9.

[0242] The above-described first lower insulating capping pattern (INS_C1c in FIG. 6d) and the above-described second lower insulating capping pattern (INS_C1b in FIG. 6c) can be deformed into a lower insulating capping pattern INS_C3a that covers the gate pad GP_2a' of the first intermediate gate electrode GE_Ma and the lower gate electrode GE_L as shown in FIG. 9.

[0243] The above-described first upper insulating capping pattern (INS_C2c in FIG. 6d) and the above-described second upper insulating capping pattern (INS_C2b in FIG. 6c) can be deformed into an upper insulating capping pattern INS_C3b that covers the gate pad GP_2b' of the second intermediate gate electrode GE_Mb.

[0244] The upper insulating capping pattern INS_C3b is disposed on the lower insulating capping pattern INS_C3a and can be in contact with the lower insulating capping pattern INS_C3a.

[0245] The connecting plug portion 160P of the above-described second gate contact plug 160b can be arranged according to the arrangement shape of the gate pads GP_2b' and GP_2a'. Therefore, the connecting plug portion 160P of the second gate contact plug 160b can be arranged to be lower in order in the +X direction.

[0246] FIG. 10 is a cross-sectional view showing a region cut along the line I-I' of FIG. 4 to explain a modified example of a semiconductor device according to an embodiment of the present invention.

[0247] Referring to FIGS. 4 and 10, the second intermediate gate electrode GE_Mb, the first intermediate gate electrode GE_Ma, and the lower gate electrode GE_L disposed in the second connection region R1b can have gate pads GP_2bb and GP_2aa arranged in descending order in the +X direction, like the gate pads (GP_2b' and GP_2a' in FIG. 9) described with reference to FIG. 9. The first upper gate electrode GE_Ua can have a gate pad GP_1 arranged in a stepped shape that descends in the -X direction, like the gate pad (G_P1a in FIG. 6b) described above.

[0248] The above-described gate contact plug (160 in FIG. 9) can be deformed into a gate contact plug 260 that does not penetrate a gate electrode located at a level lower than the gate pad in the vertical direction Z. The gate contact plug 260 can have a lower surface that contacts the gate pad. For example, the above-described first gate contact plug 160a can be deformed into a first gate contact plug 260a disposed on the gate pad GP_1 of the first upper gate electrode GE_Ua, and the above-described second gate contact plug 160b can be deformed into a second gate contact plug 260b disposed on the gate pads GP_2bb and GP_2aa of the second intermediate gate electrode GE_Mb, the first intermediate gate electrode GE_Ma, and the lower gate electrode GE_L.

[0249] FIG. 11 is a cross-sectional view showing a region cut along the line I-I' of FIG. 4 for explaining a modification of a semiconductor device according to an embodiment of the present invention, and FIG. 12 is a partially enlarged view of the region represented by "Ab" in FIG. 11.

[0250] In the modification, referring to FIGS. 4, 11, and 12, the above-described first structure ST1 and second structure ST2 can be deformed into a first structure ST1a and a second structure ST2a as shown in FIGS. 11 and 12.

[0251] The second structure ST2a can be disposed under the first structure ST1a.

[0252] The second structure ST2a can include a substrate 206’, a peripheral active region 209a’ on the substrate 206’, a peripheral element isolation region 209s’ that defines the peripheral active region 209a’ on the substrate 206’, peripheral elements PTR on the substrate 206’, an upper routing wiring structure 220’, and a second insulating structure 230’. As described above, the peripheral elements PTR can include peripheral transistors each including peripheral source / drain regions PTR_SD spaced apart from each other within the peripheral active region 209a’, a peripheral channel region PTR_CH between the peripheral source / drain regions PTR_SD, and a peripheral gate PTR_G on the peripheral channel region PTR_CH.

[0253] The upper routing wiring structure 220’ can be embedded in the upper insulating structure 230’ and can be electrically connected to the peripheral elements PTR. The upper routing wiring structure 220’ can include a horizontal portion and a vertical portion. The upper surface of the upper insulating structure 230’ can be disposed at a level higher than the upper surface of the upper routing wiring structure 220’.

[0254] The first structure ST1a can be disposed on the upper insulating structure 230’.

[0255] The first structure ST1a can include a plate pattern 306 and an insulating pattern 309 on the side surface of the plate pattern 306. The first structure ST1a can include the above-described laminated structure GS that is substantially the same as the foregoing. For example, the first structure ST1a can include the gate electrode GE and the interlayer insulating layers ILDa and ILDb as in any one of the foregoing embodiments. The gate electrodes GE_L, GE_M, GE_Ua, and GE_Ub can be disposed on the plate pattern 306 and the insulating pattern 309. Therefore, the gate electrodes GE_L, GE_M, GE_Ua, and GE_Ub can have a gate pad according to any one of the foregoing embodiments.

[0256] The above-described vertical memory structure VS can be deformed into a vertical memory structure VS” as shown in FIG. 12. Therefore, the first structure ST1a can include the vertical memory structure VS”.

[0257] The vertical memory structure VS” can include a first vertical memory structure VS_L’ in which the lower region is deformed in the above-described first vertical memory structure VS_L. Therefore, the vertical memory structure VS” can include the above-described second vertical memory structure VS_U and the connection structure VS_C together with the first vertical memory structure VS_L’.

[0258] The plate pattern 306 can include a first layer 306a, a second layer 306b on the first layer 306a, and a third layer 306c on the second layer 306b. At least one of the first to third layers 306a, 306b, and 306c can include polysilicon. For example, the second layer 306b can include a polysilicon layer having an N-type conductivity type.

[0259] As described above, the first vertical memory structure VS_L’ can include the insulating core region 116, the channel layer 114 covering the side and bottom surfaces of the insulating core region 116, and the information storage structure 112 disposed on the outer surface of the channel layer 114. The first vertical memory structure VS_L’ can be formed of the same material layer as the information storage structure 112, and can further include a dummy information storage structure 112’ covering the bottom surface of the channel layer 114 and the side surfaces of the lower region of the channel layer 114. The channel layer 114 can be separated from the first layer 306a by the dummy information storage structure 112’.

[0260] The second layer 306b can contact the channel layer 114 through the space between the information storage structure 112 and the dummy information storage structure 112’.

[0261] The first structure ST1a can include a gate contact plug 360 configured to be electrically connected to the gate pads of the lower, intermediate, and first upper gate electrodes GE_L, GE_M, GE_Ua, an upper gate contact plug 163 configured to be electrically connected to the gate pad of the second upper gate electrode GE_Ub, and an upper gate connection wiring 169’ on the upper gate contact plug 163.

[0262] The gate contact plug 360 may be configured to be electrically connected to the upper routing wiring structure 220’. For example, the gate contact plug 360 can extend downward from the gate contact plug 160 as shown in FIGS. 5, 6b to 6d, penetrate the insulating pattern 309, and be electrically connected to the pad portion of the upper routing wiring structure 220’. Therefore, the gate contact plug 360 can have a shape extending downward from the shape of the gate contact plug 160 as shown in FIGS. 5, 6b to 6d.

[0263] FIG. 13 is a diagram for explaining a modification of the embodiment of FIG. 3a described above, and FIG. 14 is a cross-sectional view showing a region cut along the line I-I' of FIG. 4 for explaining a modification of a semiconductor device according to an embodiment of the present invention.

[0264] In the modification, referring to FIG. 13 of FIGS. 13 and 14, the first upper gate line UL1a of the first memory mat MAT1 described in FIG. 3a can be deformed into a first upper gate line UL1a' having a gate pad P1b in the first connection region R1a and a gate pad P1a in the second connection region R1b. The third upper gate line UL2a of the second memory mat MAT2 described in FIG. 3a can be deformed into a third upper gate line UL2a' having a gate pad P2a in the third connection region R2b and a gate pad P2b in the fourth connection region R2a.

[0265] Therefore, the first upper gate line UL1a’ can have a voltage applied thereto in the +X direction and the -X direction via a routing wiring structure 1115b1 electrically connected to the gate pad P1b in the first connection region R1a and a routing wiring structure 1115a1 electrically connected to the gate pad P1b in the second connection region R1b. The third upper gate line UL2a can have a voltage applied thereto in the +X direction and the -X direction via a routing wiring structure 1115a2 electrically connected to the gate pad P2a in the third connection region R2b and a routing wiring structure 1115b2 electrically connected to the gate pad P2b in the fourth connection region R2a. Therefore, since a voltage can be applied more quickly to the entire first and third upper gate lines UL1a’, UL2a’, the performance of a transistor including the first and third upper gate lines UL1a’, UL2a’ as gate electrodes can be improved. Referring to FIG. 14 of FIGS. 13 and 14, the above-described first upper gate electrode (GE_Ua in FIG. 5) can be deformed into a first upper gate electrode GE_Ua’ having gate pads on both sides as shown in FIG. 14. For example, the first upper gate electrode GE_Ua’ can have a first side gate pad G_P1a disposed in the first connection region R1a and a second side gate pad G_P1a’ disposed in the second connection region R1b. The first side gate pad G_P1a can be arranged in a stepped shape that decreases in order in the -X direction. The second side gate pad G_P1a’ can be arranged in a stepped shape that decreases in order in the +X direction. The first upper gate electrode GE_Ua’ can correspond to the first upper gate line UL1a’ described in FIG. 13. In FIG. 14, the regions represented by “A”, “B”, “C”, and “D” can be substantially the same as the partial enlarged views of FIGS. 6a, 6b, 6c, and 6d described above.

[0266] The above-described gate contact plug 160 can further include a third gate contact plug 160c that is connected to the second side gate pad G_P1a' of the first upper gate electrode GE_Ua'. Therefore, a voltage can be applied to the first upper gate electrode GE_Ua' via the first gate contact plug 160a that is electrically connected to the first side gate pad G_P1a disposed in the first connection region R1a and the third gate contact plug 160c that is electrically connected to the second side gate pad G_P1a' disposed in the second connection region R1b. The first upper gate electrode GE_Ua' can correspond to the first upper gate line (UL1a' in FIG. 13). Therefore, the performance of the transistor including the first upper gate electrode GE_Ua' as a gate electrode can be improved.

[0267] FIG. 15 is a diagram for explaining a modification in the embodiment of FIG. 3a described above.

[0268] In the modification, referring to FIG. 15, the second upper gate line UL1b of the first memory mat MAT1 described in FIG. 3a can be deformed into a second upper gate line UL1b' having a gate pad P1a disposed in the second connection region R1b. The fourth upper gate line UL2b of the second memory mat MAT2 described in FIG. 3a can be deformed into a fourth upper gate line UL2b' having a gate pad P2a disposed in the third connection region R2b.

[0269] Therefore, the second upper gate line UL1b’ can have a voltage applied thereto in the -X direction via a routing wiring structure 1115a1 that is electrically connected to the gate pad P1a within the second connection region R1b, and the fourth upper gate line UL2b’ can have a voltage applied thereto in the +X direction via a routing wiring structure 1115a2 that is electrically connected to the gate pad P2a within the third connection region R2b. Therefore, the directions in which voltages are applied to the first upper gate line UL1a and the second upper gate line UL1b’ can be different, and the directions in which voltages are applied to the third upper gate line UL2a and the fourth upper gate line UL2b’ can be different. The aforementioned second upper gate electrode (GE_Ub in FIG. 5) that can correspond to the second upper gate line UL1b’ can be deformed into a second upper gate electrode having a gate pad disposed within the second connection region R1b.

[0270] FIG. 16 is a diagram for explaining a modified example in the embodiment of FIG. 3a described above, and FIG. 17 is a cross-sectional view showing a region cut along the line I-I’ of FIG. 4 for explaining a modified example of a semiconductor device according to an embodiment of the present invention.

[0271] In the modified example, referring to FIG. 16 among FIGS. 16 and 17, the first and second upper gate lines UL1a and UL1b described in FIG. 3a can be deformed into first and second upper gate lines UL1a’ and UL1b’ having a gate pad P1b within the first connection region R1a and a gate pad P1a within the second connection region R1b. The third and fourth upper gate lines UL2a and UL2b of the second memory mat MAT2 described in FIG. 3a can be deformed into third and fourth upper gate lines UL2a’ and UL2b’ having a gate pad P2a within the third connection region R2b and a gate pad P2b within the fourth connection region R2a.

[0272] Therefore, the first and second upper gate lines UL1a’ and UL1b’ can have voltages applied in the +X direction and the -X direction through routing wiring structures 1115b1 and 1115a1 that are electrically connected to the gate pad P1b in the first connection region R1a and the gate pad P1a in the second connection region R1b. The third and fourth upper gate lines UL2a’ and UL2b’ can have voltages applied in the +X direction and the -X direction through routing wiring structures 1115a2 and 1115b2 that are electrically connected to the gate pad P2a in the third connection region R2b and the gate pad P2b in the fourth connection region R2a.

[0273] Referring to FIG. 17 together with FIG. 16, as described in FIG. 14, the first upper gate electrode GE_Ua’ can have the first side gate pad G_P1a in the first connection region R1a and the second side gate pad G_P1a’ in the second connection region R1b. The second upper gate electrode GE_Ub in FIG. 14 can be deformed into a second upper gate electrode GE_Ub’ having a first side gate pad G_P1b arranged in the first connection region R1a and a second side gate pad G_P1b’ arranged in the second connection region R1b.

[0274] Voltages can be applied to both sides of the second upper gate electrode GE_Ub’ through the first upper gate contact plug 163 on the first side gate pad G_P1b arranged in the first connection region R1a and the second upper gate contact plug 163’ on the second side gate pad G_P1b’ arranged in the second connection region R1b.

[0275] The first side gate pads G_P1a and G_P1b arranged in the first connection region R1a can be arranged in a stepped structure that decreases in order in the -X direction. The second side gate pads G_P1a’ and G_P1b’ arranged in the second connection region R1b can be arranged in a stepped structure that decreases in order in the +X direction.

[0276] The above-mentioned first upper gate electrode GE_Ua’ can correspond to the above-mentioned first upper gate line (UL1a’ in FIG. 16), and the above-mentioned second upper gate electrode GE_Ub’ can correspond to the above-mentioned second upper gate line (UL1b’ in FIG. 16). Therefore, the performance of the transistor including the above-mentioned first upper gate electrode GE_Ua’ and the above-mentioned second upper gate electrode GE_Ub’ as gate electrodes can be improved.

[0277] FIG. 18 is a diagram for explaining a modification in the embodiment of FIG. 3a described above, and FIG. 19 is a cross-sectional view showing a region cut along the line I-I’ of FIG. 4 for explaining a modification of a semiconductor device according to an embodiment of the present invention.

[0278] In the modification, referring to FIG. 18 among FIGS. 18 and 19, the above-mentioned first word line (WL1 in FIG. 3a) can be modified into a first word line WL1’ including a first lower word line WL1_L having a gate pad P1a disposed in the above-mentioned second connection region R1b and a first upper word line WL1_U having a gate pad P1b disposed in the above-mentioned first connection region R1a. The above-mentioned first upper word line WL1_U can be disposed at a higher level than the above-mentioned first lower word line WL1_L.

[0279] A voltage can be applied to the above-mentioned first lower word line WL1_L in the -X direction from the above-mentioned second connection region R1b toward the above-mentioned first memory cell array region M1, and a voltage can be applied to the above-mentioned first upper word line WL1_U in the +X direction from the above-mentioned first connection region R1a toward the above-mentioned first memory cell array region M1.

[0280] The above-mentioned second word line (WL2 in FIG. 3a) can be modified into a second word line WL2’ including a second lower word line WL2_L having a gate pad P2a disposed in the above-mentioned third connection region R2b and a second upper word line WL2_U having a gate pad P2b disposed in the above-mentioned fourth connection region R2a.

[0281] The second lower word line WL2_L can have a voltage applied thereto in the +X direction from the third connection region R2b toward the second memory cell array region M2, and the second upper word line WL2_U can have a voltage applied thereto in the -X direction from the fourth connection region R2a toward the second memory cell array region M2.

[0282] Referring to FIG. 19 together with FIG. 18, as described above, the first intermediate gate electrode GE_Ma can have gate pads G_P2a1, G_P2a2 disposed in the second connection region R1b as described above.

[0283] The second intermediate gate electrode GE_Mb described above can be deformed into a second intermediate gate electrode GE_Mb' including a second - 1 intermediate gate electrode GE_Mb_L having a gate pad G_P2b1 disposed in the second connection region R1b and a second - 2 intermediate gate electrode GE_Mb_U having a gate pad disposed in the first connection region R1a.

[0284] The second intermediate gate electrode GE_Mb' and the first upper gate electrode GE_Ua can have gate pads G_P1aa arranged in a stepped shape that decreases in order in the -X direction. The gate pads G_P1aa can be electrically connected to the first gate contact plug 160a.

[0285] In an embodiment, the first intermediate gate electrode GE_Ma and the second - 1 intermediate gate electrode GE_Mb_L may be the first lower word line WL1_L described in FIG. 18, and the second - 2 intermediate gate electrode GE_Mb_U may be the first upper word line WL1_U described in FIG. 18.

[0286] FIG. 20 is a diagram for explaining a modification in the embodiment of FIG. 3a described above, FIG. 21 is a plan view for explaining a modification in the embodiment of FIG. 4 described above, and FIG. 22 is a cross - sectional view showing a region taken along line Ia - Ia' of FIG. 21, and can show a modification in the cross - sectional structure of FIG. 5.

[0287] In a modified example, referring to FIG. 20 among FIGS. 20, 21, and 22, the above-described first connection region R1a can be deformed into a first connection region R1aa with an increased width in the +X direction, the above-described second connection region R1b can be deformed into a second connection region R1bb with a decreased width in the +X direction, the above-described third connection region R2b can be deformed into a third connection region R2bb with a decreased width in the +X direction, and the above-described fourth connection region R2a can be deformed into a fourth connection region R2aa with an increased width in the +X direction. In the +X direction, the widths of the first and fourth connection regions R1aa and R2aa may be larger than the widths of the second and third connection regions R1bb and R2bb, respectively.

[0288] The first and second lower gate lines LL1a and LL1b described with reference to FIG. 3a can be deformed into first and second lower gate lines LL1a” and LL1b” having a gate pad P1aa disposed in the first connection region R1aa.

[0289] The first word line WL1 described with reference to FIG. 3a can be deformed into a first word line WL1” having a gate pad P1aa disposed in the first connection region R1aa.

[0290] The first and second upper gate lines UL1a and UL1b described with reference to FIG. 3a can be deformed into first and second upper gate lines UL1a” and UL1b” having a gate pad P1bb disposed in the second connection region R1bb.

[0291] The third and fourth lower gate lines LL2a and LL2b described with reference to FIG. 3a can be deformed into third and fourth lower gate lines LL2a” and LL2b” having a gate pad P2aa disposed in the fourth connection region R2aa.

[0292] The second word line WL2 described with reference to FIG. 3a can be transformed into a second word line WL2” having a gate pad P2aa disposed within the fourth connection region R2aa.

[0293] The third and fourth upper gate lines UL2a, UL2b described with reference to FIG. 3a can be transformed into third and fourth upper gate lines UL2a”, UL2b” having a gate pad P2bb disposed within the third connection region R2bb.

[0294] Referring to FIGS. 21 and 22 together with FIG. 20, the first connection region R1a described above can be transformed into a first connection region R1aa with an increased width in the +X direction, the second connection region R1b described above can be transformed into a second connection region R1bb with a decreased width in the +X direction, the third connection region R2b described above can be transformed into a third connection region R2bb with a decreased width in the +X direction, and the fourth connection region R2a described above can be transformed into a fourth connection region R2aa with an increased width in the +X direction.

[0295] In the +X direction, the widths of the first and fourth connection regions R1aa, R2aa may each be larger than the widths of the second and third connection regions R1bb, R2bb.

[0296] In the embodiments of FIGS. 21 and 22, the cross-sectional structure of the second memory mat MAT2 in the +X direction may be substantially the same as the cross-sectional structure of FIG. 5 described above. In the embodiments of FIGS. 21 and 22, the cross-sectional structure of the first memory mat MAT1 in the +X direction may be substantially the same as a structure obtained by mirror-symmetry of the cross-sectional structure of FIG. 5 in the +X direction or the -X direction. Accordingly, in the first memory mat MAT1, the gate pads of the lower gate electrode GE_L and the intermediate gate electrode GE_M can be disposed within the first connection region R1aa, and the gate pads of the upper gate electrodes GE_Ua, GE_Ub can be disposed within the second connection region R1bb.

[0297] In FIG. 22, the lower gate electrode GE_L can correspond to the first and second lower gate lines LL1a”, LL1b” in FIG. 20, the intermediate gate electrode GE_M can correspond to the first word line WL1” in FIG. 20, and the first and second upper gate electrodes GE_Ua, GE_Ub can correspond to the first and second upper gate lines UL1a”, UL1b” in FIG. 20.

[0298] In FIG. 22, the region represented by “Ca” may have the same structure as the partial enlarged view of FIG. 6c mirrored in the +X direction, and the region represented by “Da” may have the same structure as the structure obtained by mirroring the partial enlarged view of FIG. 6d in the +X direction.

[0299] The above-described first outer capping insulating structure (INS_C1a in FIG. 6b) and the second outer capping insulating structure (INS_C2a in FIG. 6b) can be deformed into a first capping insulating structure INS_C1a’ and a second capping insulating structure INS_C2a’ disposed between the first memory mat MAT1 and the second memory mat MAT2.

[0300] Next, with reference to FIG. 23, an example of a method for forming a semiconductor device according to an embodiment of the present invention will be described. FIG. 23 is a process flowchart for explaining an example of a method for forming a semiconductor device according to an embodiment of the present invention.

[0301] Referring to FIG. 23, a lower mold structure can be formed (S10). The lower mold structure can include a first interlayer insulating layer and a first sacrificial gate layer that are repeatedly laminated. The lower mold structure can be patterned to form a first lower stepped shape in the intermediate connection region (S20).

[0302] The intermediate connection region may be the second and third connection regions R1b, R2b described above.

[0303] The first lower step shape may be the step shape of the gate pads (G_P2a2 in FIG. 6c and G_P2a1 in FIG. 6d) of the lower part and the first intermediate gate electrodes (GE_L and GE_Ma in FIGS. 6c and 6d) described in the foregoing embodiment.

[0304] The upper mold structure can be formed (S30). The upper mold structure can include a second interlayer insulating layer and a second sacrificial gate layer that are repeatedly laminated. The upper mold structure can be patterned to form an upper step shape in the outer connection region (S40).

[0305] The outer connection region may be the first and fourth connection regions R1a and R2a described above.

[0306] The upper step shape may be the step shape of the gate pad (G_P1a in FIG. 6b) of the first upper gate electrode GE_Ua described in the foregoing embodiment.

[0307] The upper mold structure can be patterned to form a second lower step shape in the intermediate connection region (S50).

[0308] The second lower step shape may be the step shape of the gate pads (G_P2b2 in FIG. 6c and G_P2b1 in FIG. 6d) of the second intermediate gate electrode (GE_Mb in FIGS. 6c and 6d) described in the foregoing embodiment.

[0309] A vertical memory structure penetrating the lower and upper mold structures can be formed (S60).

[0310] In one example, the vertical memory structure may be the vertical memory structure (VS' in FIGS. 7 and 8a) as shown in FIGS. 7 and 8a.

[0311] In another example, when the vertical memory structure is a vertical memory structure (VS in FIGS. 5 and 6a) as shown in FIGS. 5 and 6a, forming the vertical memory structure includes forming a first vertical memory structure (VS_L in FIG. 6a) that penetrates the lower and upper mold structures, forming a buffer insulating layer (120 in FIGS. 5, 6a to 6d) on the upper mold structure, forming a connection structure (VS_C in FIG. 6a) that penetrates the buffer insulating layer (120 in FIGS. 5, 6a to 6d) and is connected to the first vertical memory structure (VS_L in FIG. 6a), forming a second upper gate electrode (GE_Ub in FIGS. 5 and 6a) on the buffer insulating layer (120 in FIGS. 5, 6a to 6d), and forming a second vertical memory structure (VS_U in FIG. 6a) that penetrates the second upper gate electrode (GE_Ub in FIGS. 5 and 6a).

[0312] The sacrificial gate layer in the lower and upper mold structures can be replaced with a gate electrode (S70).

[0313] The gate electrode may be the gate electrode (in FIGS. 7, 8a and 8b) as shown in FIGS. 7, 8a and 8b or the lower, middle, and first gate electrodes GE_L, GE_M, GE_Ua as shown in FIGS. 5, 6a to 6d. Forming the gate electrode (in FIGS. 7, 8a and 8b) or the lower, middle, and first gate electrode layers GE_L, GE_M, GE_Ua as shown in FIGS. 5, 6a to 6d includes forming a separation trench that penetrates the lower and upper mold structures to expose the sacrificial gate layer in the lower and upper mold structures, removing the sacrificial gate layer exposed by the separation trench to form a vacant space, forming the gate electrode (in FIGS. 7, 8a and 8b) in the vacant space, and forming a separation structure (SP in FIG. 4) in the separation trench.

[0314] When the gate electrode is the lower, intermediate, and first gate electrodes GE_L, GE_M, GE_Ua as shown in FIGS. 5, 6a to 6d, after forming the lower, intermediate, and first gate electrodes GE_L, GE_M, GE_Ua, the aforementioned buffer insulating layer (120 in FIGS. 5, 6a to 6d), the connecting structure (VS_C in FIG. 6a), the second upper gate electrode (GE_Ub in FIGS. 5 and 6a), and the second vertical memory structure (VS_U in FIG. 6a) can be formed.

[0315] A gate contact plug electrically connected to the gate pad of the gate electrode can be formed (S80). The gate contact plug may be the gate contact plug 160 described in the foregoing embodiments.

[0316] Next, referring to FIG. 24, an example of a method for forming a semiconductor device according to an embodiment of the present invention will be described. FIG. 24 is a process flowchart for explaining an example of a method for forming a semiconductor device according to an embodiment of the present invention.

[0317] Referring to FIG. 24, a mold structure can be formed (S110). The mold structure can include an interlayer insulating layer and a sacrificial gate layer that are repeatedly stacked. The mold structure can be patterned to form an upper stepped shape in the outer connection region (S120).

[0318] The outer connection region may be the first and fourth connection regions R1a, R2a described above. The upper stepped shape may be the stepped shape of the gate pad of the first upper gate electrode (GE_Ua in FIGS. 9 and 10) described in the foregoing embodiments.

[0319] The mold structure can be patterned to form a lower stepped shape in the intermediate connection region (S130).

[0320] The intermediate connection region may be the second and third connection regions R1b, R2b described above.

[0321] The stepped shape of the lower stage may be the stepped shape of the gate pads (G_P2a’, G_P2b’ in Fig. 9 and G_P2aa, G_P2bb in Fig. 10) of the lower part, the first intermediate gate electrode, and the second intermediate gate electrode (GE_La, GE_Ma, GE_Mb in Figs. 9 and 10) described in the foregoing embodiment.

[0322] A vertical memory structure penetrating the mold structure can be formed in the same manner as described with reference to Fig. 23 (S140).

[0323] The sacrificial gate layer in the mold structure can be replaced with a gate electrode in the same manner as described with reference to Fig. 23 (S150).

[0324] A gate contact plug electrically connected to the gate pad of the gate electrode can be formed in the same manner as described with reference to Fig. 23 (S160).

[0325] As described above, embodiments of the present invention have been described with reference to the accompanying drawings. Those having ordinary knowledge in the technical field to which the present invention pertains can understand that the present invention can be implemented in other specific forms without changing its technical idea and essential features. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not restrictive.

Description of Reference Numerals

[0326] 1 Data storage system 160, 260, 360 Gate contact plug 1100, CH Semiconductor device 1200 Controller ST1 First structure ST2 Second structure BLK Memory block M1, M2 Memory cell array regions M1, M2 R1a, R1b, R2b, R2a Connection regions VS Vertical memory structure GE Gate electrode GP, G_P gate pad IOP input / output pad PC peripheral circuit

Claims

1. a first structure including a first memory block and a second memory block having a first side and a second side facing each other and sequentially arranged in a first direction from the first side to the second side; a second structure including a peripheral circuit and vertically overlapping the first structure; and the first memory block includes a first connection region, a first memory cell array region, and a second connection region, which are sequentially arranged in the first direction; the second memory block includes a third connection region, a second memory cell array region, and a fourth connection region, which are sequentially arranged in the first direction; the first memory block includes first gate electrodes spaced apart from each other in the vertical direction and extending from the first connecting region to the second connecting region; the second memory block includes second gate electrodes spaced apart from each other in the vertical direction and extending from the third connecting region to the fourth connecting region; The first gate electrode of the first memory block is a first word line having a first word line pad disposed within the second connection region; a first upper gate line having a first upper gate pad disposed in the first connection region and disposed on the first word line; The second gate electrode of the second memory block is a second word line having a second word line pad disposed within the third connecting region; a second upper gate line having a second upper gate pad disposed in the fourth connecting region and disposed on the second word line; The first structure is a first word line contact plug connected to the first word line pad; a first upper gate contact plug connected to the first upper gate pad; a second word line contact plug connected to the second word line pad; a second upper gate contact plug connected to the second upper gate pad.

2. the first word line contact plug penetrates the first word line pad and contacts the first word line pad; the first upper gate contact plug penetrates the first upper gate pad and contacts the first upper gate pad; the second word line contact plug penetrates the second word line pad and contacts the second word line pad; The semiconductor device according to claim 1 , wherein the second upper gate contact plug penetrates the second upper gate pad and contacts the second upper gate pad.

3. the first upper gate line further includes a first inner upper gate pad disposed in the second connection region; the second upper gate line further includes a second inner upper gate pad disposed in the third connection region; The first structure is a first inner upper gate contact plug connected to the first inner upper gate pad; The semiconductor device of claim 1 , further comprising: a second inner upper gate contact plug connected to the second inner upper gate pad.

4. a first structure having a first side surface and a second side surface facing each other, the first structure including a first connection region, a first memory cell array region, a second connection region, a third connection region, a second memory cell array region, and a fourth connection region, the first connection region and the second memory cell array region being sequentially arranged in a first direction from the first side surface to the second side surface; a second structure including a peripheral circuit and vertically overlapping the first structure; and The first structure is a first side conductive layer disposed in the first connecting region, the first memory cell array region, and the second connecting region; a first vertical memory structure extending through the first side conductive layer in the first memory cell array region; a second side conductive layer disposed in the third connecting region, the second memory cell array region, and the fourth connecting region; a second vertical memory structure extending through the second side conductive layer in the second memory cell array region; The first side conductive layer is a first lower conductive group having first lower pads arranged in a staircase shape in the second connection region; a first upper conductive group disposed at a level higher than the first lower conductive group and having first upper pads arranged in a staircase shape within the first connecting region; The second side conductive layer is a second lower conductive group having second lower pads disposed at the same level as the first lower conductive group and arranged in a staircase shape within the third connection region; a second upper conductive group disposed at the same level as the first upper conductive group and having second upper pads arranged in a staircase shape within the fourth connecting region.

5. 5. The semiconductor device according to claim 4, wherein, among the first side conductive layers, the number of first side conductive layers in the first lower conductive group is greater than the number of first side conductive layers in the first upper conductive group.

6. Among the first side conductive layers, the first side conductive layers of the first lower conductive group include a first lower word line having a first lower word line pad and a second lower word line disposed at a level higher than the first lower word line and having a second lower word line pad; 5. The semiconductor device of claim 4, wherein the first structure further comprises a dummy conductive layer disposed at the same level as the second lower word line and overlapping the first lower word line pad.

7. The semiconductor device of claim 4 , wherein a thickness of at least one of the first side conductive layers of the first lower conductive group is greater than a thickness of at least one of the first side conductive layers of the first upper conductive group.

8. a semiconductor device including an input / output pad; a controller electrically connected to the semiconductor device via the input / output pad and configured to control the semiconductor device; and The semiconductor device includes: a first structure including a first memory block and a second memory block having a first side and a second side facing each other and sequentially arranged in a first direction from the first side to the second side; a second structure including a peripheral circuit and vertically overlapping the first structure; the first memory block includes a first connection region, a first memory cell array region, and a second connection region, which are sequentially arranged in the first direction; the second memory block includes a third connection region, a second memory cell array region, and a fourth connection region, which are sequentially arranged in the first direction; the first memory block includes first gate electrodes spaced apart from each other in the vertical direction and extending from the first connecting region to the second connecting region; the second memory block includes second gate electrodes spaced apart from each other in the vertical direction and extending from the third connecting region to the fourth connecting region; The first gate electrode of the first memory block is a first word line having a first word line pad disposed within the second connection region; a first upper gate line having a first upper gate pad disposed in the first connection region and disposed on the first word line; The second gate electrode of the second memory block is a second word line having a second word line pad disposed within the third connecting region; a second upper gate line having a second upper gate pad disposed in the fourth connecting region and disposed on the second word line; The first structure is a first word line contact plug connected to the first word line pad; a first upper gate contact plug connected to the first upper gate pad; a second word line contact plug connected to the second word line pad; a second upper gate contact plug coupled to the second upper gate pad.

9. the first upper gate line further includes a first inner upper gate pad disposed in the second connection region; the second upper gate line further includes a second inner upper gate pad disposed in the third connection region; The first structure is a first inner upper gate contact plug connected to the first inner upper gate pad; The data storage system of claim 8 , further comprising: a second inner upper gate contact plug coupled to the second inner upper gate pad.

10. 9. The data storage system of claim 8, wherein a thickness of each of the first and second upper gate lines is greater than a thickness of each of the first and second word lines.

Images