Communication hub

Abstract

To provide a communication hub circuit and a system that address different calculation and data processing requirements between products in the same product range.SOLUTION: In a system 100, a communication hub circuit (102) comprises: two ports (P1) for exchanging data with another communication hub circuit (102); a port (P2) for exchanging data with a computing microchip (106); a port (P3) for exchanging data with an accelerator microchip (108); an interface (ITm) for exchanging data with a memory circuit (110); an interface (ITs) for exchanging data with a sensor (104); a data processing circuit; a network-on-chip for transferring data between elements of the communication hub circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This description generally relates to electronic circuits.

Background Art

[0002] In the automotive field, usually a single manufacturer has a wide lineup of vehicles.

[0003] Furthermore, the electronic / electrical architecture of vehicles is moving towards centralization of computing and data processing on a single platform, system, or computer that can handle the multimedia and assistive or autonomous driving application requirements of each vehicle.

[0004] However, in a certain lineup of vehicles, each vehicle has, on the one hand, the multimedia devices it is equipped with, i.e., the multimedia experience provided by this vehicle, and on the other hand, the level of its advanced driver assistance system (ADAS), i.e., different computing and data processing requirements depending on, for example, the level L2, L2+, L3, or L4 of the driving assistance system used by the vehicle.

[0005] To meet the computing and data processing requirements of all vehicles in the lineup, a first solution is to install the same high-performance processor in each vehicle and program this processor by software according to the specific requirements of the vehicle. However, since such a processor needs to be able to meet the computing and data processing requirements of the top-of-the-line vehicles, it becomes large and undesirable when installed in lower-level vehicles.

[0006] A second solution is to develop specific dedicated different computers for each set of vehicles having similar computing and processing requirements, in the form of system-on-chips. However, the development of several different system-on-chips is complex and undesirable, and furthermore lacks scalability. This complexity results in high development costs and technical difficulties.

Summary of the Invention

Problems to be Solved by the Invention

[0007] It is necessary to overcome some or all of the drawbacks of known computers that address different computing and data processing requirements among products within the same product lineup, for example, among vehicles within the same vehicle lineup.

Means for Solving the Problems

[0008] One embodiment overcomes some or all of the drawbacks of known computers that address different computing and data processing requirements among products within the same product lineup, for example, among vehicles within the same vehicle lineup.

[0009] One embodiment provides a communication hub circuit. This communication hub circuit at least two first physical ports, each of which forms part of the same cache coherent memory region as the hub circuit and is configured to exchange data when the first port is connected to the other communication hub circuit via a high-speed link, at least two first physical ports; at least one second physical port, a computing microchip that forms part of the same cache coherent memory region, and at least one second physical port configured to exchange data when the at least one second physical port is connected to the computing microchip via a high-speed link; at least one third physical port, an accelerator microchip that forms part of the input / output coherent memory region for the same cache coherent memory region, and at least one third physical port configured to exchange data when the at least one third physical port is connected to the accelerator microchip via a high-speed link; At least one first interface, comprising a memory circuit forming part of the same cache coherent memory region, and at least one first interface configured to exchange data when the at least one first interface is connected to the memory circuit. At least one second interface configured to exchange data with a sensor. At least one processing circuit configured to perform data processing. At least one network-on-chip configured to transfer data between elements of a communication hub circuit, the elements comprising the at least two first ports, the at least one second port, the at least one third port, the at least one processing circuit, and the at least one first interface. Comprising.

[0010] According to one embodiment, Each of the at least two first physical ports is configured to implement the CXL.mem and CXL.cache or AXI stream protocol when exchanging data with other communication hub circuits. The at least one second physical port is configured to implement the CXL.cache and CXL.mem protocols when exchanging data with a computing microchip. The at least one third physical port is configured to implement the CXL.mem, CXL.io, or PCIe protocol when exchanging data with an accelerator microchip.

[0011] According to one embodiment, the hub circuit is configured to merge received data flows without performing any processing on the data flows.

[0012] According to one embodiment, the hub circuit is configured to execute processing on the received individual data flows and then merge the results of these processes.

[0013] According to one embodiment, the hub circuit is configured to implement cache coherence within the same cache coherent memory region.

[0014] According to one embodiment, the hub circuit is configured to implement I / O coherence between the same cache coherent memory region and other memory regions to which the accelerator microchip belongs.

[0015] According to one embodiment, the at least one first interface comprises an interface for DDR type memory and / or an interface for FLASH type memory.

[0016] According to one embodiment, the hub circuit further comprises a direct memory access circuit.

[0017] According to one embodiment, the at least one second interface comprises at least one CSI type interface and / or at least one Ethernet type interface.

[0018] According to one embodiment, the hub circuit further comprises at least one third interface configured to exchange data with a display.

[0019] Another embodiment provides a system. This system exactly one hub circuit as described above, and a memory connected to the at least one first interface and neither the computing microchip nor the accelerator microchip is connected to the hub circuit.

[0020] Another embodiment provides a system. This system the just-mentioned exactly one hub circuit, and a computing microchip connected to the at least one second port of the hub circuit by a high-speed link, and wherein no other computing microchips or accelerator microchips are connected to the hub circuit.

[0021] Another embodiment provides a system. This system includes the just-mentioned exactly one first hub circuit and the just-mentioned one second hub circuit, wherein one of the first ports of the first hub circuit is connected to one of the first ports of the second hub circuit by a first high-speed link, and the first and second hub circuits, a first computing microchip connected to the at least one second port of the first hub circuit by a second high-speed link, wherein no other computing microchips or accelerator microchips are connected to the first hub circuit, and the first computing microchip, a second computing microchip connected to the at least one second port of the second hub circuit by a third high-speed link, wherein no other computing microchips or accelerator microchips are connected to the second hub circuit, and the second computing microchip and is provided with.

[0022] Another embodiment provides a system. This system includes the just-mentioned exactly one first hub circuit and the just-mentioned one second hub circuit, wherein one of the first ports of the first hub circuit is connected to one of the first ports of the second hub circuit by a first high-speed link, and the first and second hub circuits, A first computing microchip connected to the at least one second port of the first hub circuit by a second high-speed link, wherein no other computing microchips or accelerator microchips are connected to the first hub circuit, and the first computing microchip; A first accelerator microchip connected to the at least one third port of the second hub circuit by a third high-speed link, wherein no other accelerator microchips or computing microchips are connected to the second hub circuit, and the first accelerator microchip Comprising.

[0023] Another embodiment provides a system. This system is The just one first hub circuit described above, the one second hub circuit described above, the one third hub circuit described above, and the one fourth hub circuit described above, wherein one of the first ports of the first circuit is connected to one of the first ports of the second circuit by a first high-speed link, another one of the first ports of the second circuit is connected to one of the first ports of the third circuit by a second high-speed link, another one of the first ports of the third circuit is connected to one of the first ports of the fourth circuit by a third high-speed link, and another one of the first ports of the fourth circuit is connected to another one of the first ports of the first circuit by a fourth high-speed link, the first to fourth hub circuits; A first computing microchip connected to the at least one second port of the first hub circuit by a fifth high-speed link, wherein no other computing microchips or accelerator microchips are connected to the first hub circuit, and the first computing microchip; A second computing microchip connected to the at least one second port of the second hub circuit by a sixth high-speed link, wherein no other computing microchips or accelerator microchips are connected to the second hub circuit, and the second computing microchip; A first accelerator microchip connected to the at least one third port of the third hub circuit by a seventh high-speed link, wherein no other accelerator microchips or computing microchips are connected to the third hub circuit, and the first accelerator microchip; A second accelerator microchip connected to the at least one third port of the fourth hub circuit by an eighth high-speed link, wherein no other accelerator microchips or computing microchips are connected to the fourth hub circuit, and the second accelerator microchip Comprising.

[0024] According to one embodiment, each accelerator microchip is configured to perform data processing for a high-level pilot assistance system having levels L2+, L3, or L4.

Brief Description of the Drawings

[0025] The foregoing features and advantages, as well as other features, are described in detail in the following description of specific embodiments given by way of example and not limitation with reference to the accompanying drawings.

[0026]

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DETAILED DESCRIPTION OF THE INVENTION

[0027] Like features are indicated by like reference numerals in the various figures. In particular, structural and / or functional features common between the various embodiments may have the same reference numeral and may indicate the same structural, dimensional, and material characteristics.

[0028] For clarity, only the operations and elements useful for understanding the embodiments described herein have been illustrated and described in detail.

[0029] Unless otherwise indicated, when referring to two elements that are connected to each other, this means a direct connection without intervening elements other than conductors, and when referring to two elements that are coupled together, this means that these two elements may be connected or that these two elements may be coupled through one or more other elements.

[0030] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers such as "front", "rear", "top", "bottom", "left", "right", relative position qualifiers such as "above", "below", "higher", "lower", or direction qualifiers such as "horizontal", "vertical", etc., it is referring to the orientation shown in the drawings.

[0031] Unless otherwise specified, the terms "about," "substantially," and "on the order of" mean within 10%, preferably within 5%.

[0032] To address different computing and data processing requirements among vehicles within the same vehicle line-up, a solution based on the hardware breakdown of a range of computing and data processing systems is proposed here. The hardware breakdown consists of splitting the hardware architecture of a circuit into several different functional elements separately manufactured in the form of integrated circuits called "chiplets," and then rearranging and assembling these chiplets into a single package to form a component. U.S. Patent No. 11,756,150 shows the principle of decomposing hardware into microchips.

[0033] However, in the above patent, the breakdown is based on computing functions, and thus it cannot address products related to the management of a large number of data flows from a large number of sensors, for example, requirements of products such as automobiles that function as input data for the computing algorithms executed by microchips.

[0034] U.S. Patent No. 11,100,028 presents programmable components for data routing and data flow protocol replacement between microchips. However, in this solution, it is necessary to associate the programmable component with at least one microchip, which may not be desirable for addressing the computing and data processing requirements of the lowest-end product in a product line-up, for example, the lowest-end vehicle in an automobile line-up. Further, even when this component is associated with one or more microchips, the limitations of this component for data routing and data flow protocol replacement may not be sufficient to address the specific requirements of products within a product line-up, for example, vehicles within a vehicle line-up.

[0035] Regarding the design of a computer based on microchip decomposition, in order to overcome the above-mentioned drawbacks, a component hereinafter referred to as a communication hub is proposed.

[0036] FIG. 1 schematically shows an exemplary embodiment of a system 100 that performs calculations and data processing based on the decomposition into a microchip and at least one data hub in block form.

[0037] System 100 includes at least one communication hub 102 (block "COM HUB" in FIG. 1). In this example, system 100 includes two hubs 102.

[0038] Each hub 102 is configured to be connected in a modular manner to several other integrated circuits within system 100. Each hub 102 is further configured to exchange data flow or, more simply put, data with other integrated circuits or elements within system 100.

[0039] The hub(s) 102 of system 100 is configured to route data flow through system 100.

[0040] For example, each hub 102 is configured to obtain data or data flow from one or more sensors 104 (block "sensor" in FIG. 1) of system 100. In the example shown in FIG. 1, system 100 includes a single sensor 104, but in practice, system 100 may further include more sensors.

[0041] For example, each hub 102 is configured to redirect the received data or data flow to a microchip of system 100 for processing by the microchip. For example, a hub that receives data from a sensor can, after simple encapsulation, send the data back to another microchip or another hub of system 100 so that this data can be processed, that is, calculations and processing can be performed on this data, without performing calculations on this data.

[0042] System 100 can include two types of microchips, namely computing microchips 106 (block "Chiplet C" in FIG. 1) and accelerator microchips 108 (block "Chiplet A" in FIG. 1). The microchip 106 is a general computing and processing circuit. Thus, each microchip 106 can handle a relatively simple and diverse set of processing and computing tasks compared to those handled by the microchip 108. For example, each microchip 106 can be programmed with software. For example, each microchip 106 is a general-purpose processor. Conversely, the microchip 108 is an integrated circuit specifically designed to handle specific computing and processing requirements that are relatively complex compared to those handled by the microchip 106. In other words, unlike the microchip 106 that realizes general computing and processing functions, the microchip 108 realizes specific computing and processing functions for accelerating the realization of a certain specific system function. Thus, the microchip 108 is, for example, referred to as an accelerator microchip 108.

[0043] As an example, when the system 100 implements an automotive computer, the microchip 108 of the system 100 can realize accelerator functions specific to the requirements of autonomous driving, such as ADAS levels L3 and L4.

[0044] In the example shown in FIG. 1, the system 100 includes exactly two microchips 108 and exactly one microchip 106. However, in other examples, the system 100 can be configured as follows: Include any non-zero number of microchips 106 and no microchips 108; Include any non-zero number of microchips 108 and no microchips 106; Include any non-zero number of microchips 108 and any non-zero number of microchips 106; or, Include neither microchips 106 nor 108.

[0045] As a further example, each hub 102 is further configured to ensure collection of data or data flow in memory, for subsequent use of this data by, for example, system 100. As an example, each hub 102 is, for example: within a memory circuit or memory 110 (block "MEM" in FIG. 1) associated with, i.e., connected to, this hub 102, within a memory 110 associated with another hub 102 to which this hub 102 is connected or coupled, within a memory 110 associated with, i.e., connected to, microchip 106 or 108 (regardless of whether this microchip 106 or 108 is associated with, i.e., connected to, this hub 102 or is merely coupled to this hub 102 via another hub 102), configured to control recording of data or data flow of.

[0046] For example, each hub 102 is associated with at least one memory 110. For example, each microchip 106 is associated with at least one memory 110, preferably exactly one memory 110. For example, each microchip 108 is associated with at least one memory 110, preferably exactly one memory 110.

[0047] As an example, each memory 110 associated with (i.e., connected to) microchip 108 or 106 is of dual data rate (DDR) type, but each memory associated with microchip 106 or 108 can also be of another type, such as flash memory for example.

[0048] As an example, each memory 110 associated with (i.e., connected to) circuit 102 is of dual data rate (DDR) or flash type, but other types of memory are also conceivable.

[0049] Thus, in system 100, there is a functional division in that, on the one hand, the hub(s) 102 of system 100 manages communication, and on the other hand, the microchips 106 and 108 manage calculation and processing.

[0050] This division, where the microchips 106 and 108 are not responsible for communication or redistributing data within system 100, is advantageous for the grouping of analog functions in the communication hub(s) 102 of system 100. For example, since the physical layer of the communication interface is grouped within the circuit(s) 102 of system 100, the microchips 106 and 108 may not require these physical layers at their communication interfaces.

[0051] To perform the function of redistributing data flows within system 100, each hub 102 includes a network-on-chip (NoC), which is configured to redistribute data among the various components forming the circuit 102 within the circuit 102, for example, particularly between the input / output ports and the interfaces of the hub.

[0052] In addition to managing the redistribution of communication or data transmission among the various circuits forming it within system 100, each hub 102 is preferably configured to perform protocol substitution between the data it receives and the corresponding data it re-transmits to another element of the system.

[0053] Furthermore, in addition to managing the redistribution of data flows within system 100, regardless of the presence or absence of protocol substitution, each hub 102 is preferably configured to perform a merge of the received distinct data flows without preprocessing the received data flows and then provide the resulting merged data flow to another element of system 100. In other words, each hub 102 is configured to perform "early fusion" of the distinct data flows it receives. Preferably, each hub 102 is further configured to perform processing beyond simple protocol substitution on the distinct data flows it receives and then merge the results of this preprocessing to provide a corresponding merged data flow. In other words, each hub 102 is configured to perform "late fusion" of the distinct data flows it receives. The fact that each hub 102 is configured to perform both late fusion and early fusion enables the implementation of multimodal fusion of distinct data flows, and multimodal fusion strategies are particularly advantageous for implementation in, for example, the field of artificial intelligence.

[0054] As an example, to perform the above-described fusion, each circuit 102 comprises at least one data processing circuit configured to perform calculations and processing of data beyond simple protocol substitution.

[0055] According to one embodiment, each hub 102 is configured to perform relatively simple processing or calculations on data, for example, as compared to those performed by the accelerator microchip 108. In this way, a system 100 having only a single hub and lacking the microchips 106 and 108 can meet relatively low computing and processing requirements, for example, the computing and processing requirements of the lowest vehicle in the vehicle lineup. In other words, a system 100 having only one hub 102 and lacking the microchips 106 and 108 has a relatively low operating intensity, that is, the maximum number of operations per second that the system can process is relatively low as compared to a system having the microchips 106, 108 and / or other hubs. As an example, the hub 102 has an operating intensity that is at least twice lower than the operating intensity of each of the microchips 106, 108 that can be connected to this hub.

[0056] For example, to perform the above-described data processing, each hub 102 includes at least one processing circuit selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and a neural processing unit (NPU).

[0057] To be connected to one or more memory circuits 110, each hub 102 includes at least one memory interface ITm, which is configured to exchange data with the memory circuit 110 when such a memory 110 is connected to the interface ITm.

[0058] As an example, each interface ITm can be configured to connect to a DDR type memory. In this case, the interface is said to be of the DDR type. For example, a DDR type interface ITm is implemented by a memory controller for the DDR type memory. As an alternative, each interface ITm can be configured to connect to a flash memory. In this case, the interface ITm is said to be of the FLASH type. For example, a FLASH type interface ITm is implemented by a low voltage differential signaling (LVDS) interface adapted to communicate with a FLASH type memory circuit 110. As an example, when the hub 102 includes several interfaces ITm, these interfaces ITm can be of different types. For example, the first interface ITm is of the DDR type and the second interface ITm is of the FLASH type.

[0059] Each interface ITm of each hub 102 can be either connected to the memory circuit 110 or not connected at all. However, it is preferred that at least one interface ITm of each hub 102 is connected to the memory 110.

[0060] Similarly, in order to be connected to the memory circuit 110, each microchip 106 includes a memory interface ITmc configured to be connected to this memory 110. Similar to the interface ITm, each interface ITmc can be of a given type, for example different from the type of another interface ITmc, such as DDR or FLASH.

[0061] Each interface ITmc on each microchip 106 can be either connected to the memory circuit 110 or not connected at all.

[0062] Furthermore, in order to be connected to the memory circuit 110, each microchip 108 includes a memory interface ITma configured to be connected to this memory 110. Similar to the interfaces ITm and ITmc, each interface ITma can be of a given type, for example different from the type of another interface ITma, such as DDR or FLASH.

[0063] Each interface ITma on each microchip 108 can be connected to the memory circuit 110 or not connected at all.

[0064] Furthermore, each memory circuit 110 is preferably connected to only one of the hub 102, the microchip 106, and the microchip 108, in which case the memory 110 is said to be associated with this element.

[0065] This does not apply to the example shown in FIG. 1, but the microchip 108 may not be connected to any memory 110, and / or the microchip 106 may not be connected to any memory 110, and / or the hub may not be connected to any memory 110. However, the hub 102 is preferably associated with a memory 110, for example a memory comprising code executable by the hub 102, in order to program the hub 102.

[0066] The memory 110 of the system 100 implements the shared memory or the distributed memory of the system 100.

[0067] Furthermore, each hub 102 includes at least two physical ports P1. Each port P1 is configured to exchange data with other hubs 102 when the hub 102 having this port P1 is connected. In other words, each port P1 is configured to exchange data with other hubs 102 to which this port P1 is connected. The connection of two hubs 102 via two respective ports P1 of these two hubs 102 is realized by a high-speed link (HSL). As an example, the high-speed link is configured to transfer at least 4 gigabytes per second, preferably at least 8 gigabytes per second, regardless of whether this HSL link is a serial link or a parallel link. In FIG. 1, the high-speed link between two circuits 102 is referenced by 112, and the system 100 of the example shown in FIG. 1 includes only one link 112.

[0068] Each hub 102, more specifically, each port P1 of this hub 102, when connected by link 112 to a port P1 of another hub 102, for example another hub 102 that forms part of the same system as this hub 102, is configured such that the two hubs 102 and the memory(ies) 110 to which these hubs are connected form part of the same cache coherent memory region 116 (delimited by a dotted line in FIG. 1). This cache coherent memory region 116 is attached to or associated with these two hubs 102. Preferably, all hubs 102 within system 100 are part of the same cache coherent memory region. The cache coherent memory region 116 is, for example, memory that is distributed among several memories 110 that form part of the memory region 116.

[0069] In this way, each port P1 of each hub 102 can either be connected via link 112 to a port P1 of another hub 102 or not connected to anything.

[0070] Each hub 102 further comprises at least one interface, for example an interface ITs configured to exchange data with a sensor 104 when connected to the sensor 104. The connection of the interface ITs to the sensor is realized via a link 118 which is not, for example, a high-speed link. As an example, each hub 102 can comprise at least one interface ITs of the camera serial interface (CSI) type. Of course, each interface ITs of each hub 102 can be of a type other than CSI.

[0071] Each hub 102 comprises at least one physical port P2. Each port P2 is configured to exchange data with a computing microchip 106 when this port P2 is connected to the computing microchip 106. The connection of the microchip 106 to the port P2 of the hub 102 is realized by a high-speed link (HSL). In FIG. 1, since the system 100 of the example shown in FIG. 1 comprises only one link 120, the high-speed link between the two circuits 102 and 106 is referred to as 120. As an example, each microchip 106 comprises a physical port P2c similar to the port P2 of the hub 102, and this microchip 106 is connected to this port by a corresponding link 120 connecting these ports P2 and P2c to each other.

[0072] Each hub 102, more specifically each port P2 of the hub 102, when connected to the computing microchip 106 by the link 120, is configured such that the computing microchip 106 and any memory 110 to which the computing microchip 106 is connected form part of the same cache coherent memory region 116 as the hub 102 to which the computing microchip 106 is connected. As an example, this cache coherence within the shared memory region 116 is realized by each of the hubs 102 to which this region 116 is attached.

[0073] Each port P2 on each hub 102 can either be connected to a computing microchip 106 via the link 120 or not connected at all.

[0074] Each hub 102 includes at least one physical port P3. Each port P3 is configured to exchange data with the accelerator microchip 108 when this port P3 is connected to the microchip 108. The connection of the microchip 108 to the port P3 of the hub 102 is realized by a high-speed link (HSL). In FIG. 1, since the system 100 of the example shown in FIG. 1 includes only two links 122, the high-speed link between the two circuits 102 and 108 is referred to as 122. As an example, each microchip 108 includes a physical port P3a similar to the port P3 of the hub 102 and is connected by a corresponding link 122 that connects these ports P3 and P3a to each other.

[0075] Each hub 102, more specifically each port P3 of the hub 102, when connected to the microchip 108 by the link 122, is configured such that the microchip 108 and any memory 110 to which the microchip 108 is connected form a part of a memory region 124 having input / output coherence with respect to the cache coherent memory region 116 to which the hub 102 to which this microchip 108 is connected belongs. In the exemplary system 100 shown in FIG. 1, two microchips 108 are each connected to two hubs 102, the two hubs 102 form a part of the cache coherent region 116, and the two microchips 108 each form a part of a respective memory region 124 (delimited by the dotted lines in FIG. 1) having input / output coherence with respect to the memory region 116.

[0076] As an example, this input / output coherence between the memory region 124 to which the microchip 108 belongs and the cache coherent memory region 116 to which the hub 102 to which this microchip 108 is connected belongs is realized by the hub(s) 102 of the system 100.

[0077] Each port P3 of each hub 102 can be connected to the accelerator microchip 108 via the link 122, or can be left unconnected entirely.

[0078] Although not shown in the exemplary system 100 illustrated in FIG. 1, in addition to the physical ports P1, P2, and P3, and the interfaces ITm and ITs, each hub may include at least one Ethernet-type interface ITe, for example, for connection to a modem, i.e., a modulator / demodulator circuit, or for example, for connection to a light detection and ranging (LIDAR) sensor (thus, like the interface ITs, the interface ITe can be used to connect the sensor 104 to the hub 102), and / or at least one interface ITd for connection to a display, for example, a low voltage differential signaling (LVDS) interface may also be provided.

[0079] Furthermore, although not shown in the exemplary system 100 of FIG. 1, in addition to its processing circuit(s) and the physical ports and interfaces of the network-on-chip, each circuit 102 may include a direct memory access (DMA) circuit. This circuit is configured to handle data transfers, for example, mainly data from the sensor 104 connected to the interface ITs or ITe of the hub 102.

[0080] Preferably, if the system 100 includes several hubs 102 connected within a network, these hubs are identical to each other.

[0081] As an example, ports P3 and P3a are each configured to implement the "CXL.mem", "CXL.io", or "PCIe" protocol during data exchange between the hub 102 and the accelerator microchip 108 when the port P3 is connected to the port P3a via the link 122.

[0082] As an example, ports P2 and P2c are each configured to implement the "CXL.cache" and "CXL.mem" protocols when port P2 is connected to port P2c via link 120, i.e., during data exchange between hub 102 and computing microchip 106.

[0083] As an example, each port P1 is configured to implement the "CXL.mem" and "CXL.cache" or "AXI stream" protocols when connected to the port P1 of another hub 102 via link 112, i.e., during data exchange with this other hub.

[0084] FIG. 2 shows in more detail an exemplary embodiment of circuit 102 of the system shown in FIG. 1.

[0085] Circuit 102 (block "COM HUB" in FIG. 2), as shown above in connection with FIG. 1, has at least two ports P1, for example, in the example shown in FIG. 2, exactly two ports P1, at least one port P2, for example, in the example shown in FIG. 2, exactly one port P2, at least one port P3, for example, in the example shown in FIG. 2, exactly one port P3, at least one interface ITs, for example, in the example shown in FIG. 2, exactly five interfaces ITs, for example, all of CSI type, at least one interface ITm, for example, in the example shown in FIG. 2, exactly two interfaces ITm, for example, one FLASH type interface ITm and one DDR type interface ITm, at least one processing unit, shown as block PU in FIG. 2, and, network-on-chip NoC and includes.

[0086] In the example shown in FIG. 2, circuit 102 further includes a direct memory access circuit (block "DMA" in FIG. 2).

[0087] Furthermore, in the example shown in FIG. 2, circuit 102 includes at least one Ethernet type interface ITe, for example, exactly three interfaces ITe in the example shown in FIG. 2.

[0088] Furthermore, in this example, circuit 102 includes at least one interface ITd, for example, exactly one interface ITd in the example shown in FIG. 2, for example, of the low voltage differential signaling (LVDS) type.

[0089] FIG. 3 shows in more detail an exemplary embodiment of the computing microchip 106 of the system 100 shown in FIG. 1.

[0090] Microchip 106 (block "chiplet C" in FIG. 3) includes at least one memory interface ITmc, preferably a single memory interface ITmc. For example, this interface ITmc is of the DDR type and is configured to be connected to a DDR type memory 110.

[0091] Microchip 106 further includes a physical port P2c for connecting to port P2 of hub 102 via link 120.

[0092] Finally, microchip 106 includes one or more processing units, represented by a single block PU in FIG. 3. By way of example, the processing unit(s) of microchip 106 are selected from the group consisting of a CPU, a GPU, and an NPU. By way of example, since microchip 106 is designed to implement general functions as compared to the specific functions of microchip 108, microchip 106 does not include a DSP.

[0093] Preferably, all the microchips 106 within the system 100 have an architecture similar to or identical to the architecture of the microchip 106 described in connection with FIG. 3.

[0094] FIG. 4 shows in more detail an exemplary embodiment of the accelerator microchip 108 of the system 100 shown in FIG. 1.

[0095] The microchip 108 (block “Chiplet A” in FIG. 4) comprises at least one memory interface ITma, preferably a single memory interface ITma. For example, this interface ITma is of the DDR type and is configured to be connected to the DDR type memory 110.

[0096] The microchip 108 further comprises a physical port P3a for connecting to port P3 of the hub 102 via the link 122.

[0097] Finally, the microchip 108 comprises one or more processing units, represented by the single block ACC in FIG. 4. By way of example, the processing unit(s) of the microchip 108 are selected from the group consisting of a CPU, a GPU, a DSP and an NPU. By way of example, since the microchip 108 is designed to implement specific functions as compared to the general functions of the microchip 106, the microchip 108 comprises a DSP and / or a GPU.

[0098] Preferably, all the microchips 108 within the system 100 have an architecture similar to or identical to the architecture of the microchip 108 described in connection with FIG. 4.

[0099] According to one embodiment, the processing unit(s) PUs of the microchip 108 are configured to implement assistance or autonomous driving functions.

[0100] Next, various examples of systems based on at least one hub 102 and, if required by the application, at least one microchip 106 and / or at least one microchip 108 will be described.

[0101] Of course, these examples of systems are not limiting, and those skilled in the art will be able to foresee many other examples of systems or computers obtained by assembling, i.e., reassembling, one or more hubs 102 together with one or more microchips 106 and / or 108.

[0102] FIG. 5 schematically shows an exemplary embodiment of a computing and data processing system 500 in block form.

[0103] Compared with system 100, system 500 has only one circuit 102 and lacks microchips 106 and microchip 108.

[0104] In other words, system 500 has exactly one circuit 102, and no microchips 106 or 108 are connected to this circuit 102.

[0105] Memory circuit 110 is connected to interface ITm of circuit 102.

[0106] Circuit 102 and its associated memory 110 belong to cache coherent memory region 116.

[0107] Since circuit 102 includes at least one processing unit, system 500 can handle processing and computing requirements even if microchips 106 and 108 are not connected to circuit 102.

[0108] FIG. 6 schematically shows an exemplary embodiment of a computing and data processing system 600 in block form.

[0109] Similar to system 500, system 600 includes exactly one circuit 102 and a memory circuit 110 associated with this circuit 102.

[0110] However, compared to system 500, the microchip 106 is connected to port P2 of circuit 102 via link 120. For example, link 120 connects port P2 of circuit 102 to port P2c of microchip 106.

[0111] In this example, the memory circuit 110 is connected to the interface ITmc of the microchip 106, and this memory is associated with the microchip 106.

[0112] Hub 102 and its associated memory 110, as well as microchip 106 and its associated memory 110, are part of the same cache - coherent memory region 116.

[0113] FIG. 7 schematically shows an exemplary embodiment of a computing and data - processing system 700 in block form.

[0114] Compared to systems 500 and 600, system 700 includes exactly two hub circuits 102, exactly one microchip 106, and exactly one microchip 108.

[0115] The two circuits 102 are connected to each other. For example, port P1 of one circuit 102 is connected to port P1 of the other circuit 102 via link 112.

[0116] As an example, each circuit 102 is associated with a corresponding memory circuit 110. For example, each circuit 102 has an interface ITm that is connected to the memory circuit 110 with which it is associated.

[0117] Microchip 106 is connected via link 120 to port P2 of the first of the two circuits 102 (the left circuit 102 in FIG. 7), for example, link 120 connects port P2 of the first circuit 102 to port P2c of microchip 106.

[0118] In this example, memory circuit 110 is connected to interface ITmc of microchip 106, and this memory is associated with microchip 106.

[0119] Furthermore, microchip 108 is connected via link 122 to port P3 of the second of the two circuits 102 (the right circuit 102 in FIG. 7), for example, link 122 connects port P3 of the second circuit 102 to port P3a of microchip 108.

[0120] In this example, memory circuit 110 is connected to interface ITma of microchip 108, and this memory is associated with microchip 108.

[0121] The two hubs 102 and their associated memories 110, and microchip 106 and its associated memory 110 form part of a single cache coherent memory region 116.

[0122] In contrast, microchip 108 and its associated memory 110 form part of another memory region 124, which is input / output coherent with respect to memory region 116.

[0123] FIG. 8 schematically shows an exemplary embodiment of a computing and data processing system 800 in block form.

[0124] Similar to system 700, system 800 includes exactly two hub circuits 102. However, unlike system 700, system 800 includes exactly two microchips 106 and does not include microchip 108.

[0125] The two circuits 102 are connected to each other. For example, port P1 of one circuit 102 is connected via link 112 to port P1 of the other circuit 102.

[0126] As an example, each circuit 102 is associated with a corresponding memory circuit 110. For example, each circuit 102 has an interface ITm that connects it to the memory circuit 110 with which it is associated.

[0127] The first microchip 106 is connected via link 120 to port P2 of the first of the two circuits 102. For example, link 120 connects port P2 of the first circuit 102 to port P2c of the first microchip 106.

[0128] In this example, the memory circuit 110 is connected to the interface ITmc of the first microchip 106, and this memory is associated with the microchip 106.

[0129] Furthermore, the second microchip 106 is connected via link 120 to port P2 of the second of the two circuits 102. For example, link 120 connects port P2 of the second circuit 102 to port P2c of the second microchip 106.

[0130] In this example, the memory circuit 110 is connected to the interface ITmc of the second microchip 106, and this memory is associated with the microchip 106.

[0131] The two hubs 102 and their associated memories 110, and the two microchips 106 and their associated memories 110 form part of a single cache coherent memory region 116.

[0132] FIG. 9 schematically shows an exemplary embodiment of a computing and data processing system 900 in block form.

[0133] System 900 includes exactly four circuits 102, namely, a first hub 102 (upper left in FIG. 9), a second hub 102 (upper right in FIG. 9), a third hub 102 (lower right in FIG. 9), and a fourth hub 102 (lower left in FIG. 9).

[0134] In this example, each of the hubs 102 is associated with a corresponding memory circuit 110, and the memory circuit 110 associated with the hub 102 is connected to the interface ITm of this hub 102.

[0135] The circuits 102 are connected to each other. For example, the circuits 102 form a two-dimensional network. For example, port P1 of the first circuit 102 is connected to port P1 of the second circuit 102 by a first link 112, another port P1 of the second circuit 102 is connected to port P1 of the third circuit 102 by a second link 112, another port P1 of the third circuit 102 is connected to port P1 of the fourth circuit by a third link 112, and another port P1 of the fourth circuit is connected to another port P1 of the first circuit 102 by a fourth link 112.

[0136] Furthermore, system 900 includes exactly two microchips 106. The first microchip 106 is connected to port P2 of the third circuit 102 via a link 120. For example, link 120 connects port P2 of the third circuit 102 to port P2c of the first microchip 106. In this example, a memory circuit 110 is connected to the interface ITmc of the first microchip 106, and this memory is associated with the microchip 106. The second microchip 106 is connected to port P2 of the fourth circuit 102 via a further link 120. For example, this further link 120 connects port P2 of the fourth circuit 102 to port P2c of the second microchip 106. In this example, a memory circuit 110 is connected to the interface ITmc of the second microchip 106, and this memory is associated with the microchip 106.

[0137] Furthermore, system 900 comprises exactly two microchips 108. The first microchip 108 is connected to port P3 of the first circuit 102 via link 122. For example, link 122 connects port P3 of the first circuit 102 to port P3a of the first microchip 108. In this example, the memory circuit 110 is connected to interface ITma of the first microchip 108, and this memory is associated with the microchip 108. The second microchip 108 is connected to port P3 of the second circuit 102 via a further link 122. For example, this further link 122 connects port P3 of the second circuit 102 to port P3a of the second microchip 108. In this example, the memory circuit 110 is connected to interface ITma of the second microchip 108, and this memory is associated with the microchip 108.

[0138] The two hubs 102 and their associated memories 110, and the two microchips 106 and their associated memories 110 form part of the same cache coherent memory region 116.

[0139] In contrast, the two microchips 108 and their associated memories 110 each form part of another memory region 124, which is input / output coherent with respect to the memory region 116.

[0140] Figure 10 shows, in tabular form, the suitability of the systems shown in FIGS. 5-9 for the computing and data processing requirements of a certain lineup of motor vehicles.

[0141] In particular, the x-axis of the table (referred to as MEDIA in FIG. 10) represents the computing and data processing requirements as a function of the multimedia experience provided by the vehicle, and these requirements are lowest when the vehicle provides a low multimedia experience ("BASIC, MID" in FIG. 10), higher when the vehicle provides a medium multimedia experience ("HIGH" in FIG. 10), and highest when the vehicle provides a high multimedia experience ("PREMIUM" in FIG. 10).

[0142] Furthermore, the y-axis of the table (referred to as ADAS in FIG. 10) represents the level of the pilot assistance system ADAS. Only levels L2, L2+, L3, and L4 are shown in FIG. 10, and levels L3 and L4 are grouped into a single group L3, L4.

[0143] For a vehicle that provides multimedia experiences BASIC, MID with ADAS level L2, i.e., a low-end vehicle, a single circuit 102 can meet the computing and data processing requirements of the vehicle, and system 500 can be used as the computer of this vehicle.

[0144] For a vehicle that has the same infotainment levels BASIC, MID but has ADAS level L2+, the increase in the ADAS level results in an increase in computing and data processing requirements, and thus a microchip 106 is added to meet this increase. Therefore, system 600 can handle the application requirements of this vehicle. And the microchip 106 of system 600 is configured to handle calculations related to, for example, ADAS level L2+.

[0145] Furthermore, the microchip 106 of system 600 is sufficiently general-purpose to handle the computing and data processing requirements of vehicles with infotainment level HIGH and ADAS level L2 or even L2+.

[0146] In contrast, for vehicles with infotainment levels BASIC, MID, or HIGH and ADAS levels L3 or L4, additional microchips 108 and hubs 102 are required for the calculations and processing requirements specific to ADAS levels L3 and L4. In this way, system 700 is enabled to handle the computing and data processing requirements of vehicles with ADAS levels L3 or L4 and infotainment levels BASIC, MID, or HIGH.

[0147] For vehicles with an Infotainment level of PREMIUM, the computing and data processing requirements increase, especially due to the increase in screen management and the number of infotainment devices, as compared to Infotainment levels HIGH, BASIC, and MID. However, as long as the ADAS level of the vehicle is L2+ or L2, the computing and data processing requirements remain relatively common. And the computing and data processing requirements are addressed by a system 800 having two hubs 102, each of which is associated with a microchip 106 for performing the computing and data processing associated with this infotainment level and the ADAS level L2 or L2+.

[0148] Finally, for vehicles with an Infotainment level of PREMIUM and an ADAS level of L3 or L4, by using four circuits 102, it becomes possible to manage the large amount of data processed and redistributed within the system. By using two microchips 106, the general computing and data processing requirements associated with the Infotainment level PREMIUM can be met, and by using two microchips 108, the specific computing and data processing requirements associated with the ADAS level L3 or L4 can be met. Therefore, the system 900 can meet the requirements of the vehicles in this lineup.

[0149] Various embodiments and variations have been described. Those skilled in the art will understand that specific features of these embodiments can be combined and other variations will readily occur to them. In particular, while the circuits 102, and more generally, the computing and data processing systems, have been shown in the context of the automotive field, the circuits 102 obtained from the module structure from at least one circuit 102 as well as the computing and data processing systems can be used with the same advantages in other fields such as, for example, the field of avionics, the field of drones, the field of robotics, etc. Further, while in the above two hubs 102 forming part of the same system or computer are interconnected via their ports P1 and links 112, the case where the two hubs form part of the same cache coherent memory region has been described, but by way of example, it is also possible to interconnect two systems or computers via a link 112 between port P1 of a hub of the first system and port P1 of a hub of the second system. In the latter case, the two hubs are preferably part of two memory regions having different cache coherencies, for example, input / output coherency is achieved between the two hubs, i.e., between the two systems. In other words, port P1 configured to achieve cache coherency is preferably also configured to enable the achievement of input / output coherency, but the reverse is not true. For example, connecting several systems together can realize a redundant system.

[0150] Finally, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional description provided above.

Claims

1. 1. A communications hub circuit comprising: at least two first physical ports, each configured to exchange data with another communications hub circuit that forms part of the same cache coherent memory region as said hub circuit, when said first ports are connected to said other communications hub circuit via a high speed link; at least one second physical port configured to exchange data with a computing microchip forming part of the same cache coherent memory region when the at least one second physical port is connected to the computing microchip via a high speed link; at least one third physical port, the accelerator microchip forming part of an I / O coherent memory region for the same cache coherent memory region, the at least one third physical port configured to exchange data when the at least one third physical port is connected to the accelerator microchip via a high speed link; at least one first interface configured to exchange data with a memory circuit that forms part of the same cache coherent memory region when the at least one first interface is connected to the memory circuit; at least one second interface configured to exchange data with the sensor; at least one processing circuit configured to perform data processing; at least one network-on-chip configured to transfer data between elements of the communications hub circuit, the elements comprising the at least two first ports, the at least one second port, the at least one third port, the at least one processing circuit, and the at least one first interface; A communication hub circuit comprising:

2. each of the at least two first physical ports is configured to implement a CXL.mem and CXL.cache or an AXI stream protocol when exchanging data with the other communications hub circuit; The at least one second physical port is configured to implement CXL.cache and CXL.mem protocols when exchanging data with the computing microchip; and 2. The hub circuit of claim 1, wherein the at least one third physical port is configured to implement a CXL.mem, CXL.io, or PCIe protocol when exchanging data with the accelerator microchip.

3. 10. The hub circuit of claim 1, wherein the hub circuit is configured to merge received ones of the data flows without performing any processing on the ones of the data flows.

4. 10. The hub circuit of claim 1, wherein the hub circuit is configured to perform processing on received separate data flows and then merge the results of those processing.

5. The hub circuit of claim 1 , wherein the hub circuit is configured to provide cache coherency within the same cache coherent memory region.

6. 2. The hub circuit of claim 1, wherein the hub circuit is configured to provide I / O coherency between the same cache coherent memory region and other memory regions in which accelerator microchips reside.

7. 2. The hub circuit of claim 1, wherein the at least one first interface comprises an interface for a DDR type memory and / or an interface for a FLASH type memory.

8. The hub circuit of claim 1 , wherein said hub circuit further comprises a direct memory access circuit.

9. 2. The hub circuit of claim 1, wherein the at least one second interface comprises at least one CSI type interface and / or at least one Ethernet type interface.

10. The hub circuit of claim 1 , wherein the hub circuit further comprises at least one third interface configured to exchange data with a display.

11. Exactly one hub circuit according to any one of claims 1 to 10; a memory coupled to the at least one first interface; and wherein neither a computing microchip nor an accelerator microchip is connected to the hub circuit. system.

12. Exactly one hub circuit according to any one of claims 1 to 10; a computing microchip connected to the at least one second port of the hub circuit by a high speed link; and no other computing microchip or accelerator microchip is connected to the hub circuit. system.

13. exactly one first hub circuit according to any one of claims 1 to 10, and one second hub circuit according to any one of claims 1 to 10, wherein one of the first ports of the first hub circuit is connected to one of the first ports of the second hub circuit by a first high speed link; a first computing microchip connected to the at least one second port of the first hub circuit by a second high speed link, where no other computing microchips or accelerator microchips are connected to the first hub circuit; a second computing microchip connected to the at least one second port of the second hub circuit by a third high speed link, where no other computing microchips or accelerator microchips are connected to the second hub circuit; A system comprising:

14. exactly one first hub circuit according to any one of claims 1 to 10, and one second hub circuit according to any one of claims 1 to 10, wherein one of the first ports of the first hub circuit is connected to one of the first ports of the second hub circuit by a first high speed link; a first computing microchip connected to the at least one second port of the first hub circuit by a second high speed link, where no other computing microchips or accelerator microchips are connected to the first hub circuit; a first accelerator microchip connected to the at least one third port of the second hub circuit by a third high speed link, where no other accelerator microchips or computing microchips are connected to the second hub circuit; A system comprising:

15. exactly one first hub circuit according to any one of claims 1 to 10, a second hub circuit according to any one of claims 1 to 10, a third hub circuit according to any one of claims 1 to 10, and a fourth hub circuit according to any one of claims 1 to 10, wherein one of the first ports of the first circuit is connected to one of the first ports of the second circuit by a first high speed link, another one of the first ports of the second circuit is connected to one of the first ports of the third circuit by a second high speed link, another one of the first ports of the third circuit is connected to one of the first ports of the fourth circuit by a third high speed link, and another one of the first ports of the fourth circuit is connected to another one of the first ports of the first circuit by a fourth high speed link; a first computing microchip connected to the at least one second port of the first hub circuit by a fifth high speed link, wherein no other computing microchips or accelerator microchips are connected to the first hub circuit; a second computing microchip connected to the at least one second port of the second hub circuit by a sixth high speed link, where no other computing microchips or accelerator microchips are connected to the second hub circuit; a first accelerator microchip connected to the at least one third port of the third hub circuit by a seventh high speed link, where no other accelerator microchips or computing microchips are connected to the third hub circuit; a second accelerator microchip connected to the at least one third port of the fourth hub circuit by an eighth high speed link, where no other accelerator microchips or computing microchips are connected to the fourth hub circuit; A system comprising:

16. 15. The system of claim 14, wherein each accelerator microchip is configured to perform data processing for a Level L2+, L3, or L4 advanced pilot assistance system.

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