Semiconductor device, and manufacturing method thereof

Abstract

To provide a manufacturing method of a high-density semiconductor device with an excellent chip-to-chip transmission capable of being manufactured with satisfactory yield and at a low cost.SOLUTION: The manufacturing method of a high-density semiconductor device includes: an insulation layer forming step of forming an insulation layer 3 having a groove 4 on a circuit board 1; a copper layer forming step of forming a copper layer 5a over the insulation layer 3 to fill the groove 4; and a removal step of removing the copper layer 5a on the insulation layer 3 excluding the copper layer part in the groove 4 by the fly cut method.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. More specifically, the present disclosure relates to a manufacturing method for efficiently and inexpensively manufacturing a semiconductor device with high requirements for miniaturization and high density, and a semiconductor device manufactured by the manufacturing method.

Background Art

[0002] For the purpose of high density and high performance of semiconductor packages, a mounting form in which chips with different performances are mixed and mounted in one package has been proposed. In this case, a high-density interconnect technology between chips, which is excellent in terms of cost, has become important (see, for example, Patent Document 1).

[0003] Package-on-package, which is connected by laminating different packages on a package by flip-chip mounting, is widely adopted in smartphones and tablet terminals (see, for example, Non-Patent Document 1 and Non-Patent Document 2).

[0004] Furthermore, as other forms for mounting a plurality of chips at high density, package technologies using an organic substrate having high-density wiring (organic interposer), fan-out type package technologies having through-mold vias (TMV) (FO-WLP), package technologies using a silicon or glass interposer, package technologies using through-silicon vias (TSV), or package technologies using chips embedded in a substrate for inter-chip transmission have been proposed.

[0005] Particularly in the case of organic interposers and FO-WLP, when semiconductor chips are mounted in parallel, a fine wiring layer is required to conduct the semiconductor chips at high density (see, for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

[0007] [Non-Patent Document 1] Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 [Non-Patent Document 2] Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012 [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] In order to form fine wiring, usually, processes such as seed layer formation by sputtering, resist formation, electroplating, resist removal, and removal of unnecessary seed layers are required, and the process cost has been a problem. Therefore, in the formation of fine wiring, cost reduction by simplifying the above processes is strongly desired.

[0009] An object of the present disclosure is to provide a high-density semiconductor device excellent in chip-to-chip transmission and a manufacturing method thereof that can be manufactured with good yield and low cost. [Means for Solving the Problems]

[0010] As a result of advancing studies to solve the above problems, the inventors have found a manufacturing method having excellent characteristics.

[0011] The first aspect of this embodiment is a method for manufacturing a semiconductor device, which includes an insulating layer forming step of forming an insulating layer having a groove portion on a substrate, a copper layer forming step of forming a copper layer on the insulating layer so as to fill the groove portion, and a removing step of leaving the copper layer portion in the groove portion and removing the copper layer on the insulating layer by a fly cut method.

[0012] According to the first aspect of this embodiment, when forming the wiring (the copper layer portion in the groove), chemical mechanical polishing (CMP) is not required, the yield can be improved compared with the conventional process, and since dishing of the wiring (copper) does not occur, wiring can be formed at high density and the manufacturing cost can be significantly reduced.

[0013] The second aspect of this embodiment is a semiconductor device in which semiconductor elements are mounted on a wiring body provided on a substrate. The wiring body has a plurality of wiring layers laminated on each other, and each of the plurality of wiring layers is provided with an insulating layer having a groove portion on one surface side of the wiring layer and a copper wiring formed so as to fill the groove portion, and the surface roughness of the insulating layer and the copper wiring on one surface side is 0.03 μm or more and 0.1 μm or less.

[0014] According to the second aspect of this embodiment, the surface roughness of the insulating layer and the copper wiring on one surface side of each wiring layer is 0.03 μm or more and 0.1 μm or less. This surface roughness is a larger value compared with the surface roughness when the insulating layer and the copper wiring are exposed using CMP. Therefore, when manufacturing the above semiconductor device, it is not necessary to use CMP when forming the copper wiring in the groove portion, so the yield can be improved compared with the conventional process, and since dishing of the copper wiring does not occur, wiring can be formed at high density and the manufacturing cost can be significantly reduced. In addition, since the insulating layer and the copper wiring on one surface side of each of the plurality of wiring layers have the above surface roughness, the adhesion between the wiring layers that contact each other through the one surface side can be improved. Thereby, peeling of the wiring layer can be suppressed.

Effects of the Invention

[0015] According to this embodiment, a high-density semiconductor device excellent in transmission between chips can be provided with good yield and low cost.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

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Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

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Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Embodiments for Carrying Out the Invention

[0017] Hereinafter, this embodiment will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions are omitted. Also, the positional relationships such as up, down, left, right, etc. are based on the positional relationships shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[0018] In the description and claims, when terms such as "left", "right", "front", "back", "up", "down", "above", "below", "first", "second", etc. are used, these are for the purpose of explanation and are not necessarily always in this relative position. Also, the term "layer" includes not only a structure formed over the entire surface when observed as a plan view, but also a structure formed in part. Also, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended purpose of that process is achieved. Also, the numerical range indicated using "~" indicates a range including the numerical values described before and after "~" as the minimum value and the maximum value, respectively. Also, in the numerical ranges described step by step in this specification, the upper limit value or the lower limit value of a numerical range at a certain step may be replaced with the upper limit value or the lower limit value of a numerical range at another step.

[0019] A method for manufacturing a semiconductor package (semiconductor device) 101 shown in FIG. 6 and a semiconductor package (semiconductor device) 103 shown in FIG. 16 according to an embodiment of the present disclosure will be described. Note that the method for manufacturing a semiconductor device of the present disclosure is particularly suitable in a form that requires miniaturization and multi-pinning. In particular, the manufacturing method of the present disclosure can be used in a package form that requires an interposer for mounting different types of chips.

[0020] With reference to FIGS. 1 to 6, a method for manufacturing the semiconductor package 101 will be described.

[0021] As shown in FIG. 1, first, a first copper wiring 2 is formed on a substrate 1 (copper wiring forming step). Thereby, the first copper wiring 2 patterned on a part of the upper surface of the substrate 1 is formed.

[0022] The substrate 1 is not particularly limited, but is a silicon plate, a glass plate, a SUS plate, a substrate including a glass cloth (for example, prepreg, etc.), or a resin substrate for sealing a semiconductor element. The substrate 1 may be a substrate having a storage elastic modulus of 1 GPa or more at 25°C.

[0023] The thickness t0 of the substrate 1 is, for example, 0.2 to 2.0 mm. When the thickness t0 is 0.2 mm or more, the handleability of the substrate 1 is improved. When the thickness t0 is 2.0 mm or less, the material cost of the substrate 1 tends to be suppressed low.

[0024] The substrate 1 may be in the form of a wafer or a panel. The size of the substrate 1 in plan view is not particularly limited. When the substrate 1 is in the form of a wafer, the diameter of the substrate 1 is, for example, 200 mm, 300 mm, or 450 mm. When the substrate 1 is in the form of a panel, the substrate 1 is, for example, a rectangular panel with a side length of 300 to 700 mm.

[0025] The first copper wiring 2 can be formed, for example, by an inkjet method, a screen printing method, or a spray coating method. For example, the first copper wiring 2 can be formed on the substrate 1 by using a printing apparatus to apply a copper paste onto the substrate 1. Further, a copper layer can be formed by copper foil lamination, sputtering, or plating, and then etched through a resist pattern to form the first copper wiring 2. By forming the first copper wiring 2 using a copper paste, a seed layer for wiring formation is not required, and the resist formation process and the resist removal process can also be omitted. Therefore, the manufacturing cost can be significantly reduced as compared with the conventional process of forming a seed layer.

[0026] The copper paste is a material in which copper particles are dispersed in a solvent. The solvent for dispersing the copper particles is not particularly limited, but a solvent containing a compound having an alcohol group, an ester group, an amino group, or the like can be used.

[0027] The average particle diameter of the copper particles is not particularly limited, but is, for example, 10 to 500 nm. From the viewpoint of dispersibility, the average particle diameter of the copper particles is preferably 20 to 300 nm. Further, from the viewpoint of sinterability, the average particle diameter of the copper particles is more preferably 50 to 200 nm. The average particle diameter of the copper particles in this specification is the arithmetic average value of the major axis lengths measured for 200 randomly selected copper particles. Note that the major axis length of the copper particles can be measured, for example, using a scanning electron microscope.

[0028] The viscosity of the copper paste can be selected according to the usage method. For example, when applying the copper paste onto the substrate 1 using the screen printing method, the viscosity of the copper paste may be 0.1 to 30 Pa·s. Further, when using the inkjet printing method or the spray coating method, the viscosity of the copper paste may be 0.1 to 30 mPa·s.

[0029] Next, as shown in FIG. 2, an insulating layer 3 covering the first copper wiring 2 is formed on the substrate 1 (insulating layer formation step).

[0030] The insulating layer 3 is formed using, for example, a liquid or film-like insulating material. From the viewpoints of film thickness flatness and cost, it is preferable to use a film-like insulating material. Further, the insulating layer 3 may contain a filler. The average particle size of this filler is, for example, 500 nm or less from the viewpoint of forming the fine groove portion 4. The content of the filler with respect to the total amount of the insulating material may be, for example, less than 1% by mass. Note that the insulating layer 3 may not contain a filler.

[0031] When forming the insulating layer 3 using the above film-like insulating material, for example, the insulating material is pasted onto the substrate 1 on which the first copper wiring 2 is formed by a lamination process. This lamination process is performed, for example, with the temperature set to 40 to 120°C. Therefore, it is preferable to use a photosensitive insulating film that can be laminated at 40 to 120°C as the film-like insulating material. By setting the laminatable temperature to 40°C or higher, it is possible to suppress the increase in the tack (adhesiveness) of the photosensitive insulating film at room temperature and maintain good handleability of the photosensitive insulating film. By setting the laminatable temperature of the photosensitive insulating film to 120°C or lower, it is possible to prevent warping of the photosensitive insulating film after the lamination process. Note that "room temperature" indicates about 25°C.

[0032] The thickness of the insulating layer 3 is, for example, 10 μm or less from the viewpoint of forming the fine groove portion 4 described later. Further, the thickness of the insulating layer 3 is preferably 5 μm or less, and more preferably 3 μm or less. Also, the thickness of the insulating layer 3 is, for example, 1 μm or more from the viewpoint of electrical reliability.

[0033] The thermal expansion coefficient of the insulating layer 3 after curing is, for example, 80 ppm / °C or less from the viewpoint of suppressing warping of the insulating layer 3. The thermal expansion coefficient is preferably 70 ppm / °C or less from the viewpoint of suppressing peeling or cracking in the reflow process and the temperature cycle test. Also, the thermal expansion coefficient is more preferably 20 ppm / °C or more from the viewpoint of improving the stress relaxation property of the insulating layer 3 and facilitating the formation of the fine groove portion 4.

[0034] After forming the insulating layer 3, a groove portion 4 is formed in the insulating layer 3 (groove forming step). Both side walls of the groove portion 4 are formed of the insulating layer 3. A part of the upper surface of the first copper wiring 2 is exposed from between both side walls in a part of the groove portion 4. The groove portion 4 has a line width of, for example, 0.5 to 5 μm.

[0035] Specifically, in the groove forming step, as the groove portion 4 having a substantially rectangular cross-section, a plurality of first groove portions 4a formed so as to overlap the first copper wiring 2 and a plurality of second groove portions 4b formed so as not to overlap the first copper wiring 2 are formed. The first groove portion 4a is provided so as to expose the upper surface of the first copper wiring 2. Therefore, both side surfaces (both side walls) of the first groove portion 4a are constituted by the insulating layer 3, and the bottom surface of the first groove portion 4a is constituted by the first copper wiring 2. Accordingly, in the state after the completion of the groove forming step, a part of the upper surface of the first copper wiring 2 is exposed from between both side walls of the first groove portion 4a. On the other hand, both side surfaces (both side walls) and the bottom surface of the second groove portion 4b are constituted by the insulating layer 3. Note that at least a part of the bottom surface of the first groove portion 4a may be constituted by the first copper wiring 2, and a part of the bottom surface of the first groove portion 4a may be constituted by the insulating layer 3.

[0036] Examples of the method for forming the groove portion 4 include laser ablation, photolithography, or imprinting. From the viewpoints of miniaturization and cost of the groove portion 4, photolithography that performs exposure and development is preferable. When using photolithography, it is preferable to use a film-like photosensitive resin material (photosensitive insulating film) having insulating properties as the insulating layer 3.

[0037] When the insulating layer 3 is a photosensitive insulating film, the groove portion 4 can be formed by directly performing exposure and development on the insulating layer 3 without using a resist mask. In this case, the resist forming step and the resist removing step can be omitted, so that the simplification of the process can be realized. Note that the photosensitive resin material may be a negative type or a positive type.

[0038] As a method of exposing the photosensitive resin material in the above photolithography, a known projection exposure method, contact exposure method, direct drawing exposure method, or the like can be used. Further, in order to develop the photosensitive resin material, an alkaline aqueous solution such as sodium carbonate or TMAH may be used.

[0039] In the groove forming step, after forming the groove 4, the insulating layer 3 may be further heat-cured. For example, the heating temperature is set to 100 to 200 ° C, and the heating time is set to 30 minutes to 3 hours, and then the insulating layer 3 is heat-cured.

[0040] Next, as shown in FIG. 3, a copper layer 5a is formed so as to cover the groove 4 (copper layer forming step).

[0041] Specifically, for example, by applying a copper paste on the upper surface of the insulating layer 3, the copper paste is applied on the insulating layer 3 so as to fill the groove 4 (the first groove 4a and the second groove 4b) (coating step). Then, the applied copper paste is sintered to obtain a sintered copper layer 5a (sintering step). The copper layer 5a (particularly, the copper layer portion in the groove 4) is electrically connected to the first copper wiring 2 exposed from the groove 4. Here, it is considered that the copper layer 5a obtained by sintering the copper paste and the copper obtained by conventional sputtering, plating, etc. have different densities. Therefore, for example, based on the cross-sectional view, the two can be judged. By forming the copper layer 5a using the copper paste, a seed layer for forming the second copper wiring 5 described later is not required, and the resist forming step and the resist removing step can also be omitted. Therefore, the manufacturing cost can be significantly reduced as compared with the conventional process of forming the seed layer.

[0042] Examples of the method of applying the copper paste include an inkjet method, a printing method, a spin coating method, or a spray coating method.

[0043] As a method for sintering the copper paste, for example, sintering by heating or photo-sintering by xenon flash can be mentioned. When sintering the copper paste by heating, for example, the sintering process of the copper paste is performed in a nitrogen atmosphere, in the presence of hydrogen, or in the presence of an acid. From the viewpoint of obtaining a dense copper layer with a low volume resistance value, it is preferable to perform the sintering process in the presence of an acid. The presence of an acid means that there is an acid volatilized in the gas. Further, as the acid, formic acid, acetic acid, etc. can be used, and it is preferable to use formic acid. From the viewpoint of obtaining a dense copper layer with a low volume resistance value in a shorter time, it is more preferable to perform the sintering process in an atmosphere in which nitrogen and formic acid are mixed. The formic acid content in nitrogen is, for example, 0.005 to 10% by volume. From the viewpoint of obtaining a homogeneous copper layer, the formic acid content in nitrogen is preferably 0.01 to 5% by volume.

[0044] From the viewpoint of being able to sinter in a short time and suppressing the thermal denaturation of the insulating layer, the sintering temperature of the copper paste is set, for example, to 80 to 200°C. From the viewpoint of reducing the volume resistance value, it is preferable to set the sintering temperature to 120 to 200°C. Further, from the viewpoint of obtaining a denser copper layer, it is more preferable to set the sintering temperature to 120 to 180°C.

[0045] From the viewpoint of transmission efficiency, the volume resistivity of the sintered copper layer is, for example, 40 μΩ·cm or less. From the viewpoint of suppressing the calorific value, it is preferable that the volume resistivity is 30 μΩ·cm or less. Further, from the viewpoint of reliability, it is more preferable that the volume resistivity is 20 μΩ·cm or less. Incidentally, the volume resistivity is usually 3 μΩ·cm or more.

[0046] Next, as shown in FIG. 4, the copper layer 5a on the upper part of the insulating layer 3 is removed by the fly cut method (removing step). Thereby, the copper layer portion filled in the groove portion 4 is exposed, and a wiring layer 30 having the first copper wiring 2, the insulating layer 3, and the copper layer portion filled on the insulating layer 3 is formed.

[0047] Specifically, leaving the copper layer portion in the groove portion 4, the copper layer 5a on the insulating layer 3 is removed by the fly-cut method. As a result, the copper layer portion that is applied and sintered in the groove portion 4 provided in the insulating layer 3 is exposed.

[0048] Note that the copper layer portion in the first groove portion 4a in the groove portion 4 can also be said to be the second copper wiring 5 electrically connected to the first copper wiring 2. That is, in the above removal step, a part of the copper layer 5a is removed to form the second copper wiring 5. As shown in FIG. 3, the copper layer 5a is formed on the entire surfaces of the insulating layer 3 and the groove portion 4. In other words, the copper layer 5a is also formed in a region other than the region (groove portion 4) where the second copper wiring 5 is to be formed. Therefore, the above removal step can be said to be a step of removing the copper layer portion formed in the region other than the inside of the groove portion 4 in the copper layer 5a.

[0049] In the fly-cut method, for example, a grinding device using a diamond bite is used. As a specific example, an automatic surface planer compatible with a 300 mm wafer (manufactured by DISCO Corporation, product name "DAS8930") can be used. Note that the above removal of the copper layer 5a by the fly-cut method can also be said to be a planarization process. Further, in the above removal step, etching or the like may be combined in addition to the fly-cut method.

[0050] When removing the copper layer 5a on the insulating layer 3 while leaving the copper layer portion in the groove portion 4 by grinding by the fly-cut method, a part of the insulating layer 3 may be removed. A part of the insulating layer 3 is the upper surface of the insulating layer 3 and a region near the upper surface. The thickness of the region near the upper surface of the insulating layer 3 is set, for example, within 10% of the total thickness of the insulating layer 3. By removing a part of the insulating layer 3 in this way, contamination can be reduced by copper, so the reliability is improved. Note that at the same time as a part of the insulating layer 3 is removed, a part of the second copper wiring 5 in the groove portion 4 is also removed.

[0051] In the wiring layer 30 ground by the fly cut method, the surface roughness (arithmetic mean roughness (Ra) defined in JIS B 0601 2001) of the insulating layer 3 and the second copper wiring 5 that constitute the surface on the side opposite to the substrate 1 is, for example, 0.03 μm or more and 0.1 μm or less respectively. In order to make these surface roughnesses 0.03 μm or more and 0.1 μm or less, it is preferable to physically grind the second copper wiring 5, the insulating layer 3, and the copper layer 5a on the insulating layer 3 using a surface planer. As the surface planer, for example, an automatic surface planer (manufactured by DISCO Corporation, trade name "DAS8930") is used. For example, grinding by the fly cut method is performed under the conditions of a feed rate of 1 mm / s and a spindle rotation speed of 2000 rpm. The surface roughness of the insulating layer 3 and the second copper wiring 5 after grinding is measured, for example, by scanning a 100 μm × 100 μm range including the insulating layer 3 and the second copper wiring 5 using a laser microscope ("LEXT OLS3000" manufactured by Olympus Corporation). Incidentally, for example, when the upper copper layer 5a is removed by CMP to expose the insulating layer 3 and the second copper wiring 5, the surface roughness of each of the insulating layer 3 and the second copper wiring 5 becomes 20 nm or less (0.02 μm or less).

[0052] Next, as shown in FIG. 5, by repeating the above copper wiring forming step, the above insulating layer forming step, the above groove forming step, the above copper layer forming step, and the above removing step, a high-density wiring layer (wiring body) 100 in which a plurality of wiring layers 30 are laminated on the substrate 1 is formed. The surfaces of the plurality of wiring layers 30 on the side opposite to the substrate 1 are each ground by the fly cut method. For this reason, the surface roughness of the surfaces of the plurality of wiring layers 30 on the side opposite to the substrate 1 is 0.03 μm or more and 0.1 μm or less.

[0053] Specifically, as shown in FIG. 5, after forming the second copper wiring 5, another first copper wiring 2 is formed on the insulating layer 3 and the second copper wiring 5. Here, another first copper wiring 2 is formed so as to be electrically connected to the second copper wiring 5. Next, another insulating layer 3 having another groove portion 4 is formed so as to cover another first copper wiring 2. The another groove portion 4 may be provided so as to overlap the groove portion 4, or may be provided so as not to overlap the groove portion 4. Next, in the same manner as the above copper layer forming step and the above removing step, another second copper wiring 5 is formed. The another second copper wiring 5 is provided so as to be electrically connected to the first copper wiring 2 via another first copper wiring 2 and the second copper wiring 5.

[0054] Next, as shown in FIG. 6, a semiconductor element 7 is mounted on the obtained high-density wiring layer 100 using an underfill material 10 to form a semiconductor package 101.

[0055] In mounting the semiconductor element 7 on the high-density wiring layer 100, before mounting the semiconductor element 7 on the high-density wiring layer 100, first, an electrode 9 is formed on the high-density wiring layer 100. The electrode 9 of the high-density wiring layer 100 is formed, for example, by using the same method as the above-described copper wiring forming step.

[0056] The electrode 9 is provided so as to be electrically connected to another second copper wiring 5 exposed in the high-density wiring layer 100. Further, when the electrode 9 is formed by using the same method as the above copper wiring forming step, the electrode 9 is composed of copper.

[0057] Next, the electrode 8 of the semiconductor element 7 and the electrode 9 of the high-density wiring layer 100 are metallically connected. As a method of metallically connecting the electrode 8 and the electrode 9, for example, solder 8a is formed between the electrode 8 and the electrode 9, and the electrode 8 and the electrode 9 are metallically connected to each other by joining the solder 8a. At this time, the electrode 8 and the electrode 9 may be metallically connected using the solder 8a by thermocompression bonding. The solder 8a has, for example, a ball shape. The solder 8a may be formed, for example, by plating or printing method.

[0058] As the underfill material 10 for fixing the semiconductor element 7 on the high-density wiring layer 100, for example, capillary underfill (CUF), mold underfill (MUF), paste underfill (NCP), film underfill (NCF), or photosensitive underfill can be used.

[0059] The semiconductor element 7 is not particularly limited. For example, a graphic processing unit (GPU), a volatile memory such as DRAM or SRAM, a non-volatile memory such as a flash memory, an RF chip, a silicon photonics chip, MEMS, a sensor chip, etc. can be used. In addition, a semiconductor element having TSV can be used.

[0060] As the semiconductor element 7, a stacked semiconductor element can also be used. For example, a semiconductor element stacked using TSV can be used. The thickness of the semiconductor element 7 is, for example, 200 μm or less. From the viewpoint of thinning the semiconductor package 101, the thickness of the semiconductor element 7 is preferably 100 μm or less. Also, from the viewpoint of the handleability of the semiconductor package 101, for example, the thickness of the semiconductor element 7 may be 30 μm or more.

[0061] Hereinafter, with reference to FIGS. 7 to 16, a method for manufacturing the semiconductor package 103 will be described.

[0062] As shown in FIG. 7, first, a temporary fixing layer 11 is formed on a carrier 14 which is a temporary substrate (temporary fixing layer forming step).

[0063] The method for forming the temporary fixing layer 11 is not particularly limited, and examples include spin coating, spray coating, or lamination. The temporary fixing layer 11 contains, for example, a resin containing a non-polar component such as polyimide, polybenzoxazole, silicon, or fluorine, a resin containing a component that expands in volume or foams by heating or UV irradiation (ultraviolet irradiation), a resin containing a component in which a crosslinking reaction proceeds by heating or UV irradiation, or a resin that generates heat by light irradiation.

[0064] From the perspective of highly achieving both handleability and ease of peeling from the carrier 14, the temporary fixing layer 11 preferably has a property of being easily peeled by applying an external stimulus such as light or heat. From the perspective of easily peeling the temporary fixing layer 11 without leaving it on the semiconductor device described later, the temporary fixing layer 11 more preferably contains particles that expand in volume by heat treatment. When a material containing a component (foaming agent) that expands in volume or foams by heating is used for the temporary fixing layer 11, from the perspective of the curing temperature and sintering temperature of the insulating material 12 described later, it is preferable that the foaming agent rapidly foams or expands in volume at 200°C or higher.

[0065] Next, as shown in FIG. 8, the first copper wiring 2 is formed on the temporary fixing layer 11 (copper wiring forming step).

[0066] The first copper wiring 2 may also be used as a connection electrode portion that is later connected to an electrode provided on another substrate.

[0067] Next, as shown in FIG. 9, an insulating layer 3 covering the first copper wiring 2 is formed on the temporary fixing layer 11 (insulating layer forming step).

[0068] Then, a groove portion 4 is formed in the insulating layer 3 (groove portion forming step).

[0069] Next, as shown in FIG. 10, copper paste is applied to the groove portion 4. Specifically, the copper paste is applied onto the insulating layer 3 so as to fill the groove portion 4 by applying the copper paste onto the upper surface of the insulating layer 3 (applying step). Then, the applied copper paste is sintered to obtain a sintered copper layer 5a (sintering step). Here, a laminate 50 is obtained, which includes the insulating layer 3 having the groove portion 4 and the copper layer 5a, which is a sintered body of the copper paste, formed in the groove portion 4, and has the temporary fixing layer 11 as the lower layer of the insulating layer 3.

[0070] Next, as shown in FIG. 11, the copper layer 5a on the upper portion of the insulating layer 3 is removed (removing step).

[0071] In the removal step, for example, using the fly cutting method, the copper layer portion in the groove 4 is left, and the copper layer 5a on the insulating layer 3 is removed.

[0072] Next, as shown in FIG. 12, by repeating the above copper wiring formation step, the above insulating layer formation step, the above groove formation step, the above coating step, the above sintering step, and the above removal step, a high-density wiring layer 100 is formed on the temporary fixing layer 11.

[0073] In FIG. 12, similar to FIG. 5, another first copper wiring 2, another insulating layer 3, and another second copper wiring 5 are sequentially formed on the insulating layer 3 and the second copper wiring 5, thereby forming a high-density wiring layer 100 on the temporary fixing layer 11.

[0074] Next, as shown in FIG. 13, the semiconductor element 7 is mounted on the obtained high-density wiring layer 100 using the underfill material 10.

[0075] Note that the above-described electrode 9 is provided on the high-density wiring layer 100, and the electrode 9 is electrically connected to the electrode 8 of the semiconductor element 7 via the solder 8a.

[0076] Next, as shown in FIG. 14, the semiconductor element 7 is sealed with the insulating material 12 (sealing step). As the insulating material 12, a liquid, solid, or sheet-like material can be used. The insulating material 12 can also be used in common with the underfill material 10.

[0077] Next, as shown in FIG. 15, the carrier 14 and the temporary fixing layer 11 are peeled off to obtain a semiconductor element 102 with a wiring layer. By going through the steps described above, a high-density semiconductor device excellent in chip-to-chip transmission can be manufactured with a better yield, more easily obtaining economic benefits.

[0078] Examples of the method for peeling the carrier 14 from the high-density wiring layer 100 include peel peeling, slide peeling, or heat peeling. Further, after peeling the carrier 14 from the high-density wiring layer 100, the high-density wiring layer 100 may be cleaned with a solvent or plasma, etc., and the remaining temporary fixing layer 11 may be removed.

[0079] Before peeling off the carrier 14, as a process for enhancing the peelability of the temporary fixing layer 11, heat treatment, light irradiation, or the like may be performed.

[0080] As long as it does not inhibit the functions of the semiconductor device, the temporary fixing layer 11 may remain on the high-density wiring layer 100. Note that the peeled carrier 14 may be recycled.

[0081] In the semiconductor element 102 with a wiring layer from which the carrier 14 and the temporary fixing layer 11 have been peeled, a connection electrode portion such as solder or a copper pad may be newly formed on the surface where the first copper wiring 2 is exposed. From the viewpoint of improving the transmission density, there may be a plurality of wiring layers (the first and second copper wirings). Also, from the viewpoint of easily obtaining economic benefits, a plurality of semiconductor elements 7 may be included.

[0082] The method for forming the new connection electrode portion is not particularly limited. For example, the method of applying the aforementioned copper paste and performing sintering treatment can be used. In addition, a new connection electrode portion may be formed using a method using molten solder or a method of forming a resist and performing electroplating or electroless plating. The new connection electrode portion may be composed of a single metal or a plurality of metals.

[0083] The new connection electrode portion contains, for example, at least any one of gold, silver, copper, nickel, indium, palladium, tin, or bismuth.

[0084] Next, as shown in FIG. 16, the semiconductor element 102 with a wiring layer sealed with the insulating material 12 is cut. As a result, a plurality of semiconductor elements 102 with a wiring layer sealed with the insulating material 12 can be obtained by singulating them, so that economic benefits can be obtained more easily. Then, the sealed semiconductor elements 102 with a wiring layer are respectively mounted on the substrate 13 to fabricate the semiconductor package 103.

[0085] The substrate 13 has, for example, a substrate core material 21 provided with wiring 24, an insulating layer 22 formed on the substrate core material 21, and a substrate connection material 23 that is exposed from a part of the insulating layer 22 and is connected to the wiring 24. Further, an underfill material 25 is formed on the substrate 13 so that the substrate connection material 23 is exposed. The underfill material 25 is provided between the substrate 13 and the semiconductor element 102 with a wiring layer, and has a function of relaxing the stress between the substrate 13 and the semiconductor element 102 with a wiring layer.

[0086] The insulating layer 3 of the semiconductor element 102 with a wiring layer and the insulating layer 22 of the substrate 13 may be made of the same material as each other, or may be made of different materials from each other. Similarly, the underfill material 10 and the underfill material 25 may be made of the same material as each other, or may be made of different materials from each other. From the viewpoint of suppressing the warpage of the semiconductor package 103, the linear expansion coefficient of the substrate 13 may be, for example, 30 ppm / °C or less. From the viewpoint of suppressing peeling or cracking in the reflow process and the temperature cycle test, the thermal expansion coefficient is preferably 20 ppm / °C or less.

[0087] In the process of manufacturing a conventional semiconductor device, when a copper paste is used as the material for the copper wiring, the adhesion between the organic material (for example, the organic material forming the insulating layer 3) and the copper paste may be insufficient, and the strength of the copper wiring, which is a sintered body of the copper paste, may be insufficient. However, by using the method for manufacturing a semiconductor device according to the above-described embodiment, the reflow resistance, temperature cycle resistance, flexibility, etc. of the copper wiring can be sufficiently exhibited, and a copper wiring having high reliability can be formed.

[0088] As described above, the method for manufacturing a semiconductor device according to an embodiment of the present disclosure has been described. However, the present disclosure is not limited to the above-described embodiment, and appropriate modifications may be made without departing from the spirit thereof.

[0089] In the above embodiment, the copper layer 15 is formed using a copper paste, but it is not limited thereto. For example, the copper layer 15 may be formed using at least any one of sputtering, electroplating, and electroless plating. Alternatively, the copper layer 15 may be formed by combining at least any one of sputtering, electroplating, and electroless plating with the coating step and the sintering step of the copper paste. It should be noted that the copper layer obtained using the copper paste and the copper layer obtained by conventional sputtering or plating, etc. are considered to have different copper densities, etc. from each other. Therefore, for example, it is possible to determine whether it is a copper layer obtained using a copper paste by observing a cross-sectional view.

[0090] Also, in the above embodiment, the groove portion 4 is formed by directly performing exposure and development on the insulating layer 3, but it is not limited thereto. For example, photolithography of the insulating layer 3 may be performed using a resist mask.

Explanation of Reference Numerals

[0091] 1, 13... substrate, 2... first copper wiring, 3, 22... insulating layer, 4... groove portion, 5... second copper wiring, 7... semiconductor element, 8, 9... electrode, 10, 25... underfill material, 11... temporary fixing layer, 12... insulating material, 14... carrier, 21... substrate core material, 23... substrate connection material, 24... wiring, 30... wiring layer, 100... high-density wiring layer (wiring body), 101... semiconductor package (semiconductor device), 102... semiconductor element with wiring layer, 103... semiconductor package (semiconductor device).

Claims

1. an insulating layer forming step of forming an insulating layer having a groove on a substrate; a copper layer forming step of forming a copper layer on the insulating layer so as to fill the groove; and removing the copper layer on the insulating layer by a flycut method while leaving a copper layer portion in the groove.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in said removing step, the insulating layer is also partially removed by the flycut method.

3. The insulating layer is formed using a photosensitive resin material, 3 . The method for manufacturing a semiconductor device according to claim 1 , further comprising, before said copper layer forming step, a groove forming step of forming said groove in said insulating layer by exposing and developing said insulating layer.

4. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the groove has a line width of 0.5 to 5 μm.

5. 5. The method for manufacturing a semiconductor device according to claim 1, wherein in the copper layer forming step, a copper paste is applied to at least the groove portion of the insulating layer, and the copper paste is sintered to form the copper layer.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the volume resistivity of the copper layer after the sintering treatment is 3 to 40 μΩ·cm.

7. 7. The method for manufacturing a semiconductor device according to claim 5, wherein in the sintering treatment, the copper paste is heated at 80 to 200.degree. C. in the presence of an acid.

8. A temporary fixing layer forming step of forming a temporary fixing layer on the substrate is further provided, 8. The method for manufacturing a semiconductor device according to claim 1, wherein in the insulating layer forming step, the insulating layer is formed on the temporary fixing layer.

9. The method for manufacturing a semiconductor device according to claim 8 , wherein in the temporary fixing layer forming step, the temporary fixing layer contains particles that expand in volume at 200° C. or higher.

10. A semiconductor device having a semiconductor element mounted on a wiring body provided on a substrate, The wiring body has a plurality of wiring layers stacked on top of each other, Each of the plurality of wiring layers includes an insulating layer having a groove on one surface side of the wiring layer, and a copper wiring formed to fill the groove, The surface roughness of the insulating layer and the copper wiring on the one surface side is 0.03 μm or more and 0.1 μm or less. Semiconductor device.

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