Semiconductor device and method for manufacturing semiconductor device

Abstract

To suppress an electrode detachment from an insulating film in a semiconductor device where an electrode formed on the insulating film may detach from the insulating film.SOLUTION: A semiconductor device 1 has a semiconductor substrate 2, an insulating film 3, and an electrode 4. The insulating film 3 is formed on the semiconductor substrate 2. The electrode 4 is formed on the insulating film 3. The semiconductor device 1 further has an anchor member 5. The anchor member 5 contacts the insulating film 3 and electrode 4 at the periphery of electrode 4.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] For example, as a technology related to a semiconductor device constituting a MOSFET (metal-oxide-semiconductor field-effect transistor), Patent Document 1 is known. Patent Document 1 describes In a semiconductor device constituting a trench gate type MOSFET, a source electrode is formed on an insulating film on a semiconductor substrate, and a source contact for connecting a source region in the semiconductor substrate and the source electrode through the insulating film is formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in related technologies such as Patent Document 1, there is a problem that an electrode formed on an insulating film may peel off from the insulating film.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, a semiconductor device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, and an electrode formed on the insulating film. Further, the semiconductor device includes an anchor member that contacts the insulating film and the electrode at an outer peripheral portion of the electrode in a plan view.

Effects of the Invention

[0007] According to the above-described embodiment, peeling of the electrode can be suppressed.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26A

Figure 26B

Figure 27A

Figure 27B

Figure 28A

Figure 28B

Figure 29A

Figure 29B

Figure 30A

Figure 30B

Figure 31A

Figure 31B

Figure 32A

Figure 32B

Figure 33A

Figure 33B

Figure 34A

Figure 34B

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Figure 46

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. For clarity of explanation, the following description and drawings are appropriately omitted and simplified. Also, in each drawing, the same elements are denoted by the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] In each drawing, an XYZ three-dimensional orthogonal coordinate system is shown, and the XY plane is a plane parallel to the surface (front or back surface) of the semiconductor substrate. The Z direction orthogonal to the XY plane is the up-down direction, height direction, or thickness direction in the semiconductor substrate. Plan view means looking at the XY plane from the Z direction.

[0011] (Overview of the Embodiment) First, an overview of the embodiment will be described. FIG. 1 is a plan view showing a schematic configuration of a semiconductor device 1 according to the embodiment. FIG. 1 shows a state in which an insulating film and electrodes on a semiconductor substrate are seen through. FIG. 2 is a cross-sectional view taken along line A-A' of the semiconductor device 1 in FIG. 1. The semiconductor device 1 constitutes, for example, a power MOSFET. The semiconductor device 1 may also be other semiconductor devices having the configurations shown in FIGS. 1 and 2. For example, the semiconductor device 1 may constitute a transistor such as an IGBT (Insulated Gate Bipolar Transistor) or other semiconductor elements.

[0012] As shown in FIGS. 1 and 2, the semiconductor device 1 includes a semiconductor substrate 2, an insulating film 3, an electrode 4, and an anchor member 5. The semiconductor substrate 2 is a silicon-based substrate that serves as the base of the semiconductor device 1. For example, a trench gate, a source region, a body region, etc. for constituting a power MOSFET may be formed in the semiconductor substrate 2, but are not limited thereto.

[0013] The insulating film 3 is formed on the semiconductor substrate 2. For example, the insulating film 3 is also called an interlayer insulating film. The electrode 4 is formed on the insulating film 3. The electrode 4 is a wiring electrically connected to a semiconductor region in the semiconductor substrate 2. For example, the electrode 4 may be a source wiring in a power MOSFET, but is not limited thereto.

[0014] The anchor member 5 is in contact with the insulating film 3 and the electrode 4 at the outer peripheral portion of the electrode 4 in a plan view. The anchor member 5 is a member that produces an anchor effect, and the material and structure are not limited. The anchor member 5 improves the bonding property between the insulating film 3 and the electrode 4 by the anchor effect.

[0015] For example, the anchor member 5 may be a contact that electrically connects the semiconductor substrate 2 and the electrode 4. As an example of the contact, it may be a source contact that electrically connects the source electrode and the source region. The anchor member 5 may be a member separate from the contact, that is, a member that does not electrically connect the semiconductor substrate 2 and the electrode 4. As shown in FIG. 2, the anchor member 5 may be formed to penetrate the insulating film 3 from the side of the electrode 4 to the side of the semiconductor substrate 2, or may be formed from the side of the electrode 4 to the inside of the insulating film 3 without penetrating the insulating film 3.

[0016] The outer peripheral portion of the electrode 4 may include the outer peripheral end portion or the vicinity of the outer peripheral end portion of the electrode 4 in plan view. The anchor member 5 overlaps the outer peripheral portion of the electrode 4 in plan view. As shown in FIG. 1, the anchor member 5 may extend from the inside to the outside of the electrode 4 in plan view. As shown in FIG. 1, the outer end portion of the anchor member 5 may extend to a region outside the outer peripheral portion of the electrode 4, or may overlap the outer peripheral portion of the electrode 4 in plan view. The extending direction, number, shape, etc. of the anchor member 5 are not limited. The anchor member 5 may extend in the outer peripheral direction of the electrode 4 in plan view. The anchor member 5 may include a plurality of spaced-apart anchor member portions.

[0017] In the embodiment, as described above, an anchor member that contacts the insulating film and the electrode is provided at the outer peripheral portion of the electrode. Due to the anchor effect of the anchor member, the bonding property between the insulating film and the electrode is improved, so that peeling of the electrode from the insulating film can be suppressed at the outer peripheral portion of the electrode.

[0018] (Embodiment 1) Next, Embodiment 1 will be described. In this embodiment, a source contact is used to suppress peeling of the source wiring.

[0019] FIG. 3 is a plan view of a semiconductor chip that is the semiconductor device 100 according to the present embodiment. For example, the semiconductor device 100 constitutes a trench gate type N-channel power MOSFET in which a field plate is connected to a gate electrode. The semiconductor device 100 is not limited to an N-channel MOSFET, and may constitute a P-channel MOSFET. The semiconductor device 100 may constitute a trench gate type power MOSFET that does not include a field plate. The semiconductor device 100 is not limited to a trench gate type MOSFET, and may constitute transistors having other structures.

[0020] As shown in FIG. 3, the semiconductor device 100 includes a semiconductor substrate SUB that serves as a base of the semiconductor device 100. A gate wiring GW and a source wiring SW are formed on the semiconductor substrate SUB. The gate wiring GW is a ring-shaped wiring that circulates around an end portion on the semiconductor substrate SUB. The gate wiring GW is a wiring (electrode) for leading out a gate electrode in the semiconductor substrate SUB to the outside.

[0021] The source wiring SW is formed entirely inside the gate wiring GW on the semiconductor substrate SUB. The source wiring SW is a wiring (electrode) for leading out a source region and a body region in the semiconductor substrate SUB to the outside.

[0022] For example, the surfaces of the gate wiring GW and the source wiring SW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the gate wiring GW and the source wiring SW exposed at the opening become a gate pad GD and a source pad SD that are external terminals.

[0023] For example, a region overlapping the source wiring SW becomes a cell region 10. In this example, an outer peripheral end portion of the cell region 10 is inside an outer peripheral end portion of the source wiring SW. The cell region 10 is an active region in which main elements such as power MOSFETs are operably formed.

[0024] Here, the comparative examples studied by the inventor will be described. FIG. 4 is an enlarged plan view of the end portion of the cell region in the semiconductor device 9 of the comparative example. FIG. 4 is an enlarged view of the end portion 10a of the cell region in FIG. 3. FIG. 4 shows a state in which the source wiring and the interlayer insulating film are seen through. The same applies to the enlarged views of the end portions of the cell region hereinafter.

[0025] As shown in FIG. 4, in the semiconductor device 9 of the comparative example, trenches (gate trenches) TR including gate electrodes GE and source regions SA extend alternately in a line. For example, the Y direction (the first direction) in FIG. 4 is referred to as the vertical direction, and the trenches TR and the source regions SA extend in the vertical direction. The vertical direction is also a direction orthogonal to the outer peripheral end portion 11b of the source wiring SW. A source contact SC is disposed on the source region SA. The source contact SC is a contact that electrically connects the source region SA (and the body region) of the semiconductor substrate SUB and the source wiring SW. The source contact SC overlaps the source region SA and extends linearly in the vertical direction. It can also be said that the source contact SC extends from the inside to the outside of the source wiring SW in plan view. When simply referring to the inside and outside of the source wiring SW (semiconductor substrate SUB) in plan view, they may be simply referred to as the inside and the outside. For example, the direction from the inside to the outside is the direction from the inside of the semiconductor device 100 to the end portion 10a or the end portion 10b of the cell region in the plan view of the semiconductor device 100 in FIG. 3, which is the positive or negative direction of the Y axis.

[0026] In the comparative example, the outer end portion 11a of the source contact SC is inside the outer peripheral end portion 11b of the source wiring SW. That is, a margin is provided between the outer end portion 11a of the source contact SC and the outer peripheral end portion 11b of the source wiring SW. For example, when the source contact SC is formed by a photolithography method, the margin is set so that even if a deviation occurs at the outer end portion 11a of the source contact SC, the source wiring SW can completely cover the source contact SC. The source wiring SW includes a barrier metal layer BM such as TiW (titanium tungsten) and an aluminum layer AL.

[0027] When a reliability test at high temperature was performed on the semiconductor device 9 of the comparative example having the configuration as shown in FIG. 4, a defect occurred. Specifically, the threshold value Vth varied with time and saturation was lost. As a cause thereof, peeling of the source wiring SW was confirmed at the outer peripheral portion of the cell.

[0028] FIG. 5 shows the analysis result of the outer peripheral portion of the cell during the high-temperature reliability test in the semiconductor device 9 of the comparative example. FIG. 5 is a perspective view of the cross section of the region 12 of the outer peripheral portion of the cell in FIG. 4 as viewed from the inside. FIG. 5 shows a state in which the uppermost aluminum layer AL included in the source wiring SW is removed. As shown in FIG. 5, as a result of the high-temperature reliability test, the barrier metal layer BM is peeled off from the semiconductor substrate SUB (interlayer insulating film) at the end of the source wiring SW and is floating. The barrier metal layer BM is peeled off from the end of the source wiring SW to the end of the source contact SC, and the barrier metal layer BM is cracked at the end of the source contact SC.

[0029] As described above, in the comparative example, there is a problem that the barrier metal layer BM (source wiring SW) peels off from the semiconductor substrate SUB (interlayer insulating film) at high temperature. This is considered to be due to stress generated from the difference in the thermal expansion and thermal contraction characteristics of the barrier metal layer BM (source wiring SW) and the semiconductor substrate SUB (interlayer insulating film) at high temperature.

[0030] Therefore, the inventor studied a method for reinforcing the bonding property between the barrier metal layer BM (source wiring SW) and the semiconductor substrate SUB (interlayer insulating film). From the analysis result of FIG. 5, it was found that the barrier metal layer BM peels off in the region where the source contact SC is not formed, and the barrier metal layer BM does not peel off in the region where the source contact SC is formed. From this, the inventor found that the source contact SC has an anchor effect for suppressing peeling. Therefore, in the present embodiment, by utilizing the anchor effect of the source contact SC, it is possible to suppress the peeling of the barrier metal layer BM (source wiring SW).

[0031] FIG. 6 is an enlarged plan view of an end portion of the cell region of the semiconductor device 100 according to the present embodiment. FIG. 6 is an enlarged view of the end portion 10a of the cell region in FIG. 3. Although the description is omitted, the end portion 10b of the cell region facing the end portion 10a in FIG. 3 has the same configuration as FIG. 6. The same applies to the enlarged views of the end portions of the cell region hereinafter.

[0032] In the present embodiment, the source contact SC having the anchor effect is arranged at the same or outside the end portion of the source wiring SW. That is, the source contact SC is extended to the region including the end portion of the source wiring SW. As shown in FIG. 6, similar to FIG. 4, in the semiconductor device 100, the trenches TR including the gate electrodes GE and the source regions SA are alternately arranged side by side in a line in the vertical direction and extend. Further, the source contact SC is arranged on the source region SA. The source contact SC overlaps the source region SA and extends in a line in the vertical direction.

[0033] As shown in FIG. 6, in the present embodiment, the source contact SC is extended and arranged as compared with the comparative example in FIG. 4. That is, the source contact SC is extended from the outer end portion 11a of the comparative example to the outer end portion 11c. The portion from the outer end portion 11a to the outer end portion 11c of the source contact SC in the comparative example is also referred to as an extension portion SCa. In the example of FIG. 6, the outer end portion 11c of the source contact SC is included in a region outside the outer peripheral end portion 11b of the source wiring SW. The source contact SC extends from the inside to the outside of the source wiring SW in a plan view. At least a part of the source contact SC overlaps the outer peripheral end portion 11b of the source wiring SW in a plan view. In the example of FIG. 6, due to the anchor effect of the source contact SC extending from the inside to the outside of the source wiring SW, peeling of the outer peripheral portion (region including the outer peripheral end portion) of the source wiring SW can be reliably suppressed.

[0034] The outer end portion 11c of the source contact SC is set within a range necessary to suppress the peeling of the source wiring SW (for example, the peeling in the region 12 of FIG. 4). For example, the outer end portion 11c of the source contact SC is set within the outer end portion range 13a. The outer end portion range 13a is a predetermined range extending outward from the outer peripheral end portion 11b of the source wiring SW. Since the stress due to thermal expansion varies depending on the size and material of the source wiring SW, the material of the source contact SC, etc., the outer end portion range 13a may be set according to the size and material of the source wiring SW, the material of the source contact SC, etc.

[0035] In addition, in the present embodiment, compared with the comparative example of FIG. 4, no margin is set between the outer end portion 11a of the comparative example of the source contact SC and the outer peripheral end portion 11b of the source wiring SW. Even without setting a margin as in the comparative example, for example, by forming the source contact SC with a metal plug, the influence on the source contact SC from etching or the like on the source wiring SW can be suppressed.

[0036] FIG. 7 is an arrangement example when the position of the outer end portion 11c of the source contact SC is changed. In the example of FIG. 7, the outer end portion 11c of the source contact SC is in the same position as the outer peripheral end portion 11b of the source wiring SW in plan view. It is not limited to the case where the position of the outer end portion 11c of the source contact SC is the same as the position of the outer peripheral end portion 11b of the source wiring SW. The outer end portion 11c of the source contact SC may be in the vicinity of the outer peripheral end portion 11b of the source wiring SW, or may overlap in plan view with the region (outer peripheral portion) including the outer peripheral end portion 11b of the source wiring SW. Even in the case of FIG. 7, the peeling of the outer peripheral portion of the source wiring SW can be suppressed by the anchor effect of the source contact SC extending from the inside to the outer peripheral end portion 11b of the source wiring SW. Note that if it is possible to suppress the peeling of the source wiring SW, the outer end portion 11c of the source contact SC may be inside the outer peripheral end portion 11b of the source wiring SW.

[0037] The extension SCa of the source contact SC may be integral with the source contact SC up to the outer end 11a of the comparative example, or may be separated (spaced apart). In other words, the source contact SC may include a first source contact portion (first anchor member portion) and a second source contact portion (second anchor member portion) that are spaced apart. Either the first source contact portion or the second source contact portion may be the extension SCa. For example, when the extension SCa is separated, the inner end 11d of the extension SCa of the source contact SC is set within the inner end range 13b. The inner end range 13b is a predetermined range from the outer end 11a of the same source contact SC as in the comparative example to before the outer peripheral end 11b of the source wiring SW (to the extent that they do not overlap). The outer end 11a of the source contact SC is also the end of the region where the source contact SC is formed. Similar to the outer end range 13a, the inner end range 13b may be set according to the size and material of the source wiring SW, the material of the source contact SC, etc.

[0038] Figures 8 and 9 are arrangement examples when the extension SCa of the source contact SC is separated. In the example of Figure 8, the outer end 11c of the extension SCa of the source contact SC is outside the outer peripheral end 11b of the source wiring SW, similar to Figure 6. The inner end 11d of the extension SCa of the source contact SC is in the middle between the outer peripheral end 11b of the source wiring SW and the outer end 11a of the source contact SC. Even in the case of Figure 8, the peeling of the outer peripheral portion of the source wiring SW can be suppressed by the anchor effect of the extension SCa of the source contact SC extending from the inner side to the outer side in the vicinity of the outer peripheral end 11b of the source wiring SW.

[0039] In the example of FIG. 9, the outer end portion 11c of the extension SCa of the source contact SC is in the same position in plan view as the outer peripheral end portion 11b of the source wiring SW, similar to FIG. 7. The inner end portion 11d of the extension SCa of the source contact SC is intermediate between the outer peripheral end portion 11b of the source wiring SW and the outer end portion 11a of the source contact SC, similar to FIG. 8. Also in the case of FIG. 9, due to the anchor effect of the extension SCa of the source contact SC extending from the inner side to the outer peripheral end portion 11b in the vicinity of the outer peripheral end portion 11b of the source wiring SW, peeling of the outer peripheral portion of the source wiring SW can be suppressed.

[0040] Note that in FIGS. 6 to 9, the patterns of the plurality of source contacts SC are the same pattern, but they may also be different patterns. The patterns of FIGS. 6 to 9 may be combined. For example, the source contacts SC of one pattern among FIGS. 6 to 9 and the source contacts SC of another pattern among FIGS. 6 to 9 may be arranged alternately. Further, any pattern among FIGS. 6 to 9 may be combined with the pattern of the comparative example in FIG. 4.

[0041] Next, the cross-sectional configuration of the semiconductor device 100 according to the present embodiment will be described. FIG. 10 is a cross-sectional view taken along line A1 - A1' at the cell region end 10a of the semiconductor device 100 in FIG. 6.

[0042] For example, the semiconductor substrate SUB is an N+-type silicon substrate. A drain region ND, which is an N+-type semiconductor region, is formed on the back surface (lower surface) 100b side of the semiconductor substrate SUB. A drain electrode DE is formed under the N+ drain region ND of the semiconductor substrate SUB. The drain electrode DE is a metal electrode and is formed of, for example, Ti (titanium) / Ni (nickel) / Ag (silver) or the like from the side closer to the semiconductor substrate SUB.

[0043] On the substrate surface (upper surface) 100a side of the N+ drain region ND, a drift region NV which is an N-type semiconductor region is formed. The N- drift region NV is a silicon epitaxial region. On the N- drift region NV, a body region PB which is a P-type semiconductor region is formed. The P-body region PB is a channel region (implantation layer). On the substrate surface (upper surface) 100a side of the P-body region PB, a source region SA which is an N+ type semiconductor region is formed.

[0044] A trench TR is formed on the substrate surface 100a side of the semiconductor substrate SUB. The trench TR is a gate trench for a gate electrode. The trench TR is formed so as to penetrate the N+ source region SA and the P-body region PB from the substrate surface 100a side and reach inside the N- drift region NV. A field plate electrode FE is formed on the lower side (bottom side) in the trench TR. The field plate electrode FE is an electrode connected to the gate. For example, the field plate electrode FE is an N+ polysilicon field plate electrode. The lower part and the lateral periphery of the field plate electrode FE are surrounded by a field plate peripheral insulating film FF. For example, the field plate peripheral insulating film FF is a silicon oxide film.

[0045] Above the field plate electrode FE in the trench TR, a gate electrode GE is formed via a field plate-gate insulating film FG. For example, the gate electrode GE is an N+ polysilicon trench gate electrode. The lateral periphery of the gate electrode GE is surrounded by a gate insulating film GF. For example, the field plate-gate insulating film FG and the gate insulating film GF are silicon oxide films. The field plate peripheral insulating film FF and the gate insulating film GF may be integrally formed.

[0046] On the surface 100a side of the semiconductor substrate SUB, an interlayer insulating film IL is formed so as to cover the gate electrode GE and the source region SA. A contact hole CH for the source contact SC is formed in the interlayer insulating film IL. The contact hole CH is formed so as to penetrate the interlayer insulating film IL and the N+ source region SA from the upper side (surface side) of the interlayer insulating film IL and reach the P+ body contact region PC inside the P- body region PB. The source contact SC is embedded in the inner surface of the contact hole CH. The source contact SC is a metal plug and is formed of, for example, Ti (titanium) / TiN (titanium nitride) / W (tungsten) or the like from the side closer to the semiconductor substrate SUB. The upper part of the source contact SC is in contact with the source wiring SW (barrier metal layer BM) and penetrates the interlayer insulating film IL to the semiconductor substrate SUB. An anchor structure for driving an anchor into the interlayer insulating film IL from the source wiring SW side causes an anchor effect to enhance the bonding property between the source wiring SW and the interlayer insulating film IL. The source contact SC is an anchor member having an anchor function and a contact function that cause the anchor effect.

[0047] The source wiring SW is formed on the upper surface of the interlayer insulating film IL. In this example, as the source wiring SW, a barrier metal layer and an aluminum layer AL are laminated. That is, the barrier metal layer BM is formed on the upper surface of the interlayer insulating film IL. The barrier metal layer BM is a metal film such as TiW, for example. Further, a relatively thick aluminum layer AL is formed on the upper surface of the barrier metal layer BM.

[0048] Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described. FIGS. 11 to 17 show the cross section taken along the line A1 - A1' in FIG. 6 as in FIG. 10.

[0049] As shown in FIG. 11, first, a semiconductor substrate SUB having an N-drift region NV which is an N-type semiconductor region is prepared, and a trench TR is formed in the N-drift region NV. For example, an N-drift region NV is formed by growing a silicon layer while introducing P (phosphorus) by an epitaxial growth method on an N+-type silicon substrate (N+ drain region ND). Next, for example, an insulating film made of a silicon oxide film is formed on the semiconductor substrate SUB by a CVD (Chemical Vapor Deposition) method, and a resist pattern having an opening is formed on the insulating film by a photolithography method. By performing a dry etching process on the insulating film and the N-drift region NV exposed from the opening using the resist pattern as a mask, a trench TR is formed in the N-drift region NV. Thereafter, the resist pattern is removed by an ashing process, and the insulating film is removed by a wet etching process.

[0050] Next, as shown in FIG. 12, a field plate electrode FE is formed in the trench TR via a field plate peripheral insulating film FF. First, for example, a field plate peripheral insulating film FF made of a silicon oxide film is formed on the semiconductor substrate SUB including the inside of the trench TR by a thermal oxidation method. Next, for example, a high-concentration phosphorus-doped polysilicon layer into which an N-type impurity is introduced is formed on the semiconductor substrate SUB by a CVD method so as to fill the inside of the trench TR via the field plate peripheral insulating film FF. Next, for example, by a CMP method or a dry etching process, the high-concentration phosphorus-doped polysilicon layer located outside the trench TR and the upper high-concentration phosphorus-doped polysilicon layer inside the trench TR are etched back to form the field plate electrode FE. Next, for example, by a wet etching process, the field plate peripheral insulating film FF is removed to such an extent that the upper end portion of the field plate electrode FE and the silicon side wall above the field plate electrode FE in the trench TR are exposed.

[0051] Next, as shown in FIG. 13, a gate electrode GE is formed above the field plate electrode FE in the trench TR. First, for example, a gate insulating film GF made of a silicon oxide film is formed by a thermal oxidation method on a semiconductor substrate SUB including the inside of the trench TR in which the field plate electrode FE is formed. At the same time as the gate insulating film GF, a field plate-gate insulating film FG is formed. Next, for example, a high-concentration phosphorus-doped polysilicon layer into which N-type impurities are introduced is formed on the semiconductor substrate SUB by a CVD method so as to fill the inside of the trench TR through the gate insulating film GF. Next, for example, the high-concentration phosphorus-doped polysilicon layer located outside the trench TR is etched back by a CMP method or a dry etching process to form the gate electrode GE.

[0052] Next, as shown in FIG. 14, a P-body region PB is formed on the surface of the N-drift region NV, and an N+ source region SA is formed on the surface of the body region PB. First, the P-body region PB is formed by introducing B (boron) or the like onto the surface of the N-drift region NV by a photolithography method and an ion implantation method. Next, the N+ source region SA is formed by introducing As (arsenic) or the like onto the surface of the P-body region PB by a photolithography method and an ion implantation method.

[0053] Next, as shown in FIG. 15, an interlayer insulating film IL is formed on the semiconductor substrate SUB, a contact hole CH is formed in the interlayer insulating film IL, and a P+ body contact region PC is formed in the P-body region PB. First, for example, an interlayer insulating film IL made of a silicon oxide film is formed on the semiconductor substrate SUB by CVD so as to cover the gate electrode GE and the source region SA. Next, by photolithography, a resist is patterned on the interlayer insulating film IL so as to form the pattern of the source contact SC. Further, by dry etching, a contact hole CH penetrating the interlayer insulating film IL and the N+ source region SA is formed from the opening of the resist pattern. The bottom of the contact hole CH is formed so as to be located within the P-body region PB. Further, the resist pattern is removed by ashing or wet etching. Next, at the bottom of the contact hole CH, by ion-implanting B (boron) or the like into the P-body region PB, a P+ body contact region PC having an impurity concentration higher than that of the P-body region PB is formed.

[0054] Next, as shown in FIG. 16, a source contact SC is formed in the contact hole CH. First, for example, a metal film such as Ti / TiN is formed on the entire inner surface of the contact hole CH reaching from the interlayer insulating film IL to the P+ body contact region PC by sputtering or CVD. Next, for example, a metal plug such as W is formed on the metal film such as Ti / TiN by sputtering or CVD so as to fill the contact hole CH, and the metal (Ti / TiN, W) on the surface layer of the interlayer insulating film IL is removed by dry etching to form the source contact SC.

[0055] Next, as shown in FIG. 17, a source wiring SW is formed on the source contact SC and the interlayer insulating film IL. First, for example, a barrier metal layer BM made of TiW is formed on the entire surface of the source contact SC and the interlayer insulating film IL by sputtering or CVD. Next, for example, an aluminum layer AL is formed on the entire surface of the barrier metal layer BM by sputtering or CVD. Further, the source wiring SW including the barrier metal layer BM and the aluminum layer AL is patterned by photolithography.

[0056] As described above, in this embodiment, the source contact is extended and arranged up to the region including the outer peripheral end of the source wiring. By the anchor effect of this source contact, peeling of the source wiring at the outer peripheral end of the source wiring can be suppressed. By using the source contact that electrically connects the source region and the source wiring, peeling of the source wiring can be efficiently suppressed.

[0057] (Embodiment 2) Next, Embodiment 2 will be described. In this embodiment, a shallow contact different from the source contact is used to suppress peeling of the source wiring.

[0058] FIG. 18 is an enlarged plan view of an end portion of a cell region of the semiconductor device 100 according to this embodiment. FIG. 18 is an enlarged view of the end portion 10a of the cell region in FIG. 3. FIG. 19 is a cross-sectional view taken along line A2 - A2' in FIG. 18. FIG. 20 is a cross-sectional view taken along line A3 - A3' in FIG. 18.

[0059] In this embodiment, a shallow contact NC, which is a member different from the source contact SC, is arranged at the same position as or outside the end of the source wiring SW. Note that the configuration other than the shallow contact NC is the same as that in Embodiment 1.

[0060] As shown in FIGS. 19 and 20, the shallow contact NC is shallower in depth than the source contact SC. The shallow contact NC does not penetrate the interlayer insulating film IL, and the bottom of the shallow contact NC is located inside the interlayer insulating film IL. If the shallow contact NC does not contact the gate electrode GE, the depth of the shallow contact NC is not limited. A contact hole CH2 for the shallow contact NC is formed in the interlayer insulating film IL. The contact hole CH2 is formed so as to reach from the upper side (surface side) of the interlayer insulating film IL to the inside of the interlayer insulating film IL. The shallow contact NC is embedded in the inner surface of the contact hole CH2. For example, the width (thickness) of the shallow contact NC is the same as that of the source contact SC, but may be any width different from that of the source contact SC.

[0061] The upper part of the shallow contact NC contacts the source wiring SW (barrier metal layer BM) and reaches inside the interlayer insulating film IL. Due to the anchor structure that drives an anchor into the interlayer insulating film IL from the side of the source wiring SW, an anchor effect similar to that of the source contact SC occurs to enhance the bonding property between the source wiring SW and the interlayer insulating film IL.

[0062] Since the bottom of the shallow contact NC is inside the interlayer insulating film IL, it does not electrically connect the source wiring SW and the gate electrode GE of the semiconductor substrate SUB, etc. Since the shallow contact NC does not affect the characteristics of the power MOSFET, it may be arranged at any position. The shallow contact NC is an anchor member that has an anchor function to produce an anchor effect and does not have a contact function. For example, the shallow contact NC may be a metal plug such as Ti / TiN / W, similar to the source contact SC. The shallow contact NC may also be a metal film such as TiW, similar to the barrier metal layer BM. The shallow contact NC may be formed of any other material as long as it can produce an anchor effect.

[0063] As shown in FIG. 18, for example, the shallow contact NC extends linearly in the vertical direction, similar to the source contact SC, and is arranged in parallel with the source contact SC. For example, the shallow contact NC is arranged to overlap the gate electrode GE between adjacent source contacts SC, that is, at the center of the trench TR. It can also be said that the shallow contact NC extends from the inside to the outside of the source wiring SW in a plan view, similar to the source contact SC.

[0064] In the example of FIG. 18, the outer end 11c of the shallow contact NC is included in a region outside the outer peripheral end 11b of the source wiring SW, similar to FIG. 6 of Embodiment 1. The inner end 11d of the shallow contact NC is included in a region inside the outer end 11a of the source contact SC (similar to the comparative example). That is, the region of the inner end 11d of the shallow contact NC overlaps the region of the outer end 11a of the source contact SC. At least a part of the shallow contact NC overlaps the outer peripheral end 11b of the source wiring SW in a plan view. In the example of FIG. 18, similar to Embodiment 1, due to the anchor effect of the shallow contact NC extending from the inside to the outside of the source wiring SW, peeling of the outer peripheral portion of the source wiring SW can be reliably suppressed.

[0065] The outer end 11c and the inner end 11d of the shallow contact NC are set within a range necessary to suppress peeling of the source wiring SW (for example, peeling in the region 12 of FIG. 4). For example, the outer end 11c of the shallow contact NC is set in the outer end range 13a. The outer end range 13a is a predetermined range extending outward from the outer peripheral end 11b of the source wiring SW. The inner end 11d of the shallow contact NC is set in the inner end range 13b. The inner end range 13b is a predetermined range from inside the outer end 11a of the source contact SC to before the outer peripheral end 11b of the source wiring SW (to the extent that they do not overlap). Similar to Embodiment 1, the outer end range 13a and the inner end range 13b may be set according to the size and material of the source wiring SW, the material of the shallow contact NC, etc.

[0066] FIG. 21 shows an arrangement example when the position of the outer end portion 11c of the shallow contact NC is changed. In the example of FIG. 21, similar to FIG. 7 of Embodiment 1, the outer end portion 11c of the shallow contact NC is in the same position as the outer peripheral end portion 11b of the source wiring SW in a plan view. That is, the outer end portion 11c of the shallow contact NC may be in the vicinity of the outer peripheral end portion 11b of the source wiring SW, or may overlap with the region (outer peripheral portion) including the outer peripheral end portion 11b of the source wiring SW in a plan view. The inner end portion 11d of the shallow contact NC is inside the outer end portion 11a of the source contact SC, similar to FIG. 18. Also in the case of FIG. 21, the peeling of the outer peripheral portion of the source wiring SW can be suppressed by the anchor effect of the shallow contact NC extending from the inside to the outer peripheral end portion 11b of the source wiring SW. Note that if it is possible to suppress the peeling of the source wiring SW, the outer end portion 11c of the shallow contact NC may be inside the outer peripheral end portion 11b of the source wiring SW.

[0067] FIGS. 22 and 23 show arrangement examples when the position of the inner end portion 11d of the shallow contact NC is changed. In the example of FIG. 22, the outer end portion 11c of the shallow contact NC is outside the outer peripheral end portion 11b of the source wiring SW, similar to FIG. 18. The inner end portion 11d of the shallow contact NC is in the middle between the outer peripheral end portion 11b of the source wiring SW and the outer end portion 11a of the source contact SC, similar to FIG. 8 of Embodiment 1. That is, the region of the inner end portion 11d of the shallow contact NC does not overlap with the region of the outer end portion 11a of the source contact SC. Also in the case of FIG. 22, the peeling of the outer peripheral portion of the source wiring SW can be suppressed by the anchor effect of the shallow contact NC extending from the inside to the outside in the vicinity of the outer peripheral end portion 11b of the source wiring SW.

[0068] In the example of FIG. 23, the outer end portion 11c of the shallow contact NC is in the same position in plan view as the outer peripheral end portion 11b of the source wiring SW, similar to FIG. 21. The inner end portion 11d of the shallow contact NC is in the middle between the outer peripheral end portion 11b of the source wiring SW and the outer end portion 11a of the source contact SC, similar to FIG. 22. Even in the case of FIG. 23, due to the anchor effect of the shallow contact NC extending from the inner side to the outer peripheral end portion 11b in the vicinity of the outer peripheral end portion 11b of the source wiring SW, peeling of the outer peripheral portion of the source wiring SW can be suppressed.

[0069] Note that the shallow contact NC may be separated as in FIGS. 8 and 9 of Embodiment 1. That is, the shallow contact NC may include a first shallow contact portion (first anchor member portion) and a second shallow contact portion (second anchor member portion) arranged apart from each other. Also, the pattern of the source contact SC of Embodiment 1 and the pattern of the shallow contact NC of the present embodiment may be combined. For example, in addition to the source contact SC having any pattern from FIGS. 6 to 9 of Embodiment 1, a shallow contact NC having any pattern from FIGS. 18, 21 to 23 may be further arranged. Thereby, peeling of the outer peripheral portion of the source wiring SW can be more reliably suppressed.

[0070] FIGS. 24 and 25 are arrangement examples when the position of the shallow contact NC in the X direction is changed. In the examples of FIGS. 24 and 25, the shallow contact NC is arranged on the source region SA, that is, on the extension line of the source contact SC. In the example of FIG. 24, the positions of the outer end portion 11c and the inner end portion 11d of the shallow contact NC are the same as those in FIG. 22. The position of the shallow contact NC in FIG. 24 is also the same as the extension portion SCa of FIG. 8 of Embodiment 1. In the example of FIG. 25, the positions of the outer end portion 11c and the inner end portion 11d of the shallow contact NC are the same as those in FIG. 23. The position of the shallow contact NC in FIG. 25 is also the same as the extension portion SCa of FIG. 9 of Embodiment 1. Even in these cases, similar to FIGS. 22 and 23, peeling of the outer peripheral portion of the source wiring SW can be suppressed.

[0071] In FIGS. 18 and 21 to 25, the patterns of the plurality of shallow contact NCs may be the same pattern, or may be different patterns. The patterns of FIGS. 18 and 21 to 25 may be combined. For example, shallow contact NCs of one pattern among FIGS. 18 and 21 to 23 and shallow contact NCs of another pattern among FIGS. 18 and 21 to 23 may be alternately arranged. For example, after arranging shallow contact NCs of any pattern among FIGS. 18 and 21 to 23, shallow contact NCs of any pattern of FIG. 24 or FIG. 25 may be further arranged.

[0072] Next, an example of a method for manufacturing the semiconductor device 100 according to the present embodiment will be described. This example is an example in which an NC contact hole for a shallow contact is formed before forming the source contact SC after the contact hole opening of the source contact SC, and the source contact SC and the shallow contact NC are formed simultaneously. FIGS. 26A to 30A are cross-sections taken along line A3 - A3' of FIG. 18, showing a cross-section of a region where the shallow contact NC is formed. FIGS. 26B to 30B are cross-sections taken along line A4 - A4' of FIG. 18, showing a cross-section of a region where the source contact SC is formed.

[0073] First, after performing the same steps as in FIGS. 11 to 14 of Embodiment 1, the process proceeds to the steps of FIGS. 26A and 26B. FIGS. 26A and 26B correspond to the step of FIG. 15 of Embodiment 1. That is, as shown in FIGS. 26A and 26B, similar to FIG. 15, an interlayer insulating film IL is formed on the semiconductor substrate SUB. Next, as shown in FIG. 26B, in the region where the source contact SC is formed, a contact hole CH for the source contact SC that penetrates the interlayer insulating film IL and the N+ source region SA and reaches into the P - body region PB is formed. Further, a P+ body contact region PC is formed in the P - body region PB through the contact hole CH. At this time, as shown in FIG. 26A, in the region where the shallow contact NC is formed, the interlayer insulating film IL is formed on the semiconductor substrate SUB.

[0074] Next, as shown in FIGS. 27A and 27B, a resist RS is formed on the interlayer insulating film IL, and a resist pattern for the shallow contact NC is formed. That is, as shown in FIG. 27A, in the region where the shallow contact NC is to be formed, the resist RS is patterned on the interlayer insulating film IL by photolithography so as to form the pattern of the shallow contact NC. Further, by dry etching, the interlayer insulating film IL is removed from the opening of the resist RS pattern to a certain depth to form a contact hole CH2 for the shallow contact NC. The bottom of the contact hole CH2 is formed to be located within the interlayer insulating film IL. At this time, as shown in FIG. 27B, in the region where the source contact SC is to be formed, the resist RS is formed in the contact hole CH for the source contact SC and on the interlayer insulating film IL.

[0075] Next, as shown in FIGS. 28A and 28B, the resist RS pattern is removed by ashing or wet etching. As shown in FIG. 28A, in the region where the shallow contact NC is to be formed, the resist RS pattern in the contact hole CH2 for the shallow contact NC and on the interlayer insulating film IL is removed. At the same time, as shown in FIG. 28B, in the region where the source contact SC is to be formed, the resist RS pattern in the contact hole CH for the source contact SC and on the interlayer insulating film IL is removed.

[0076] Next, as shown in FIGS. 29A and 29B, the source contact SC and the shallow contact NC are formed simultaneously. In this example, the source contact SC and the shallow contact NC are formed of the same material. The method of forming the contacts is the same as that in FIG. 16 of Embodiment 1. That is, as shown in FIGS. 29A and 29B, in the region where the source contact SC is formed, a metal film such as Ti / TiN is formed on the entire inner surface of the contact hole CH reaching from the interlayer insulating film IL to the P+ body contact region PC, and at the same time, in the region where the shallow contact NC is formed, a metal film such as Ti / TiN is formed on the entire inner surface of the contact hole CH2 reaching inside the interlayer insulating film IL. Next, in the region where the source contact SC is formed, by sputtering or CVD, a metal plug such as W is formed on the metal film such as Ti / TiN so as to fill the contact hole CH, and the metal (Ti / TiN, W) on the surface layer of the interlayer insulating film IL is removed by dry etching to form the source contact SC. At the same time, in the region where the shallow contact NC is formed, a metal plug such as W is formed on the metal film such as Ti / TiN so as to fill the contact hole CH2 to form the shallow contact NC.

[0077] Next, as shown in FIGS. 30A and 30B, the source wiring SW is formed. The method of forming the source wiring SW is the same as that in FIG. 17 of Embodiment 1. That is, as shown in FIGS. 30A and 30B, in the region where the source contact SC is formed, a barrier metal layer BM made of TiW is formed on the entire surface of the source contact SC and the interlayer insulating film IL, and at the same time, in the region where the shallow contact NC is formed, a barrier metal layer BM made of TiW is formed on the entire surface of the shallow contact NC and the interlayer insulating film IL. Next, by sputtering or CVD, an aluminum layer AL is formed on the entire surface of the barrier metal layer BM in the region where the source contact SC is formed and the region where the shallow contact NC is formed.

[0078] Next, another example of the manufacturing method of the semiconductor device 100 according to the present embodiment will be described. This example is an example in which a shallow contact is formed in a process different from the source contact SC after the formation of the source contact SC. FIGS. 31A to 34A are cross-sections taken along line A3-A3' of FIG. 18, showing the cross-section of the region where the shallow contact NC is formed. FIGS. 31B to 34B are cross-sections taken along line A4-A4' of FIG. 18, showing the cross-section of the region where the source contact SC is formed.

[0079] First, similar to the example of the above manufacturing method, the steps up to FIGS. 26A and 26B are performed. That is, an interlayer insulating film IL is formed on the semiconductor substrate SUB, and in the region where the source contact SC is to be formed, a contact hole CH for the source contact SC is formed.

[0080] Next, as shown in FIGS. 31A and 31B, the source contact SC is formed. The method of forming the contact is the same as that in FIG. 16 of Embodiment 1. That is, as shown in FIG. 31B, in the region where the source contact SC is formed, a metal film such as Ti / TiN is formed on the entire inner surface of the contact hole CH reaching from the interlayer insulating film IL to the P+ body contact region PC by a sputtering method or a CVD method. Next, a metal plug such as W is formed on the metal film such as Ti / TiN so as to fill the contact hole CH by a sputtering method or a CVD method, and the metal (Ti / TiN, W) on the surface layer of the interlayer insulating film IL is removed by a dry etching method to form the source contact SC. At this time, as shown in FIG. 31A, in the region where the shallow contact NC is formed, the interlayer insulating film IL remains formed on the semiconductor substrate SUB.

[0081] Next, as shown in FIGS. 32A and 32B, a resist RS is formed on the interlayer insulating film IL, and a resist pattern for the shallow contact NC is formed. That is, as shown in FIG. 32A, in the region where the shallow contact NC is formed, the resist RS is patterned on the interlayer insulating film IL by photolithography so as to form the pattern of the shallow contact NC. Further, by dry etching, the interlayer insulating film IL is removed from the opening of the resist RS pattern to a certain depth to form a contact hole CH2 for the shallow contact NC. The bottom of the contact hole CH2 is formed to be located within the interlayer insulating film IL. At this time, as shown in FIG. 32B, in the region where the source contact SC is formed, the resist RS is formed on the source contact SC and the interlayer insulating film IL.

[0082] Next, as shown in FIGS. 33A and 33B, the resist RS pattern is removed by ashing treatment or wet etching treatment. As shown in FIG. 33A, in the region where the shallow contact NC is formed, the resist RS pattern in the contact hole CH2 for the shallow contact NC and on the interlayer insulating film IL is removed. At the same time, as shown in FIG. 33B, in the region where the source contact SC is formed, the resist RS pattern on the source contact SC and the interlayer insulating film IL is removed.

[0083] Next, as shown in FIGS. 34A and 34B, a shallow contact NC and a source wiring SW are formed. That is, the shallow contact NC and the barrier metal layer BM are formed simultaneously. In this example, the shallow contact NC and the barrier metal layer BM are made of the same material and are integrally formed. By integrally forming the shallow contact NC and the barrier metal layer BM, the anchor effect is further improved. As shown in FIGS. 34A and 34B, in the region where the source contact SC is formed by a sputtering method or a CVD method, a barrier metal layer BM made of TiW is formed on the source contact SC and the interlayer insulating film IL, and at the same time, in the region where the shallow contact NC is formed, the contact hole CH2 is filled and TiW is formed on the interlayer insulating film IL to integrally form the shallow contact NC and the barrier metal layer BM. Next, by a sputtering method or a CVD method, in the region where the source contact SC is formed and the region where the shallow contact NC is formed, an aluminum layer AL is formed on the entire surface of the barrier metal layer BM.

[0084] As described above, in the present embodiment, a shallow contact having no electrical connection function is disposed in a region including the outer peripheral end portion of the source wiring. Due to the anchor effect of this shallow contact, peeling of the source wiring at the outer peripheral end portion of the source wiring can be suppressed in the same manner as in the first embodiment. Since the shallow contact does not affect the characteristics of the MOSFET, it can be disposed at an arbitrary position.

[0085] (Embodiment 3) Next, Embodiment 3 will be described. This embodiment is an example in which the extending direction of the shallow contact shown in Embodiment 2 is changed.

[0086] FIG. 35 is an enlarged plan view of an end portion of a cell region of the semiconductor device 100 according to the present embodiment. FIG. 35 is an enlarged view of the end portion 10a of the cell region in FIG. 3. FIG. 36 is a cross-sectional view taken along line A5 - A5' of FIG. 35.

[0087] As shown in FIG. 35, in the present embodiment, the shallow contact NC is arranged so as to extend in parallel with the outer peripheral end portion 11b of the source wiring SW. For example, the X direction (second direction) in FIG. 35 can be referred to as the horizontal direction, and it can also be said that the shallow contact NC extends in the horizontal direction. The horizontal direction is the same direction as the direction of the outer peripheral end portion 11b of the source wiring SW, that is, the outer peripheral direction, and is a direction orthogonal to the extending direction of the source contact SC. The shallow contact NC of the present embodiment is also referred to as the horizontal shallow contact NC. Note that the shallow contact NC may be arranged not only in the horizontal direction but also in an oblique direction with respect to the outer peripheral end portion 11b of the source wiring SW.

[0088] As shown in FIG. 36, the shallow contact NC is shallower in depth than the source contact SC and reaches the depth inside the interlayer insulating film IL, similar to Embodiment 2. Note that the configuration other than the layout of the shallow contact NC is the same as that in Embodiment 2. The manufacturing method of the shallow contact NC is also the same as that in Embodiment 2.

[0089] The arrangement position of the horizontal shallow contact NC is set within a range necessary for suppressing the peeling of the source wiring SW (for example, the peeling in region 12 of FIG. 4). For example, the arrangement position of the horizontal shallow contact NC is set within the inner range 13c. The inner range 13c is a predetermined range from the outside (vicinity) of the region of the outer end portion 11a of the source contact SC to the outer peripheral end portion 11b of the source wiring SW. Similar to Embodiment 2, the inner range 13c may be set according to the size and material of the source wiring SW, the material of the shallow contact NC, etc.

[0090] In the example of FIG. 35, the horizontal shallow contact NC is arranged in the middle between the outer peripheral end portion 11b of the source wiring SW and the outer end portion 11a of the source contact SC. Thereby, similar to Embodiment 2, the peeling of the outer peripheral portion of the source wiring SW can be suppressed by the anchor effect of the shallow contact NC extending in the outer peripheral direction near the outer peripheral end portion 11b of the source wiring SW.

[0091] Figures 37 and 38 are layout examples when the position of the lateral shallow contact NC is changed. In the example of Figure 37, the lateral shallow contact NC is in the same position as the outer peripheral end portion 11b of the source wiring SW in a plan view. That is, the lateral shallow contact NC may overlap with the vicinity of the outer peripheral end portion 11b of the source wiring SW or the region (outer peripheral portion) including the outer peripheral end portion 11b of the source wiring SW in a plan view. In the example of Figure 38, the lateral shallow contact NC is arranged in the vicinity of the outer side end portion 11a of the source contact SC. Even in this case, the peeling of the outer peripheral portion of the source wiring SW can be suppressed by the anchor effect of the lateral shallow contact NC extending in the outer peripheral direction of the source wiring SW. By arranging the lateral shallow contact NC closer to the outer peripheral end portion 11b of the source wiring SW, the peeling of the end portion of the source wiring SW can be further suppressed.

[0092] Figures 39 and 40 are layout examples when the lateral shallow contact NC is separated. That is, the shallow contact NC may include a first shallow contact portion (first anchor member portion) and a second shallow contact portion (second anchor member portion) arranged separately. In the example of Figure 39, similar to Figure 37, the lateral shallow contact NC is arranged at the same position as the outer peripheral end portion 11b of the source wiring SW in a plan view, and further, the lateral shallow contact NC is separated into two. In the example of Figure 40, similar to Figure 38, the lateral shallow contact NC is arranged in the vicinity of the outer side end portion 11a of the source contact SC, and further, the lateral shallow contact NC is separated into two. By separating and spacing apart the shallow contact NC, while suppressing the material cost, the peeling of the outer peripheral portion of the source wiring SW can be suppressed by the anchor effect of the shallow contact NC.

[0093] Figs. 41 and 42 are layout examples when two lateral shallow contacts NC are arranged. That is, the first shallow contact NC (the first anchor member) and the second shallow contact NC (the second anchor member) may be arranged to extend in parallel along the outer peripheral direction of the source wiring SW in a plan view. Note that not only two, but more shallow contacts NC may be arranged. In the example of Fig. 41, similar to Fig. 37, a lateral shallow contact NC is arranged at the same position as the outer peripheral end portion 11b of the source wiring SW in a plan view, and further, a lateral shallow contact NC is added in the middle between the outer peripheral end portion 11b of the source wiring SW and the outer side end portion 11a of the source contact SC. In the example of Fig. 42, similar to Fig. 38, a lateral shallow contact NC is arranged in the vicinity of the outer side end portion 11a of the source contact SC, and further, a lateral shallow contact NC is added in the middle between the outer peripheral end portion 11b of the source wiring SW and the outer side end portion 11a of the source contact SC. By arranging a plurality of shallow contacts NC, the anchor effect of the shallow contact NC is further enhanced, and peeling of the outer peripheral portion of the source wiring SW can be surely suppressed.

[0094] Figures 43 to 46 are layout examples when two horizontal shallow contacts NC are separated. In Figures 43 and 44, similar to Figure 41, horizontal shallow contacts NC are respectively arranged at the same position as the outer peripheral end 11b of the source wiring SW in a plan view and at the middle between the outer peripheral end 11b of the source wiring SW and the outer end 11a of the source contact SC, and further, similar to Figure 39, the two horizontal shallow contacts NC are separated. In Figure 43, the separated shallow contacts NC overlap in the vertical direction (Y direction) and are arranged side by side. That is, the shallow contact NC portion separated from the first shallow contact NC and the shallow contact NC portion separated from the second shallow contact NC are arranged opposite to each other. In Figure 44, the separated shallow contacts NC are arranged in a zigzag pattern without overlapping in the vertical direction. That is, the separation region between the shallow contact NC portions separated from the first shallow contact NC and the shallow contact NC portion separated from the second shallow contact NC are arranged opposite to each other. Figures 45 and 46 are similar to Figure 42, where horizontal shallow contacts NC are respectively arranged near the outer end 11a of the source contact SC and at the middle between the outer peripheral end 11b of the source wiring SW and the outer end 11a of the source contact SC, and further, similar to Figure 40, the two horizontal shallow contacts NC are separated. In Figure 45, similar to Figure 43, the separated shallow contacts NC overlap in the vertical direction and are arranged side by side. In Figure 46, similar to Figure 44, the separated shallow contacts NC are arranged in a zigzag pattern without overlapping in the vertical direction. Even in the cases of Figures 43 to 46, by separating and spacing apart a plurality of shallow contacts NC, while suppressing the material cost, the peeling of the outer peripheral portion of the source wiring SW can be suppressed by the anchor effect of the shallow contacts NC. Note that the vertical shallow contacts of Embodiment 2 and the horizontal shallow contacts of this embodiment may be combined. For example, the horizontally separated shallow contacts in Figures 43 to 46 may be connected by vertical shallow contacts.

[0095] As described above, in this embodiment, the shallow contact is arranged in parallel with the outer peripheral end of the source wiring. Also in this case, as in the second embodiment, it is possible to suppress the peeling of the source wiring at the outer peripheral end of the source wiring. Further, by adding a shallow contact in a direction rotated 90° from the source contact SC, the warpage of the wafer (semiconductor substrate) can be improved.

[0096] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

[0097] For example, in the semiconductor device according to the above embodiment, the conductivity type (P-type or N-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. may be reversed. Therefore, when one of the N-type and P-type conductivity types is defined as the first conductivity type and the other is defined as the second conductivity type, the first conductivity type can be P-type and the second conductivity type can be N-type, or conversely, the first conductivity type can be N-type and the second conductivity type can be P-type.

Explanation of Reference Numerals

[0098] 1 Semiconductor device 2 Semiconductor substrate 3 Insulating film 4 Electrode 5 Anchor member 9 Semiconductor device 10 Cell region 10a Cell region end 10b Cell region end 11a Outer end 11b Outer peripheral end 11c Outer end 11d Inner end 12 Region 13a Outer end range 13b Inner end range 13c Inner range 100 Semiconductor device 100a Substrate surface 100b Substrate back surface AL Aluminum layer BM Barrier metal layer CH Contact hole CH2 Contact hole DE Drain electrode FE Field plate electrode FF Field plate peripheral insulating film FG Field plate - gate insulating film GD Gate pad GE Gate electrode GF Gate insulating film GW Gate wiring IL Interlayer insulating film NC Shallow contact ND Drain region NV Drift region PB Body region PC Body contact region RS Resist SA Source region SC Source contact SCa Extension SD Source pad SUB Semiconductor substrate SW Source wiring TR Trench

Claims

1. A semiconductor substrate, an insulating film formed on the semiconductor substrate, an electrode formed on the insulating film, and an anchor member in contact with the insulating film and the electrode at an outer peripheral portion of the electrode in a plan view. A semiconductor device comprising the above.

2. The anchor member includes a contact that electrically connects the semiconductor substrate and the electrode. The semiconductor device according to Claim 1.

3. The anchor member is formed from the electrode side through the insulating film to the semiconductor substrate side. The semiconductor device according to Claim 1.

4. The anchor member is formed from the electrode side to the inside of the insulating film. The semiconductor device according to Claim 1.

5. The anchor member extends from the inside to the outside of the electrode in a plan view. The semiconductor device according to Claim 1.

6. An outer end portion of the anchor member overlaps with an outer peripheral portion of the electrode in a plan view. The semiconductor device according to Claim 5.

7. An outer end portion of the anchor member is included outside an outer peripheral portion of the electrode in a plan view. The semiconductor device according to Claim 5.

8. An inner end portion of the anchor member is included in a region where a contact for electrically connecting the semiconductor substrate and the electrode is formed. The semiconductor device according to Claim 5.

9. An inner end portion of the anchor member is included in a region from a region where a contact for electrically connecting the semiconductor substrate and the electrode is formed to an outer peripheral portion of the electrode. The semiconductor device according to Claim 5.

10. The anchor member includes a first anchor member portion and a second anchor member portion that are spaced apart, and either the first anchor member portion or the second anchor member portion overlaps with an outer peripheral portion of the electrode in a plan view. The semiconductor device according to Claim 5.

11. The anchor member extends in an outer peripheral direction of the electrode in a plan view. The semiconductor device according to Claim 1.

12. The anchor member is included in a region from a region where a contact for electrically connecting the semiconductor substrate and the electrode is formed to an outer peripheral portion of the electrode. The semiconductor device according to Claim 11.

13. The anchor member includes a first anchor member portion and a second anchor member portion that are spaced apart. The semiconductor device according to Claim 11.

14. The anchor member includes a first anchor member and a second anchor member that extend in parallel along the outer peripheral direction of the electrode in a plan view. The semiconductor device according to claim 11.

15. Each of the first anchor member and the second anchor member includes a plurality of spaced-apart anchor member portions. The plurality of anchor member portions included in the first anchor member and the plurality of anchor member portions included in the second anchor member are arranged to face each other. The semiconductor device according to claim 14.

16. Each of the first anchor member and the second anchor member includes a plurality of spaced-apart anchor member portions. A spaced region between the plurality of anchor member portions included in the first anchor member and the plurality of anchor member portions included in the second anchor member are arranged to face each other. The semiconductor device according to claim 14.

17. The material of the anchor member includes any one of titanium, titanium nitride, tungsten, and titanium tungsten. The semiconductor device according to claim 1.

18. Forming an insulating film on a semiconductor substrate, Forming an electrode on the insulating film, and further including forming an anchor member in contact with the insulating film and the electrode at the outer peripheral portion of the electrode in a plan view. A method of manufacturing a semiconductor device.

19. Forming the anchor member includes simultaneously forming a contact that electrically connects the semiconductor substrate and the electrode and the anchor member. The method of manufacturing a semiconductor device according to claim 18.

20. Forming the anchor member includes forming the anchor member after forming a contact that electrically connects the semiconductor substrate and the electrode. The method of manufacturing a semiconductor device according to claim 18.

Images