Semiconductor device and method of manufacturing the same

Abstract

To improve the performance of semiconductor devices.SOLUTION: A gate electrode GE is formed on a semiconductor substrate via a gate insulating film, and an n-type drift region and a p-type well region are formed in the semiconductor substrate. N-type drain regions DR1, DR2 are formed in the n-type drift region, and an n-type source region SR and an n-type semiconductor region EX are formed in the p-type well region. An impurity concentration of the n-type semiconductor region EX is lower than an impurity concentration of the n-type source region SR. The gate electrode GE includes n-type gate electrode portions GE1, GE2 extending in a Y direction, and a p-type gate connection portion GEC connecting the gate electrode portion GE1 and the gate electrode portion GE2. In plan view, the n-type source region SR is arranged between the gate electrode portion GE1 and the gate electrode portion GE2. In plan view, the n-type semiconductor region EX is formed along a side surface S2 of the gate electrode portion GE1, a side surface S5 of the gate connection portion GEC, and a side surface S3 of the gate electrode portion GE2.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device having a MOSFET and a method for manufacturing the same.

Background Art

[0002] In a power conversion circuit such as an inverter circuit, a power switching element such as an LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) is used. The power switching element is formed on a semiconductor substrate.

[0003] Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2019-46875) describes a technique related to a semiconductor device having an LDMOSFET.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] It is desired to improve the performance of a semiconductor device having a MOSFET.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] According to one embodiment, a semiconductor device includes a gate electrode formed on a main surface of a semiconductor substrate with a gate insulating film therebetween, a drift region of a first conductivity type and a well region of a second conductivity type formed in the semiconductor substrate, and a first drain region and a second drain region of the first conductivity type formed in the drift region. The semiconductor device further includes a source region and an LDD region of the first conductivity type formed in the well region. The gate electrode has a first gate electrode portion and a second gate electrode portion of the first conductivity type each extending in a first direction, and a gate connection portion of the second conductivity type connecting the first gate electrode portion and the second gate electrode portion. In a plan view, a part of each of the first gate electrode portion, the second gate electrode portion, and the gate connection portion overlaps with the well region, and another part of each of the first gate electrode portion, the second gate electrode portion, and the gate connection portion overlaps with the drift region. In a plan view, the LDD region is formed along the first gate electrode portion, the gate connection portion, and the second gate electrode portion.

Advantages of the Invention

[0008] According to one embodiment, the performance of the semiconductor device can be improved.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] In the following embodiments, when necessary for convenience, they will be described by being divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a part or all of the other as a modification example, details, supplementary explanation, etc. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified and unless it is clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified and unless it is clearly not the case in principle, it shall include those substantially approximating or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. In addition, in the following embodiments, explanations of the same or similar parts are not repeated in principle unless particularly necessary.

[0012] In addition, in the drawings used in the embodiments, hatching may be omitted even for sectional views in order to make the drawings easier to view. Also, hatching may be added even for plan views in order to make the drawings easier to view.

[0013] Also, the plan view corresponds to the case of viewing from a plane substantially parallel to the main surface or the back surface of the semiconductor substrate SB. Also, the bottom surface and the lower surface have the same meaning. Also, the height position corresponds to the distance from the back surface of the semiconductor substrate SB. Also, the depth position corresponds to the distance from the main surface of the semiconductor substrate SB.

[0014] In addition, in the present application, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) includes not only a MOSFET using an oxide film as a gate insulating film but also a MOSFET using an insulating film other than the oxide film as a gate insulating film. Also, an LDMOSFET may be called an HV-MOSFET (High Voltage Metal Oxide Semiconductor Field Effect Transistor) or a DEMOSFET (Drain Extended Metal Oxide Semiconductor Field Effect Transistor).

[0015] Also, an n-channel MOSFET can be regarded as an n-type MOSFET, and a p-channel MOSFET can be regarded as a p-type MOSFET. In this case, the n-type means that the conduction type of the channel during conduction is n-type, and the p-type means that the conduction type of the channel during conduction is p-type.

[0016] (Embodiment 1) <Regarding the structure of the semiconductor device> Figures 1 to 3 show cross-sectional views perpendicular to the main surface of the semiconductor substrate SB. Figures 4 to 6 show plan views parallel to the main surface of the semiconductor substrate SB. The planar regions shown in Figures 4, 5, and 6 are the same as each other. The cross-sectional view along the line A-A in Figures 4 to 6 corresponds to Figure 1, the cross-sectional view along the line B-B in Figures 4 to 6 corresponds to Figure 2, and the cross-sectional view along the line C-C in Figures 4 to 6 corresponds to Figure 3. Although Figure 4 is a plan view, in Figure 4, the gate electrode GE is hatched. Figure 5 is a plan view at the height position H1 shown in Figures 1 to 3. Figure 6 is a plan view at the height position H2 shown in Figures 1 to 3. In Figure 6, the planar position of the gate electrode GE is indicated by a dotted line, and the planar positions of the n-type drain region DR1 and the n-type drain region DR2 are indicated by a two-dot chain line.

[0017] The semiconductor device of this Embodiment 1 has a power switching element used in a power conversion circuit such as an inverter circuit. Here, it has an LDMOSFET as a transistor constituting the power switching element.

[0018] As shown in Figures 1 to 6, the semiconductor device of this Embodiment 1 has a semiconductor substrate SB, an LDMOSFET1 formed on the main surface of the semiconductor substrate SB, and an insulating film IL formed on the main surface of the semiconductor substrate SB.

[0019] The semiconductor substrate SB is made of, for example, p-type single-crystalline silicon into which a p-type impurity such as boron (B) is introduced.

[0020] As the semiconductor substrate SB, an epitaxial wafer may be used. In that case, the semiconductor substrate SB has a p-type substrate body made of a single crystal silicon substrate or the like, and a p-type semiconductor layer formed by epitaxial growth on the p-type substrate body. The main surface of the semiconductor substrate SB is formed by the main surface of the p-type semiconductor layer. In FIGS. 1 to 3, a structure including the p-type substrate body and the p-type semiconductor layer is shown as the semiconductor substrate SB. An n-type buried layer may be formed inside the upper portion of the p-type substrate body, and a p-type semiconductor layer may be formed on the n-type buried layer.

[0021] LDMOSFET1 is an n-type (n-channel type) LDMOSFET.

[0022] LDMOSFET1 has a p-type well region PB, an n-type drift region ND, an n-type drain region DR1, an n-type drain region DR2, an n-type semiconductor region EX, a plurality of n-type source regions SR, a plurality of p-type semiconductor regions PR, a p-type resurf region RF, a p-type semiconductor region HP, a gate insulating film GF, and a gate electrode GE.

[0023] The p-type well region PB, the n-type drift region ND, the n-type drain region DR1, the n-type drain region DR2, the n-type semiconductor region EX, the plurality of n-type source regions SR, the plurality of p-type semiconductor regions PR, the p-type resurf region RF, and the p-type semiconductor region HP are formed in the semiconductor substrate SB. The gate electrode GE is formed on the main surface of the semiconductor substrate SB with the gate insulating film GF interposed therebetween. The insulating film IL is formed on the main surface of the semiconductor substrate SB so as to cover LDMOSFET1.

[0024] The gate electrode GE has a gate electrode portion GE1, a gate electrode portion GE2, and a gate connection portion GEC that connects the gate electrode portion GE1 and the gate electrode portion GE2. The gate connection portion GEC, the gate electrode portion GE1, and the gate electrode portion GE2 are integrally formed.

[0025] The gate electrode part GE1 and the gate electrode part GE2 each extend in the Y direction. The gate electrode part GE1 and the gate electrode part GE2 are spaced apart from each other in the X direction. One end of the gate electrode part GE1 and one end of the gate electrode part GE2 in the Y direction are connected to a gate connection part GEC extending in the X direction.

[0026] Although not shown in FIG. 4, the other end of the gate electrode part GE1 and the other end of the gate electrode part GE2 in the Y direction are connected to a gate connection part similar to the gate connection part GEC. The structure of the semiconductor substrate SB below that gate connection part is the same as the structure of the semiconductor substrate SB below the gate connection part GEC. The LDMOSFET1 has a structure symmetric with respect to the D-D line shown in FIG. 4.

[0027] Here, the Y direction corresponds to the gate width direction of each of the gate electrode part GE1 and the gate electrode part GE2. The X direction corresponds to the gate length direction of each of the gate electrode part GE1 and the gate electrode part GE2. The X direction and the Y direction intersect with each other, and preferably, are orthogonal to each other. Each of the X direction and the Y direction is parallel to the main surface of the semiconductor substrate SB.

[0028] As shown in FIG. 4, the gate electrode part GE1 has a side surface S1 and a side surface S2 opposite to the side surface S1. The side surface S1 and the side surface S2 are each substantially parallel to the Y direction. The gate electrode part GE2 has a side surface S3 and a side surface S4 opposite to the side surface S3. The side surface S3 and the side surface S4 are each substantially parallel to the Y direction. The gate connection part GEC has a side surface S5 and a side surface S6 opposite to the side surface S5. The side surface S5 and the side surface S6 are each substantially parallel to the X direction. The side surfaces S2, S3, S5 are the inner peripheral side surfaces of the gate electrode GE, and the side surfaces S1, S4, S6 are the outer peripheral side surfaces of the gate electrode GE. The side surface S2 of the gate electrode part GE1 and the side surface S3 of the gate electrode part GE2 face each other in the X direction. The side surface S5 of the gate connection part GEC intersects the side surface S2 of the gate electrode part GE1 and the side surface S3 of the gate electrode part GE2.

[0029] As shown in FIGS. 1 to 4, a sidewall spacer (sidewall insulating film) SW1 made of an insulating film is formed on the inner peripheral side surface of the gate electrode GE. A sidewall spacer (sidewall insulating film) SW2 made of an insulating film is formed on the outer peripheral side surface of the gate electrode GE. For this reason, the sidewall spacer SW1 is formed on the side surface S2 of the gate electrode portion GE1, the side surface S3 of the gate electrode portion GE2, and the side surface S5 of the gate connection portion GEC. The sidewall spacer SW2 is formed on the side surface S1 of the gate electrode portion GE1, the side surface S4 of the gate electrode portion GE2, and the side surface S6 of the gate connection portion GEC.

[0030] As shown in FIGS. 1 to 3, a p-type well region (p-type semiconductor region) PB and an n-type drift region (n-type semiconductor region) ND are formed in the upper part of the semiconductor substrate SB. In the case of FIGS. 1 to 3, a p-type RESURF region (p-type semiconductor region) RF is formed under the bottom surfaces of the n-type drift region ND and the p-type well region PB, respectively. The p-type impurity concentration of the p-type RESURF region RF is higher than the p-type impurity concentration of the semiconductor substrate SB. There may be a case where the p-type RESURF region RF is not formed. In the case of FIG. 3, a p-type semiconductor region HP is formed under the gate connection portion GEC. The p-type impurity concentration of the p-type semiconductor region HP is higher than the p-type impurity concentration of the semiconductor substrate SB. There may be a case where the p-type semiconductor region HP is not formed.

[0031] As shown in FIGS. 4 and 6, in plan view, the p-type well region PB is formed so as to include the region between the gate electrode portion GE1 and the gate electrode portion GE2. In plan view, the p-type well region PB is surrounded by the n-type drift region ND. In plan view, a part of the gate electrode portion GE1, a part of the gate electrode portion GE2, and a part of the gate connection portion GEC overlap the p-type well region PB, and another part of the gate electrode portion GE1, another part of the gate electrode portion GE2, and another part of the gate connection portion GEC overlap the n-type drift region ND.

[0032] A part of the p-type well region PB is located below the gate electrode portion GE1, another part of the p-type well region PB is located below the gate electrode portion GE2, and still another part of the p-type well region PB is located below the gate connection portion GEC. A part of the n-type drift region ND is located below the gate electrode portion GE1, another part of the n-type drift region ND is located below the gate electrode portion GE2, and still another part of the n-type drift region ND is located below the gate connection portion GEC.

[0033] As shown in FIGS. 1, 2, and 6, below the gate electrode portion GE1, the n-type drift region ND and the p-type well region PB are adjacent to each other in the X direction. Below the gate electrode portion GE2, the n-type drift region ND and the p-type well region PB are adjacent to each other in the X direction. As shown in FIGS. 3 and 6, below the gate connection portion GEC, the n-type drift region ND and the p-type well region PB are adjacent to each other in the Y direction.

[0034] A PN junction is formed at the boundary between the p-type well region PB and the n-type drift region ND. The boundary between the p-type well region PB and the n-type drift region ND extends in the Y direction below the gate electrode portion GE1, extends in the X direction below the gate connection portion GEC, and extends in the Y direction below the gate electrode portion GE2.

[0035] As shown in FIGS. 1 to 3, a plurality of n-type source regions (n-type semiconductor regions) SR and a plurality of p-type semiconductor regions PR are formed in the p-type well region PB. The p-type impurity concentration of each of the plurality of p-type semiconductor regions PR is higher than the p-type impurity concentration of the p-type well region PB. The p-type impurity concentration of the p-type well region PB is higher than the p-type impurity concentration of the semiconductor substrate SB. The upper surfaces of each of the plurality of n-type source regions SR and the upper surfaces of each of the plurality of p-type semiconductor regions PR reach the main surface of the semiconductor substrate SB. The bottom surfaces of each of the plurality of n-type source regions SR and the bottom surfaces of each of the plurality of p-type semiconductor regions PR are shallower than the bottom surface of the p-type well region PB.

[0036] As shown in FIG. 4, in a plan view, a plurality of n-type source regions SR and a plurality of p-type semiconductor regions PR are arranged in a row in the Y direction within a region surrounded by the gate electrode GE. In a plan view, a p-type semiconductor region PR and an n-type source region SR are alternately arranged in the Y direction between the gate electrode portion GE1 and the gate electrode portion GE2. A PN junction is formed at the boundary between the n-type source region SR and the p-type semiconductor region PR adjacent to each other in the Y direction. The plurality of n-type source regions SR and the plurality of p-type semiconductor regions PR arranged in the Y direction constitute an array region RG. P-type semiconductor regions PR, rather than n-type source regions SR, are respectively arranged at both ends in the Y direction of the array region RG. The p-type semiconductor region PR arranged at the end in the Y direction of the array region RG is referred to as a p-type semiconductor region PR1. In a plan view, the array region RG is surrounded by the gate electrode GE.

[0037] The p-type well region PB can function as a back gate. The p-type well region PB can also have a function as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET. Each of the plurality of p-type semiconductor regions PR can function as a contact portion of the p-type well region PB.

[0038] As shown in FIGS. 1 and 2, an n-type drain region (n-type semiconductor region) DR1 and an n-type drain region (n-type semiconductor region) DR2 are formed in the n-type drift region ND. The n-type impurity concentration of the n-type drain region DR1 and the n-type impurity concentration of the n-type drain region DR2 are each higher than the n-type impurity concentration of the n-type drift region ND. The upper surfaces of the n-type drain region DR1 and the n-type drain region DR2 each reach the main surface of the semiconductor substrate SB. The bottom surfaces of the n-type drain region DR1 and the n-type drain region DR2 are each shallower than the bottom surface of the n-type drift region ND.

[0039] As shown in FIG. 4, in a plan view, the n-type drain region DR1 extends in the Y direction such that the distance from the side surface S1 of the gate electrode portion GE1 to the n-type drain region DR1 is substantially constant. In a plan view, the n-type drain region DR2 extends in the Y direction such that the distance from the side surface S4 of the gate electrode portion GE2 to the n-type drain region DR2 is substantially constant. In a plan view, the n-type drain region DR1 and the n-type drain region DR2 are spaced apart from each other in the X direction. The gate electrode portion GE1 and the gate electrode portion GE2 are disposed between the n-type drain region DR1 and the n-type drain region DR2. The array region RG is disposed between the gate electrode portion GE1 and the gate electrode portion GE2. In a plan view, the gate electrode portion GE1 is disposed between the n-type drain region DR1 and the array region RG, and the gate electrode portion GE2 is disposed between the n-type drain region DR2 and the array region RG. In a plan view, the interval between the n-type drain region DR1 and the gate electrode portion GE1 is larger than the interval between the array region RG and the gate electrode portion GE1. In a plan view, the interval between the n-type drain region DR2 and the gate electrode portion GE2 is larger than the interval between the array region RG and the gate electrode portion GE2.

[0040] In a plan view, the n-type semiconductor region EX is formed so as to surround the array region RG. As shown in FIGS. 1 to 3, the n-type semiconductor region EX is formed in the p-type well region PB so as to be in contact with a plurality of n-type source regions SR and a plurality of p-type semiconductor regions PR.

[0041] The n-type impurity concentration of the n-type semiconductor region EX is lower than the n-type impurity concentration of each of the plurality of n-type source regions SR. The upper surface of the n-type semiconductor region EX reaches the main surface of the semiconductor substrate SB. The bottom surface of the n-type semiconductor region EX is shallower than the bottom surface of each of the plurality of n-type source regions SR and shallower than the bottom surface of each of the plurality of p-type semiconductor regions PR. The n-type semiconductor region EX can function as an LDD (Lightly doped drain) region. Each n-type source region SR and the n-type semiconductor region EX adjacent to each n-type source region SR can function as a source region having an LDD structure.

[0042] The n-type semiconductor region EX is formed under the sidewall spacer SW1. In plan view, the n-type semiconductor region EX extends along the sidewall spacer SW1 while overlapping with the sidewall spacer SW1. As shown in FIG. 4, in plan view, the n-type semiconductor region EX is formed along the inner peripheral side surface of the gate electrode GE. Therefore, the n-type semiconductor region EX extends in the Y direction along the side surface S2 of the gate electrode portion GE1, extends in the X direction along the side surface S5 of the gate connection portion GEC, and extends in the Y direction along the side surface S3 of the gate electrode portion GE2.

[0043] As shown in FIGS. 1 to 3, the n-type semiconductor region EX includes an n-type semiconductor region EX1 that extends along the side surface S2 of the gate electrode portion GE1, an n-type semiconductor region EX2 that extends along the side surface S5 of the gate connection portion GEC, and an n-type semiconductor region EX3 that extends along the side surface S3 of the gate electrode portion GE2. The n-type semiconductor region EX is not formed under the sidewall spacer SW2.

[0044] As shown in FIGS. 1 and 5, in the X direction, one side surface of each of the plurality of n-type source regions SR and one side surface of each of the plurality of p-type semiconductor regions PR are in contact with the n-type semiconductor region EX1. In the X direction, the other side surface of each of the plurality of n-type source regions SR and the other side surface of each of the plurality of p-type semiconductor regions PR are in contact with the n-type semiconductor region EX3. As shown in FIGS. 2 and 5, in the Y direction, one side surface of the p-type semiconductor region PR1 is in contact with the n-type semiconductor region EX2. In the Y direction, the other side surface of the p-type semiconductor region PR1 is in contact with the adjacent n-type source region SR of the p-type semiconductor region PR1.

[0045] As shown in FIG. 5, the n-type semiconductor region EX1 is in contact with a plurality of n-type source regions SR and a plurality of p-type semiconductor regions PR, and the n-type semiconductor region EX3 is in contact with a plurality of n-type source regions SR and a plurality of p-type semiconductor regions PR. On the other hand, the n-type semiconductor region EX2 is in contact with the p-type semiconductor region PR1 but not in contact with any of the plurality of n-type source regions SR.

[0046] In a cross-sectional view perpendicular to the Y direction and crossing the n-type source region SR, as shown in FIG. 1, a part of the p-type well region PB and a part of the n-type drift region ND are located below the gate electrode portion GE1, and another part of the p-type well region PB and another part of the n-type drift region ND are located below the gate electrode portion GE2.

[0047] In a cross-sectional view perpendicular to the Y direction and crossing the p-type semiconductor region PR, as shown in FIG. 2, a part of the p-type well region PB and a part of the n-type drift region ND are located below the gate electrode portion GE1, and another part of the p-type well region PB and another part of the n-type drift region ND are located below the gate electrode portion GE2.

[0048] In a cross-sectional view perpendicular to the X direction and crossing the p-type semiconductor region PR1, as shown in FIG. 3, a part of the p-type well region PB and a part of the n-type drift region ND are located below the gate connection portion GEC.

[0049] A channel (n-type inversion layer) is formed in the upper part of the p-type well region PB located under the gate electrode GE. Hereinafter, the region where the channel is formed is referred to as the channel formation region. The n-type semiconductor region EX is adjacent to the channel formation region. In a plan view, the n-type semiconductor region EX is interposed between the channel formation region and the array region RG. In a plan view, the n-type semiconductor region EX surrounds the array region RG, and the channel formation region surrounds the n-type semiconductor region EX and the array region RG.

[0050] The gate insulating film GF is made of, for example, a silicon oxide film. The gate electrode GE is made of a silicon film, specifically a polycrystalline silicon film (doped polysilicon film). The gate electrode part GE1, the gate connection part GEC, and the gate electrode part GE2 are integrally formed, but the conductivity type of the gate connection part GEC is different from the conductivity types of the gate electrode part GE1 and the gate electrode part GE2, respectively. The gate electrode part GE1 is made of an n-type silicon region PSN, the gate connection part GEC is made of a p-type silicon region PSP, and the gate electrode part GE2 is made of an n-type silicon region PSN. Therefore, the gate electrode part GE1 and the gate electrode part GE2 each have an n-type conductivity type, and the gate connection part GEC has a p-type conductivity type.

[0051] When a voltage equal to or higher than the threshold voltage is applied to the gate electrode GE, a channel made of an n-type inversion layer is formed in the upper part of the p-type well region PB located under the gate electrode GE. The n-type drain region DR1 and the plurality of n-type source regions SR are electrically connected to each other through the n-type drift region ND and the channel under the gate electrode part GE1, and the n-type drain region DR2 and the plurality of n-type source regions SR are electrically connected to each other through the n-type drift region ND and the channel under the gate electrode part GE2.

[0052] As shown in FIGS. 4 to 6, in a plan view, an n-type drift region ND is interposed between the p-type well region PB and the n-type drain region DR1, and an n-type drift region ND is interposed between the p-type well region PB and the n-type drain region DR2. Therefore, in a plan view, an n-type semiconductor region EX1, a channel formation region, and an n-type drift region ND exist between the array region RG and the n-type drain region DR1, and an n-type semiconductor region EX2, a channel formation region, and an n-type drift region ND exist between the array region RG and the n-type drain region DR2.

[0053] Also, a metal silicide layer (not shown) may be formed on the n-type drain region DR1, on the n-type drain region DR2, on each of the plurality of n-type source regions SR, on each of the plurality of p-type semiconductor regions PR, and on the gate electrode GE.

[0054] Next, the structure on the semiconductor substrate SB will be described.

[0055] As shown in FIGS. 1 to 3, the semiconductor device according to the first embodiment further includes a plurality of plugs (contact plugs) embedded in the insulating film IL and a plurality of wirings formed on the insulating film IL.

[0056] The insulating film IL is formed on the main surface of the semiconductor substrate SB so as to cover the gate electrode GE. The insulating film IL is composed of, for example, a laminated film including a silicon nitride film and a silicon oxide film on the silicon nitride film. The upper surface of the insulating film IL is planarized.

[0057] A plurality of contact holes (through holes) are formed in the insulating film IL, and a plurality of conductive plugs are formed in the plurality of contact holes. The plurality of plugs include a plurality of plugs P1, a plurality of plugs P2, a plurality of plugs P3, and a plurality of plugs P4. Each of the plugs P1, P2, P3, and P4 penetrates the insulating film IL.

[0058] Each of the plurality of plugs P1 is disposed on the n-type drain region DR1 and is electrically connected to the n-type drain region DR1. Each of the plurality of plugs P2 is disposed on the n-type drain region DR2 and is electrically connected to the n-type drain region DR2. Each of the plurality of plugs P3 is disposed on each n-type source region SR and is electrically connected to the n-type source region SR. Each of the plurality of plugs P4 is disposed on each p-type semiconductor region PR and is electrically connected to the p-type semiconductor region PR. Therefore, each plug P4 is electrically connected to the p-type well region PB through the p-type semiconductor region PR.

[0059] Also, a plug is disposed on the gate electrode GE, but in FIGS. 1 to 3, the plug on the gate electrode GE is not shown.

[0060] A plurality of wirings are formed on the insulating film IL. The plurality of wirings include a source wiring WS, a drain wiring WD1, and a drain wiring WD2.

[0061] The drain wiring WD1 is electrically connected to the n-type drain region DR1 via a plurality of plugs P1. A drain potential is supplied from the drain wiring WD1 to the n-type drain region DR1 via the plurality of plugs P1. The drain wiring WD2 is electrically connected to the n-type drain region DR2 via a plurality of plugs P2. A drain potential is supplied from the drain wiring WD2 to the n-type drain region DR2 via the plurality of plugs P2. The drain wiring WD1 and the drain wiring WD2 are electrically connected to each other via a wiring (not shown) that is upper than the drain wiring WD1 and the drain wiring WD2.

[0062] The source wiring WS is electrically connected to a plurality of n-type source regions SR via a plurality of plugs P3, and is also electrically connected to a plurality of p-type semiconductor regions PR via a plurality of plugs P4. That is, the source wiring WS is electrically connected to the plurality of plugs P3 disposed on the plurality of n-type source regions SR and the plurality of plugs P4 disposed on the plurality of p-type semiconductor regions PR. Therefore, a source potential is supplied from the source wiring WS to the plurality of n-type source regions SR via the plurality of plugs P3, and is also supplied from the source wiring WS to the plurality of p-type semiconductor regions PR via the plurality of plugs P4. Since the bottom surface of each of the plurality of p-type semiconductor regions PR is covered with a p-type well region PB, the source potential supplied to the plurality of p-type semiconductor regions PR is supplied from the plurality of p-type semiconductor regions PR to the p-type well region PB.

[0063] A gate wiring that is electrically connected to the gate electrode GE via a plug is formed on the insulating film IL, but the gate wiring is not shown in FIGS. 1 to 3.

[0064] The illustration and description of the structure upper than the insulating film IL, the drain wiring WD1, the drain wiring WD2, and the source wiring WS are omitted.

[0065] The LDMOSFET1 may be configured by connecting a plurality of unit LDMOSFETs in parallel. In the cases of FIGS. 1 to 6, the LDMOSFET1 has a configuration in which two unit LDMOSFETs sharing a source are connected in parallel. The number of unit LDMOSFETs connected in parallel can be set as required.

[0066] <Regarding the manufacturing process of the semiconductor device> FIGS. 9, 10, 12, 15, 17, 19, 21, 23, 25, and 27 are cross-sectional views corresponding to FIG. 1 above, and cross-sectional views taken along line A-A from FIGS. 4 to 6 above are shown. FIGS. 11, 13, 16, 18, 20, 22, 24, 26, and 28 are cross-sectional views corresponding to FIG. 3 above, and cross-sectional views taken along line C-C from FIGS. 4 to 6 above are shown.

[0067] As shown in FIG. 7, a semiconductor substrate SB is prepared. The semiconductor substrate SB is made of, for example, p-type single crystal silicon. An epitaxial wafer may be used as the semiconductor substrate SB. The semiconductor substrate SB may have an n-type buried layer formed therein.

[0068] Next, as shown in FIGS. 8 and 9, a p-type RESURF region RF and a p-type semiconductor region HP are formed in the semiconductor substrate SB using an ion implantation method or the like. In the first embodiment, the p-type RESURF region RF and the p-type semiconductor region HP are formed, but one or both of the p-type RESURF region RF and the p-type semiconductor region HP may not be formed.

[0069] Next, as shown in FIGS. 10 and 11, a photoresist pattern (mask layer) RP1 is formed on the main surface of the semiconductor substrate SB using photolithography technology. Thereafter, an n-type impurity is implanted into the semiconductor substrate SB by ion implantation using the photoresist pattern RP1 as an ion implantation blocking mask, thereby forming an n-type drift region ND in the semiconductor substrate SB. After the ion implantation, the photoresist pattern RP1 is removed. The n-type drift region ND is formed over a predetermined depth from the main surface of the semiconductor substrate SB. In plan view, the n-type drift region ND includes the region where the p-type well region PB will be formed later.

[0070] Next, as shown in FIGS. 12 and 13, a silicon film PS is formed on the main surface of the semiconductor substrate SB with a gate insulating film GF interposed therebetween. The gate insulating film GF is made of, for example, a silicon oxide film. The silicon film PS is specifically made of a polycrystalline silicon film.

[0071] Next, as shown in FIG. 14, an n-type silicon region PSN and a p-type silicon region PSP are formed in the silicon film PS using an ion implantation method or the like.

[0072] FIG. 14 is a plan view, and in FIG. 14, the n-type silicon region PSN and the p-type silicon region PSP are hatched to indicate different directions from each other. In FIG. 14, the position of the gate electrode GE to be formed later is indicated by a dotted line. As can be seen from FIG. 14 and the above FIG. 4, the regions where the gate electrode portions GE1 and GE2 of the gate electrode GE are formed are included in the n-type silicon region PSN, and the region where the gate connection portion GEC of the gate electrode GE is formed is included in the p-type silicon region PSP.

[0073] Next, as shown in FIGS. 12 and 13, a photoresist pattern (mask layer) RP2 is formed on the silicon film PS using photolithography technology. The photoresist pattern RP2 has an opening OP. The opening OP has side surfaces OP1, OP2, and OP3. The side surface OP1 and the side surface OP2 face each other and are parallel to the Y direction. The side surface OP3 intersects the side surfaces OP1 and OP2 and is parallel to the X direction. In FIGS. 12 and 13, the side surface facing the side surface OP3 is not shown.

[0074] Next, as shown in FIGS. 15 and 16, by etching the silicon film PS using the photoresist pattern RP2 as an etching mask, an opening matching the opening OP of the photoresist pattern RP2 is formed in the silicon film PS. As a result, the side surfaces S2, S3, and S5 are formed as the side surfaces of the opening of the silicon film PS. The side surface S2 of the silicon film PS aligns with the side surface OP1 of the opening OP, the side surface S3 of the silicon film PS aligns with the side surface OP2 of the opening OP, and the side surface S5 of the silicon film PS aligns with the side surface OP3 of the opening OP. Hereinafter, the whole of the opening OP of the photoresist pattern RP2 and the opening of the silicon film PS together is referred to as the opening OP.

[0075] Next, as shown in FIGS. 17 and 18, using the silicon film PS and the photoresist pattern RP2 on the silicon film PS as an ion implantation blocking mask, a p-type impurity is implanted into the semiconductor substrate SB by ion implantation, thereby forming a p-type well region PB in the semiconductor substrate SB. The p-type well region PB is formed by implanting a p-type impurity into a part of the n-type drift region ND. Therefore, the effective p-type impurity concentration of the p-type well region PB is defined by the difference between the concentration of the n-type impurity contained in the n-type drift region ND and the concentration of the p-type impurity implanted to form the p-type well region PB. The p-type impurity concentration of the p-type well region PB is higher than the p-type impurity concentration of the p-type semiconductor substrate SB. The p-type well region PB is formed over a predetermined depth from the main surface of the semiconductor substrate SB.

[0076] As ion implantation for forming the p-type well region PB, oblique ion implantation is used. In the case of oblique ion implantation, the implantation direction of the ion implantation is inclined with respect to the normal direction of the main surface of the semiconductor substrate SB. By forming the p-type well region PB using oblique ion implantation, the p-type well region PB is formed at a position overlapping the opening OP in plan view, and a part of the p-type well region PB is formed below the silicon film PS. Therefore, in plan view, the p-type well region PB is formed so as to enclose the opening OP. The planar dimension (planar area) of the p-type well region PB is larger than the planar dimension (planar area) of the opening OP.

[0077] Next, as shown in FIGS. 19 and 20, using the silicon film PS and the photoresist pattern RP2 on the silicon film PS as an ion implantation blocking mask, an n-type impurity is implanted into the semiconductor substrate SB by ion implantation to form an n-type semiconductor region EX in the semiconductor substrate SB. The n-type semiconductor region EX is formed over a predetermined depth from the main surface of the semiconductor substrate SB. The depth of the bottom surface of the n-type semiconductor region EX is shallower than the depth of the p-type well region PB.

[0078] As ion implantation for forming the n-type semiconductor region EX, vertical ion implantation is used. In the case of vertical ion implantation, the implantation direction of the ion implantation is parallel to the normal direction of the main surface of the semiconductor substrate SB. By forming the n-type semiconductor region EX using vertical ion implantation, the n-type semiconductor region EX is formed self-aligned with the opening OP. Therefore, in plan view, the n-type semiconductor region EX is formed so as to overlap the opening OP, and the outer peripheral side surface of the n-type semiconductor region EX substantially coincides with the side surfaces of the opening OP. Accordingly, in plan view, the outer peripheral side surface of the n-type semiconductor region EX substantially coincides with the side surfaces S2, S3, S5 of the silicon film PS. In plan view, the n-type semiconductor region EX is enclosed by the p-type well region PB.

[0079] In the first embodiment, the n-type semiconductor region EX is formed after the p-type well region PB is formed. The p-type well region PB may be formed after the n-type semiconductor region EX is formed.

[0080] Next, after removing the photoresist pattern RP2, as shown in FIGS. 21 and 22, using photolithography technology, an opening (OP) in the silicon film PS is filled, and a photoresist pattern (mask layer) RP3 is formed so as to cover a part of the silicon film PS. The opening (OP) of the silicon film PS is covered by the photoresist pattern RP2. Then, the silicon film PS is patterned by etching the silicon film PS using the photoresist pattern RP3 as an etching mask. Then, the photoresist pattern RP3 is removed. As shown in FIGS. 23 and 24, a gate electrode GE is formed by the patterned silicon film PS.

[0081] By etching using the photoresist pattern RP3, an outer peripheral side surface of the gate electrode GE is formed. Therefore, the side surfaces S1, S4, S6 are formed by etching using the photoresist pattern RP3. An inner peripheral side surface of the gate electrode GE is formed by a side surface of the opening OP. Therefore, the side surfaces S2, S3, S5 are formed by the side surface of the opening OP. The gate electrode portions GE1 and GE2 of the gate electrode GE are formed by the n-type silicon region PSN (see FIG. 14), and the gate connection portion GEC of the gate electrode GE is formed by the p-type silicon region PSP (see FIG. 14).

[0082] Next, as shown in FIGS. 25 and 26, a sidewall spacer SW1 is formed on an inner peripheral side surface of the gate electrode GE, and a sidewall spacer SW2 is formed on an outer peripheral side surface of the gate electrode GE. The sidewall spacer SW1 and the sidewall spacer SW2 can be formed in the same process. For example, after forming an insulating film so as to cover the gate electrode GE on the semiconductor substrate SB, the sidewall spacers SW1, SW2 can be formed by etching back the insulating film.

[0083] Next, as shown in FIGS. 25 and 26, an n-type drain region DR1, an n-type drain region DR2, and a plurality of n-type source regions SR are formed in the semiconductor substrate SB using an ion implantation method or the like.

[0084] The n-type drain region DR1 and the n-type drain region DR2 are formed in the n-type drift region ND. The n-type impurity concentration of the n-type drain region DR1 and the n-type impurity concentration of the n-type drain region DR2 are each higher than the n-type impurity concentration of the n-type drift region ND.

[0085] The plurality of n-type source regions SR are formed in the p-type well region PB. The n-type impurity concentration of each of the plurality of n-type source regions SR is higher than the n-type impurity concentration of the n-type semiconductor region EX. The depth of the bottom surface of each of the plurality of n-type source regions SR is deeper than the depth of the bottom surface of the n-type semiconductor region EX.

[0086] Vertical ion implantation is used as the ion implantation for forming the plurality of n-type source regions SR. For this reason, the plurality of n-type source regions SR are formed self-aligned with the sidewall spacer SW1. Therefore, an n-type semiconductor region EX remains under the sidewall spacer SW1 so as to be adjacent to the plurality of n-type source regions SR. The n-type drain region DR and the plurality of n-type source regions SR can be formed by the same ion implantation process to suppress the number of manufacturing steps, but can also be formed by separate ion implantation processes.

[0087] Next, as shown in FIGS. 25 and 26, a plurality of p-type semiconductor regions PR are formed in the semiconductor substrate SB using an ion implantation method or the like.

[0088] The plurality of p-type semiconductor regions PR are formed in the p-type well region PB. The impurity concentration of each of the plurality of p-type semiconductor regions PR is higher than the impurity concentration of the p-type well region PB. The bottom surface of each of the plurality of p-type semiconductor regions PR is deeper than the bottom surface of the p-type well region PB.

[0089] In Embodiment 1, after forming the n-type drain region DR1, the n-type drain region DR2, and the plurality of n-type source regions SR, a plurality of p-type semiconductor regions PR are formed. After forming the plurality of p-type semiconductor regions PR, it is also possible to form the n-type drain region DR1, the n-type drain region DR2, and the plurality of n-type source regions SR.

[0090] After forming the plurality of n-type source regions SR, the n-type drain region DR1, the n-type drain region DR2, and the plurality of p-type semiconductor regions PR, a metal silicide layer (not shown) may be formed on the n-type drain region DR1, on the n-type drain region DR2, on each of the plurality of n-type source regions SR, on each of the plurality of p-type semiconductor regions PR, and on the gate electrode GE. The metal silicide layer is formed using salicide (Self Aligned Silicide) technology.

[0091] Next, as shown in FIGS. 26 and 27, an insulating film IL is formed on the main surface of the semiconductor substrate SB by using a method such as CVD (Chemical Vapor Deposition) so as to cover the gate electrode GE. After forming the insulating film IL, the upper surface of the insulating film IL can also be polished and planarized by using a method such as CMP.

[0092] Next, as shown in FIGS. 1 to 3 above, by etching the insulating film IL using a photoresist pattern (not shown) formed on the insulating film IL as an etching mask, a plurality of contact holes penetrating the insulating film IL are formed. Thereafter, a plurality of conductive plugs are respectively formed in the plurality of contact holes. The plurality of plugs includes a plurality of plugs P1, a plurality of plugs P2, a plurality of plugs P3, and a plurality of plugs P4.

[0093] Next, as shown in FIGS. 1 to 3 above, a plurality of wirings are formed on the insulating film IL. The plurality of wirings includes a drain wiring WD1, a drain wiring WD2, and a source wiring WS.

[0094] Furthermore, illustration and description of the process of forming the upper insulating film and wiring are omitted.

[0095] In the first embodiment, by performing ion implantation of n-type impurities and ion implantation of p-type impurities on the silicon film PS, an n-type silicon region PSN and a p-type silicon region PSP are formed in the silicon film PS, and then the silicon film PS is processed to form a gate electrode GE. After processing the silicon film PS to form the gate electrode GE, n-type impurities may be ion-implanted into the gate electrode portion GE1 and the gate electrode portion GE2 of the gate electrode GE, and p-type impurities may be ion-implanted into the gate connection portion GEC of the gate electrode GE. In that case, in the ion implantation process for forming a plurality of n-type source regions SR, n-type drain regions DR1, and n-type drain regions DR2, it is preferable to implant n-type impurities into the gate electrode portion GE1 and the gate electrode portion GE2. Also, in the ion implantation process for forming a plurality of p-type semiconductor regions PR, it is preferable to implant p-type impurities into the gate connection portion GEC.

[0096] <Regarding the process of the study example> In FIGS. 29 and 30, a planar region corresponding to FIGS. 4 to 6 described above is shown.

[0097] In the semiconductor device of the study example examined by the present inventor, the conductivity type of the entire gate electrode GE is n-type. Therefore, in the case of the study example, all of the gate electrode portion GE1, the gate electrode portion GE2, and the gate connection portion GEC are made of an n-type silicon film into which n-type impurities are introduced and have an n-type conductivity type.

[0098] When a voltage equal to or higher than the threshold voltage of LDMOSFET1 is applied to the gate electrode GE, a channel made of an n-type inversion layer is formed in the upper part of the p-type well region PB located under the gate electrode part GE1 and under the gate electrode part GE2. As a result, the n-type drain region DR1 and the plurality of n-type source regions SR are electrically connected to each other through the n-type drift region ND and the channel under the gate electrode part GE1, and the n-type drain region DR2 and the plurality of n-type source regions SR are electrically connected to each other through the n-type drift region ND and the channel under the gate electrode part GE1. Thereby, as in the current path DP1 shown in FIG. 29, current flows in the X direction from the n-type drain region DR1 to the plurality of n-type source regions SR, passing under the gate electrode part GE1, and as in the current path DP2 shown in FIG. 29, current flows in the X direction from the n-type drain region DR2 to the plurality of n-type source regions SR, passing under the gate electrode part GE2.

[0099] However, since the gate connection part GEC and the n-type semiconductor region EX2 are formed, a parasitic MOSFET2 is formed on the main surface of the semiconductor substrate SB. In FIG. 29, the region where the parasitic MOSFET2 is formed is indicated by a dotted line. The gate connection part GEC functions as the gate electrode of the parasitic MOSFET2, the n-type semiconductor region EX2 functions as the source region of the parasitic MOSFET2, and the n-type drift region ND under the gate connection part GEC functions as the drain region of the parasitic MOSFET2.

[0100] When a voltage equal to or higher than the threshold voltage of the parasitic MOSFET2 is applied to the gate connection part GEC, a channel made of an n-type inversion layer is formed in the upper part of the p-type well region PB located under the gate connection part GEC, whereby the parasitic MOSFET2 is turned on.

[0101] When the parasitic MOSFET2 is turned on, in the cross-section shown in FIG. 3 above, the n-type semiconductor region EX2 and the n-type drift region ND under the gate connection part GEC are electrically connected to each other through the channel under the gate connection part GEC. As a result, like the current path LP shown in FIGS. 3 and 29 above, current flows from the n-type drain regions DR1 and DR2 through the n-type drift region ND and the channel under the gate connection part GEC to the n-type semiconductor region EX2, and further flows through the n-type semiconductor regions EX1 and EX3 to the n-type source region SR.

[0102] The current path LP is not the intended current path for the LDMOSFET, but a leakage current path flowing through the parasitic MOSFET2. For current to flow from the n-type drain regions DR1 and DR2 to the n-type source region SR via the parasitic MOSFET2 as in the current path LP can cause leakage current, which is undesirable. Therefore, it is desirable to suppress or prevent current from flowing from the n-type drain regions DR1 and DR2 to the n-type source region SR via the parasitic MOSFET2.

[0103] The p-type impurity concentration of the p-type well region PB under the gate connection part GEC tends to be lower than the p-type impurity concentrations of the p-type well regions PB under the gate electrode parts GE1 and GE2 respectively. In FIG. 29, the p-type regions PB1, PB2, PB3 are shown hatched. The p-type region PB1 corresponds to the p-type well region PB located under the gate electrode part GE1. The p-type region PB2 corresponds to the p-type well region PB located under the gate connection part GEC. The p-type region PB3 corresponds to the p-type well region PB located under the gate electrode part GE2. The p-type impurity concentration of the p-type region PB2 tends to be lower than the p-type impurity concentrations of the p-type regions PB1 and PB3 respectively.

[0104] In the case of the above-described study example, reflecting the fact that the p-type impurity concentration of the p-type region PB2 is lower than the p-type impurity concentrations of the p-type regions PB1 and PB3, respectively, the threshold voltage of the parasitic MOSFET2 becomes lower than the threshold voltage of the LDMOSFET1. This is because, in the case of an n-type MOSFET, the threshold voltage tends to decrease as the p-type impurity concentration of the p-type well region under the gate electrode decreases. Note that the threshold voltage of the LDMOSFET1 corresponds to the threshold voltage based on the current paths DP1 and DP2. The threshold voltage of the parasitic MOSFET2 corresponds to the threshold voltage based on the current path LP.

[0105] When the threshold voltage of the parasitic MOSFET2 is lower than the threshold voltage of the LDMOSFET1, when a voltage is applied to the gate electrode GE, the parasitic MOSFET2 operates before the LDMOSFET1 operates. This is desirable to prevent, as it can cause an increase in leakage current or punch-through.

[0106] The reason why the p-type impurity concentration of the p-type well region PB (p-type region PB2) under the gate connection portion GEC is lower than the p-type impurity concentrations of the p-type well regions PB (p-type regions PB1 and PB3) under the gate electrode portions GE1 and GE2, respectively, is as follows.

[0107] The p-type well region PB is formed by oblique ion implantation. During oblique ion implantation, p-type impurity ions are reflected from the side surfaces of the opening OP, and the reflected p-type impurity ions are also implanted into the semiconductor substrate SB and contribute to the formation of the p-type well region PB. P-type impurity ions reflected from the side surface OP2 (see FIG. 17) of the opening OP during oblique ion implantation are also introduced into the p-type well region PB under the gate electrode portion GE1. P-type impurity ions reflected from the side surface OP1 (see FIG. 17) of the opening OP during oblique ion implantation are also introduced into the p-type well region PB under the gate electrode portion GE2. However, almost no p-type impurity ions reflected from any side surface of the opening OP during oblique ion implantation are introduced into the p-type well region PB under the gate connection portion GEC. This is due to the fact that the dimension (length) of the opening OP in the Y direction is larger than the dimension (length) of the opening OP in the X direction. Since the distance between the side surface OP3 of the opening OP and the side surface facing the side surface OP3 is larger than the distance between the side surfaces OP1 and OP2 of the opening OP, the p-type impurity ions reflected from the side surfaces of the opening OP hardly affect the p-type impurity concentration in the p-type region PB2. As a result, the p-type impurity concentration in the p-type well region PB (p-type region PB2) under the gate connection portion GEC is lower than the p-type impurity concentrations in the p-type well regions PB (p-type regions PB1, PB3) under the gate electrode portion GE1 and the gate electrode portion GE2, respectively.

[0108] <Features and Effects of Embodiment 1> In Embodiment 1, the conductivity type of the gate electrode GE is not uniform. The gate electrode portion GE1 and the gate electrode portion GE2 each have an n-type conductivity type, and the gate connection portion GEC has a p-type conductivity type. Specifically, the gate electrode portion GE1 is composed of an n-type silicon region PSN, the gate connection portion GEC is composed of a p-type silicon region PSP, and the gate electrode portion GE2 is composed of an n-type silicon region PSN. Thereby, the influence of the parasitic MOSFET2 can be suppressed or prevented, and the performance of the semiconductor device including the LDMOSFET1 can be improved.

[0109] When comparing the case of using an n-type silicon gate as the gate electrode of an n-channel MOSFET with the case of using a p-type silicon gate, if the structures other than the gate electrode are the same, the threshold voltage of the n-channel MOSFET using a p-type silicon gate is higher than the threshold voltage of the n-channel MOSFET using an n-type silicon gate. For this reason, it is common to use an n-type silicon gate as the gate electrode of an n-channel MOSFET. This is because if the threshold voltage of the n-channel MOSFET is lowered, the operating voltage of the n-channel MOSFET can be lowered.

[0110] However, during the operation of the LDMOSFET1, it is desirable to suppress the operation of the parasitic MOSFET2. Therefore, in the first embodiment, the gate electrode portion GE1 and the gate electrode portion GE2 each have an n-type conductivity type, and the gate connection portion GEC has a p-type conductivity type. Thereby, while maintaining the threshold voltage of the LDMOSFET1 in which the gate electrode portion GE1 and the gate electrode portion GE2 function as gate electrodes at a predetermined voltage, the threshold voltage of the parasitic MOSFET2 in which the gate connection portion GEC functions as a gate electrode can be increased. Specifically, when comparing the above study example with the first embodiment, the threshold voltage of the LDMOSFET1 in the first embodiment is the same as the threshold voltage of the LDMOSFET1 in the above study example, and the threshold voltage of the parasitic MOSFET2 in the first embodiment is higher than the threshold voltage of the parasitic MOSFET2 in the above study example. Thereby, in the first embodiment, the influence of the parasitic MOSFET2 can be suppressed or prevented, so that the performance of the semiconductor device including the LDMOSFET1 can be improved. For example, when a voltage is applied to the gate electrode GE, it is possible to suppress or prevent the parasitic MOSFET2 from operating before the LDMOSFET1 operates. As a result, the leakage current can be suppressed. Alternatively, punch-through caused by the parasitic MOSFET2 can be prevented.

[0111] Unlike in the first embodiment, it is also conceivable to form the n-type semiconductor region EX so that the n-type semiconductor region EX2 is not formed along the side surface S5 of the gate connection portion GEC. Since the n-type semiconductor region EX2 functions as the source region of the parasitic MOSFET2, if the n-type semiconductor region EX2 is not formed along the side surface S5 of the gate connection portion GEC, the parasitic MOSFET2 is not formed.

[0112] However, in order to form the n-type semiconductor region EX so that the n-type semiconductor region EX2 is not formed, in the ion implantation process for forming the n-type semiconductor region EX, an ion implantation blocking mask (a different photoresist pattern from the above photoresist pattern RP2) used in the ion implantation process for forming the p-type well region PB is required. This leads to an increase in the number of manufacturing steps of the semiconductor device and an increase in the manufacturing cost of the semiconductor device.

[0113] On the other hand, in the case of the first embodiment, a common ion implantation blocking mask (the above photoresist pattern RP2) can be used in the ion implantation process for forming the n-type semiconductor region EX and the ion implantation process for forming the p-type well region PB. Therefore, the number of manufacturing steps of the semiconductor device and the manufacturing cost of the semiconductor device can be suppressed.

[0114] When a common ion implantation blocking mask (the above photoresist pattern RP2) is used in the ion implantation process for forming the n-type semiconductor region EX and the ion implantation process for forming the p-type well region PB, the n-type semiconductor region EX includes the n-type semiconductor region EX2 along the side surface S5 of the gate connection portion GEC. When the n-type semiconductor region EX includes the n-type semiconductor region EX2, the parasitic MOSFET2 is formed. In the case of the first embodiment, the n-type semiconductor region EX2 is formed along the side surface S5 of the gate connection portion GEC, but as described above, the threshold voltage of the parasitic MOSFET2 can be increased. Therefore, it is acceptable that the n-type semiconductor region EX2 along the side surface S5 of the gate connection portion GEC forms the parasitic MOSFET2. As a result, it is possible to achieve both performance improvement of the semiconductor device and suppression of the manufacturing cost of the semiconductor device.

[0115] The technical idea of the first embodiment is to lower the threshold voltage of the LDMOSFET1 in the current paths DP1 and DP2 and raise the threshold voltage of the parasitic MOSFET2 in the current path LP.

[0116] In order to lower the threshold voltage of the LDMOSFET1 in the current paths DP1 and DP2, the gate electrode portions GE1 and GE2 on the channel formation region are composed of an n-type silicon region PSN. Therefore, in a cross-sectional view perpendicular to the Y direction, the gate electrode portions GE1 and GE2 on the p-type well region PB are composed of the n-type silicon region PSN at any cross-section cutting across any of the plurality of n-type source regions SR. Thereby, the threshold voltage of the LDMOSFET1 can be lowered in the current paths DP1 and DP2.

[0117] In order to raise the threshold voltage of the parasitic MOSFET2 in the current paths DP1 and DP2, the gate connection portion GEC on the channel formation region is composed of a p-type silicon region PSP. Therefore, in a cross-sectional view perpendicular to the X direction, the gate connection portion GEC on the p-type well region PB is composed of the p-type silicon region PSP at any cross-section cutting across any position of the side surface S5 of the gate connection portion GEC. Thereby, the threshold voltage of the parasitic MOSFET2 can be raised in the current paths DP1 and DP2.

[0118] (Second Embodiment) FIG. 31 is a cross-sectional view corresponding to FIG. 11 above, showing a cross-sectional view along the line C-C in FIGS. 4 to 6 above. In FIG. 32, the position of the gate electrode GE formed later is indicated by a dotted line, and the positions of the n-type drain regions DR1 and DR2 formed later are indicated by a two-dot chain line.

[0119] The difference between the second embodiment and the first embodiment above is the step of forming the n-type drift region ND.

[0120] In the above-described Embodiment 1, the n-type drift region ND is formed by vertical ion implantation without using oblique ion implantation. Therefore, in the above-described Embodiment 1, the n-type impurity concentration in the surface layer portion of the n-type drift region ND shown in FIGS. 10 and 11 is substantially constant regardless of the planar position.

[0121] In the present Embodiment 2, as shown in FIG. 31, after forming a photoresist pattern RP1 on the main surface of a semiconductor substrate SB using photolithography technology, n-type impurities are implanted into the semiconductor substrate SB by ion implantation using the photoresist pattern RP1 as a mask, thereby forming an n-type semiconductor region ND1 in the semiconductor substrate SB. The n-type semiconductor region ND1 is formed using oblique ion implantation. Next, n-type impurities are implanted into the semiconductor substrate SB by ion implantation using the photoresist pattern RP1 as a mask, thereby forming an n-type semiconductor region ND2 in the semiconductor substrate SB. The n-type semiconductor region ND2 is formed using vertical ion implantation. Thereafter, the photoresist pattern RP1 is removed.

[0122] The implantation energy of the ion implantation for forming the n-type semiconductor region ND1 is smaller than the implantation energy of the ion implantation for forming the n-type semiconductor region ND2. Therefore, in the semiconductor substrate SB, the n-type semiconductor region ND2 is formed under the n-type semiconductor region ND1. The n-type semiconductor region ND1 and the n-type semiconductor region ND2 under the n-type semiconductor region ND1 form the n-type drift region ND. The n-type semiconductor region ND1 constitutes the upper part of the n-type drift region ND, and the n-type semiconductor region ND2 constitutes the lower part of the n-type drift region ND.

[0123] When performing oblique ion implantation using the photoresist pattern RP1 as a mask, due to the shielding effect of the photoresist pattern RP1, the impurity implantation density into the semiconductor substrate SB becomes locally low in the vicinity of the side surface of the photoresist pattern RP1. Therefore, when forming the n-type semiconductor region ND1 by oblique ion implantation, the n-type impurity concentration of the n-type semiconductor region ND1 becomes locally low in the vicinity of the side surface of the photoresist pattern RP1. As a result, the n-type impurity concentration of the n-type semiconductor region ND1b shown in FIGS. 31 and 32 is lower than the n-type impurity concentration of the n-type semiconductor region ND1a. The n-type impurity concentration in the surface layer portion of the n-type semiconductor region ND1a is substantially constant regardless of the planar position.

[0124] The n-type semiconductor region ND1b is a part of the n-type semiconductor region ND1, and the n-type semiconductor region ND1a is another part of the n-type semiconductor region ND1. The n-type semiconductor region ND1b and the n-type semiconductor region ND1a are adjacent to each other in the Y direction. The side surface RP1a of the photoresist pattern RP1 is parallel to the X direction. In plan view, the side surface RP1a of the photoresist pattern RP1 crosses the region where the gate connection portion GEC is formed. In plan view, the side surface RP1a of the photoresist pattern RP1 and the n-type semiconductor region ND1a are separated from each other in the X direction, and the n-type semiconductor region ND1b exists between the side surface RP1a of the photoresist pattern RP1 and the n-type semiconductor region ND1a. In plan view, it is preferable to set the implantation angle of the oblique ion implantation so that the region where the gate connection portion GEC is formed is located within the n-type semiconductor region ND2. The n-type semiconductor region ND1 forming step may be performed after the n-type semiconductor region ND2 forming step.

[0125] Regarding the steps after the n-type drift region ND forming step, the second embodiment is the same as the first embodiment described above.

[0126] In the case of the second embodiment, compared with the first embodiment, the threshold voltage of the parasitic MOSFET2 can be further increased. As a result, the performance of the semiconductor device can be further improved.

[0127] In Embodiment 2, the reason why the threshold voltage of parasitic MOSFET2 can be further increased will be described.

[0128] After the n-type drift region ND is formed, a p-type well region PB is formed. In a plan view, the p-type well region PB is formed within the n-type drift region ND. Therefore, within the p-type well region PB, there are n-type impurities introduced by ion implantation for forming the n-type drift region ND and p-type impurities introduced by ion implantation for forming the p-type well region PB. Due to the fact that the density of p-type impurities in the p-type well region PB is higher than the density of n-type impurities in the p-type well region PB, the effective conduction type of the p-type well region PB becomes p-type. Thus, the difference between the density of p-type impurities and the density of n-type impurities defines the effective p-type impurity concentration of the p-type well region PB.

[0129] In Embodiment 2, the n-type impurity concentration of the n-type semiconductor region ND1b is lower than the n-type impurity concentration of the n-type semiconductor region ND1a. The gate connection portion GEC formed later is located within the n-type semiconductor region ND1b in a plan view. By utilizing this, the effective p-type impurity concentration at the upper part of the p-type well region PB (PB2) located under the gate connection portion GEC can be increased. As a result, the effective p-type impurity concentration in the channel formation region of parasitic MOSFET2 can be increased.

[0130] On the other hand, in the case of Embodiment 1 above, the n-type impurity concentration of the n-type semiconductor region ND1b is the same as the n-type impurity concentration of the n-type semiconductor region ND1a. Therefore, in the case of Embodiment 2, compared with Embodiment 1, the effective p-type impurity concentration in the upper part of the p-type well region PB (PB2) located under the gate connection portion GEC can be increased. Thereby, the effective p-type impurity concentration in the channel formation region of parasitic MOSFET2 can be increased. Accordingly, in the case of Embodiment 2, compared with Embodiment 1, the threshold voltage of parasitic MOSFET2 can be increased.

[0131] A channel is formed on the upper portion of the p-type well region PB located under the gate electrode GE. Therefore, the n-type impurity concentration of the n-type semiconductor region ND1 affects the impurity concentration of the channel formation region, while the n-type impurity concentration of the n-type semiconductor region ND2 hardly affects the impurity concentration of the channel formation region. For this reason, the n-type semiconductor region ND2 can be formed by vertical ion implantation. As a result, the n-type impurity concentration of the n-type semiconductor region ND2 becomes substantially constant regardless of the planar position. Therefore, the characteristics of the semiconductor device can be stabilized.

[0132] On the other hand, in the case of the first embodiment, since the n-type drift region ND can be formed by vertical ion implantation without using oblique ion implantation, the process of forming the n-type drift region ND can be simplified. As a result, for example, the manufacturing time of the semiconductor device can be shortened. Alternatively, the manufacturing cost of the semiconductor device can be suppressed.

[0133] When the gate connection portion GEC is formed of p-type silicon as in the first embodiment, if the process of forming the n-type drift region ND of the second embodiment is applied, the threshold voltage of the parasitic MOSFET2 can be further increased.

[0134] Unlike the first embodiment, when the gate electrode portion GE1, the gate electrode portion GE2, and the gate connection portion GEC are formed of n-type silicon, the process of forming the n-type drift region ND of the second embodiment may be applied. Also in that case, the threshold voltage of the parasitic MOSFET2 can be increased as compared with the case where the process of forming the n-type drift region ND of the second embodiment is not applied. As a result, since the influence of the parasitic MOSFET2 can be suppressed, the performance of the semiconductor device including the LDMOSFET can be improved.

[0135] As described above, the invention made by the present inventor has been specifically described based on its embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Reference Numerals

[0136] 1 LDMOSFET 2 Parasitic MOSFET DP1, DP2 Current path DR1, DR2 n-type drain region EX, EX1, EX2, EX3 n-type semiconductor region GE Gate electrode GE1, GE2 Gate electrode part GEC Gate connection part GF Gate insulating film HP p-type semiconductor region IL Insulating film LP Current path ND n-type drift region ND1, ND1a, ND1b, ND2 n-type semiconductor region OP Opening OP1, OP2, OP3 Side surface P1, P2, P3, P4 Plug PB p-type well region PB1, PB2, PB3 p-type region PR p-type semiconductor region PS Silicon film PSN n-type silicon region PSP p-type silicon region RP1, RP2, RP3 Photoresist pattern RP1a Side surface S1, S2, S3, S4, S5, S6 Side surface RF p-type RESURF region RG Array region SB Semiconductor substrate SR n-type source region SW1, SW2 Sidewall spacer WD1, WD2 Drain wiring WS Source wiring

Claims

1. A semiconductor substrate, a gate electrode formed on a main surface of the semiconductor substrate via a gate insulating film, a drift region of a first conductivity type formed in the semiconductor substrate, a well region of a second conductivity type, opposite to the first conductivity type, formed in the semiconductor substrate, a first drain region of the first conductivity type formed in the drift region and having an impurity concentration higher than that of the drift region, a second drain region of the first conductivity type formed in the drift region and having an impurity concentration higher than that of the drift region, a first semiconductor region of the first conductivity type formed in the well region, at least one source region of the first conductivity type formed in the well region and having an impurity concentration higher than that of the first semiconductor region, comprising, the gate electrode has a first gate electrode portion of the first conductivity type extending in a first direction, a second gate electrode portion of the first conductivity type extending in the first direction and spaced apart from the first gate electrode portion in a second direction orthogonal to the first direction, a gate connection portion of the second conductivity type connecting the first gate electrode portion and the second gate electrode portion, and having, in a plan view, the first drain region and the second drain region are spaced apart from each other in the second direction, in a plan view, between the first drain region and the second drain region, the first gate electrode portion and the second gate electrode portion are disposed, in a plan view, between the first gate electrode portion and the second gate electrode portion, the at least one source region is disposed, in a plan view, the well region is surrounded by the drift region, in a plan view, a part of the first gate electrode portion, a part of the second gate electrode portion, and a part of the gate connection portion overlap the well region, in a plan view, another part of the first gate electrode portion, another part of the second gate electrode portion, and another part of the gate connection portion overlap the drift region, the first gate electrode portion has a first side surface facing the second gate electrode portion, the second gate electrode portion has a second side surface facing the first gate electrode portion, the gate connection portion has a third side surface intersecting the first side surface and the second side surface, In a plan view, the first semiconductor region is formed along the first side surface of the first gate electrode portion, the third side surface of the gate connection portion, and the second side surface of the second gate electrode portion. A semiconductor device.

2. In the semiconductor device according to claim 1, The first gate electrode portion is made of silicon of the first conductivity type, The second gate electrode portion is made of silicon of the first conductivity type, The gate connection portion is made of silicon of the second conductivity type. A semiconductor device.

3. In the semiconductor device according to claim 2, The first conductivity type is an n-type, The second conductivity type is a p-type. A semiconductor device.

4. In the semiconductor device according to claim 2, The first gate electrode portion, the gate connection portion, and the second gate electrode portion are integrally formed. A semiconductor device.

5. In the semiconductor device according to claim 1, The at least one source region is in contact with the first semiconductor region along the first side surface of the first gate electrode portion and the first semiconductor region along the two side surfaces of the second gate electrode portion. A semiconductor device.

6. In the semiconductor device according to claim 1, Including a plurality of second semiconductor regions of the second conductivity type, The at least one source region has a plurality of source regions, In a plan view, between the first gate electrode portion and the second gate electrode portion, the plurality of source regions and the plurality of second semiconductor regions are alternately arranged in the first direction. A semiconductor device.

7. In the semiconductor device according to claim 1, The first semiconductor region along the third side surface of the gate connection portion is in contact with any one of the plurality of second semiconductor regions. A semiconductor device.

8. In the semiconductor device according to claim 1, The impurity concentration of the well region under the gate connection portion is lower than the impurity concentration of the well region under the first gate electrode portion and lower than the impurity concentration of the well region under the second gate electrode portion. A semiconductor device.

9. In the semiconductor device according to claim 1, The first side surface of the first gate electrode portion and the second side surface of the second gate electrode portion are each parallel to the first direction, The third side surface of the gate connection portion is parallel to the second direction. A semiconductor device.

10. (a) A step of preparing a semiconductor substrate, (b) A step of forming a drift region of the first conductivity type in the semiconductor substrate, Step (c): forming a silicon film on the main surface of the semiconductor substrate with a gate insulating film therebetween; Step (d): forming an opening in the silicon film by etching the silicon film; Step (e): after step (d), forming a well region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate so as to enclose the opening in plan view; Step (f): after step (d), forming a first semiconductor region of the first conductivity type in the semiconductor substrate so as to overlap the opening in plan view; Step (g): after steps (e) and (f), forming a gate electrode by etching the silicon film; Step (h): forming sidewall spacers on side surfaces of the gate electrode; Step (i): after step (h), forming a first drain region of the first conductivity type having an impurity concentration higher than that of the drift region and a second drain region having an impurity concentration higher than that of the drift region in the drift region, and forming at least one source region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region in the well region; comprising; The gate electrode has a first gate electrode portion of the first conductivity type extending in a first direction; a second gate electrode portion of the first conductivity type extending in the first direction and spaced apart from the first gate electrode portion in a second direction orthogonal to the first direction; and a gate connection portion of the second conductivity type connecting the first gate electrode portion and the second gate electrode portion; In plan view, the first drain region and the second drain region are spaced apart from each other in the second direction; In plan view, the first gate electrode portion and the second gate electrode portion are located between the first drain region and the second drain region; In plan view, the at least one source region is located between the first gate electrode portion and the second gate electrode portion; In plan view, a part of the first gate electrode portion, a part of the second gate electrode portion, and a part of the gate connection portion overlap the well region; In plan view, another part of the first gate electrode portion, another part of the second gate electrode portion, and another part of the gate connection portion overlap the drift region; The first gate electrode portion has a first side surface facing the second gate electrode portion; The second gate electrode portion has a second side surface facing the first gate electrode portion; ​ The gate connection portion has a third side surface that intersects the first side surface and the second side surface, The first side surface, the second side surface, and the third side surface constitute a part of the side surface of the opening, and a method for manufacturing a semiconductor device.

11. In the method for manufacturing a semiconductor device according to claim 10, In the step (e), the well region is formed by oblique ion implantation, In the step (f), the first semiconductor region is formed by vertical ion implantation, and a method for manufacturing a semiconductor device.

12. In the method for manufacturing a semiconductor device according to claim 11, (d1) After the step (c) and before the step (d), a step of forming a first mask layer on the silicon film, (h1) After the step (e) and the step (f) and before the step (g), a step of removing the first mask layer, further comprising, In the step (d), by using the first mask layer as an etching mask to etch the silicon film, an opening is formed in the silicon film, In the step (e), by using the silicon film and the first mask layer as an ion implantation blocking mask and implanting impurities of the second conductivity type into the semiconductor substrate by oblique ion implantation, the well region is formed, In the step (f), by using the silicon film and the first mask layer as an ion implantation blocking mask and implanting impurities of the first conductivity type into the semiconductor substrate by vertical ion implantation, the first semiconductor region is formed, and a method for manufacturing a semiconductor device.

13. In the method for manufacturing a semiconductor device according to claim 12, (h2) After the step (h1) and before the step (g), a step of forming a second mask layer on the main surface of the semiconductor substrate so as to cover the opening and partially cover the silicon film, further comprising, In the step (g), by using the second mask layer as an etching mask to etch the silicon film, the gate electrode is formed, and a method for manufacturing a semiconductor device.

14. In the method for manufacturing a semiconductor device according to claim 10, (k) After the step (h), a step of forming a plurality of second semiconductor regions of the second conductivity type having an impurity concentration higher than that of the well region in the well region, further comprising, The at least one source region has a plurality of source regions, In a plan view, a method of manufacturing a semiconductor device, wherein the plurality of source regions and the plurality of second semiconductor regions are alternately arranged in the first direction between the first gate electrode portion and the second gate electrode portion.

15. In the method of manufacturing a semiconductor device according to claim 14, in the step (k), the first semiconductor region along the third side surface of the gate connection portion is in contact with any one of the plurality of second semiconductor regions, a method of manufacturing a semiconductor device.

16. In the method of manufacturing a semiconductor device according to claim 10, the step (b) includes (b1) forming a third mask layer on the main surface of the semiconductor substrate; after the step (b1), forming the drift region in the semiconductor substrate by an ion implantation method; after the step (b2), removing the third mask layer, a method of manufacturing a semiconductor device.

17. In the method of manufacturing a semiconductor device according to claim 16, the step (b2) includes (b4) using the third mask layer as an ion implantation blocking mask to implant impurities of the second conductivity type into the semiconductor substrate by oblique ion implantation; (b5) using the third mask layer as an ion implantation blocking mask to implant impurities of the second conductivity type into the semiconductor substrate by vertical ion implantation, and the implantation energy of the oblique ion implantation in the step (b4) is smaller than the implantation energy of the vertical ion implantation in the step (b5), a method of manufacturing a semiconductor device.

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