Semiconductor device

Abstract

To provide a semiconductor device that can increase the breakdown voltage further.SOLUTION: A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, an embedded region formed in the semiconductor substrate, a second semiconductor region disposed on the embedded region, a third semiconductor region disposed on the embedded region, a drain region formed in the second semiconductor region, a source region formed in the third semiconductor region, and a gate electrode layer formed on an upper surface of the semiconductor substrate. The first semiconductor region includes a first region formed between the third semiconductor region and the embedded region, and a second formed between the second semiconductor region and the embedded region. Each of the semiconductor substrate, the first semiconductor region, and the second semiconductor region has a first conductivity type. Each of the embedded region and the third semiconductor region has a second conductivity type that is opposite to the first conductivity type.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a laterally diffused metal oxide semiconductor (LDMOS) transistor.

Background Art

[0002] An LDMOS transistor has a structure that relaxes the electric field strength between the drain and the gate by laterally expanding the drain region. Therefore, since the LDMOS transistor has a high breakdown voltage, it is used in automobiles, motor drives, audio amplifiers, and the like.

[0003] Patent Document 1 discloses an LDMOS transistor including an impurity region of a second conductivity type that separates an embedded region having a first conductivity type and a body region having a first conductivity type. By providing the impurity region, the electric field in the vertical direction (depth direction) of the drain region when a high voltage is applied to the drain and the back gate can be relaxed, so that the breakdown voltage can be improved.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As the device size of the LDMOS transistor is reduced, further improvement in breakdown voltage is required. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] In the present disclosure, a semiconductor device includes a semiconductor substrate having an upper surface, a first semiconductor region formed in the semiconductor substrate, a buried region formed in the semiconductor substrate or in the first semiconductor region, a second semiconductor region formed in the first semiconductor region and disposed on the buried region, a third semiconductor region formed in the first semiconductor region and disposed on the buried region, a drain region formed in the second semiconductor region, a source region formed in the third semiconductor region, and a gate electrode layer formed on the upper surface of the semiconductor substrate. The first semiconductor region has a first region formed between the third semiconductor region and the buried region in a direction perpendicular to the upper surface of the semiconductor substrate, and a second region formed between the second semiconductor region and the buried region in a direction perpendicular to the upper surface of the semiconductor substrate. The semiconductor substrate, the first semiconductor region, and the second semiconductor region each have a first conductivity type. The buried region and the third semiconductor region each have a second conductivity type opposite to the first conductivity type. The impurity concentration of the first region and the impurity concentration of the second region are higher than the impurity concentration of the first semiconductor region.

Advantages of the Invention

[0007] According to the present disclosure, a semiconductor device capable of further increasing the breakdown voltage can be provided.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same reference numerals are given to the same components or corresponding components, and redundant descriptions are omitted. In the drawings, for convenience of explanation, the configuration may be omitted or simplified in some cases. Also, at least a part of each embodiment may be arbitrarily combined with each other.

[0010] In the semiconductor device according to the present disclosure, the conductivity type (p-type or n-type) of the semiconductor substrate, semiconductor region, diffusion region, transistor, etc. may be inverted. Therefore, when one conductivity type of n-type and p-type is defined as the first conductivity type and the other conductivity type is defined as the second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0011] The impurity concentration of a component included in the semiconductor device according to the present disclosure refers to the peak value in the measured region of the component. Further, when comparing the impurity concentrations of two components, the description "about the same" does not mean only complete coincidence. Even if the impurity concentrations of two components differ due to manufacturing variations, if the set values of the impurity concentrations of the two components are the same, the impurity concentrations of the two components are regarded as the same as each other.

[0012] <Embodiment 1> FIG. 1 is a cross-sectional view of a semiconductor device 1, and the semiconductor device 1 includes a semiconductor substrate 10 having a first conductivity type and a plurality of regions formed in or on the semiconductor substrate 10. FIGS. 2 and 3 are diagrams for explaining the positional relationship of the plurality of regions, respectively. The components shown in the figures are the same as those in FIG. 1, and some of the reference numerals are omitted.

[0013] Examples of the semiconductor device 1 include a semiconductor chip including an LDMOS transistor, a semiconductor wafer, and a package in which these are mounted inside. FIG. 1 shows a cross-sectional view in the channel length direction of the LDMOS transistor.

[0014] The semiconductor substrate 10 has an upper surface 11 and a lower surface 12. Hereinafter, unless otherwise specified, the components included in the semiconductor device 1 shown in FIG. 1 are formed on the upper surface 11 side of the semiconductor substrate 10. The semiconductor substrate 10 may be a laminate including a substrate body and an epitaxial layer formed on the substrate body. This epitaxial layer corresponds to the first semiconductor region 100 described later.

[0015] An embedded region 110 having a second conductivity type opposite to the first conductivity type is formed in the semiconductor substrate 10. The embedded region 110 is formed, for example, by introducing impurities indicating the second conductivity type into the semiconductor substrate 10. When the semiconductor substrate 10 is a laminate including a substrate body and an epitaxial layer, the embedded region 110 may be formed in the epitaxial layer.

[0016] The embedded region 110 may be formed over the entire surface of the semiconductor substrate 10, or may be partially formed using a mask. Further, the method for forming the embedded region 110 described above is an example, and the method for forming the embedded region 110 is not limited thereto.

[0017] In the present disclosure, the epitaxial layer included in the semiconductor substrate 10 is defined as the first semiconductor region 100. Since the first semiconductor region 100 and the embedded region 110 are formed by any of the above methods, the first semiconductor region 100 is formed over the embedded region 110 or includes the embedded region 110.

[0018] Further, the first semiconductor region 100 has the same first conductivity type as the semiconductor substrate 10. Here, the impurity concentration of the first semiconductor region 100 is preferably approximately the same as or higher than the impurity concentration of the semiconductor substrate 10, and is preferably lower than the impurity concentration of the embedded region 110.

[0019] The second semiconductor region 120 is disposed over the embedded region 110 within the first semiconductor region 100. The second semiconductor region 120 has the first conductivity type, and the impurity concentration of the second semiconductor region 120 is preferably higher than the impurity concentration of the first semiconductor region 100.

[0020] Within the second semiconductor region 120, a drift region 121 of the first conductivity type, a drain region 122 of the first conductivity type, and a well region 123 of the first conductivity type are formed. The drift region 121 is formed within the second semiconductor region 120 so as to extend toward the third semiconductor region 130. The impurity concentration of the drift region 121 is preferably lower than the impurity concentration of the well region 123. The impurity concentration of the drain region 122 is preferably higher than the impurity concentration of the well region 123. The well region 123 is disposed under the drain region 122, and the width of the well region 123 is smaller than the width of the drift region 121.

[0021] The drain region 122 is formed on the upper surface 11 of the semiconductor substrate 10. Further, the conductive layer 41 is formed on the drain region 122, and the drain electrode layer 40 is formed on the conductive layer 41. The drain region 122 is electrically connected to the drain electrode layer 40 via the conductive layer 41.

[0022] The third semiconductor region 130 is disposed within the first semiconductor region 100 and on the buried region 110. The third semiconductor region 130 has a second conductivity type, and preferably, the impurity concentration of the third semiconductor region 130 is higher than the impurity concentration of the first semiconductor region 100.

[0023] Within the third semiconductor region 130, a source region 131 of the first conductivity type, a contact region 132 of the second conductivity type, and a well region 133 of the second conductivity type are formed. Preferably, the impurity concentration of the source region 131 and the impurity concentration of the contact region 132 are each higher than the impurity concentration of the well region 133. Also, preferably, the impurity concentration of the source region 131 and the impurity concentration of the contact region 132 are of the same order.

[0024] The source region 131 and the contact region 132 are each disposed on the upper surface 11 of the semiconductor substrate 10. The conductive layer 51 is formed on the source region 131, and the conductive layer 52 is formed on the contact region 132. Further, the source electrode layer 50 is formed on the conductive layer 51 and on the conductive layer 52. The source region 131 and the contact region 132 are connected to the source electrode layer 50 via the conductive layer 51 and the conductive layer 52.

[0025] In the cross-sectional view shown in FIG. 1, the second semiconductor region 120 and the third semiconductor region 130 are separated from each other in the direction along the upper surface 11 of the semiconductor substrate 10.

[0026] The first device isolation insulating layers 30 and 31 are STI (Shallow Trench Isolation), and have the function of preventing leakage between the gate and the drain or between the gate and the source. The first device isolation insulating layer 30 is formed within the second semiconductor region 120, and more specifically, is formed within the drift region 121 and on the upper surface 11 of the semiconductor substrate 10. Also, the first device isolation insulating layer 30 is disposed between the drain region 122 and the source region 131. The first device isolation insulating layer 31 is formed within the third semiconductor region 130 and on the upper surface 11 of the semiconductor substrate 10.

[0027] The second device isolation insulating layer 60 is DTI (Deep Trench Isolation), and has the function of preventing leakage between adjacent transistors. The second device isolation insulating layer 60 penetrates through the first device isolation insulating layer 31, the third semiconductor region 130, the first semiconductor region 100, and the embedded region 110. Although not shown, the second device isolation insulating layer 60 is formed so as to surround the LDMOS transistor in plan view.

[0028] Furthermore, the semiconductor device 1 includes a gate electrode layer 70 formed on the semiconductor substrate 10 with a gate insulating layer 71 interposed therebetween. The gate electrode layer 70 is disposed on the upper surface of the semiconductor substrate located between the drain region 122 and the source region 131 in the direction along the upper surface of the semiconductor substrate 10. In other words, in plan view, the gate electrode layer is disposed between the drain region 122 and the source region 131. Also, the gate electrode layer 70 and the gate insulating layer 71 are formed on the upper surface 11 of the semiconductor substrate 10.

[0029] The gate electrode layer 70 is preferably formed so as to overlap a part of the first device isolation insulating layer 30, a part of the second semiconductor region 120, and a part of the third semiconductor region 130. The gate insulating layer 71 is disposed between the gate electrode layer 70 and the semiconductor substrate 10.

[0030] The gate electrode layer 70 is disposed on the upper surface 11 of the semiconductor substrate 10 and on the first element isolation insulating layer 30. Also, an end portion of the gate electrode layer 70 facing the drain region 122 is disposed on the first element isolation insulating layer 30.

[0031] When the gate electrode layer 70 is formed so as to overlap a part of the first element isolation insulating layer 30, the first element isolation insulating layer 30 insulates between the gate electrode layer 70 and the second semiconductor region 120. Therefore, the gate insulating layer 71 is not disposed between the gate electrode layer 70 and the first element isolation insulating layer 30.

[0032] The semiconductor device 1 has, within the first semiconductor region 100, a first region 101 having a first conductivity type and a second region 102 having a first conductivity type. The impurity concentration of the first region 101 and the impurity concentration of the second region 102 are each higher than the impurity concentration of the first semiconductor region 100. Also, it is preferable that the impurity concentration of the second region 102 is equal to or lower than the impurity concentration of the first region 101.

[0033] The first region 101 is disposed under the third semiconductor region 130 in the cross-sectional view shown in FIG. 1. It is preferable that an end portion of the first region 101 facing the second region 102 is aligned with an end portion of the third semiconductor region 130 facing the second semiconductor region 120, or extends further toward the drain region 122. Also, it is preferable that an end portion of the first region 101 facing the second element isolation insulating layer 60 is in contact with a side surface of the second element isolation insulating layer 60. Such a shape is obtained by forming the second element isolation insulating layer 60 after forming the first region 101.

[0034] FIG. 2 is a diagram for explaining the positional relationship between the first region 101 and other regions. The first distance (S1) between the end portion of the first region 101 facing the second region 102 and the side surface of the second element isolation insulating layer 60 is preferably equal to or less than the second distance (S2) between the end portion of the gate electrode layer 70 facing the drain region 122 and the side surface of the second element isolation insulating layer 60. Further, the first distance (S1) is preferably equal to or greater than the third distance (S3) between the end portion of the third semiconductor region 130 facing the second semiconductor region 120 and the side surface of the second element isolation insulating layer 60.

[0035] Also, in a plan view, the end portion of the first region 101 facing the second region 102 is located between the second semiconductor region 120 and the third semiconductor region 130. Further, in a plan view, the well region 123 is included in the first region 101.

[0036] The first region 101 is separated from the embedded region 110 in a direction perpendicular to the upper surface 11 of the semiconductor substrate 10. Also, the first region 101 is preferably separated from the second semiconductor region 120 and the third semiconductor region 130, but the upper surface of the first region 101 may be in contact with the bottom portions of the second semiconductor region 120 and the third semiconductor region 130.

[0037] The second region 102 is disposed below the second semiconductor region 120 in the cross-sectional view shown in FIG. 1. In a plan view, the end portion of the second semiconductor region 120 facing the first region 101 is located between the end portion of the second region 102 facing the first region 101 and the second element isolation insulating layer 60.

[0038] FIG. 3 is a diagram for explaining the positional relationship between the second region 102 and other regions. The first distance (D1) between the end portion of the second region 102 facing the first region 101 and the side surface of the second element isolation insulating layer 60 is preferably equal to or less than the second distance (D2) between the end portion of the well region 123 of the second semiconductor region 120 facing the third semiconductor region 130 and the second element isolation insulating layer 60. Further, the first distance (D1) is preferably equal to or greater than the third distance (D3) between the end portion of the gate electrode layer 70 facing the drain region 122 and the side portion of the second element isolation insulating layer 60.

[0039] Also, in a plan view, an end portion of the second region 102 facing the first region 101 is located between a well region 123 of the second semiconductor region 120 and an end portion of the gate electrode layer 70 facing a drain region 122.

[0040] The second region 102 is separated from the embedded region 110 in a direction perpendicular to the upper surface 11 of the semiconductor substrate 10. Further, although the second region 102 is preferably separated from the second semiconductor region 120, the upper surface of the second region 102 may be in contact with the bottom of the second semiconductor region 120.

[0041] With such a configuration, the electric field strength at the bottom of the well region 123 and the electric field strength between the drain and the gate can be further relaxed, so that a semiconductor device enabling further high breakdown voltage can be provided.

[0042] FIG. 4 is a cross-sectional view of a semiconductor device 2 having no second region 102 as a comparative example. FIG. 5 shows simulation results of the concentration distribution of impact ions in the semiconductor device 1 and the semiconductor device 2. FIG. 6 shows simulation results of the electric field strength in the semiconductor device 1 and the semiconductor device 2.

[0043] FIG. 5(a) shows simulation results of the concentration distribution of impact ions when the gate voltage Vg is 0V, the drain voltage Vd and the back gate voltage Vbg are -100V in the semiconductor device 2 which is a comparative example. FIG. 5(b) shows simulation results of the concentration distribution of impact ions when the same voltage as that of the semiconductor device 2 is applied to the semiconductor device 1.

[0044] In the semiconductor device 2 which is a comparative example, it can be seen that impact ions are concentrated directly below the well region 123 of the second semiconductor region 120. On the other hand, in the semiconductor device 1, it can be seen that impact ions are not concentrated directly below the well region 123 and are dispersed in the vicinity of the embedded region 110.

[0045] FIG. 6 shows a plot indicating the simulation results of the electric field strength in semiconductor device 1 and semiconductor device 2 with respect to the depth (hereinafter referred to as "relative depth") when the distance between the upper surface 11 of the semiconductor substrate 10 and the embedded region 110 is 1. The electric field strengths of semiconductor device 1 and semiconductor device 2 when a voltage is applied to semiconductor device 1 and semiconductor device 2 in the same manner as in FIG. 5 are shown respectively.

[0046] It can be seen that in the vicinity of a relative depth of 0.2, that is, in the region close to the upper surface 11, the electric field strength of semiconductor device 2 is higher than that of semiconductor device 1. Also, in the vicinity of a relative depth of 0.9, that is, in the region close to the embedded region 110, it can be seen that the electric field strength of semiconductor device 1 is higher than that of semiconductor device 2.

[0047] From the above, by forming the second region 102, the electric field directly below the well region 123 of the second semiconductor region 120 can be relaxed, so that a high-voltage LDMOS transistor can be obtained.

[0048] Next, the correlation between the breakdown voltage in the OFF state of semiconductor device 1 and the impurity doping amount of the second region 102 will be described with reference to FIG. 7. FIG. 7 shows a plot of the impurity doping amount of the second region 102 (hereinafter referred to as "relative doping amount") when the impurity doping amount of the first region 101 is 1 and the simulation results of the breakdown voltage BVoff in the OFF state of semiconductor device 1.

[0049] It was confirmed that when the relative doping amount of the second region 102 with respect to the first region 101 is around 0.6, the condition that the breakdown voltage BVoff in the OFF state of semiconductor device 1 becomes larger than 1 is satisfied. Therefore, it can be seen that by making the impurity concentration of the second region 102 lower than that of the first region 101, further increase in the breakdown voltage of semiconductor device 1 is possible.

[0050] FIG. 8 shows a plot of the measured data of the breakdown voltage BVoff in the OFF state of the semiconductor device 1 and the semiconductor device 2. The horizontal axis of the plot shown in FIG. 8 represents the width (hereinafter referred to as "relative width") normalized with the width of the first element isolation insulating layer 30 in the channel length direction when the breakdown voltage BVoff in the OFF state of the semiconductor device 1 reaches 135V as 1. The vertical axis of the plot shown in FIG. 8 represents the breakdown voltage BVoff in the OFF state of the semiconductor device 1 and the semiconductor device 2.

[0051] The breakdown voltage BVoff in the OFF state of the semiconductor device 1 is improved by about 3V compared with the breakdown voltage BVoff in the OFF state of the semiconductor device 2 which is a comparative example. Furthermore, it was found that an LDMOS transistor having a breakdown voltage BVoff in the OFF state of 135V or more can be obtained by the configuration of the semiconductor device 1.

[0052] FIG. 9 shows a plot of the measured data of the normalized on-resistance Rsp. The horizontal axis represents the relative width of the first element isolation insulating layer 30 in the channel length direction, and the vertical axis represents the normalized on-resistance Rsp.

[0053] As an example, referring to FIG. 8, when the breakdown voltage BVoff in the OFF state of the semiconductor device 2 which is a comparative example can reach 135V, the relative width of the first element isolation insulating layer 30 in the channel length direction is predicted to be about 1.10. When the plot of the comparative example in FIG. 9 is extrapolated to the position where the relative width is 1.10, the value of the normalized on-resistance Rsp is predicted to be about 708 mΩ·mm 2 or so.

[0054] On the other hand, since the relative width of the first element isolation insulating layer 30 in the channel length direction when the breakdown voltage BVoff in the OFF state of the semiconductor device 1 can reach 135V is 1, the normalized on-resistance Rsp is about 594 mΩ·mm 2 or so. Therefore, it was found that the normalized on-resistance Rsp at the relative width capable of achieving the breakdown voltage BVoff of 135V of the LDMOS transistor can be reduced by about 16.1%.

[0055] <Embodiment 2> In Embodiment 2, a modification of the semiconductor device 1 according to Embodiment 1 will be described. Note that descriptions of configurations similar to those in the configuration example of Embodiment 1 will be omitted.

[0056] The semiconductor device 1 shown in FIG. 10 shows a case where the first region 101 and the second region 102 are formed at different depths. Such a first region 101 and second region 102 may be formed using different masks, or may be formed by changing the impurity introduction conditions for each other. In FIG. 10, the first region 101 is formed at a deeper position than the second region 102, but the second region 102 may be formed at a deeper position than the first region 101. Further, when the upper surface 11 of the semiconductor substrate 10 is used as a reference plane, the formation position of the first region 101 may be shallower than the formation position of the second region 102.

[0057] The semiconductor device 1 shown in FIG. 11 shows a case where the end of the first region 101 is in contact with the end of the second region 102. When impurities diffuse laterally by heat treatment after impurity introduction, the first region 101 and the second region 102 may come into contact with each other.

[0058] In the semiconductor device 1 according to the present embodiment, it is preferable that the first region 101 and the second region 102 are separated from each other. On the other hand, when the impurity concentration of the first region 101 and the impurity concentration of the second region 102 have a gradient, if the region showing the peak value of the impurity concentration of the first region 101 and the region showing the peak value of the impurity concentration of the second region 102 are separated from each other, the effect of the configuration of the semiconductor device 1 of Embodiment 2 can be obtained.

[0059] As described above, the invention made by the present inventors has been specifically described based on the embodiments. However, it goes without saying that the present disclosure is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

Description of Reference Numerals

[0060] 1, 2 Semiconductor device 10 Semiconductor substrate 11 Upper surface Below 12 30, 31 First element isolation insulating layer 40 Drain electrode layer 41, 51, 52 Conductive layer 50 Source electrode layer 60 Second element isolation insulating layer 70 Gate electrode layer 71 Gate insulating layer 100 First semiconductor region 101 First region 102 Second region 110 Embedded region 120 Second semiconductor region 121 Drift region 122 Drain region 123 Well region 130 Third semiconductor region 131 Source region 132 Contact region 133 Well region

Claims

1. A semiconductor substrate having an upper surface, A first semiconductor region formed in the semiconductor substrate, An embedded region formed in the semiconductor substrate or in the first semiconductor region, A second semiconductor region formed in the first semiconductor region and disposed on the embedded region, A third semiconductor region formed in the first semiconductor region and disposed on the embedded region, A drain region formed in the second semiconductor region, A source region formed in the third semiconductor region, A gate electrode layer formed on the upper surface of the semiconductor substrate, and comprising, The first semiconductor region, In a direction perpendicular to the upper surface of the semiconductor substrate, a first region formed between the third semiconductor region and the embedded region, In a direction perpendicular to the upper surface of the semiconductor substrate, a second region formed between the second semiconductor region and the embedded region, and having, The semiconductor substrate, the first semiconductor region, and the second semiconductor region each have a first conductivity type, The embedded region and the third semiconductor region each have a second conductivity type opposite to the first conductivity type, The impurity concentration of the first region and the impurity concentration of the second region are higher than the impurity concentration of the first semiconductor region, A semiconductor device.

2. The impurity concentration of the second region is less than or equal to the impurity concentration of the first region, The semiconductor device according to claim 1.

3. When the upper surface of the semiconductor substrate is used as a reference plane, the depth of the first region and the depth of the second region are different from each other, The semiconductor device according to claim 1.

4. When the upper surface of the semiconductor substrate is used as a reference plane, the formation position of the first region is shallower than the formation position of the second region, The semiconductor device according to claim 1.

5. The first region is separated from the second region in a direction along the upper surface of the semiconductor substrate, The semiconductor device according to claim 1.

6. The second semiconductor region has the drain region, a drift region, and a well region having the first conductivity type, The well region is disposed under the drain region, In a plan view, the well region is included in the first region, The impurity concentration of the drift region is lower than the impurity concentration of the well region, The impurity concentration of the drain region is higher than the impurity concentration of the well region, The semiconductor device according to claim 1.

7. In a plan view, an end portion of the first region facing the second region is located between an end portion of the gate electrode layer facing the drain region and the third semiconductor region. The semiconductor device according to claim 6.

8. In a plan view, an end portion of the second region facing the first region is located between the well region and an end portion of the gate electrode layer facing the drain region. The semiconductor device according to claim 6.

9. Furthermore, a first element isolation insulating layer formed within the second semiconductor region and on the upper surface of the semiconductor substrate, and a second element isolation insulating layer formed to penetrate the third semiconductor region, the first semiconductor region, and the buried region, are provided. When the upper surface of the semiconductor substrate is used as a reference plane, the depth of the second element isolation insulating layer is greater than the depth of the first element isolation insulating layer. The semiconductor device according to claim 6.

10. The first element isolation insulating layer is formed within the drift region. The semiconductor device according to claim 9.

11. The first region is in contact with a side surface of the second element isolation insulating layer. The semiconductor device according to claim 9.

12. A first distance between an end portion of the first region facing the second region and a side surface of the second element isolation insulating layer is equal to or less than a second distance between an end portion of the gate electrode layer facing the drain region and the side surface of the second element isolation insulating layer, and is equal to or greater than a third distance between an end portion of the third semiconductor region facing the second semiconductor region and the side surface of the second element isolation insulating layer. The semiconductor device according to claim 9.

13. A first distance between an end portion of the second region facing the first region and a side surface of the second element isolation insulating layer is equal to or less than a second distance between an end portion of the well region facing the third semiconductor region and the side surface of the second element isolation insulating layer, and is equal to or greater than a third distance between an end portion of the gate electrode layer facing the drain region and the side surface of the second element isolation insulating layer. The semiconductor device according to claim 9.

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