Device and method for supplying logic power supply voltage in mixed signal circuit

Abstract

To provide a power supply circuit that suppresses or avoids a reduction in logic power supply voltage even when a logic circuit for a mixed signal circuit consumes high power or high current.SOLUTION: The mixed signal circuit includes a logic circuit, an analog circuit, a logic power supply line 160, and first and second regulator circuits 500A, 500B. The analog circuit receives an analog power supply voltage AVDD. The logic power supply line is coupled to the logic circuit. The first regulator circuit includes an output PMOS transistor MP1 having a drain connected to the logic power supply line and a first pre-stage 510A that receives a first logic power supply voltage IOVCC and drives an output PMOS transistor. The second regulator circuit includes an output NMOS transistor MN3 having a source coupled to the logic power supply line and a second pre-stage 510B that receives the analog power supply voltage and drives an output NMOS transistor. The analog power supply voltage is higher than the first logic power supply voltage.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates generally to mixed-signal circuits, and more particularly, to an apparatus and method for supplying a power supply voltage to a logic circuit in a mixed-signal circuit.

Background Art

[0002] Mixed-signal circuits that include both analog and logic (or digital) circuits are widely used in electronic devices. A mixed-signal circuit may include a power supply circuit configured to generate a logic power supply voltage from an external power supply voltage received from an external power supply and supply the logic power supply voltage to the logic circuit. In implementations where the external power supply voltage is low, e.g., 1.8V or less, the power supply circuit may use a low dropout (LDO) regulator to generate the logic power supply voltage. However, when the external power supply voltage is low, an undesired drop in the logic power supply voltage may occur when the logic circuit consumes high power or high current. Therefore, there is a need for a technique that enables the power supply circuit to suppress or avoid a drop in the logic power supply voltage even when the logic circuit consumes high power or high current.

Summary of the Invention

[0003] This summary is provided to introduce a selection of concepts in a simplified form that are further described below. This summary is not necessarily intended to identify key features or essential features of the present disclosure. The present disclosure may include the following various aspects and embodiments.

[0004] In an exemplary embodiment, the present disclosure provides a mixed-signal circuit including a logic circuit, an analog circuit, a logic power line, a first regulator circuit, and a second regulator circuit. The analog circuit is configured to receive an analog power voltage. The logic power line is coupled to the logic circuit. The first regulator circuit includes an output p-channel metal-oxide-semiconductor (PMOS) transistor having a drain coupled to the logic power line, and a first stage configured to receive a first logic power voltage and drive the gate of the output PMOS transistor. The second regulator circuit includes an output n-channel metal-oxide-semiconductor (NMOS) transistor having a source coupled to the logic power line, and a second stage configured to receive the analog power voltage and drive the gate of the output NMOS transistor. The analog power voltage is higher than the first logic power voltage.

[0005] In other exemplary embodiments, the present disclosure provides a system including a power management circuit and a mixed-signal circuit. The power management circuit generates a first logic power voltage and an analog power voltage higher than the first logic power voltage. The mixed-signal circuit includes a logic circuit, an analog circuit, a logic power line, a first regulator circuit, and a second regulator circuit. The analog circuit is configured to receive the analog power voltage. The logic power line is coupled to the logic circuit. The first regulator circuit includes an output PMOS transistor having a drain coupled to the logic power line, and a first stage configured to receive the first logic power voltage and drive the gate of the output PMOS transistor. The second regulator circuit includes an output NMOS transistor having a source coupled to the logic power line, and a second stage configured to receive the analog power voltage and drive the gate of the output NMOS transistor.

[0006] In yet another exemplary embodiment, the present disclosure provides a method. The method includes supplying a first logic supply voltage to a first pre-stage of a first regulator circuit. The first regulator circuit includes an output p-channel metal-oxide-semiconductor (PMOS) transistor having a drain coupled to a logic supply line coupled to a logic circuit. The method includes driving, by the first pre-stage, a gate of the output PMOS transistor to drive the logic supply line to the output PMOS transistor. The method further includes supplying an analog supply voltage to an analog circuit. The analog supply voltage is higher than the first logic supply voltage. The method further includes supplying the analog supply voltage to a second pre-stage of a second regulator circuit. The second regulator circuit includes an output n-channel metal-oxide-semiconductor (NMOS) transistor having a source coupled to the logic supply line. The method further includes driving, by the second pre-stage, a gate of the output NMOS transistor to drive the logic supply line to the output NMOS transistor.

[0007] Other features and aspects are described in more detail below with reference to the accompanying drawings.

Brief Description of the Drawings

[0008]

Figure 1

[0009]

Figure 2

[0010]

Figure 3

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Figure 4

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Figure 5

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Figure 6

[0014]

Figure 7A

[0015]

Figure 7B

[0016]

Figure 8

[0017]

Figure 9

[0018]

Figure 10

[0019] For ease of understanding, wherever possible, the same reference numerals are used to denote the same elements common to the drawings. It is contemplated that elements disclosed in one embodiment may be used in other embodiments without particular recitation. Subscripts may be attached to the reference numerals to distinguish identical elements from one another. The drawings referred to herein are not to be understood as being drawn to scale unless otherwise noted. Also, the drawings are often simplified, and details or components may be omitted for clarity of presentation and explanation. The drawings and discussion are useful for explaining the principles discussed below.

Best Mode for Carrying Out the Invention

[0020] The following detailed description is, in essence, merely exemplary and is not intended to limit the disclosure, its application, or its uses. Further, there is no intention to be bound by any theory, whether explicit or implicit, presented in the foregoing background, summary, brief description of the drawings, or the following detailed description.

[0021] In the following detailed description of the embodiments, numerous specific details are presented to provide a deeper understanding of the disclosed technology. However, it will be apparent to those skilled in the art that the disclosed technology may be practiced without these specific details. In other instances, well-known configurations are not described in detail to avoid unnecessarily complicating the description.

[0022] As used herein, the term "coupled" means directly connected or connected through one or more intervening components or circuits. Further, throughout the application, ordinal numbers (e.g., first, second, third, etc.) may be used as adjectives of elements (i.e., any noun in the application). The use of ordinal numbers is not for implying or generating a specific ordering of any elements, nor for limiting any element to only a single element, unless specified and disclosed by the use of terms such as "before", "after", "single", and other similar terms. Rather, the use of ordinal numbers is for distinguishing elements. For example, the first element is different from the second element, the first element may include more than one element, and may follow (or precede) the second element in the ordering of elements.

[0023] Mixed-signal circuits that include an analog circuit and a logic (or digital) circuit are widely used in electronic devices. An example of a mixed-signal circuit is a display driver configured to drive a display panel such as, for example, a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, or a micro light emitting diode (μLED) display panel. The display driver may include a data driver circuit that is an analog circuit for driving the data lines (also referred to as source lines) of the display panel, and various logic circuits such as a timing controller, an image processing circuit.

[0024] A mixed-signal circuit may include, inside thereof, a power supply circuit configured to generate a logic power supply voltage from an external power supply voltage received from an external power supply and supply the logic power supply voltage to a logic circuit integrated in the mixed-signal circuit. This is because a significant voltage drop may occur in the power supply line for supplying the logic power supply voltage from the external power supply to the mixed-signal circuit if the logic power supply voltage is directly supplied from the external power supply to the logic circuit of the mixed-signal circuit. When a voltage drop occurs in the power supply line, it may become difficult to adjust the logic power supply voltage supplied to the logic circuit to a desired voltage range.

[0025] Due to specifications such as the recent reduction in power consumption and the miniaturization of transistor sizes in integrated circuits, the external power supply voltage supplied to the mixed-signal circuit to generate the logic power supply voltage may be as low as 1.8 V or less. When the external power supply voltage is low, the current driving ability of the power supply circuit in the mixed-signal circuit may become insufficient, which can cause an undesired drop in the logic power supply voltage when the logic circuit consumes high power or high current. Therefore, there is a need to provide a technique for suppressing or avoiding a drop in the logic power supply voltage even when the external power supply voltage supplied to the mixed-signal circuit is low.

[0026] The present disclosure presents various embodiments for increasing the current driving ability of a power supply circuit that supplies power to a logic circuit in a mixed-signal circuit even when the external power supply voltage supplied to the mixed-signal circuit to generate the logic power supply voltage is low. In one embodiment, the mixed-signal circuit includes a logic circuit, an analog circuit, a logic power supply line coupled to the logic circuit, a first regulator circuit, and a second regulator circuit. The analog circuit is configured to receive an analog power supply voltage. The first regulator circuit includes an output p-channel metal-oxide-semiconductor (PMOS) transistor having a drain coupled to the logic power supply line, and a first stage configured to receive a first logic power supply voltage and drive the gate of the output PMOS transistor. The second regulator circuit includes an output n-channel metal-oxide-semiconductor (NMOS) transistor having a source coupled to the logic power supply line, and a second stage configured to receive the analog power supply voltage and drive the gate of the output NMOS transistor. The analog power supply voltage is higher than the first logic power supply voltage. Using the second regulator circuit makes it easy to provide sufficient current driving ability to drive the logic power supply line, thereby effectively suppressing or avoiding a drop in the logic power supply voltage. Detailed embodiments of the present disclosure will be described below.

[0027] FIG. 1 is a block diagram showing a configuration example of a system including a mixed-signal circuit 1000 and a power management circuit 2000 according to one or more embodiments. The power management circuit 2000 is configured to supply a logic power supply voltage IOVCC and an analog power supply voltage AVDD to the mixed-signal circuit 1000. The analog power supply voltage AVDD is higher than the logic power supply voltage IOVCC. In one implementation, the standard value of the logic power supply voltage IOVCC is 1.8V, and the standard value of the analog power supply voltage AVDD is 5.0V. In other implementations, the logic power supply voltage IOVCC and the analog power supply voltage AVDD may have different voltage levels. The power management circuit 2000 may be configured as a power management integrated circuit (PMIC) that monolithically integrates a circuit section for generating the logic power supply voltage IOVCC and a circuit section for generating the analog power supply voltage AVDD on a single semiconductor chip.

[0028] The mixed-signal circuit 1000 is configured to receive the logic power supply voltage IOVCC at the IOVCC terminal 110 and the analog power supply voltage AVDD at the AVDD terminal 120. In the illustrated embodiment, the mixed-signal circuit 1000 includes an IOVCC line 140, an AVDD line 150, a logic power supply line 160, a power supply circuit 200, an analog circuit 300, and a logic circuit 400. In one implementation, the mixed-signal circuit 1000 may be configured as a mixed-signal integrated circuit (IC) that integrates the IOVCC line 140, the AVDD line 150, the logic power supply line 160, the power supply circuit 200, the analog circuit 300, and the logic circuit 400 on a single semiconductor chip. The IOVCC line 140 is configured to supply the logic power supply voltage IOVCC from the IOVCC terminal 110 to the power supply circuit 200, and the AVDD line 150 is configured to supply the analog power supply voltage AVDD to the analog circuit 300.

[0029] According to some embodiments, the mixed signal circuit 1000 may be configured as a display driver configured to drive a display panel such as a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, a micro light emitting diode (μLED) display panel, or other types of display panels. In such embodiments, the analog circuit 300 may include a data driver circuit configured to drive the data lines (also referred to as source lines) of the display panel, and the logic circuit 400 may include an image processing circuit configured to supply the processed image data to the data driver circuit and a timing controller configured to control the operation timing of the display driver.

[0030] The power supply circuit 200 is configured to generate an internal logic power supply voltage VDD from a logic power supply voltage IOVCC and supply the internal logic power supply voltage VDD to the logic circuit 400 via a logic power supply line 160. The logic power supply line 160 may be coupled to a VDD terminal 130 that may be coupled to system ground via an external power supply line capacitor 2100. The internal logic power supply voltage VDD is lower than the logic power supply voltage IOVCC. In one implementation, the standard value of the internal logic power supply voltage VDD is 1.00V. The standard value of the internal logic power supply voltage VDD may be a different value. The power supply circuit 200 is configured to adjust the internal logic power supply voltage VDD so that the internal logic power supply voltage VDD falls within a specified power supply range defined in the vicinity of the standard value of the internal logic power supply voltage VDD. In one implementation, the power supply circuit 200 may be configured to adjust the internal logic power supply voltage VDD to fall within a voltage range, for example, between the standard value minus 0.10V and the standard value plus 0.10V.

[0031] In one or more embodiments, the power supply circuit 200 includes a first regulator circuit 500A and a second regulator circuit 500B whose outputs are commonly coupled to the logic power supply line 160. The first regulator circuit 500A and the second regulator circuit 500B are used to drive the logic power supply line 160.

[0032] The first regulator circuit 500A includes a first pre-stage 510A, an output PMOS transistor MP1, and an output NMOS transistor MN1. The output PMOS transistor MP1 and the output NMOS transistor MN1 constitute an output stage that drives the output of the first regulator circuit 500A. The output PMOS transistor MP1 has a source coupled to the IOVCC line 140 and a drain coupled to the output of the first regulator circuit 500A. The output NMOS transistor MN1 has a source coupled to ground and a drain coupled to the output of the first regulator circuit 500A. The output PMOS transistor MP1 is a pull-up transistor used to pull up the output of the first regulator circuit 500A, and the output NMOS transistor MN1 is a pull-down transistor used to pull down the output of the first regulator circuit 500A. The output of the first regulator circuit 500A is coupled to the logic power supply line 160.

[0033] The first pre-stage 510A is configured to receive the logic power supply voltage IOVCC and drive the gates of the output PMOS transistor MP1 and the output NMOS transistor MN1. In one implementation, the first pre-stage 510A receives a reference voltage V REF_A at its input and may be configured to adjust the gate voltages of the output PMOS transistor MP1 and the output NMOS transistor MN1 to reduce the difference between the reference voltage V REF_A and the output voltage VDD_A of the first regulator circuit 500A. In one implementation, the reference voltage V REF_A may be set slightly lower than the upper limit of the specified voltage range of the internal logic power supply voltage VDD. For example, in an embodiment where the upper limit of the specified voltage range of the internal logic power supply voltage VDD is 1.10V, the reference voltage V REF_A may be set to 1.09V.

[0034] The second regulator circuit 500B includes a second pre-stage 510B and a pair of output NMOS transistors MN2 and MN3. The output NMOS transistors MN2 and MN3 constitute an output stage that drives the output of the second regulator circuit 500B. The output NMOS transistor MN3 has a source coupled to the output of the second regulator circuit 500B and a drain coupled to the IOVCC line 140. The output NMOS transistor MN2 has a source coupled to ground and a drain coupled to the output of the second regulator circuit 500B. The output NMOS transistor MN3 is a pull-up transistor used to pull up the output of the second regulator circuit 500B, and the output NMOS transistor MN2 is a pull-down transistor used to pull down the output of the second regulator circuit 500B.

[0035] The second pre-stage 510B is configured to receive the analog power supply voltage AVDD and drive the gates of the output NMOS transistors MN2 and MN3. As will be described in detail later, powering the second pre-stage 510B with the analog power supply voltage AVDD, which is higher than the logic power supply voltage IOVCC, can effectively improve the current driving ability of the second regulator circuit 500B. In one implementation, the second pre-stage 510B receives a reference voltage V REF_B at its input and may be configured to adjust the gate voltages of the output NMOS transistors MN2 and MN3 so as to reduce the difference between the reference voltage V REF_B and the output voltage VDD_B of the second regulator circuit 500B.

[0036] FIG. 2 illustrates the source-gate voltage of the output PMOS transistor MP1 of the first regulator circuit 500A and the gate-source voltage of the output NMOS transistor MN3 of the second regulator circuit 500B according to one or more embodiments. Since the output PMOS transistor MP1 of the first regulator circuit 500A receives the logic power supply voltage IOVCC at its source, the maximum value of the gate-source voltage VGS_A of the output PMOS transistor MP1 is IOVCC. This means that when the logic power supply voltage IOVCC is at a low voltage level, for example, 1.8V, the first regulator circuit 500A may not be able to provide sufficient current driving ability to maintain the internal logic power supply voltage VDD within the specified voltage range (for example, 1.0 ± 0.1V).

[0037] The second regulator circuit 500B is configured to compensate for the potential lack of current driving ability of the first regulator circuit 500A. Since the second pre-stage 510 is powered by the analog power supply voltage AVDD, and thus the maximum value of the gate-source voltage VGS_B of the output NMOS transistor MN3 is AVDD - VDD, the second regulator circuit 500B can provide sufficient current driving ability even when the logic power supply voltage IOVCC is at a low voltage level. Note that in a mixed-signal circuit, the analog power supply voltage is typically much higher than the logic power supply voltage. In an implementation where the standard values of the analog power supply voltage AVDD and the internal logic power supply voltage VDD are 5.0V and 1.0V respectively, the gate-source voltage VGS_B of the output NMOS transistor MN3 is approximately 4.0V, which makes it possible to improve the current driving ability of the second regulator circuit 500B.

[0038] Returning to FIG. 1, when the second pre-stage 510B is powered by the analog power supply voltage AVDD that is higher than the logic power supply voltage IOVCC, the power consumption of the power supply circuit 200 may undesirably increase. To reduce the power consumption of the power supply circuit 200, in one or more embodiments, the first regulator circuit 500A may operate the second regulator circuit 500B only when, for example, the internal logic power supply voltage VDD cannot be maintained alone due to an increase in the power consumption of the logic circuit 400. This is achieved by setting the reference voltage V REF_B supplied to the second pre-stage 510B to be slightly lower than the reference voltage V REF_A supplied to the first pre-stage 510A of the first regulator circuit 500A, so that the second regulator circuit 500B operates only when the internal logic power supply voltage VDD is lower than the reference voltage V REF_B . In this case, when the internal logic power supply voltage VDD is maintained higher than the reference voltage V REF_A by the first regulator circuit 500A powered by the logic power supply voltage IOVCC, the second regulator circuit 500B does not drive the internal logic power supply voltage VDD. For example, in an embodiment where the reference voltage VREF_A is 1.090V, the reference voltage V REF_B may be set to 1.085V. To improve the response to the voltage drop in the internal logic power supply voltage VDD, in one or more embodiments, the difference between the reference voltage V REF_A and the reference voltage V REF_B may be 0.01V or less.

[0039] FIG. 3 illustrates a circuit configuration example of a first pre-stage 510A of a first regulator circuit 500A according to one or more embodiments. In the illustrated embodiment, the gate of an output NMOS transistor MN1 operating as a pull-down transistor is coupled to a fixed bias voltage IBIN3, and the first pre-stage 510A is configured to drive the gate of an output PMOS transistor MP1. It should be noted that the circuit configuration illustrated in FIG. 3 is merely an example, and the first pre-stage 510A may be configured differently from that shown in FIG. 3. In the illustrated embodiment, the first pre-stage 510A includes an input operating stage 520 and current mirrors 530 and 540.

[0040] The input operating stage 520 is configured to draw a pair of currents from the current mirror 530 depending on whether the output voltage VDD_A generated at the output 504 of the first regulator circuit 500A is higher or lower than a reference voltage V REF_A In the illustrated embodiment, the input operating stage 520 includes NMOS transistors MN11, MN12, and MN13. The NMOS transistor MN11 has a gate coupled to the input 502 of the first regulator circuit 500A and receiving the reference voltage V REF_A The NMOS transistor MN12 has a gate coupled to the output 504 of the first regulator circuit 500A. The sources of the NMOS transistors MN11 and MN12 are commonly coupled to the drain of an NMOS transistor MN13 having a source coupled to a ground line 514. The NMOS transistor MN13 has a gate coupled to a fixed bias voltage IBIN1, and thus operates as a constant current source configured to draw a constant current from the common coupled source of the NMOS transistors MN11 and MN12.

[0041] Current mirrors 530 and 540 are configured to operate together as an active load that generates the gate voltage of PMOS transistor MP1 in response to a pair of currents drawn from the input operation stage 520. Current mirror 530 includes PMOS transistors MP21, MP22, MP23, and MP24. The sources of PMOS transistors MP21 and 22 are commonly coupled to an IOVCC line 512 to which a logic power supply voltage IOVCC is supplied. The drain of PMOS transistor MP21 is coupled to the source of PMOS transistor MP23, and the drain of PMOS transistor MP22 is coupled to the source of PMOS transistor MP24. The gates of PMOS transistors MP21, MP22, MP23, and MP24 are commonly coupled to the drain of PMOS transistor MP23. Current mirror 540 includes NMOS transistors MN21, MN22, MN23, and MN24. The sources of NMOS transistors MN21 and MN22 are commonly coupled to a ground line 514. The drain of NMOS transistor MN21 is coupled to the source of NMOS transistor MN23, and the drain of NMOS transistor MN22 is coupled to the source of NMOS transistor MN24. The gates of NMOS transistors MN21, MN22, MN23, and MN24 are commonly coupled to a fixed bias voltage IBIN2. The gate of PMOS transistor MP1 is coupled to a node that couples the drain of PMOS transistor MP24 of current mirror 530 and the drain of NMOS transistor MN24 of current mirror 540.

[0042] As configured as shown in FIG. 3, the first pre-stage 510A drives the gate of PMOS transistor MP1 so that the output voltage VDD_A generated at the output 504 is adjusted to the reference voltage V REF_A thereby.

[0043] FIG. 4 illustrates a circuit configuration example of a second pre-stage 510B of a second regulator circuit 500B according to one or more embodiments. In the illustrated embodiment, the gate of an output NMOS transistor MN2 operating as a pull-down transistor is coupled to a fixed bias voltage IBIN5, and the second pre-stage 510B is configured to drive the gate of an output NMOS transistor MN3 operating as a pull-up transistor. Note that the output NMOS transistor MN3 has a drain coupled to an IOVCC line 566 to receive a logic supply voltage IOVCC. It should be understood that the circuit configuration illustrated in FIG. 4 is merely an example, and the second pre-stage 510B may have a configuration different from that illustrated in FIG. 4. In the illustrated embodiment, the second pre-stage 510B includes an input operating stage 550, current mirrors 560 and 570, floating current sources 580 and 590, a PMOS transistor MP43, and an NMOS transistor MN43.

[0044] The input operating stage 550 is configured to supply a pair of currents to the current mirror 570 depending on whether an output voltage VDD_B generated at an output 554 of the second regulator circuit 500B is higher or lower than a reference voltage V REF_B In the illustrated embodiment, the input operating stage 550 includes PMOS transistors MP11, MP12, and MP13. The PMOS transistor MP11 has a gate coupled to an input 552 of the second regulator circuit 500B to receive the reference voltage V REF_B The PMOS transistor MP12 has a gate coupled to the output 554 of the second regulator circuit 500B. The sources of the PMOS transistors MP11 and MP12 are commonly coupled to the drain of the PMOS transistor MP13, and the PMOS transistor MP13 has a source coupled to an AVDD line 562 to which an analog supply voltage AVDD is supplied. The PMOS transistor MP13 has a gate coupled to a fixed bias voltage IBIP4, and thus operates as a constant current source configured to supply a constant current to the common source of the PMOS transistors MP11 and MP12.

[0045] Current mirrors 560 and 570 and floating current sources 580 and 590 are collectively configured to operate as an active load configured to generate the gate voltages of PMOS transistor MP43 and NMOS transistor MN43. Current mirror 560 includes PMOS transistors MP31, MP32, MP33, and MP34. The sources of PMOS transistors MP31 and MP32 are commonly coupled to AVDD line 562. The drain of PMOS transistor MP31 is coupled to the source of PMOS transistor MP33, and the drain of PMOS transistor MP32 is coupled to the source of PMOS transistor MP34. The gates of PMOS transistors MP31, MP32, MP33, and MP34 are commonly coupled to the drain of PMOS transistor MP33.

[0046] Current mirror 570 includes NMOS transistors MN31, MN32, MN33, and MN34. The sources of NMOS transistors MN31 and MN32 are commonly coupled to ground line 564. The drain of NMOS transistor MN31 is coupled to the source of NMOS transistor MN33, and the drain of NMOS transistor MN32 is coupled to the source of NMOS transistor MN34. The gates of NMOS transistors MN31, MN32, MN33, and MN34 are commonly coupled to the drain of NMOS transistor MN33.

[0047] The floating current source 580 includes an NMOS transistor MN41 and a PMOS transistor MP41. The NMOS transistor MN41 has a gate coupled to a fixed bias voltage IBIN4, a source coupled to the drain of the PMOS transistor MP41, and a drain coupled to the source of the PMOS transistor MP41. The PMOS transistor MP41 has a gate coupled to a fixed bias voltage IBIP5. The drain of the NMOS transistor MN41 and the source of the PMOS transistor MP41 are coupled to the drain of the PMOS transistor MP33 of the current mirror 560. The source of the NMOS transistor MN41 and the drain of the PMOS transistor MP41 are coupled to the drain of the NMOS transistor MN33 of the current mirror 570.

[0048] The floating current source 590 includes an NMOS transistor MN42 and a PMOS transistor MP42. The NMOS transistor MN42 has a gate coupled to a fixed bias voltage IBIN4, a source coupled to the drain of the PMOS transistor MP42, and a drain coupled to the source of the PMOS transistor MP42. The PMOS transistor MP42 has a gate coupled to a fixed bias voltage IBIP5. The drain of the NMOS transistor MN42 and the source of the PMOS transistor MP42 are coupled to the drain of the PMOS transistor MP34 of the current mirror 560. The source of the NMOS transistor MN42 and the drain of the PMOS transistor MP42 are coupled to the drain of the NMOS transistor MN34 of the current mirror 570.

[0049] The PMOS transistor MP43 has a source coupled to the AVDD line 562, a gate coupled to the drain of the PMOS transistor MP34 of the current mirror 560, and a drain coupled to the gate of the output NMOS transistor MN3. The NMOS transistor MN43 has a source coupled to the ground line 564, a gate coupled to the drain of the NMOS transistor MN34 of the current mirror 570, and a drain coupled to the gate of the output NMOS transistor MN3.

[0050] As configured as shown in FIG. 4, the second pre-stage 510B drives the gate of the NMOS transistor MN3 so that the output voltage VDD_B generated at the output 554 is adjusted to the reference voltage V REF_B thereby.

[0051] FIG. 5 illustrates an example of a timing diagram corresponding to the operation of the system shown in FIG. 1 according to one or more embodiments. Note that the horizontal axis in FIG. 5 represents time t. Initially (e.g., t < t1), the mixed signal circuit 1000 is in the "deep standby" state. Before time t1, the power management circuit 2000 is not operating and is not supplying the logic power supply voltage IOVCC nor the analog power supply voltage AVDD. At time t1, the power management circuit 2000 begins to drive the logic power supply voltage IOVCC to a specified level (e.g., 1.8V) to supply the logic power supply voltage IOVCC to the mixed signal circuit 1000.

[0052] At time t2, the mixed signal circuit 1000 exits the deep standby state and enters the "sleptin" state to execute the startup sequence. In response to the mixed signal circuit 1000 entering the sleptin state, the first regulator circuit 500A of the power supply circuit 200 is activated, and the internal logic power supply voltage VDD is adjusted to the reference voltage V REF_A, for example, it starts to be driven at 1.09V. Note that while the mixed-signal circuit 1000 is in the sleep-in state, the second regulator circuit 500B remains inactive. During the period 600 when the mixed-signal circuit 1000 is in the sleep-in state, the first regulator circuit 500A of the power supply circuit 200 continues to be activated, and the internal logic power supply voltage VDD is driven only by the first regulator circuit 500A.

[0053] In the illustrated embodiment, after the mixed-signal circuit 1000 enters the sleep-in state at time t2, the power management circuit 2000 starts to drive the analog power supply voltage AVDD to a specified level (e.g., 5.0V) at time t3. In other embodiments, the power management circuit 2000 starts to drive the analog power supply voltage AVDD after starting to drive the internal logic power supply voltage VDD before the mixed-signal circuit 1000 enters the sleep-in state.

[0054] At time t4, the mixed-signal circuit 1000 enters the "sleep-out" state in which both the analog circuit 300 and the logic circuit 400 operate normally. In response to the mixed-signal circuit 1000 entering the sleep-out state, the second regulator circuit 500B of the power supply circuit 200 is activated, and the internal logic power supply voltage VDD is set to the reference voltage V REF_B , for example, it is ready to be driven at 1.085V. The first regulator circuit 500A and the second regulator circuit 500B are both activated during the period 602 when the mixed-signal circuit 1000 is in the sleep-out state. However, since the reference voltage V supplied to the second regulator circuit 500B is slightly lower than the reference voltage V REF_B supplied to the first regulator circuit 500A, as long as the first regulator circuit 500A can maintain the internal logic power supply voltage VDD, the first regulator circuit 500A mainly drives the internal logic power supply voltage VDD. On the other hand, when the power or current consumption of the logic circuit 400 increases during normal operation, there may potentially be a drop in the internal logic power supply voltage VDD during the period 602. When the internal logic power supply voltage VDD reaches the reference voltage V REF_A ​REF_B When it drops lower than that, the second regulator circuit 500B drives the internal logic power supply voltage VDD to realize recovery from the drop of the internal logic power supply voltage VDD.

[0055] At time t5, the mixed signal circuit 1000 enters the sleep-in state to execute the shutdown sequence. In response to the mixed signal circuit 1000 entering the sleep-in state, the second regulator circuit 500B of the analog circuit 300 and the power supply circuit 200 is deactivated, and the second regulator circuit 500B stops driving the internal logic power supply voltage VDD. Note that the first regulator circuit 500A remains activated to execute the shutdown sequence while the mixed signal circuit 1000 is in the sleep-in state. After the mixed signal circuit 1000 enters the sleep-in state at time t5, the power management circuit 2000 stops driving the analog power supply voltage AVDD at time t6.

[0056] At time t7, the mixed signal circuit 1000 enters the deep standby state. In response to the mixed signal circuit 1000 entering the deep standby state, the first regulator circuit 500A of the power supply circuit 200 stops driving the internal logic power supply voltage VDD. The power management circuit 2000 may then stop driving the logic power supply voltage IOVCC at time t8. In other embodiments, the power management circuit 2000 may stop driving the analog power supply voltage AVDD after the mixed signal circuit 1000 enters the deep standby state.

[0057] FIG. 6 is a block diagram illustrating a system including a mixed signal circuit 3000 and a power management circuit 4000 according to one or more embodiments. In the illustrated embodiment, the power management circuit 4000 is configured to supply an external logic power voltage Ext_VDD to the mixed signal circuit 3000 in addition to a logic power voltage IOVCC and an analog power voltage AVDD. The external logic power voltage Ext_VDD is lower than the logic power voltage IOVCC, while the analog power voltage AVDD is higher than both the logic power voltage IOVCC and the external logic power voltage Ext_VDD. The power management circuit 4000 may be configured as a power management integrated circuit (PMIC) that monolithically integrates a circuit section for generating the logic power voltage IOVCC, a circuit section for generating the analog power voltage AVDD, and a circuit section for generating the external logic power voltage Ext_VDD on a single semiconductor chip.

[0058] Depending on the implementation, the logic power voltage IOVCC has a voltage level that matches the default standard of the display driver, and the external logic power voltage Ext_VDD has a voltage level arbitrarily determined by the system vendor and / or user. By using an external logic power voltage Ext_VDD that is lower than the logic power voltage IOVCC, it may be easier to reduce power consumption when supplying the internal logic power voltage VDD to the logic circuit 400. Embodiments for efficiently using the external logic power voltage Ext_VDD to supply the internal logic power voltage VDD to the logic circuit 400 will be described below.

[0059] The mixed-signal circuit 3000 is configured in the same manner as the mixed-signal circuit 1000 illustrated in FIG. 1, except that the mixed-signal circuit 3000 receives an external logic power supply voltage Ext_VDD at the Ext_VDD terminal 170 and supplies an internal logic power supply voltage VDD to the logic circuit 400 by the power supply circuit 3200 instead of the power supply circuit 200. The external logic power supply voltage Ext_VDD is supplied to the power supply circuit 3200 via the Ext_VDD line 180 coupled to the Ext_VDD terminal 170. In one implementation, the mixed-signal circuit 3000 may be configured as a mixed-signal integrated circuit (IC) that monolithically integrates the IOVCC line 140, the AVDD line 150, the logic power supply line 160, the Ext_VDD line 180, the power supply circuit 3200, the analog circuit 300, and the logic circuit 400 on a single semiconductor chip. The IOVCC line 140 is configured to supply the logic power supply voltage IOVCC from the IOVCC terminal 110 to the power supply circuit 3200, and the AVDD line 150 is configured to supply the analog power supply voltage AVDD to the analog circuit 300 and the power supply circuit 3200. Depending on the embodiment, the mixed-signal circuit 3000 may be configured as a display driver configured to drive a display panel such as an LCD panel, an OLED display panel, a μLED display panel, etc., in the same manner as the mixed-signal circuit 1000.

[0060] The power supply circuit 3200 is configured to generate an internal logic power supply voltage VDD from the logic power supply voltage IOVCC, the analog power supply voltage AVDD, and the external logic power supply voltage Ext_VDD, and supply the internal logic power supply voltage VDD to the logic circuit 400 via the logic power supply line 160. The power supply circuit 3200 is configured to adjust the internal logic power supply voltage VDD so that the internal logic power supply voltage VDD falls within a specified power supply range defined in the vicinity of the standard value of the internal logic power supply voltage VDD. In one implementation, the power supply circuit 3200 may be configured to adjust the internal logic power supply voltage VDD so that it falls within a voltage range between the standard value minus 0.10V and the standard value plus 0.10V.

[0061] In the illustrated embodiment, the power supply circuit 3200 includes the first regulator circuit 500A described in relation to FIG. 1, and further includes a second regulator circuit 500C instead of the second regulator circuit 500B illustrated in FIG. 1. The outputs of the first regulator circuit 500A and the second regulator circuit 500C are commonly coupled to the logic power line 160, and the first regulator circuit 500A and the second regulator circuit 500C are used to drive the logic power line 160.

[0062] In the embodiment illustrated in FIG. 6, the second regulator circuit 500C includes a second pre-stage 510C and a pair of output NMOS transistors MN5, MN6. The second pre-stage 510C is configured to receive the analog power supply voltage AVDD and drive the gates of the output NMOS transistors MN5 and MN6. The output NMOS transistors MN5 and MN6 constitute an output stage for driving the output of the second regulator circuit 500C. The output NMOS transistor MN5 has a source coupled to the output of the second regulator circuit 500C and a drain coupled to the Ext_VDD line 180. The output NMOS transistor MN6 has a source coupled to ground and a drain coupled to the output of the second regulator circuit 500C. The output NMOS transistor MN5 is a pull-up transistor used to pull up the output of the second regulator circuit 500C, and the output NMOS transistor MN6 is a pull-down transistor used to pull up the output of the second regulator circuit 500C.

[0063] The second pre-stage 510C is powered by the analog power supply voltage AVDD. Therefore, since the maximum gate-source voltage of the output NMOS transistor MN5 is AVDD - VDD, the second regulator circuit 500C is configured to provide sufficient current driving capability even when the external logic power supply voltage Ext_VDD is at a low voltage level. Note that the discussion regarding the gate-source voltage of the output NMOS transistor MN3 of the second regulator circuit 500B described in relation to FIG. 2 also applies to the gate-source voltage of the output NMOS transistor MN5 of the second regulator circuit 500C. In one implementation, the second pre-stage 510C receives the reference voltage V REF_C at its input and is configured to adjust the gate voltages of the output NMOS transistor MN5 and the output NMOS transistor MN6 so as to reduce the difference between the reference voltage V REF_C and the output voltage of the second regulator circuit 500C.

[0064] In one or more embodiments, during normal operation, the second regulator circuit 500C may be configured to mainly drive the internal logic power supply voltage VDD. On the other hand, when there is a mixed-signal circuit 3000 in a sleep-in state where the logic power supply voltage IOVCC is available but the analog power supply voltage AVDD may not be available, the first regulator circuit 500A may be configured to mainly drive the internal logic power supply voltage VDD. This can be achieved by setting the reference voltage V REF_A supplied to the first pre-stage 510A to be slightly lower than the reference voltage V REF_C supplied to the second pre-stage 510C of the second regulator circuit 500C. For example, in an embodiment where the reference voltage V REF_C is 1.090V, the reference voltage V REF_A may be 1.085V. In one or more embodiments, the reference voltage V REF_C and the reference voltage V REF_AThe difference is 0.01 V or less. Since the pull-up transistor of the second regulator circuit 500C, i.e., the output NMOS transistor MN5, uses an external power supply voltage Ext_VDD that is lower than the logic power supply voltage IOVCC to maintain the internal logic power supply voltage VDD, using the second regulator circuit 500C mainly to drive the internal logic power supply voltage VDD during normal operation can be advantageous for reducing the power consumption of the power supply circuit 3200.

[0065] The circuit configuration shown in FIG. 6 may effectively improve the availability of the external logic power supply voltage Ext_VDD, as described below with reference to FIGS. 7A and 7B. FIG. 7A illustrates an example of a system configuration in which a power management circuit 6000 directly supplies the external logic power supply voltage Ext_VDD to the logic power supply line 160 of a mixed signal circuit 5000 via a power supply line 6100. In this system configuration, the external logic power supply voltage Ext_VDD is required to be within the specified voltage range of the internal logic power supply voltage VDD. For example, in an implementation where the specified voltage range of the internal logic power supply voltage VDD is 1.00 ± 0.10 V, the external logic power supply voltage Ext_VDD is required to be lower than 1.10 V. On the other hand, when supplying the external logic power supply voltage Ext_VDD from the power management circuit 6000 to the mixed signal circuit 5000 via the power supply line 6100, a significant voltage drop may occur in the power supply line 6100. Since the voltage drop in the power supply line 6100 depends on the current consumption of the logic circuit 400, it becomes difficult to appropriately adjust the external logic power supply voltage Ext_VDD so that the internal logic power supply voltage VDD reliably supplied to the logic circuit 400 falls within the specified voltage range. In contrast, as shown in FIG. 7B, by using a second regulator circuit 500C to supply the internal logic power supply voltage VDD to the logic circuit 400, the adjustment of the external logic power supply voltage Ext_VDD becomes effectively easier. This is because the internal logic power supply voltage VDD supplied to the logic circuit 400 is not affected by the voltage drop in the power supply line 4100 that supplies the external logic power supply voltage Ext_VDD from the power management circuit 4000 to the mixed signal circuit 3000.

[0066] FIG. 8 illustrates an example of a timing diagram corresponding to the operation of the system shown in FIG. 6 according to one or more embodiments. The operation of the system shown in FIG. 6 is the same as the operation of the system shown in FIG. 1, except that when the mixed signal circuit 3000 is in the sleep-out state, the second regulator circuit 500C (instead of the first regulator circuit 500A) mainly drives the internal logic power supply voltage VDD.

[0067] Initially (e.g., t < t 11 ), the mixed signal circuit 3000 is in the "deep standby" state. Before time t 11 , the power management circuit 4000 is not operating and does not supply any of the logic power supply voltage IOVCC, the analog power supply voltage AVDD, and the external logic power supply voltage Ext_VDD. At time t 11 , the power management circuit 4000 starts driving the logic power supply voltage IOVCC and the external logic power supply voltage Ext_VDD to supply them to the mixed signal circuit 3000.

[0068] At time t 12 , the mixed signal circuit 3000 exits the deep standby state and enters the "sleep in" state to execute the startup sequence. In response to the mixed signal circuit 3000 entering the sleep in state, the first regulator circuit 500A of the power supply circuit 3200 is activated and starts driving the internal logic power supply voltage VDD to the reference voltage V REF_A , for example, 1.085V. Thereby, the logic circuit 400 becomes capable of executing the startup sequence. It should be noted that the second regulator circuit 500C and the analog circuit 300 remain inactive while the mixed signal circuit 3000 is in the sleep in state. During the period 610 when the mixed signal circuit 3000 is in the sleep in state, the first regulator circuit 500A of the power supply circuit 3200 remains activated, and the internal logic power supply voltage VDD is driven only by the first regulator circuit 500A.

[0069] In the illustrated embodiment, after the mixed signal circuit 3000 enters the sleep in state at time t 12 , the power management circuit 4000 is at time t 13The analog power supply voltage AVDD starts to be driven to a specified level (e.g., 5.0V). In other embodiments, after the mixed signal circuit 3000 starts driving the internal logic power supply voltage VDD, before entering the sleep-in state, the power management circuit 4000 starts driving the analog power supply voltage AVDD to the specified level.

[0070] Time t 14 At this time, the mixed signal circuit 3000 enters the "sleep-out" state in which both the analog circuit 300 and the logic circuit 400 operate normally. In response to the mixed signal circuit 3000 entering the sleep-out state, the second regulator circuit 500C of the power supply circuit 3200 starts driving the internal logic power supply voltage VDD to the reference voltage V REF_C , for example, 1.09V. During the period 612 when the mixed signal circuit 3000 is in the sleep-out state, both the first regulator circuit 500A and the second regulator circuit 500C remain activated to drive the internal logic power supply voltage VDD. However, since the reference voltage V REF_A supplied to the first regulator circuit 500A is slightly lower than the reference voltage V REF_C supplied to the second regulator circuit 500C, during the period 612, the second regulator circuit 500C mainly drives the internal logic power supply voltage VDD, and the first regulator circuit 500A drives the internal logic power supply voltage VDD only when the internal logic power supply voltage VDD becomes lower than the reference voltage V REF_A due to, for example, an increase in the power or current consumption of the logic circuit 400.

[0071] Time t 15In this case, the mixed signal circuit 3000 enters the sleep-in state to execute the shutdown sequence. In response to the mixed signal circuit 3000 entering the sleep-in state, the analog circuit 300 and the second regulator circuit 500C of the power supply circuit 3200 are deactivated, and the second regulator circuit 500C stops driving the internal logic power supply voltage VDD. It should be noted that the first regulator circuit 500A remains activated to execute the shutdown sequence while the mixed signal circuit 3000 is in the sleep-in state. After the mixed signal circuit 3000 enters the sleep-in state at time t 15 and before time t 16 the power management circuit 4000 stops driving the analog power supply voltage AVDD.

[0072] At time t 17 the mixed signal circuit 3000 enters the deep standby state. In response to the mixed signal circuit 3000 entering the deep standby state, the first regulator circuit 500A of the power supply circuit 3200 stops driving the internal logic power supply voltage VDD. The power management circuit 4000 may then stop driving the logic power supply voltage IOVCC and the external logic power supply voltage Ext_VDD at time t 18 . In other embodiments, the power management circuit 4000 may stop driving the analog power supply voltage AVDD after the mixed signal circuit 3000 enters the deep standby state.

[0073] FIG. 9 illustrates a configuration example of an analog circuit 300 and a logic circuit 400 according to one or more embodiments. In the illustrated embodiment, the mixed-signal circuit 1000 is configured as a display driver that drives the display panel 8000 based on the image data received from the host 7000. The display panel 8000 can be an LCD panel, an OLED display panel, a μLED display panel, or another type of display panel. In one or more embodiments, the logic circuit 400 includes an image buffer 410, an image processing circuit 420, and a timing controller 430, all of which are configured to receive an internal logic power supply voltage VDD. The image buffer 410 is configured to store the image data received from the host 7000 and transfer the stored image data to the image processing circuit 420. The image processing circuit 420 is configured to process the image data to generate processed image data. The timing controller 430 is configured to perform timing control of the mixed-signal circuit 1000. The analog circuit 300 includes a data driver circuit 310 configured to receive an analog power supply voltage AVDD. The data driver circuit 310 is configured to receive the processed image data from the image processing circuit 420 and drive the data lines (also called source lines) 8100 of the display panel 8000 using the analog power supply voltage AVDD based on the processed image data. FIG. 9 illustrates an embodiment in which the analog circuit 300 and the logic circuit 400 are integrated into the mixed-signal circuit 1000 illustrated in FIG. 1, but the configurations of the analog circuit 300 and the logic circuit 400 illustrated in FIG. 9 can also be used in the mixed-signal circuit 3000 illustrated in FIG. 6.

[0074] FIG. 10 is a flowchart of an example of a method 9000 for operating a mixed-signal circuit according to one or more embodiments. Method 9000 may be performed, for example, by the system shown in FIG. 1 or FIG. 6, and more specifically, by the mixed-signal circuit 1000 shown in FIG. 1 and the mixed-signal circuit 3000 shown in FIG. 6. However, it is understood that a mixed-signal circuit having additional and / or fewer components than those shown in FIG. 1 or FIG. 6 may be used to perform method 9000, and that any of the following steps may be performed in any suitable order and that method 9000 may be performed in any suitable environment, unless otherwise apparent.

[0075] Method 9000 includes, at step 9002, supplying a first logic supply voltage (e.g., the logic supply voltage IOVCC shown in FIGS. 1 and 6) to a first stage (e.g., first stage 510A) of a first regulator circuit (e.g., first regulator circuit 500A). The first regulator circuit includes an output PMOS transistor (e.g., output PMOS transistor MP1) having a drain coupled to a logic supply line (e.g., logic supply line 160) coupled to a logic circuit (e.g., logic circuit 400). The first logic supply voltage may be supplied to the mixed-signal circuit from a source external to the mixed-signal circuit. In one implementation, the first logic supply voltage is also supplied to the source of the output PMOS transistor. Method 9000 further includes, at step 9004, driving the gate of the output PMOS transistor by the first stage to drive the logic supply line to the output PMOS transistor.

[0076] Method 9000 further includes, at step 9006, supplying an analog power supply voltage (e.g., analog power supply voltage AVDD) to an analog circuit (e.g., analog circuit 300). Method 9000 further includes, at step 9008, supplying the analog power supply voltage to a second pre-stage (e.g., second pre-stages 510B and 510C illustrated in FIGS. 1 and 6) of a second regulator circuit (e.g., second regulator circuits 500B and 500C). The second regulator circuit includes output NMOS transistors (e.g., output NMOS transistors MN3 and MN5) having sources coupled to a logic power supply line. In some implementations, a first logic power supply voltage may also be supplied to the drains of the output NMOS transistors of the second regulator circuit. In other embodiments, a second logic power supply voltage (e.g., external logic power supply voltage Ext_VDD) that is lower than the first logic power supply voltage may be supplied to the drains of the output NMOS transistors of the second regulator circuit. Method 9000 further includes, at step 9010, driving the gates of the output NMOS transistors by the second pre-stage to drive the logic power supply line to the output NMOS transistors.

[0077] The use of "a", "an", "the", "at least one" and similar reference terms in the context of describing the present invention (especially in the context of the following claims) should be construed to cover both singular and plural forms, unless otherwise indicated herein or clearly contradicted by the context. The use of the term "at least one" following a list of one or more items (e.g., "at least one of A and B") should be construed to mean one item selected from the listed items (A or B), or any combination of two or more of the listed items (A and B), unless otherwise stated herein or clearly contradicted by the context. The terms "comprising", "having", "including" and "containing" should be construed as open-ended terms (i.e., meaning "including but not limited to") unless specifically stated otherwise. The recitation of a range of values herein is intended to serve merely as a shorthand reference for individually referring to each separate value falling within the range, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by the context. The use of any examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the invention and does not limit the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.

[0078] Exemplary embodiments are described herein. Variations of those exemplary embodiments will be apparent to those skilled in the art upon reading the foregoing description. The inventors expect those skilled in the art to appropriately adopt such variations, and the inventors intend for the invention to be practiced in ways other than those specifically described herein. Accordingly, the invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Further, any combination of the above-described elements in all possible variations thereof is included in the invention unless otherwise specifically indicated herein or otherwise clearly contradicted by context.

Claims

1. A logic circuit; an analog circuit configured to receive an analog supply voltage; a logic power line coupled to the logic circuit; a first regulator circuit comprising: an output p-channel metal-oxide semiconductor (PMOS) transistor having a drain coupled to the logic power line; and a first pre-stage configured to receive a first logic power supply voltage and drive a gate of the output PMOS transistor; a second regulator circuit comprising: an output n-channel metal-oxide semiconductor (NMOS) transistor having a source coupled to the logic power rail; and a second pre-stage configured to receive the analog power supply voltage and drive a gate of the output NMOS transistor; Equipped with The analog power supply voltage is higher than the first logic power supply voltage. Mixed signal circuits.

2. The first logic power supply voltage is provided to the mixed signal circuit from a source external to the mixed signal circuit.

2. The mixed signal circuit of claim 1.

3. the output PMOS transistor of the first regulator circuit having a source configured to receive the first logic power supply voltage; The output NMOS transistor of the second regulator circuit has a drain configured to receive the first logic power supply voltage.

2. The mixed signal circuit of claim 1.

4. the first regulator circuit is configured to receive a first reference voltage at an input of the first pre-stage and to drive an output of the first regulator circuit based on the first reference voltage; The second regulator circuit is configured to receive a second reference voltage at an input of the second front stage, the second reference voltage being lower than the first reference voltage, and to drive an output of the second regulator circuit based on the second reference voltage.

4. The mixed signal circuit of claim 3.

5. a difference between the first reference voltage and the second reference voltage is 0.01 V or less; 5. The mixed signal circuit of claim 4.

6. the output PMOS transistor of the first regulator circuit having a source configured to receive the first logic power supply voltage; the output NMOS transistor of the second regulator circuit has a drain configured to receive a second logic power supply voltage that is lower than the first logic power supply voltage; The first logic power supply voltage and the second logic power supply voltage are supplied to the mixed signal circuit from a source external to the mixed signal circuit.

2. The mixed signal circuit of claim 1.

7. the first regulator circuit is configured to receive a first reference voltage at an input of the first pre-stage and to drive an output of the first regulator circuit based on the first reference voltage; The second regulator circuit is configured to receive a second reference voltage at an input of the second front stage, the second reference voltage being higher than the first reference voltage, and to drive an output of the second regulator circuit based on the second reference voltage.

7. The mixed signal circuit of claim 6.

8. The difference between the second reference voltage and the first reference voltage is 0.01 V or less.

8. The mixed signal circuit of claim 7.

9. the first regulator circuit is activated for a first time period that occurs after the mixed signal circuit leaves a deep standby state; the second regulator circuit is inactivated during the first period; Both the first regulator circuit and the second regulator circuit are activated during a second period following the first period.

2. The mixed signal circuit of claim 1.

10. The analog power supply voltage begins to be supplied to the mixed signal circuit at a certain time within the second period.

10. The mixed signal circuit of claim 9.

11. The analog circuitry comprises a data driver circuit configured to drive data lines of a display panel.

2. The mixed signal circuit of claim 1.

12. a power management circuit configured to generate a first logic power supply voltage and an analog power supply voltage that is greater than the first logic power supply voltage; 1. A mixed signal circuit comprising: A logic circuit; an analog circuit configured to receive the analog power supply voltage; a logic power line coupled to the logic circuit; a first regulator circuit comprising: an output p-channel metal-oxide semiconductor (PMOS) transistor having a drain coupled to the logic power line; and a first pre-stage configured to receive the first logic power supply voltage and drive a gate of the output PMOS transistor; a second regulator circuit comprising: an output n-channel metal-oxide semiconductor (NMOS) transistor having a source coupled to the logic power rail; and a second pre-stage configured to receive the analog power supply voltage and drive a gate of the output NMOS transistor; Equipped system.

13. the output PMOS transistor of the first regulator circuit having a source configured to receive the first logic power supply voltage; The output NMOS transistor of the second regulator circuit has a drain configured to receive the first logic power supply voltage. The system of claim 12.

14. the first regulator circuit is configured to receive a first reference voltage at an input of the first pre-stage and to drive an output of the first regulator circuit based on the first reference voltage; The second regulator circuit is configured to receive a second reference voltage at an input of the second front stage, the second reference voltage being lower than the first reference voltage, and to drive an output of the second regulator circuit based on the second reference voltage. The system of claim 13.

15. the power management circuitry is further configured to generate a second logic power supply voltage that is lower than the first logic power supply voltage; the output PMOS transistor of the first regulator circuit having a source configured to receive the first logic power supply voltage; The output NMOS transistor of the second regulator circuit has a drain configured to receive the second logic power supply voltage. The system of claim 12.

16. the first regulator circuit is configured to receive a first reference voltage at an input of the first pre-stage and to drive an output of the first regulator circuit based on the first reference voltage; The second regulator circuit is configured to receive a second reference voltage at an input of the second front stage, the second reference voltage being higher than the first reference voltage, and to drive an output of the second regulator circuit based on the second reference voltage. The system of claim 15.

17. providing a first logic supply voltage to a first front stage of a first regulator circuit comprising an output p-channel metal-oxide semiconductor (PMOS) transistor having a drain coupled to a logic supply line coupled to the logic circuit; driving a gate of the output PMOS transistor by the first front stage to cause the output PMOS transistor to drive the logic power line; supplying an analog power supply voltage to an analog circuit that is higher than the first logic power supply voltage; providing the analog supply voltage to a second front stage of a second regulator circuit comprising an output n-channel metal-oxide semiconductor (NMOS) transistor having a source coupled to the logic supply line; driving a gate of the output NMOS transistor by the second front stage to cause the output NMOS transistor to drive the logic power line; Includes method.

18. Furthermore, supplying the first logic power supply voltage to a source of the output PMOS transistor; supplying the first logic power supply voltage to a drain of the output NMOS transistor; Includes 20. The method of claim 17.

19. Furthermore, supplying the first logic power supply voltage to a source of the output PMOS transistor; supplying a second logic power supply voltage lower than the first logic power supply voltage to a drain of the output NMOS transistor; Includes 20. The method of claim 17.

20. The first logic power supply voltage and the second logic power supply voltage are generated by a power management circuit external to a mixed signal circuit including the first regulator circuit, the second regulator circuit, the logic power line, the logic circuit, and the analog circuit.

20. The method of claim 19.

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