Semiconductor device, semiconductor device manufacturing method, and power conversion device

Abstract

To suppress warping of a semiconductor wafer caused by impurity ion implantation for forming a channel formation layer in contact with a side wall of a trench.SOLUTION: A semiconductor device 101 includes a drift layer, a P-type base layer 16, an N-type source layer 15, and a gate electrode 13. The base layer 16 is formed in a part of the surface layer of the drift layer 14. The source layer 15 is formed in a part of the surface layer of the base layer 16. The gate electrode 13 is provided in a plurality of trenches 10 penetrating the source layer 15 and the base layer 16 via a gate insulating film 17. The source layer 15 formed between the plurality of trenches 10 becomes shallower and has a lower impurity concentration as it is farther away from the sidewalls of the plurality of trenches 10.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a technique for suppressing warping of a semiconductor wafer by impurity ion implantation.

Background Art

[0002] Generally, a semiconductor device for power, which is generally called a power device, is used for a switching element that controls power supply to a motor load or the like. Although several performances are required for a power device, one of the most important requirements is to reduce losses. Reducing the losses of a power device has effects such as miniaturization and weight reduction of the device, and in a broad sense, it leads to an effect of considering the global environment by reducing energy consumption. Furthermore, these characteristics are required to be realized at as low a cost as possible.

[0003] As a semiconductor element for power that satisfies these requirements, insulated gate semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are widely used.

[0004] Conventionally, as a method for reducing the losses of an insulated gate semiconductor device, there is a method of increasing the channel density, and as one of the structures corresponding to this method, a structure called a trench type has been proposed (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a trench-type MOSFET, in order to achieve a narrow pitch for reducing the on-resistance, a configuration in which an interlayer insulating film is embedded inside the trench is conceivable. However, in order to embed the interlayer insulating film inside the trench, it is necessary to form the trench deeper than before by the depth of the interlayer insulating film inside the trench. Accordingly, since the source layer, which is the channel formation layer, also needs to be formed deeper, it is necessary to increase the ion implantation energy for forming the source layer. As a result, there is a problem that the warp of the semiconductor wafer becomes large after ion implantation.

[0007] The present disclosure has been made to solve the above problems, and an object thereof is to suppress the warp of a semiconductor wafer due to impurity ion implantation for forming a channel formation layer in contact with the sidewall of a trench.

Means for Solving the Problems

[0008] The semiconductor device of the present disclosure includes a drift layer, a base layer of a second conductivity type, a channel formation layer of a first conductivity type, and a gate electrode. The base layer is formed in a part of the surface layer of the drift layer. The channel formation layer is formed in a part of the surface layer of the base layer. The gate electrode is provided via a gate insulating film in a plurality of trenches penetrating the channel formation layer and the base layer. The channel formation layer formed between the plurality of trenches becomes shallower and has a lower impurity concentration as it is farther from the sidewalls of the plurality of trenches.

Effects of the Invention

[0009] The semiconductor device of the present disclosure includes a channel formation layer that becomes shallower and has a lower impurity concentration as it is farther from the sidewalls of the plurality of trenches. Such a channel formation layer can be formed with a low implantation energy by performing ion implantation from an oblique direction with respect to the sidewall of the trench. Therefore, it is possible to suppress the warp of the semiconductor after ion implantation for forming the channel formation layer.

Brief Description of the Drawings

[0010]

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Best Mode for Carrying Out the Invention

[0011] In the following description, the first conductivity type is an n-type and the second conductivity type is a p-type. Conversely, the first conductivity type may be a p-type and the second conductivity type may be an n-type.

[0012] <A. Embodiment 1> <A-1. Configuration> FIG. 1 is a plan view of a semiconductor device 101 according to Embodiment 1 as viewed from above. Hereinafter, the semiconductor device 101 will be described as a MOSFET, but the semiconductor device 101 may be other switching elements such as an IGBT. The semiconductor substrate may be a normal semiconductor wafer, an epitaxial growth layer, or a combination thereof. Note that the semiconductor device 101 is formed using a semiconductor substrate made of silicon carbide (SiC). However, the material of the semiconductor substrate is not limited to silicon carbide, and may be silicon (Si), a gallium nitride (GaN)-based material, gallium oxide, diamond, or other wide bandgap semiconductors. In FIG. 1, for convenience, illustrations of a gate insulating film, a field insulating film, an interlayer insulating film, a gate electrode, a protective film, etc. are omitted from the configuration of the upper surface of the semiconductor device 101.

[0013] In FIG. 1, a gate pad 81 is formed on a part of the upper surface of the semiconductor device 101, and a source electrode 80 is formed adjacent to this. Further, a gate wiring 82 is formed so as to extend from the gate pad 81. Note that the gate pad 81 may be provided at any location on the upper surface of the semiconductor device 101, for example, at the center. Also, control pads other than the gate pad 81 may be provided on the upper surface of the semiconductor device 101. The control pads other than the gate pad 81 include, for example, at least any one of a current sense pad, a Kelvin source pad, and a temperature sense diode pad.

[0014] Next, the current sense pad, Kelvin source pad, and temperature sense diode pad will be described. The current sense pad is a control pad for detecting the current flowing in the cell region of the semiconductor device 101. The current sense pad is electrically connected to the cell region of the semiconductor device 101. When a current flows in the cell region, a current that is one fraction to one ten-thousandth of the current flowing through the entire cell region flows into the current sense pad. The Kelvin source pad is a control pad to which a gate drive voltage for controlling the on / off of the semiconductor device 101 is applied.

[0015] The temperature sense diode pad is a control pad electrically connected to the anode and cathode of the temperature sense diode provided in the semiconductor device 101. The voltage between the anode and cathode of the temperature sense diode provided in the cell region is measured via the temperature sense diode pad, and the temperature of the semiconductor device 101 is measured based on that voltage. Note that control pads other than the gate pad 81 may be provided at any location on the upper surface of the semiconductor device 101, for example, at the edge or the center.

[0016] Figure 2 is a plan view showing mainly the silicon carbide semiconductor portion of the semiconductor device 101. In Figure 2, unit cell regions each composed of a p-type base layer 16 and a trench gate 4 having a trench-type gate electrode are arranged in a stripe pattern. In other words, the unit cell regions are repeatedly arranged in one direction in plan view. A semiconductor device 101 having such an arrangement of unit cell regions is called a stripe type. Note that the arrangement of the unit cell regions in the semiconductor device 101 is not limited to the stripe type and may be other arrangements such as a lattice type or a hexagonal type.

[0017] Note that trench sources having trench-type source electrodes may be alternately provided with trench gates 4. The trench gate 4 and the trench source together are referred to as an active trench. A region in which unit cell regions constituting the MOSFET are repeatedly arranged is referred to as an active region, and a region formed on the outer periphery of the active region is referred to as a termination region. The termination region includes a p-type termination well region 31, a JTE region 37 that holds breakdown voltage, and a gate pad 81.

[0018] Note that an FLR (Field Limiting Ring) may be provided instead of the JTE region 37. Also, a configuration combining the JTE region 37 and the FLR may be adopted.

[0019] The impurity concentration of the JTE region 37 selectively provided in the termination well region 31 is lower than the impurity concentration of the termination well region 31. Although not shown, a termination trench may be provided in the termination region, and the termination well region 31 and the JTE region 37 may be provided at the bottom of the termination trench. The depth of the termination trench may be the same as or greater than the depth of the trench of the trench gate 4. A gate wiring 82 may be provided on the termination region. The source contact hole of the source electrode 80 does not have to be provided on the termination region side at the end of the trench gate 4. That is, a source contact hole does not have to be provided in a region where the termination well region 31 and the JTE region 37 are provided below the termination trench.

[0020] FIG. 3 is an enlarged view of the region R1 in FIG. 2. FIG. 4 is a cross-sectional view taken along the line A-A in FIG. 3. FIG. 5 is an enlarged view of the region R2 in FIG. 4. As shown in FIG. 3, in the semiconductor device 101, a plurality of trench gates 4 are arranged in the first direction D1 and extend in the second direction D2 in a plan view.

[0021] As shown in FIG. 4, the semiconductor device 101 includes a semiconductor substrate 18, a drift layer 14, a base layer 16, a source layer 15, a gate insulating film 17, a gate electrode 13, an interlayer insulating film 19, a source electrode 80, and a drain electrode 12.

[0022] An n-type drift layer 14 is formed on the semiconductor substrate 18. A p-type base layer 16 is formed on the surface layer of the drift layer 14 opposite to the semiconductor substrate 18. An n-type source layer 15 is discretely formed on the surface layer of the base layer 16 opposite to the semiconductor substrate 18. The source layer 15 is also referred to as a channel formation layer. The region of the surface layer of the base layer 16 where the source layer 15 is not formed becomes a contact region.

[0023] A source electrode 80 is formed on the base layer 16, the source layer 15, and an interlayer insulating film 19 described later. Also, a drain electrode 12 is formed on the side of the semiconductor substrate 18 opposite to the drift layer 14.

[0024] A plurality of trenches 10 are formed that penetrate the source layer 15 and the base layer 16 and reach the drift layer 14. The region between the plurality of trenches 10 is a mesa region 23. The base layer 16 and the source layer 15 are formed in the mesa region 23. On the surface of the mesa region 23, it is preferable that the area of the contact region is smaller than the area of the source layer 15.

[0025] A gate insulating film 17, a gate electrode 13, and an interlayer insulating film 19 are embedded in the trench 10. The gate insulating film 17 is formed on the side surface and the bottom surface of the trench 10. The gate electrode 13 is formed on the gate insulating film 17. Therefore, the gate electrode 13 faces the base layer 16 with the gate insulating film 17 in between.

[0026] Also, a p-type electric field relaxation layer 20 is formed directly below the trench 10. By providing the electric field relaxation layer directly below the trench 10 that becomes the trench gate 4, the electric field applied to the gate insulating film 17 at the bottom of the trench 10 is relaxed, and breakdown of the gate insulating film 17 during high voltage application is suppressed. Note that it is more effective to provide the electric field relaxation layer 20 directly below all the trenches 10 than to provide the electric field relaxation layer 20 only directly below some of the trenches 10. Particularly in a trench-type MOSFET using silicon carbide that requires operation at high voltages compared to Si, providing the electric field relaxation layer 20 is effective in suppressing breakdown of the gate insulating film 17. Further, the electric field relaxation layer 20 may be electrically connected to the source electrode 80 via the base layer 16. In that case, a connection layer of a second conductivity type that connects the electric field relaxation layer 20 and the base layer 16 may be provided in a part of the mesa region 23. This connection layer is preferably disposed directly below the contact region. The electric field relaxation layer 20 may extend in the same direction as the extending direction of the trench 10 (second direction D2 in FIG. 3) and may form a superjunction structure by being provided alternately with the drift layer 14 or an n-type pillar layer provided separately. Note that the peak impurity concentration of the n-type pillar layer may be higher than that of the drift layer 14.

[0027] <A-2. Manufacturing Method> FIG. 6 is a flowchart showing the manufacturing process of the semiconductor device 101 according to Embodiment 1. Hereinafter, a method for manufacturing the semiconductor device 101 will be described with reference to the flowchart of FIG. 6.

[0028] First, in step S101, an epitaxial growth of a drift layer 14 made of silicon carbide is performed on a semiconductor substrate 18 made of n-type low-resistance silicon carbide and having a 4H polytype by a chemical vapor deposition (CVD) method. FIG. 7 shows this state. The plane orientation of the main surface of the semiconductor substrate 18 on which the drift layer 14 epitaxially grows is an off-angle (0001) plane. The impurity concentration of the drift layer 14 is 1×10 15 cm -3 or more and 1×10 17 cm -3It shall be as follows. The thickness of the drift layer 14 shall be 5 μm or more and 50 μm or less.

[0029] Next, in step S102, a base layer 16 is formed on the drift layer 14. The process of this step is also referred to as the base layer formation process. Specifically, Al, which is a p-type impurity, is ion-implanted into the surface of the drift layer 14. At this time, the depth of the Al ion implantation is set to be about 0.5 μm or more and 10 μm or less without exceeding the thickness of the drift layer 14. Also, the impurity concentration of the ion-implanted Al is made higher than the impurity concentration of the drift layer in the range of 1×10 17 cm -3 or more and 1×10 19 cm -3 or less. The region implanted with Al ions in this step becomes the base layer 16 in the active region and the terminal well region 31 in the terminal region. FIG. 8 shows this state.

[0030] Note that the base layer 16 may be formed on the drift layer 14 by an epitaxial method. Also, an implantation mask may be formed on the base layer 16 by a photoresist or the like, except for a predetermined location, and Al may be ion-implanted at an impurity concentration in the range of 1×10 18 cm -3 or more and 1×10 21 cm -3 or less, which is higher than the impurity concentration of the base layer 16, and then the implantation mask may be removed. Among the regions implanted with Al ions in this step, the p-type regions may become p+-type contact layers by being activated by a heat treatment described later.

[0031] Next, in step S103, a trench 10 that penetrates the base layer 16 and reaches the drift layer 14 is formed by dry etching. The process of this step is also referred to as the trench formation process. FIG. 9 shows this state. Specifically, an etching mask is deposited on the base layer 16 to a thickness of about 1 μm or more and 5 μm or less, and a resist mask made of a resist material is formed thereon. The resist mask is formed into a pattern with an opening in the formation region of the trench 10 by photolithography technology. When the trench 10 is in a stripe shape, the resist mask has a stripe-shaped pattern that is the inversion thereof. Then, by reactive ion etching (RIE) treatment using the resist mask as a mask, a trench 10 that penetrates the base layer 16 is formed.

[0032] The depth of the trench 10 is equal to or greater than the depth of the base layer 16 and is about 0.5 μm or more and 3 μm or less. Note that a termination trench may be formed simultaneously when the trench 10 is formed. When the main surface plane orientation of the semiconductor substrate 18 on which the drift layer 14 epitaxially grows has an off-angle in the <11-20> direction and is a (0001) plane, the trench 10 may be formed parallel to the <11-20> direction. By doing so, the threshold voltage of the MOSFET in the trench gate 4 is not affected by the off-direction of the semiconductor substrate 18, so the variation in the threshold voltage of the MOSFET is reduced.

[0033] Next, in step S104A, ions of an n-type impurity such as nitrogen (N) are implanted from an oblique direction having an angle θ with respect to the side wall of the trench 10. Such ion implantation from an oblique direction is referred to as oblique ion implantation. The process of this step is also referred to as the first oblique implantation process. FIG. 10 shows this state. The implantation energy is desirably 10 keV or more and 150 keV or less. When the implantation energy exceeds 150 keV, the semiconductor wafer is likely to warp, and particularly when it exceeds 600 keV, it is even more likely to warp.

[0034] The impurity concentration of the ions implanted in this step is 1×10 18 cm -31×10 or less above 21 cm -3 It is within the following range. Among the regions where impurities are implanted in this process, the region indicating n-type becomes the source layer 15. The source layer 15 is formed on a part of the surface layer of the base layer 16 and the side wall of the trench 10 by oblique ion implantation. Therefore, the source layer 15 becomes deeper as it goes from the center side of the mesa region 23 toward the side wall of the trench 10. As a result, a deep source layer 15 can be formed at a portion in contact with the side wall of the trench 10 with a small implantation energy. Therefore, warping of the semiconductor wafer after ion implantation is suppressed.

[0035] Hereinafter, the angle θ formed by the ion implantation direction with respect to the side wall of the trench 10 is referred to as the ion implantation angle θ. The relationship among the ion implantation angle θ, the width d of the trench 10, and the depth h of the source layer 15 in contact with the side wall of the trench 10 is represented by the following formula (1).

[0036]

Equation

[0037] As can be seen from formula (1), if the ion implantation angle θ is constant for all the trenches 10, when the trench width d varies, the depth h of the source layer 15 also varies. The depth h of the source layer 15 is the channel length Lch. Therefore, when the trench width d varies, the channel length Lch varies. When any two trenches 10 are selected from a plurality of trenches 10, and the width of the first trench 10 is d1 and the width of the second trench 10 is d2, it is desirable that d2 / d1 be 0.8 or more and 1.2 or less from the viewpoint of suppressing variations in the channel length Lch.

[0038] The ion implantation angle θ may be greater than 0 and equal to or less than 70°. When the ion implantation angle θ exceeds 70°, a shadow is formed by the upper corner of the trench 10, and the irradiation range is limited, that is, the influence of shadowing becomes large, which is not desirable. Incidentally, by oblique implantation, the impurity concentration of the source layer 15 may decrease from the side wall side of the trench 10 toward the center side of the mesa region 23. By forming the source layer 15 in a direction different from the thickness direction of the semiconductor substrate 18, warping of the semiconductor wafer is suppressed.

[0039] Hereinafter, three methods for further suppressing variations in the channel length Lch will be described. The first method is a method of adjusting the ion implantation angle θ according to the width d of the trench 10. As described above, it is assumed that d2 / d1 is 0.8 or more and 1.2 or less with respect to the widths d1 and d2 of the two trenches 10. Let the ion implantation angle θ for the trench 10 with width d1 be θ1, and let the depth h of the source layer 15 formed adjacent to this trench 10 be h1. Also, let the ion implantation angle θ for the trench 10 with width d2 be θ2, and let the depth h of the source layer 15 formed adjacent to this trench 10 be h2. By transforming Equation (1), the following Equation (2) is obtained.

[0040]

Equation

[0041] In order to reduce the variation in the depth h of the source layer 15, that is, to make h2 / h1 = 1, θ2 may be varied according to the variation in the width d of the trench 10, that is, d2 / d1, so that tanθ2 / tanθ1 = d2 / d1.

[0042] The second method is to adjust the thickness of the oxide film mask during the oblique implantation according to the variation in the width d of the trench 10. In this method, after forming the base layer 16 on the surface layer of the drift layer 14, before forming the trench 10, the source layer 15 is formed on the surface layer of the base layer 16 by ion implantation using a mask. This step is also referred to as the ion implantation step. Then, an oxide film mask 21 is formed on the source layer 15, and a trench 10 penetrating the base layer 16 is formed by dry etching using the oxide film mask 21.

[0043] Next, the thickness of the oxide film mask 21 is adjusted to Δh. This step is also referred to as the mask thickness adjustment step.

[0044] After that, with the oxide film mask 21 having a thickness of Δh remaining, oblique ion implantation is performed at an implantation angle θ with respect to the side walls of the trench 10 to form the source layer 15 on the side walls of the trench 10. FIG. 11 shows this state. Note that in FIG. 11, the illustration of the semiconductor substrate 18 is omitted, and the same applies to the cross-sectional views from FIG. 12 onwards. When oblique ion implantation is performed with the oxide film mask 21 having a thickness of Δh remaining, the depth h of the source layer 15 becomes smaller by Δh compared to the case of oblique ion implantation without the oxide film mask 21. Therefore, it is possible to adjust the depth h of the source layer 15 by determining the thickness of the oxide film mask 21 to be left in the mask thickness adjustment step. That is, the thickness of the oxide film mask 21 adjusted in the mask thickness adjustment step is determined according to the width of the trench 10 adjacent to the oxide film mask 21. For example, when the width d of the trench 10 becomes larger than the reference value, the variation in the depth h of the source layer 15 can be suppressed by increasing the thickness of the oxide film mask 21 to be left accordingly.

[0045] The third method is to adjust the etching amount of the SiC surface before oblique ion implantation according to the width d of the trench 10. First, a base layer 16 is formed on the drift layer 14. Next, ion implantation is performed on the surface layer of the base layer 16 using an implantation mask to form a source layer 15. Then, a trench 10 penetrating through the source layer 15 and the base layer 16 is formed by dry etching. Next, an etching process is carried out to etch the surface layer of the source layer 15, that is, the SiC surface, by Δh to reduce the depth of the trench 10. The etching amount Δh of the source layer 15 is determined according to the width d of the trench 10 adjacent to the source layer 15.

[0046] Thereafter, a source layer 15 is formed on the sidewall of the trench 10 by oblique ion implantation. FIG. 12 shows this state. The relationship between the width d of the trench and the depth h of the source layer 15 is as shown in Equation (1). Therefore, when the width d of the trench varies, the depth of the source layer 15 can be adjusted by adjusting the etching amount Δh of the SiC surface. If the etching amount of the SiC surface is Δh, the depth of the source layer 15 increases by Δh, and the variation in the depth of the source layer 15 can be reduced.

[0047] After various impurities are introduced by ion implantation as described above, an annealing process is performed in step S105 to diffuse and activate the impurities in the base layer 16, the source layer 15, etc. For example, annealing at a temperature of 1300°C to 1900°C for 30 seconds to 1 hour is performed on the semiconductor substrate in an inert gas atmosphere such as argon (Ar) gas using a heat treatment apparatus. By this annealing, impurities such as N and Al implanted by ion implantation are electrically activated. In this embodiment, heat treatment is performed after all the impurities have been implanted, but this is not restrictive. For example, ion implantation and heat treatment for diffusion and activation may be performed alternately.

[0048] Next, in step S106, an insulating film that will become a field insulating film (not shown) is formed on the front side of the semiconductor substrate 18. The insulating film may be formed by thermal oxidation or the like, or may be formed by a deposition method. The thickness of the insulating film is determined in consideration of cleaning in subsequent processes and loss during the etching process. For example, using a CVD method, photolithography technology, etc., a field insulating film made of silicon oxide is formed on regions excluding the active regions corresponding to the base layers (for example, the regions of gate pads, sense pads, terminal regions, etc.). The film thickness of the field insulating film is, for example, from 0.5 μm to 2 μm, and is larger than the film thickness of the gate insulating film 17 described below.

[0049] Thereafter, in step S107, the trench 10 not covered by the field insulating film is thermally oxidized, and a silicon oxide film having a desired thickness is formed as the gate insulating film 17 on the inner sidewalls and bottom surface of the trench. Note that the formation method and material of the gate insulating film 17 are not limited to this. Thereafter, a polycrystalline silicon film having conductivity is formed on the gate insulating film 17 and the field insulating film by a reduced-pressure CVD method, and this is patterned to form the gate electrode 13 inside the trench 10. Note that the formation method and material of the gate electrode 13 are not limited to this.

[0050] Next, in step S108, an insulating film made of silicon oxide and having a thickness larger than that of the gate insulating film 17 is formed as the interlayer insulating film 19 on the front side of the semiconductor substrate 18 by a reduced-pressure CVD method. The interlayer insulating film may be BPSG (Boro-Phospho Silicate Glass) containing B (boron) or P (phosphorus), or may be a laminated film of BPSG and impurity-free silicon oxide. Next, the deposited interlayer insulating film 19 is etched. As a result, the interlayer insulating film 19 remains on the gate electrode 13 formed in the trench 10 and does not remain in the mesa region 23 around the trench 10.

[0051] Next, in step S109, a silicide layer is formed over the entire front surface side of the semiconductor substrate 18. Specifically, a metal film mainly composed of Ni (for example, Ni film) is formed over the entire front surface side of the semiconductor substrate 18 by, for example, a sputtering method or the like. Then, a heat treatment is performed at a temperature of 600°C to 1100°C to react the metal film mainly composed of Ni with the semiconductor substrate in which SiC without an insulating film is exposed, and a silicide layer is formed therebetween.

[0052] Thereafter, in step S110, the remaining metal film mainly composed of Ni on the layer insulating film 19 or the like is removed by wet etching such as sulfuric acid peroxide to form an ohmic electrode.

[0053] Then, in step S111, a metal film containing Al or AlSi is formed over the entire front surface side of the semiconductor substrate 18 by, for example, sputtering or the like, a mask having a mask pattern is formed using a photolithography technique, and the deposited metal film is etched. Thereby, a gate pad 81 and a gate wiring 82 that contact the gate electrode, a source electrode, and various pads are formed.

[0054] Next, in step S112, a first metal film and a second metal film are formed. Specifically, a polyimide film (not shown) is formed on the source electrode 80, a mask having a mask pattern is formed using a photolithography technique, and the polyimide film is etched. Then, an electroless plating film containing Ni or a Ni compound is formed as the first metal film on the source electrode 80 where the polyimide film is not provided. Finally, an electroless plating film containing Au for preventing oxidation of the first metal film is formed as the second metal film on the first metal film. Note that the first metal film and the second metal film may be formed by sputtering or the like instead of electroless plating.

[0055] Thereafter, in step S113, similar to the formation of the source electrode 80, a metal film containing Ni or Au is formed over the entire back surface side of the semiconductor substrate 18 by, for example, sputtering or the like to form a drain electrode 12.

[0056] <A-3. Comparative Example> FIGS. 13 and 14 are cross-sectional views showing a method of manufacturing a semiconductor device according to a comparative example. According to the manufacturing method of the comparative example, a drift layer 14 is formed on a semiconductor substrate 18. Then, a base layer 16 is formed on the surface layer of the drift layer 14 on the side opposite to the semiconductor substrate 18. Thereafter, as shown in FIG. 13, N ions are implanted into the surface layer of the base layer 16 on the side opposite to the drift layer 14 to form a source layer 15.

[0057] Next, as shown in FIG. 14, a trench 10 is formed that penetrates the source layer 15 and the base layer 16 from the upper surface of the source layer 15 and reaches the drift layer 14.

[0058] In the comparative example, the direction of ion implantation for forming the source layer 15 is the thickness direction of the semiconductor substrate 18, that is, the direction perpendicular to the main surface of the semiconductor substrate 18. Therefore, it is impossible to suppress the implantation region of the source layer 15 in the thickness direction of the semiconductor substrate 18. As a result, after ion implantation for forming the source layer 15, the semiconductor wafer warps.

[0059] FIG. 15 compares the amount of warpage of the semiconductor wafer before and after ion implantation for forming the source layer 15 between the manufacturing method of the semiconductor device of the comparative example and the present embodiment. In FIG. 15, the circles indicate the amount of warpage of the semiconductor wafer by the manufacturing method of the comparative example, and the squares indicate the amount of warpage of the semiconductor wafer by the manufacturing method of the present embodiment. It can be seen from FIG. 15 that in the comparative example, the warpage increases after ion implantation, but in the manufacturing method of the present embodiment, the amount of warpage after ion implantation can be suppressed. For example, in the present embodiment, it is possible to suppress the amount of warpage of the semiconductor wafer to 25% or less compared to the comparative example.

[0060] <A-4. Effects> As described above, the semiconductor device 101 according to Embodiment 1 includes a drift layer 14, a base layer 16 of a second conductivity type, a channel formation layer of a first conductivity type, and a gate electrode 13. The base layer 16 is formed in a part of the surface layer of the drift layer 14. The channel formation layer is formed in a part of the surface layer of the base layer 16. The gate electrode 13 is provided via an insulating film in a plurality of trenches 10 that penetrate the channel formation layer and the base layer 16. The channel formation layer formed between the plurality of trenches 10 becomes shallower and has a lower impurity concentration as it is farther from the side walls of the plurality of trenches 10. Such a channel formation layer can be formed with low implantation energy by performing ion implantation from an oblique direction with respect to the side walls of the trenches 10. Therefore, after ion implantation for forming the channel formation layer, warping of the semiconductor wafer can be suppressed. Further, since the channel formation layer can be formed to a deep position while suppressing warping of the semiconductor wafer, it is possible to increase the thickness of the interlayer insulating film 19 embedded in the trenches 10. Therefore, the margin of the interlayer insulating film 19 with respect to variations in the depth of the gate electrode 13 in the trenches 10 can be increased, improving reliability.

[0061] Further, the method for manufacturing the semiconductor device 101 according to Embodiment 1 includes a base layer formation step, a trench formation step, and a first oblique implantation step. In the base layer formation step, impurity ions are implanted into the drift layer 14 to form a base layer 16 of the second conductivity type on the surface layer of the drift layer 14. In the trench formation step, a plurality of trenches 10 penetrating the base layer 16 are formed. In the first oblique implantation step, impurity ions are implanted from an oblique direction forming an angle θ with respect to the side walls of the plurality of trenches 10 to form a channel formation layer of the first conductivity type on the surface layer of the base layer 16. In the first oblique implantation step, since the channel formation layer is formed on the side walls of the trenches 10, the channel formation layer can be formed deeply even with low implantation energy. Therefore, warpage of the semiconductor wafer after the first oblique implantation step can be suppressed. Further, since the channel formation layer can be formed to a deep position while suppressing warpage of the semiconductor wafer, it is possible to increase the thickness of the interlayer insulating film 19 embedded in the trenches 10. Therefore, the margin of the interlayer insulating film 19 with respect to variations in the depth of the gate electrode 13 in the trenches 10 can be increased, improving reliability.

[0062] <B. Embodiment 2> FIG. 16 is a cross-sectional view schematically showing the configuration of a semiconductor device 102 according to Embodiment 2. The semiconductor device 102 is different from the semiconductor device 101 according to Embodiment 1 in that a P-type well layer 22 is provided in a region below the source layer 15 along the side walls of the trenches 10. The well layer 22 is also referred to as a well layer. The well layer 22 is adjacent to the source layer 15 from below and contacts the side walls of the trenches 10.

[0063] FIG. 17 is a flowchart showing the manufacturing process of the semiconductor device 102. In the method for manufacturing the semiconductor device 102, after the oblique implantation of N ions for forming the source layer 15 (step S104A), the oblique implantation of Al ions for forming the well layer 22 (step S104B) is performed. This oblique implantation step of Al ions is also referred to as the second oblique implantation step.

[0064] In the semiconductor device 101 according to Embodiment 1 that does not have the well layer 22, if the width d of the trench 10 varies due to reasons such as manufacturing errors, when the ion implantation angle θ is the same, the depth h of the source layer 15 varies, and the channel length Lch also varies. However, in the semiconductor device 102 provided with the well layer 22 formed by the second ion implantation, since the channel length Lch is fixed, variations in electrical characteristics due to variations in the channel length Lch are suppressed, and high reliability can be obtained.

[0065] <C. Embodiment 3> This embodiment applies the semiconductor devices 101 and 102 according to the above-described Embodiments 1 and 2 to a power conversion device. The semiconductor devices 101 and 102 are not limited to application to a specific power conversion device. Hereinafter, as Embodiment 3, a case where the semiconductor devices 101 and 102 are applied to a three-phase inverter will be described.

[0066] FIG. 18 is a block diagram showing the configuration of a power conversion system to which the power conversion device 200 according to this embodiment is applied. The power conversion system shown in FIG. 18 includes a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be configured by various things. For example, the power source 100 may be configured by a DC system, a solar cell, or a storage battery, or may be configured by a rectifier circuit or an AC / DC converter connected to an AC system. Further, the power source 100 may be configured by a DC / DC converter that converts DC power output from a DC system into predetermined power.

[0067] The power conversion device 200 is a three-phase inverter connected between a power source 100 and a load 300. The power conversion device 200 converts the DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in FIG. 18, the power conversion device 200 includes a main conversion circuit 201, a drive circuit 202, and a control circuit 203. The main conversion circuit 201 converts the DC power into AC power and outputs it. The drive circuit 202 outputs a drive signal for driving each switching element of the main conversion circuit 201. The control circuit 203 outputs a control signal for controlling the drive circuit 202 to the drive circuit 202.

[0068] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. Note that the load 300 is not limited to a specific application and is a motor mounted on various electrical devices, and is used as a motor for, for example, hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0069] Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, the DC power supplied from the power source 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to the present embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements. The semiconductor devices 101 and 102 according to any one of the above-described Embodiments 1 and 2 are applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series in pairs of two switching elements to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0070] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit 202 outputs, to the control electrodes of each switching element, a drive signal for turning on the switching element and a drive signal for turning off the switching element in accordance with control signals from a control circuit 203 described later. When maintaining the switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0071] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) during which each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control in which the on time of the switching element is modulated according to the voltage to be output. Then, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state at each point in time. The drive circuit 202 outputs an on signal or an off signal to the control electrode of each switching element as a drive signal in accordance with this control signal.

[0072] In the power conversion device according to the present embodiment, since the semiconductor devices 101 and 102 according to Embodiments 1 and 2 are applied as the switching elements of the main conversion circuit 201, it is possible to improve the reliability by reducing the warpage of the semiconductor wafer.

[0073] In this embodiment, an example in which the semiconductor devices 101 and 102 are applied to a two-level three-phase inverter has been described. However, the semiconductor devices 101 and 102 are not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device has been used, but it may be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the semiconductor devices 101 and 102 may be applied to a single-phase inverter. Also, when supplying power to a DC load or the like, the semiconductor devices 101 and 102 can be applied to a DC / DC converter or an AC / DC converter.

[0074] Further, the power conversion device to which the semiconductor devices 101 and 102 are applied is not limited to the case where the above-described load is an electric motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power feeding system. Furthermore, it can also be used as a power conditioner for a solar power generation system or a power storage system.

[0075] As described above, the preferred embodiments have been described in detail. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

[0076] Hereinafter, aspects of the present disclosure will be summarized as appendices.

[0077] (Appendix 1) A drift layer, A base layer of the second conductivity type formed on a part of the surface layer of the drift layer, A channel formation layer of the first conductivity type formed on a part of the surface layer of the base layer, A gate electrode provided via a gate insulating film in a plurality of trenches penetrating the channel formation layer and the base layer, The channel formation layer formed between the plurality of trenches is shallower and has a lower impurity concentration as it is farther from the side walls of the plurality of trenches. A semiconductor device.

[0078] (Appendix 2) Further comprising a well layer adjacent to the channel formation layer from below and in contact with the side walls of the plurality of trenches. The semiconductor device according to Appendix 1.

[0079] (Appendix 3) A base layer forming step of implanting impurity ions into the drift layer to form a base layer of a second conductivity type in the drift layer, A trench forming step of forming a plurality of trenches penetrating the base layer, An impurity ion implantation step of implanting impurity ions from an oblique direction forming an angle θ with respect to the side walls of the plurality of trenches, and forming a channel formation layer of a first conductivity type at least in a portion of the base layer in contact with the side walls of the plurality of trenches. A method for manufacturing a semiconductor device.

[0080] (Appendix 4) The implantation energy of the impurity ions in the first oblique implantation step is 10 keV or more and 150 keV or less. The method for manufacturing a semiconductor device according to Appendix 3.

[0081] (Appendix 5) When the widths of a first trench and a second trench arbitrarily selected from the plurality of trenches are d1 and d2, respectively, d2 / d1 is 0.8 or more and 1.2 or less. The method for manufacturing a semiconductor device according to Appendix 3 or Appendix 4.

[0082] (Appendix 6) In the first oblique implantation step, the angle θ is 70° or less. The method for manufacturing a semiconductor device according to any one of Appendices 3 to 5.

[0083] (Appendix 7) In the first oblique implantation step, when the angles θ with respect to the first trench and the second trench are θ1 and θ2, respectively, tanθ2 / tanθ1 = d2 / d1. The manufacturing method of the semiconductor device described in Supplementary Note 5.

[0084] (Supplementary Note 8) The trench formation step is a step of forming the plurality of trenches using an oxide film mask, Between the base layer formation step and the trench formation step, an ion implantation step of forming the channel formation layer on the surface layer of the base layer by ion implantation, Between the trench formation step and the first oblique implantation step, further comprising a mask thickness adjustment step of adjusting the thickness of the oxide film mask, The adjusted thickness of the oxide film mask is determined according to the widths of the plurality of trenches adjacent to the oxide film mask, The manufacturing method of the semiconductor device according to any one of Supplementary Notes 3 to 6.

[0085] (Supplementary Note 9) Between the base layer formation step and the trench formation step, comprising an ion implantation step of forming the channel formation layer on the surface layer of the base layer by ion implantation, After the trench formation step, comprising an etching step of etching the surface layer of the channel formation layer, The etching amount of the channel formation layer in the etching step is determined according to the width of the trench adjacent to the channel formation layer, The manufacturing method of the semiconductor device according to any one of Supplementary Notes 3 to 6.

[0086] (Supplementary Note 10) After the first oblique implantation step, further comprising a second oblique implantation step of implanting impurity ions from an oblique direction with respect to the side walls of the plurality of trenches to form a well layer of a second conductivity type in a region of the base layer that contacts the plurality of trenches, The manufacturing method of the semiconductor device according to any one of Supplementary Notes 3 to 9.

[0087] (Supplementary Note 11) Having the semiconductor device described in Supplementary Note 1 or Supplementary Note 2, a main conversion circuit that converts the input power and outputs it, A drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device, A control circuit that outputs a control signal for controlling the drive circuit to the drive circuit, and a power conversion device including the same.

Explanation of Signs

[0088] 4 trench gates, 10 trenches, 12 drain electrodes, 13 gate electrodes, 14 drift layers, 15 source layers, 16 base layers, 17 gate insulating films, 18 semiconductor substrates, 19 interlayer insulating films, 20 electric field relaxation layers, 21 oxide film masks, 22 well layers, 23 mesa regions, 31 terminal well regions, 37 JTE regions, 80 source electrodes, 81 gate pads, 82 gate wirings, 100 power supplies, 101, 102 semiconductor devices, 200 power conversion devices, 201 main conversion circuits, 202 drive circuits, 203 control circuits, 300 loads.

Claims

1. A drift layer, a p-type base layer formed on a part of the surface layer of the drift layer, an n-type channel formation layer formed on a part of the surface layer of the base layer, a gate electrode provided via a gate insulating film in a plurality of trenches penetrating the channel formation layer and the base layer, and the channel formation layer formed between the plurality of trenches is shallower and has a lower impurity concentration as it is farther from the side walls of the plurality of trenches. A semiconductor device.

2. Further comprising a well layer that is adjacent to the channel formation layer from below and contacts the side walls of the plurality of trenches. The semiconductor device according to claim 1.

3. A base layer formation step of forming a p-type base layer in the drift layer by implanting impurity ions into the drift layer, a trench formation step of forming a plurality of trenches penetrating the base layer, and a first oblique implantation step of implanting impurity ions from an oblique direction forming an angle θ with respect to the side walls of the plurality of trenches to form an n-type channel formation layer at least in a portion of the base layer that contacts the side walls of the plurality of trenches. A method of manufacturing a semiconductor device.

4. The implantation energy of the impurity ions in the first oblique implantation step is 10 keV or more and 150 keV or less. The method of manufacturing a semiconductor device according to claim 3.

5. When the widths of a first trench and a second trench arbitrarily selected from the plurality of trenches are d1 and d2, respectively, d2 / d1 is 0.8 or more and 1.2 or less. The method of manufacturing a semiconductor device according to claim 3 or claim 4.

6. In the first oblique implantation step, the angle θ is 70° or less. The method of manufacturing a semiconductor device according to claim 3.

7. In the first oblique implantation step, when the angles θ with respect to the first trench and the second trench are θ1 and θ2, respectively, tan θ2 / tan θ1 = d2 / d1. The method of manufacturing a semiconductor device according to claim 5.

8. The trench formation step is a step of forming the plurality of trenches using an oxide film mask, an ion implantation step of forming the channel formation layer on the surface layer of the base layer by ion implantation between the base layer formation step and the trench formation step, and further comprising a mask thickness adjustment step of adjusting the thickness of the oxide film mask between the trench formation step and the first oblique implantation step. The thickness of the adjusted oxide film mask is determined according to the widths of the plurality of trenches adjacent to the oxide film mask. The method of manufacturing a semiconductor device according to claim 3.

9. An ion implantation step of forming the channel formation layer on the surface layer of the base layer by ion implantation is provided between the base layer formation step and the trench formation step. After the trench formation step, an etching step of etching the surface layer of the channel formation layer is provided. The etching amount of the channel formation layer in the etching step is determined according to the widths of the trenches adjacent to the channel formation layer. The method of manufacturing a semiconductor device according to claim 3.

10. After the first oblique implantation step, impurity ions are implanted into the side walls of the plurality of trenches from an oblique direction, and a second oblique implantation step of forming a well layer of a second conductivity type in a region of the base layer that contacts the plurality of trenches is further provided. The method of manufacturing a semiconductor device according to claim 3.

11. Having the semiconductor device according to claim 1 or claim 2, a main conversion circuit that converts input power and outputs it, A drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device, A control circuit that outputs a control signal for controlling the drive circuit to the drive circuit, A power conversion device comprising the above.

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